atombios_i2c.c 4.3 KB

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  1. /*
  2. * Copyright 2011 Advanced Micro Devices, Inc.
  3. *
  4. * Permission is hereby granted, free of charge, to any person obtaining a
  5. * copy of this software and associated documentation files (the "Software"),
  6. * to deal in the Software without restriction, including without limitation
  7. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8. * and/or sell copies of the Software, and to permit persons to whom the
  9. * Software is furnished to do so, subject to the following conditions:
  10. *
  11. * The above copyright notice and this permission notice shall be included in
  12. * all copies or substantial portions of the Software.
  13. *
  14. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  17. * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18. * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19. * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20. * OTHER DEALINGS IN THE SOFTWARE.
  21. *
  22. * Authors: Alex Deucher
  23. *
  24. */
  25. #include <drm/drmP.h>
  26. #include <drm/radeon_drm.h>
  27. #include "radeon.h"
  28. #include "atom.h"
  29. #define TARGET_HW_I2C_CLOCK 50
  30. /* these are a limitation of ProcessI2cChannelTransaction not the hw */
  31. #define ATOM_MAX_HW_I2C_WRITE 3
  32. #define ATOM_MAX_HW_I2C_READ 255
  33. static int radeon_process_i2c_ch(struct radeon_i2c_chan *chan,
  34. u8 slave_addr, u8 flags,
  35. u8 *buf, u8 num)
  36. {
  37. struct drm_device *dev = chan->dev;
  38. struct radeon_device *rdev = dev->dev_private;
  39. PROCESS_I2C_CHANNEL_TRANSACTION_PS_ALLOCATION args;
  40. int index = GetIndexIntoMasterTable(COMMAND, ProcessI2cChannelTransaction);
  41. unsigned char *base;
  42. u16 out = cpu_to_le16(0);
  43. int r = 0;
  44. memset(&args, 0, sizeof(args));
  45. mutex_lock(&chan->mutex);
  46. mutex_lock(&rdev->mode_info.atom_context->scratch_mutex);
  47. base = (unsigned char *)rdev->mode_info.atom_context->scratch;
  48. if (flags & HW_I2C_WRITE) {
  49. if (num > ATOM_MAX_HW_I2C_WRITE) {
  50. DRM_ERROR("hw i2c: tried to write too many bytes (%d vs 3)\n", num);
  51. r = -EINVAL;
  52. goto done;
  53. }
  54. if (buf == NULL)
  55. args.ucRegIndex = 0;
  56. else
  57. args.ucRegIndex = buf[0];
  58. if (num)
  59. num--;
  60. if (num)
  61. memcpy(&out, &buf[1], num);
  62. args.lpI2CDataOut = cpu_to_le16(out);
  63. } else {
  64. if (num > ATOM_MAX_HW_I2C_READ) {
  65. DRM_ERROR("hw i2c: tried to read too many bytes (%d vs 255)\n", num);
  66. r = -EINVAL;
  67. goto done;
  68. }
  69. args.ucRegIndex = 0;
  70. args.lpI2CDataOut = 0;
  71. }
  72. args.ucFlag = flags;
  73. args.ucI2CSpeed = TARGET_HW_I2C_CLOCK;
  74. args.ucTransBytes = num;
  75. args.ucSlaveAddr = slave_addr << 1;
  76. args.ucLineNumber = chan->rec.i2c_id;
  77. atom_execute_table_scratch_unlocked(rdev->mode_info.atom_context, index, (uint32_t *)&args);
  78. /* error */
  79. if (args.ucStatus != HW_ASSISTED_I2C_STATUS_SUCCESS) {
  80. DRM_DEBUG_KMS("hw_i2c error\n");
  81. r = -EIO;
  82. goto done;
  83. }
  84. if (!(flags & HW_I2C_WRITE))
  85. radeon_atom_copy_swap(buf, base, num, false);
  86. done:
  87. mutex_unlock(&rdev->mode_info.atom_context->scratch_mutex);
  88. mutex_unlock(&chan->mutex);
  89. return r;
  90. }
  91. int radeon_atom_hw_i2c_xfer(struct i2c_adapter *i2c_adap,
  92. struct i2c_msg *msgs, int num)
  93. {
  94. struct radeon_i2c_chan *i2c = i2c_get_adapdata(i2c_adap);
  95. struct i2c_msg *p;
  96. int i, remaining, current_count, buffer_offset, max_bytes, ret;
  97. u8 flags;
  98. /* check for bus probe */
  99. p = &msgs[0];
  100. if ((num == 1) && (p->len == 0)) {
  101. ret = radeon_process_i2c_ch(i2c,
  102. p->addr, HW_I2C_WRITE,
  103. NULL, 0);
  104. if (ret)
  105. return ret;
  106. else
  107. return num;
  108. }
  109. for (i = 0; i < num; i++) {
  110. p = &msgs[i];
  111. remaining = p->len;
  112. buffer_offset = 0;
  113. /* max_bytes are a limitation of ProcessI2cChannelTransaction not the hw */
  114. if (p->flags & I2C_M_RD) {
  115. max_bytes = ATOM_MAX_HW_I2C_READ;
  116. flags = HW_I2C_READ;
  117. } else {
  118. max_bytes = ATOM_MAX_HW_I2C_WRITE;
  119. flags = HW_I2C_WRITE;
  120. }
  121. while (remaining) {
  122. if (remaining > max_bytes)
  123. current_count = max_bytes;
  124. else
  125. current_count = remaining;
  126. ret = radeon_process_i2c_ch(i2c,
  127. p->addr, flags,
  128. &p->buf[buffer_offset], current_count);
  129. if (ret)
  130. return ret;
  131. remaining -= current_count;
  132. buffer_offset += current_count;
  133. }
  134. }
  135. return num;
  136. }
  137. u32 radeon_atom_hw_i2c_func(struct i2c_adapter *adap)
  138. {
  139. return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
  140. }