cayman_blit_shaders.c 7.4 KB

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  1. /*
  2. * Copyright 2010 Advanced Micro Devices, Inc.
  3. *
  4. * Permission is hereby granted, free of charge, to any person obtaining a
  5. * copy of this software and associated documentation files (the "Software"),
  6. * to deal in the Software without restriction, including without limitation
  7. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8. * and/or sell copies of the Software, and to permit persons to whom the
  9. * Software is furnished to do so, subject to the following conditions:
  10. *
  11. * The above copyright notice and this permission notice (including the next
  12. * paragraph) shall be included in all copies or substantial portions of the
  13. * Software.
  14. *
  15. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  18. * THE COPYRIGHT HOLDER(S) AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  19. * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  20. * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
  21. * DEALINGS IN THE SOFTWARE.
  22. *
  23. * Authors:
  24. * Alex Deucher <alexander.deucher@amd.com>
  25. */
  26. #include <linux/bug.h>
  27. #include <linux/types.h>
  28. #include <linux/kernel.h>
  29. /*
  30. * evergreen cards need to use the 3D engine to blit data which requires
  31. * quite a bit of hw state setup. Rather than pull the whole 3D driver
  32. * (which normally generates the 3D state) into the DRM, we opt to use
  33. * statically generated state tables. The register state and shaders
  34. * were hand generated to support blitting functionality. See the 3D
  35. * driver or documentation for descriptions of the registers and
  36. * shader instructions.
  37. */
  38. const u32 cayman_default_state[] =
  39. {
  40. 0xc0066900,
  41. 0x00000000,
  42. 0x00000060, /* DB_RENDER_CONTROL */
  43. 0x00000000, /* DB_COUNT_CONTROL */
  44. 0x00000000, /* DB_DEPTH_VIEW */
  45. 0x0000002a, /* DB_RENDER_OVERRIDE */
  46. 0x00000000, /* DB_RENDER_OVERRIDE2 */
  47. 0x00000000, /* DB_HTILE_DATA_BASE */
  48. 0xc0026900,
  49. 0x0000000a,
  50. 0x00000000, /* DB_STENCIL_CLEAR */
  51. 0x00000000, /* DB_DEPTH_CLEAR */
  52. 0xc0036900,
  53. 0x0000000f,
  54. 0x00000000, /* DB_DEPTH_INFO */
  55. 0x00000000, /* DB_Z_INFO */
  56. 0x00000000, /* DB_STENCIL_INFO */
  57. 0xc0016900,
  58. 0x00000080,
  59. 0x00000000, /* PA_SC_WINDOW_OFFSET */
  60. 0xc00d6900,
  61. 0x00000083,
  62. 0x0000ffff, /* PA_SC_CLIPRECT_RULE */
  63. 0x00000000, /* PA_SC_CLIPRECT_0_TL */
  64. 0x20002000, /* PA_SC_CLIPRECT_0_BR */
  65. 0x00000000,
  66. 0x20002000,
  67. 0x00000000,
  68. 0x20002000,
  69. 0x00000000,
  70. 0x20002000,
  71. 0xaaaaaaaa, /* PA_SC_EDGERULE */
  72. 0x00000000, /* PA_SU_HARDWARE_SCREEN_OFFSET */
  73. 0x0000000f, /* CB_TARGET_MASK */
  74. 0x0000000f, /* CB_SHADER_MASK */
  75. 0xc0226900,
  76. 0x00000094,
  77. 0x80000000, /* PA_SC_VPORT_SCISSOR_0_TL */
  78. 0x20002000, /* PA_SC_VPORT_SCISSOR_0_BR */
  79. 0x80000000,
  80. 0x20002000,
  81. 0x80000000,
  82. 0x20002000,
  83. 0x80000000,
  84. 0x20002000,
  85. 0x80000000,
  86. 0x20002000,
  87. 0x80000000,
  88. 0x20002000,
  89. 0x80000000,
  90. 0x20002000,
  91. 0x80000000,
  92. 0x20002000,
  93. 0x80000000,
  94. 0x20002000,
  95. 0x80000000,
  96. 0x20002000,
  97. 0x80000000,
  98. 0x20002000,
  99. 0x80000000,
  100. 0x20002000,
  101. 0x80000000,
  102. 0x20002000,
  103. 0x80000000,
  104. 0x20002000,
  105. 0x80000000,
  106. 0x20002000,
  107. 0x80000000,
  108. 0x20002000,
  109. 0x00000000, /* PA_SC_VPORT_ZMIN_0 */
  110. 0x3f800000, /* PA_SC_VPORT_ZMAX_0 */
  111. 0xc0016900,
  112. 0x000000d4,
  113. 0x00000000, /* SX_MISC */
  114. 0xc0026900,
  115. 0x000000d9,
  116. 0x00000000, /* CP_RINGID */
  117. 0x00000000, /* CP_VMID */
  118. 0xc0096900,
  119. 0x00000100,
  120. 0x00ffffff, /* VGT_MAX_VTX_INDX */
  121. 0x00000000, /* VGT_MIN_VTX_INDX */
  122. 0x00000000, /* VGT_INDX_OFFSET */
  123. 0x00000000, /* VGT_MULTI_PRIM_IB_RESET_INDX */
  124. 0x00000000, /* SX_ALPHA_TEST_CONTROL */
  125. 0x00000000, /* CB_BLEND_RED */
  126. 0x00000000, /* CB_BLEND_GREEN */
  127. 0x00000000, /* CB_BLEND_BLUE */
  128. 0x00000000, /* CB_BLEND_ALPHA */
  129. 0xc0016900,
  130. 0x00000187,
  131. 0x00000100, /* SPI_VS_OUT_ID_0 */
  132. 0xc0026900,
  133. 0x00000191,
  134. 0x00000100, /* SPI_PS_INPUT_CNTL_0 */
  135. 0x00000101, /* SPI_PS_INPUT_CNTL_1 */
  136. 0xc0016900,
  137. 0x000001b1,
  138. 0x00000000, /* SPI_VS_OUT_CONFIG */
  139. 0xc0106900,
  140. 0x000001b3,
  141. 0x20000001, /* SPI_PS_IN_CONTROL_0 */
  142. 0x00000000, /* SPI_PS_IN_CONTROL_1 */
  143. 0x00000000, /* SPI_INTERP_CONTROL_0 */
  144. 0x00000000, /* SPI_INPUT_Z */
  145. 0x00000000, /* SPI_FOG_CNTL */
  146. 0x00100000, /* SPI_BARYC_CNTL */
  147. 0x00000000, /* SPI_PS_IN_CONTROL_2 */
  148. 0x00000000, /* SPI_COMPUTE_INPUT_CNTL */
  149. 0x00000000, /* SPI_COMPUTE_NUM_THREAD_X */
  150. 0x00000000, /* SPI_COMPUTE_NUM_THREAD_Y */
  151. 0x00000000, /* SPI_COMPUTE_NUM_THREAD_Z */
  152. 0x00000000, /* SPI_GPR_MGMT */
  153. 0x00000000, /* SPI_LDS_MGMT */
  154. 0x00000000, /* SPI_STACK_MGMT */
  155. 0x00000000, /* SPI_WAVE_MGMT_1 */
  156. 0x00000000, /* SPI_WAVE_MGMT_2 */
  157. 0xc0016900,
  158. 0x000001e0,
  159. 0x00000000, /* CB_BLEND0_CONTROL */
  160. 0xc00e6900,
  161. 0x00000200,
  162. 0x00000000, /* DB_DEPTH_CONTROL */
  163. 0x00000000, /* DB_EQAA */
  164. 0x00cc0010, /* CB_COLOR_CONTROL */
  165. 0x00000210, /* DB_SHADER_CONTROL */
  166. 0x00010000, /* PA_CL_CLIP_CNTL */
  167. 0x00000004, /* PA_SU_SC_MODE_CNTL */
  168. 0x00000100, /* PA_CL_VTE_CNTL */
  169. 0x00000000, /* PA_CL_VS_OUT_CNTL */
  170. 0x00000000, /* PA_CL_NANINF_CNTL */
  171. 0x00000000, /* PA_SU_LINE_STIPPLE_CNTL */
  172. 0x00000000, /* PA_SU_LINE_STIPPLE_SCALE */
  173. 0x00000000, /* PA_SU_PRIM_FILTER_CNTL */
  174. 0x00000000, /* */
  175. 0x00000000, /* */
  176. 0xc0026900,
  177. 0x00000229,
  178. 0x00000000, /* SQ_PGM_START_FS */
  179. 0x00000000,
  180. 0xc0016900,
  181. 0x0000023b,
  182. 0x00000000, /* SQ_LDS_ALLOC_PS */
  183. 0xc0066900,
  184. 0x00000240,
  185. 0x00000000, /* SQ_ESGS_RING_ITEMSIZE */
  186. 0x00000000,
  187. 0x00000000,
  188. 0x00000000,
  189. 0x00000000,
  190. 0x00000000,
  191. 0xc0046900,
  192. 0x00000247,
  193. 0x00000000, /* SQ_GS_VERT_ITEMSIZE */
  194. 0x00000000,
  195. 0x00000000,
  196. 0x00000000,
  197. 0xc0116900,
  198. 0x00000280,
  199. 0x00000000, /* PA_SU_POINT_SIZE */
  200. 0x00000000, /* PA_SU_POINT_MINMAX */
  201. 0x00000008, /* PA_SU_LINE_CNTL */
  202. 0x00000000, /* PA_SC_LINE_STIPPLE */
  203. 0x00000000, /* VGT_OUTPUT_PATH_CNTL */
  204. 0x00000000, /* VGT_HOS_CNTL */
  205. 0x00000000,
  206. 0x00000000,
  207. 0x00000000,
  208. 0x00000000,
  209. 0x00000000,
  210. 0x00000000,
  211. 0x00000000,
  212. 0x00000000,
  213. 0x00000000,
  214. 0x00000000,
  215. 0x00000000, /* VGT_GS_MODE */
  216. 0xc0026900,
  217. 0x00000292,
  218. 0x00000000, /* PA_SC_MODE_CNTL_0 */
  219. 0x00000000, /* PA_SC_MODE_CNTL_1 */
  220. 0xc0016900,
  221. 0x000002a1,
  222. 0x00000000, /* VGT_PRIMITIVEID_EN */
  223. 0xc0016900,
  224. 0x000002a5,
  225. 0x00000000, /* VGT_MULTI_PRIM_IB_RESET_EN */
  226. 0xc0026900,
  227. 0x000002a8,
  228. 0x00000000, /* VGT_INSTANCE_STEP_RATE_0 */
  229. 0x00000000,
  230. 0xc0026900,
  231. 0x000002ad,
  232. 0x00000000, /* VGT_REUSE_OFF */
  233. 0x00000000,
  234. 0xc0016900,
  235. 0x000002d5,
  236. 0x00000000, /* VGT_SHADER_STAGES_EN */
  237. 0xc0016900,
  238. 0x000002dc,
  239. 0x0000aa00, /* DB_ALPHA_TO_MASK */
  240. 0xc0066900,
  241. 0x000002de,
  242. 0x00000000, /* PA_SU_POLY_OFFSET_DB_FMT_CNTL */
  243. 0x00000000,
  244. 0x00000000,
  245. 0x00000000,
  246. 0x00000000,
  247. 0x00000000,
  248. 0xc0026900,
  249. 0x000002e5,
  250. 0x00000000, /* VGT_STRMOUT_CONFIG */
  251. 0x00000000,
  252. 0xc01b6900,
  253. 0x000002f5,
  254. 0x76543210, /* PA_SC_CENTROID_PRIORITY_0 */
  255. 0xfedcba98, /* PA_SC_CENTROID_PRIORITY_1 */
  256. 0x00000000, /* PA_SC_LINE_CNTL */
  257. 0x00000000, /* PA_SC_AA_CONFIG */
  258. 0x00000005, /* PA_SU_VTX_CNTL */
  259. 0x3f800000, /* PA_CL_GB_VERT_CLIP_ADJ */
  260. 0x3f800000, /* PA_CL_GB_VERT_DISC_ADJ */
  261. 0x3f800000, /* PA_CL_GB_HORZ_CLIP_ADJ */
  262. 0x3f800000, /* PA_CL_GB_HORZ_DISC_ADJ */
  263. 0x00000000, /* PA_SC_AA_SAMPLE_LOCS_PIXEL_X0Y0_0 */
  264. 0x00000000,
  265. 0x00000000,
  266. 0x00000000,
  267. 0x00000000,
  268. 0x00000000,
  269. 0x00000000,
  270. 0x00000000,
  271. 0x00000000,
  272. 0x00000000,
  273. 0x00000000,
  274. 0x00000000,
  275. 0x00000000,
  276. 0x00000000,
  277. 0x00000000,
  278. 0x00000000,
  279. 0xffffffff, /* PA_SC_AA_MASK_X0Y0_X1Y0 */
  280. 0xffffffff,
  281. 0xc0026900,
  282. 0x00000316,
  283. 0x0000000e, /* VGT_VERTEX_REUSE_BLOCK_CNTL */
  284. 0x00000010, /* */
  285. };
  286. const u32 cayman_default_size = ARRAY_SIZE(cayman_default_state);