radeon_drv.c 23 KB

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  1. /**
  2. * \file radeon_drv.c
  3. * ATI Radeon driver
  4. *
  5. * \author Gareth Hughes <gareth@valinux.com>
  6. */
  7. /*
  8. * Copyright 2000 VA Linux Systems, Inc., Sunnyvale, California.
  9. * All Rights Reserved.
  10. *
  11. * Permission is hereby granted, free of charge, to any person obtaining a
  12. * copy of this software and associated documentation files (the "Software"),
  13. * to deal in the Software without restriction, including without limitation
  14. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  15. * and/or sell copies of the Software, and to permit persons to whom the
  16. * Software is furnished to do so, subject to the following conditions:
  17. *
  18. * The above copyright notice and this permission notice (including the next
  19. * paragraph) shall be included in all copies or substantial portions of the
  20. * Software.
  21. *
  22. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  23. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  24. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  25. * VA LINUX SYSTEMS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM, DAMAGES OR
  26. * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  27. * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  28. * OTHER DEALINGS IN THE SOFTWARE.
  29. */
  30. #include <drm/drmP.h>
  31. #include <drm/radeon_drm.h>
  32. #include "radeon_drv.h"
  33. #include <drm/drm_pciids.h>
  34. #include <linux/console.h>
  35. #include <linux/module.h>
  36. #include <linux/pm_runtime.h>
  37. #include <linux/vga_switcheroo.h>
  38. #include <drm/drm_gem.h>
  39. #include "drm_crtc_helper.h"
  40. #include "radeon_kfd.h"
  41. /*
  42. * KMS wrapper.
  43. * - 2.0.0 - initial interface
  44. * - 2.1.0 - add square tiling interface
  45. * - 2.2.0 - add r6xx/r7xx const buffer support
  46. * - 2.3.0 - add MSPOS + 3D texture + r500 VAP regs
  47. * - 2.4.0 - add crtc id query
  48. * - 2.5.0 - add get accel 2 to work around ddx breakage for evergreen
  49. * - 2.6.0 - add tiling config query (r6xx+), add initial HiZ support (r300->r500)
  50. * 2.7.0 - fixups for r600 2D tiling support. (no external ABI change), add eg dyn gpr regs
  51. * 2.8.0 - pageflip support, r500 US_FORMAT regs. r500 ARGB2101010 colorbuf, r300->r500 CMASK, clock crystal query
  52. * 2.9.0 - r600 tiling (s3tc,rgtc) working, SET_PREDICATION packet 3 on r600 + eg, backend query
  53. * 2.10.0 - fusion 2D tiling
  54. * 2.11.0 - backend map, initial compute support for the CS checker
  55. * 2.12.0 - RADEON_CS_KEEP_TILING_FLAGS
  56. * 2.13.0 - virtual memory support, streamout
  57. * 2.14.0 - add evergreen tiling informations
  58. * 2.15.0 - add max_pipes query
  59. * 2.16.0 - fix evergreen 2D tiled surface calculation
  60. * 2.17.0 - add STRMOUT_BASE_UPDATE for r7xx
  61. * 2.18.0 - r600-eg: allow "invalid" DB formats
  62. * 2.19.0 - r600-eg: MSAA textures
  63. * 2.20.0 - r600-si: RADEON_INFO_TIMESTAMP query
  64. * 2.21.0 - r600-r700: FMASK and CMASK
  65. * 2.22.0 - r600 only: RESOLVE_BOX allowed
  66. * 2.23.0 - allow STRMOUT_BASE_UPDATE on RS780 and RS880
  67. * 2.24.0 - eg only: allow MIP_ADDRESS=0 for MSAA textures
  68. * 2.25.0 - eg+: new info request for num SE and num SH
  69. * 2.26.0 - r600-eg: fix htile size computation
  70. * 2.27.0 - r600-SI: Add CS ioctl support for async DMA
  71. * 2.28.0 - r600-eg: Add MEM_WRITE packet support
  72. * 2.29.0 - R500 FP16 color clear registers
  73. * 2.30.0 - fix for FMASK texturing
  74. * 2.31.0 - Add fastfb support for rs690
  75. * 2.32.0 - new info request for rings working
  76. * 2.33.0 - Add SI tiling mode array query
  77. * 2.34.0 - Add CIK tiling mode array query
  78. * 2.35.0 - Add CIK macrotile mode array query
  79. * 2.36.0 - Fix CIK DCE tiling setup
  80. * 2.37.0 - allow GS ring setup on r6xx/r7xx
  81. * 2.38.0 - RADEON_GEM_OP (GET_INITIAL_DOMAIN, SET_INITIAL_DOMAIN),
  82. * CIK: 1D and linear tiling modes contain valid PIPE_CONFIG
  83. * 2.39.0 - Add INFO query for number of active CUs
  84. * 2.40.0 - Add RADEON_GEM_GTT_WC/UC, flush HDP cache before submitting
  85. * CS to GPU on >= r600
  86. * 2.41.0 - evergreen/cayman: Add SET_BASE/DRAW_INDIRECT command parsing support
  87. * 2.42.0 - Add VCE/VUI (Video Usability Information) support
  88. * 2.43.0 - RADEON_INFO_GPU_RESET_COUNTER
  89. */
  90. #define KMS_DRIVER_MAJOR 2
  91. #define KMS_DRIVER_MINOR 43
  92. #define KMS_DRIVER_PATCHLEVEL 0
  93. int radeon_driver_load_kms(struct drm_device *dev, unsigned long flags);
  94. int radeon_driver_unload_kms(struct drm_device *dev);
  95. void radeon_driver_lastclose_kms(struct drm_device *dev);
  96. int radeon_driver_open_kms(struct drm_device *dev, struct drm_file *file_priv);
  97. void radeon_driver_postclose_kms(struct drm_device *dev,
  98. struct drm_file *file_priv);
  99. void radeon_driver_preclose_kms(struct drm_device *dev,
  100. struct drm_file *file_priv);
  101. int radeon_suspend_kms(struct drm_device *dev, bool suspend, bool fbcon);
  102. int radeon_resume_kms(struct drm_device *dev, bool resume, bool fbcon);
  103. u32 radeon_get_vblank_counter_kms(struct drm_device *dev, unsigned int pipe);
  104. int radeon_enable_vblank_kms(struct drm_device *dev, unsigned int pipe);
  105. void radeon_disable_vblank_kms(struct drm_device *dev, unsigned int pipe);
  106. int radeon_get_vblank_timestamp_kms(struct drm_device *dev, unsigned int pipe,
  107. int *max_error,
  108. struct timeval *vblank_time,
  109. unsigned flags);
  110. void radeon_driver_irq_preinstall_kms(struct drm_device *dev);
  111. int radeon_driver_irq_postinstall_kms(struct drm_device *dev);
  112. void radeon_driver_irq_uninstall_kms(struct drm_device *dev);
  113. irqreturn_t radeon_driver_irq_handler_kms(int irq, void *arg);
  114. void radeon_gem_object_free(struct drm_gem_object *obj);
  115. int radeon_gem_object_open(struct drm_gem_object *obj,
  116. struct drm_file *file_priv);
  117. void radeon_gem_object_close(struct drm_gem_object *obj,
  118. struct drm_file *file_priv);
  119. struct dma_buf *radeon_gem_prime_export(struct drm_device *dev,
  120. struct drm_gem_object *gobj,
  121. int flags);
  122. extern int radeon_get_crtc_scanoutpos(struct drm_device *dev, unsigned int crtc,
  123. unsigned int flags, int *vpos, int *hpos,
  124. ktime_t *stime, ktime_t *etime,
  125. const struct drm_display_mode *mode);
  126. extern bool radeon_is_px(struct drm_device *dev);
  127. extern const struct drm_ioctl_desc radeon_ioctls_kms[];
  128. extern int radeon_max_kms_ioctl;
  129. int radeon_mmap(struct file *filp, struct vm_area_struct *vma);
  130. int radeon_mode_dumb_mmap(struct drm_file *filp,
  131. struct drm_device *dev,
  132. uint32_t handle, uint64_t *offset_p);
  133. int radeon_mode_dumb_create(struct drm_file *file_priv,
  134. struct drm_device *dev,
  135. struct drm_mode_create_dumb *args);
  136. struct sg_table *radeon_gem_prime_get_sg_table(struct drm_gem_object *obj);
  137. struct drm_gem_object *radeon_gem_prime_import_sg_table(struct drm_device *dev,
  138. struct dma_buf_attachment *,
  139. struct sg_table *sg);
  140. int radeon_gem_prime_pin(struct drm_gem_object *obj);
  141. void radeon_gem_prime_unpin(struct drm_gem_object *obj);
  142. struct reservation_object *radeon_gem_prime_res_obj(struct drm_gem_object *);
  143. void *radeon_gem_prime_vmap(struct drm_gem_object *obj);
  144. void radeon_gem_prime_vunmap(struct drm_gem_object *obj, void *vaddr);
  145. extern long radeon_kms_compat_ioctl(struct file *filp, unsigned int cmd,
  146. unsigned long arg);
  147. #if defined(CONFIG_DEBUG_FS)
  148. int radeon_debugfs_init(struct drm_minor *minor);
  149. void radeon_debugfs_cleanup(struct drm_minor *minor);
  150. #endif
  151. /* atpx handler */
  152. #if defined(CONFIG_VGA_SWITCHEROO)
  153. void radeon_register_atpx_handler(void);
  154. void radeon_unregister_atpx_handler(void);
  155. #else
  156. static inline void radeon_register_atpx_handler(void) {}
  157. static inline void radeon_unregister_atpx_handler(void) {}
  158. #endif
  159. int radeon_no_wb;
  160. int radeon_modeset = -1;
  161. int radeon_dynclks = -1;
  162. int radeon_r4xx_atom = 0;
  163. int radeon_agpmode = 0;
  164. int radeon_vram_limit = 0;
  165. int radeon_gart_size = -1; /* auto */
  166. int radeon_benchmarking = 0;
  167. int radeon_testing = 0;
  168. int radeon_connector_table = 0;
  169. int radeon_tv = 1;
  170. int radeon_audio = -1;
  171. int radeon_disp_priority = 0;
  172. int radeon_hw_i2c = 0;
  173. int radeon_pcie_gen2 = -1;
  174. int radeon_msi = -1;
  175. int radeon_lockup_timeout = 10000;
  176. int radeon_fastfb = 0;
  177. int radeon_dpm = -1;
  178. int radeon_aspm = -1;
  179. int radeon_runtime_pm = -1;
  180. int radeon_hard_reset = 0;
  181. int radeon_vm_size = 8;
  182. int radeon_vm_block_size = -1;
  183. int radeon_deep_color = 0;
  184. int radeon_use_pflipirq = 2;
  185. int radeon_bapm = -1;
  186. int radeon_backlight = -1;
  187. int radeon_auxch = -1;
  188. int radeon_mst = 0;
  189. MODULE_PARM_DESC(no_wb, "Disable AGP writeback for scratch registers");
  190. module_param_named(no_wb, radeon_no_wb, int, 0444);
  191. MODULE_PARM_DESC(modeset, "Disable/Enable modesetting");
  192. module_param_named(modeset, radeon_modeset, int, 0400);
  193. MODULE_PARM_DESC(dynclks, "Disable/Enable dynamic clocks");
  194. module_param_named(dynclks, radeon_dynclks, int, 0444);
  195. MODULE_PARM_DESC(r4xx_atom, "Enable ATOMBIOS modesetting for R4xx");
  196. module_param_named(r4xx_atom, radeon_r4xx_atom, int, 0444);
  197. MODULE_PARM_DESC(vramlimit, "Restrict VRAM for testing, in megabytes");
  198. module_param_named(vramlimit, radeon_vram_limit, int, 0600);
  199. MODULE_PARM_DESC(agpmode, "AGP Mode (-1 == PCI)");
  200. module_param_named(agpmode, radeon_agpmode, int, 0444);
  201. MODULE_PARM_DESC(gartsize, "Size of PCIE/IGP gart to setup in megabytes (32, 64, etc., -1 = auto)");
  202. module_param_named(gartsize, radeon_gart_size, int, 0600);
  203. MODULE_PARM_DESC(benchmark, "Run benchmark");
  204. module_param_named(benchmark, radeon_benchmarking, int, 0444);
  205. MODULE_PARM_DESC(test, "Run tests");
  206. module_param_named(test, radeon_testing, int, 0444);
  207. MODULE_PARM_DESC(connector_table, "Force connector table");
  208. module_param_named(connector_table, radeon_connector_table, int, 0444);
  209. MODULE_PARM_DESC(tv, "TV enable (0 = disable)");
  210. module_param_named(tv, radeon_tv, int, 0444);
  211. MODULE_PARM_DESC(audio, "Audio enable (-1 = auto, 0 = disable, 1 = enable)");
  212. module_param_named(audio, radeon_audio, int, 0444);
  213. MODULE_PARM_DESC(disp_priority, "Display Priority (0 = auto, 1 = normal, 2 = high)");
  214. module_param_named(disp_priority, radeon_disp_priority, int, 0444);
  215. MODULE_PARM_DESC(hw_i2c, "hw i2c engine enable (0 = disable)");
  216. module_param_named(hw_i2c, radeon_hw_i2c, int, 0444);
  217. MODULE_PARM_DESC(pcie_gen2, "PCIE Gen2 mode (-1 = auto, 0 = disable, 1 = enable)");
  218. module_param_named(pcie_gen2, radeon_pcie_gen2, int, 0444);
  219. MODULE_PARM_DESC(msi, "MSI support (1 = enable, 0 = disable, -1 = auto)");
  220. module_param_named(msi, radeon_msi, int, 0444);
  221. MODULE_PARM_DESC(lockup_timeout, "GPU lockup timeout in ms (default 10000 = 10 seconds, 0 = disable)");
  222. module_param_named(lockup_timeout, radeon_lockup_timeout, int, 0444);
  223. MODULE_PARM_DESC(fastfb, "Direct FB access for IGP chips (0 = disable, 1 = enable)");
  224. module_param_named(fastfb, radeon_fastfb, int, 0444);
  225. MODULE_PARM_DESC(dpm, "DPM support (1 = enable, 0 = disable, -1 = auto)");
  226. module_param_named(dpm, radeon_dpm, int, 0444);
  227. MODULE_PARM_DESC(aspm, "ASPM support (1 = enable, 0 = disable, -1 = auto)");
  228. module_param_named(aspm, radeon_aspm, int, 0444);
  229. MODULE_PARM_DESC(runpm, "PX runtime pm (1 = force enable, 0 = disable, -1 = PX only default)");
  230. module_param_named(runpm, radeon_runtime_pm, int, 0444);
  231. MODULE_PARM_DESC(hard_reset, "PCI config reset (1 = force enable, 0 = disable (default))");
  232. module_param_named(hard_reset, radeon_hard_reset, int, 0444);
  233. MODULE_PARM_DESC(vm_size, "VM address space size in gigabytes (default 4GB)");
  234. module_param_named(vm_size, radeon_vm_size, int, 0444);
  235. MODULE_PARM_DESC(vm_block_size, "VM page table size in bits (default depending on vm_size)");
  236. module_param_named(vm_block_size, radeon_vm_block_size, int, 0444);
  237. MODULE_PARM_DESC(deep_color, "Deep Color support (1 = enable, 0 = disable (default))");
  238. module_param_named(deep_color, radeon_deep_color, int, 0444);
  239. MODULE_PARM_DESC(use_pflipirq, "Pflip irqs for pageflip completion (0 = disable, 1 = as fallback, 2 = exclusive (default))");
  240. module_param_named(use_pflipirq, radeon_use_pflipirq, int, 0444);
  241. MODULE_PARM_DESC(bapm, "BAPM support (1 = enable, 0 = disable, -1 = auto)");
  242. module_param_named(bapm, radeon_bapm, int, 0444);
  243. MODULE_PARM_DESC(backlight, "backlight support (1 = enable, 0 = disable, -1 = auto)");
  244. module_param_named(backlight, radeon_backlight, int, 0444);
  245. MODULE_PARM_DESC(auxch, "Use native auxch experimental support (1 = enable, 0 = disable, -1 = auto)");
  246. module_param_named(auxch, radeon_auxch, int, 0444);
  247. MODULE_PARM_DESC(mst, "DisplayPort MST experimental support (1 = enable, 0 = disable)");
  248. module_param_named(mst, radeon_mst, int, 0444);
  249. static struct pci_device_id pciidlist[] = {
  250. radeon_PCI_IDS
  251. };
  252. MODULE_DEVICE_TABLE(pci, pciidlist);
  253. #ifdef CONFIG_DRM_RADEON_UMS
  254. static int radeon_suspend(struct drm_device *dev, pm_message_t state)
  255. {
  256. drm_radeon_private_t *dev_priv = dev->dev_private;
  257. if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
  258. return 0;
  259. /* Disable *all* interrupts */
  260. if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RS600)
  261. RADEON_WRITE(R500_DxMODE_INT_MASK, 0);
  262. RADEON_WRITE(RADEON_GEN_INT_CNTL, 0);
  263. return 0;
  264. }
  265. static int radeon_resume(struct drm_device *dev)
  266. {
  267. drm_radeon_private_t *dev_priv = dev->dev_private;
  268. if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_R600)
  269. return 0;
  270. /* Restore interrupt registers */
  271. if ((dev_priv->flags & RADEON_FAMILY_MASK) >= CHIP_RS600)
  272. RADEON_WRITE(R500_DxMODE_INT_MASK, dev_priv->r500_disp_irq_reg);
  273. RADEON_WRITE(RADEON_GEN_INT_CNTL, dev_priv->irq_enable_reg);
  274. return 0;
  275. }
  276. static const struct file_operations radeon_driver_old_fops = {
  277. .owner = THIS_MODULE,
  278. .open = drm_open,
  279. .release = drm_release,
  280. .unlocked_ioctl = drm_ioctl,
  281. .mmap = drm_legacy_mmap,
  282. .poll = drm_poll,
  283. .read = drm_read,
  284. #ifdef CONFIG_COMPAT
  285. .compat_ioctl = radeon_compat_ioctl,
  286. #endif
  287. .llseek = noop_llseek,
  288. };
  289. static struct drm_driver driver_old = {
  290. .driver_features =
  291. DRIVER_USE_AGP | DRIVER_PCI_DMA | DRIVER_SG |
  292. DRIVER_HAVE_IRQ | DRIVER_HAVE_DMA | DRIVER_IRQ_SHARED,
  293. .dev_priv_size = sizeof(drm_radeon_buf_priv_t),
  294. .load = radeon_driver_load,
  295. .firstopen = radeon_driver_firstopen,
  296. .open = radeon_driver_open,
  297. .preclose = radeon_driver_preclose,
  298. .postclose = radeon_driver_postclose,
  299. .lastclose = radeon_driver_lastclose,
  300. .set_busid = drm_pci_set_busid,
  301. .unload = radeon_driver_unload,
  302. .suspend = radeon_suspend,
  303. .resume = radeon_resume,
  304. .get_vblank_counter = radeon_get_vblank_counter,
  305. .enable_vblank = radeon_enable_vblank,
  306. .disable_vblank = radeon_disable_vblank,
  307. .master_create = radeon_master_create,
  308. .master_destroy = radeon_master_destroy,
  309. .irq_preinstall = radeon_driver_irq_preinstall,
  310. .irq_postinstall = radeon_driver_irq_postinstall,
  311. .irq_uninstall = radeon_driver_irq_uninstall,
  312. .irq_handler = radeon_driver_irq_handler,
  313. .ioctls = radeon_ioctls,
  314. .dma_ioctl = radeon_cp_buffers,
  315. .fops = &radeon_driver_old_fops,
  316. .name = DRIVER_NAME,
  317. .desc = DRIVER_DESC,
  318. .date = DRIVER_DATE,
  319. .major = DRIVER_MAJOR,
  320. .minor = DRIVER_MINOR,
  321. .patchlevel = DRIVER_PATCHLEVEL,
  322. };
  323. #endif
  324. static struct drm_driver kms_driver;
  325. static int radeon_kick_out_firmware_fb(struct pci_dev *pdev)
  326. {
  327. struct apertures_struct *ap;
  328. bool primary = false;
  329. ap = alloc_apertures(1);
  330. if (!ap)
  331. return -ENOMEM;
  332. ap->ranges[0].base = pci_resource_start(pdev, 0);
  333. ap->ranges[0].size = pci_resource_len(pdev, 0);
  334. #ifdef CONFIG_X86
  335. primary = pdev->resource[PCI_ROM_RESOURCE].flags & IORESOURCE_ROM_SHADOW;
  336. #endif
  337. remove_conflicting_framebuffers(ap, "radeondrmfb", primary);
  338. kfree(ap);
  339. return 0;
  340. }
  341. static int radeon_pci_probe(struct pci_dev *pdev,
  342. const struct pci_device_id *ent)
  343. {
  344. int ret;
  345. /* Get rid of things like offb */
  346. ret = radeon_kick_out_firmware_fb(pdev);
  347. if (ret)
  348. return ret;
  349. return drm_get_pci_dev(pdev, ent, &kms_driver);
  350. }
  351. static void
  352. radeon_pci_remove(struct pci_dev *pdev)
  353. {
  354. struct drm_device *dev = pci_get_drvdata(pdev);
  355. drm_put_dev(dev);
  356. }
  357. static int radeon_pmops_suspend(struct device *dev)
  358. {
  359. struct pci_dev *pdev = to_pci_dev(dev);
  360. struct drm_device *drm_dev = pci_get_drvdata(pdev);
  361. return radeon_suspend_kms(drm_dev, true, true);
  362. }
  363. static int radeon_pmops_resume(struct device *dev)
  364. {
  365. struct pci_dev *pdev = to_pci_dev(dev);
  366. struct drm_device *drm_dev = pci_get_drvdata(pdev);
  367. return radeon_resume_kms(drm_dev, true, true);
  368. }
  369. static int radeon_pmops_freeze(struct device *dev)
  370. {
  371. struct pci_dev *pdev = to_pci_dev(dev);
  372. struct drm_device *drm_dev = pci_get_drvdata(pdev);
  373. return radeon_suspend_kms(drm_dev, false, true);
  374. }
  375. static int radeon_pmops_thaw(struct device *dev)
  376. {
  377. struct pci_dev *pdev = to_pci_dev(dev);
  378. struct drm_device *drm_dev = pci_get_drvdata(pdev);
  379. return radeon_resume_kms(drm_dev, false, true);
  380. }
  381. static int radeon_pmops_runtime_suspend(struct device *dev)
  382. {
  383. struct pci_dev *pdev = to_pci_dev(dev);
  384. struct drm_device *drm_dev = pci_get_drvdata(pdev);
  385. int ret;
  386. if (!radeon_is_px(drm_dev)) {
  387. pm_runtime_forbid(dev);
  388. return -EBUSY;
  389. }
  390. drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
  391. drm_kms_helper_poll_disable(drm_dev);
  392. vga_switcheroo_set_dynamic_switch(pdev, VGA_SWITCHEROO_OFF);
  393. ret = radeon_suspend_kms(drm_dev, false, false);
  394. pci_save_state(pdev);
  395. pci_disable_device(pdev);
  396. pci_ignore_hotplug(pdev);
  397. pci_set_power_state(pdev, PCI_D3cold);
  398. drm_dev->switch_power_state = DRM_SWITCH_POWER_DYNAMIC_OFF;
  399. return 0;
  400. }
  401. static int radeon_pmops_runtime_resume(struct device *dev)
  402. {
  403. struct pci_dev *pdev = to_pci_dev(dev);
  404. struct drm_device *drm_dev = pci_get_drvdata(pdev);
  405. int ret;
  406. if (!radeon_is_px(drm_dev))
  407. return -EINVAL;
  408. drm_dev->switch_power_state = DRM_SWITCH_POWER_CHANGING;
  409. pci_set_power_state(pdev, PCI_D0);
  410. pci_restore_state(pdev);
  411. ret = pci_enable_device(pdev);
  412. if (ret)
  413. return ret;
  414. pci_set_master(pdev);
  415. ret = radeon_resume_kms(drm_dev, false, false);
  416. drm_kms_helper_poll_enable(drm_dev);
  417. vga_switcheroo_set_dynamic_switch(pdev, VGA_SWITCHEROO_ON);
  418. drm_dev->switch_power_state = DRM_SWITCH_POWER_ON;
  419. return 0;
  420. }
  421. static int radeon_pmops_runtime_idle(struct device *dev)
  422. {
  423. struct pci_dev *pdev = to_pci_dev(dev);
  424. struct drm_device *drm_dev = pci_get_drvdata(pdev);
  425. struct drm_crtc *crtc;
  426. if (!radeon_is_px(drm_dev)) {
  427. pm_runtime_forbid(dev);
  428. return -EBUSY;
  429. }
  430. list_for_each_entry(crtc, &drm_dev->mode_config.crtc_list, head) {
  431. if (crtc->enabled) {
  432. DRM_DEBUG_DRIVER("failing to power off - crtc active\n");
  433. return -EBUSY;
  434. }
  435. }
  436. pm_runtime_mark_last_busy(dev);
  437. pm_runtime_autosuspend(dev);
  438. /* we don't want the main rpm_idle to call suspend - we want to autosuspend */
  439. return 1;
  440. }
  441. long radeon_drm_ioctl(struct file *filp,
  442. unsigned int cmd, unsigned long arg)
  443. {
  444. struct drm_file *file_priv = filp->private_data;
  445. struct drm_device *dev;
  446. long ret;
  447. dev = file_priv->minor->dev;
  448. ret = pm_runtime_get_sync(dev->dev);
  449. if (ret < 0)
  450. return ret;
  451. ret = drm_ioctl(filp, cmd, arg);
  452. pm_runtime_mark_last_busy(dev->dev);
  453. pm_runtime_put_autosuspend(dev->dev);
  454. return ret;
  455. }
  456. static const struct dev_pm_ops radeon_pm_ops = {
  457. .suspend = radeon_pmops_suspend,
  458. .resume = radeon_pmops_resume,
  459. .freeze = radeon_pmops_freeze,
  460. .thaw = radeon_pmops_thaw,
  461. .poweroff = radeon_pmops_freeze,
  462. .restore = radeon_pmops_resume,
  463. .runtime_suspend = radeon_pmops_runtime_suspend,
  464. .runtime_resume = radeon_pmops_runtime_resume,
  465. .runtime_idle = radeon_pmops_runtime_idle,
  466. };
  467. static const struct file_operations radeon_driver_kms_fops = {
  468. .owner = THIS_MODULE,
  469. .open = drm_open,
  470. .release = drm_release,
  471. .unlocked_ioctl = radeon_drm_ioctl,
  472. .mmap = radeon_mmap,
  473. .poll = drm_poll,
  474. .read = drm_read,
  475. #ifdef CONFIG_COMPAT
  476. .compat_ioctl = radeon_kms_compat_ioctl,
  477. #endif
  478. };
  479. static struct drm_driver kms_driver = {
  480. .driver_features =
  481. DRIVER_USE_AGP |
  482. DRIVER_HAVE_IRQ | DRIVER_IRQ_SHARED | DRIVER_GEM |
  483. DRIVER_PRIME | DRIVER_RENDER,
  484. .load = radeon_driver_load_kms,
  485. .open = radeon_driver_open_kms,
  486. .preclose = radeon_driver_preclose_kms,
  487. .postclose = radeon_driver_postclose_kms,
  488. .lastclose = radeon_driver_lastclose_kms,
  489. .set_busid = drm_pci_set_busid,
  490. .unload = radeon_driver_unload_kms,
  491. .get_vblank_counter = radeon_get_vblank_counter_kms,
  492. .enable_vblank = radeon_enable_vblank_kms,
  493. .disable_vblank = radeon_disable_vblank_kms,
  494. .get_vblank_timestamp = radeon_get_vblank_timestamp_kms,
  495. .get_scanout_position = radeon_get_crtc_scanoutpos,
  496. #if defined(CONFIG_DEBUG_FS)
  497. .debugfs_init = radeon_debugfs_init,
  498. .debugfs_cleanup = radeon_debugfs_cleanup,
  499. #endif
  500. .irq_preinstall = radeon_driver_irq_preinstall_kms,
  501. .irq_postinstall = radeon_driver_irq_postinstall_kms,
  502. .irq_uninstall = radeon_driver_irq_uninstall_kms,
  503. .irq_handler = radeon_driver_irq_handler_kms,
  504. .ioctls = radeon_ioctls_kms,
  505. .gem_free_object = radeon_gem_object_free,
  506. .gem_open_object = radeon_gem_object_open,
  507. .gem_close_object = radeon_gem_object_close,
  508. .dumb_create = radeon_mode_dumb_create,
  509. .dumb_map_offset = radeon_mode_dumb_mmap,
  510. .dumb_destroy = drm_gem_dumb_destroy,
  511. .fops = &radeon_driver_kms_fops,
  512. .prime_handle_to_fd = drm_gem_prime_handle_to_fd,
  513. .prime_fd_to_handle = drm_gem_prime_fd_to_handle,
  514. .gem_prime_export = radeon_gem_prime_export,
  515. .gem_prime_import = drm_gem_prime_import,
  516. .gem_prime_pin = radeon_gem_prime_pin,
  517. .gem_prime_unpin = radeon_gem_prime_unpin,
  518. .gem_prime_res_obj = radeon_gem_prime_res_obj,
  519. .gem_prime_get_sg_table = radeon_gem_prime_get_sg_table,
  520. .gem_prime_import_sg_table = radeon_gem_prime_import_sg_table,
  521. .gem_prime_vmap = radeon_gem_prime_vmap,
  522. .gem_prime_vunmap = radeon_gem_prime_vunmap,
  523. .name = DRIVER_NAME,
  524. .desc = DRIVER_DESC,
  525. .date = DRIVER_DATE,
  526. .major = KMS_DRIVER_MAJOR,
  527. .minor = KMS_DRIVER_MINOR,
  528. .patchlevel = KMS_DRIVER_PATCHLEVEL,
  529. };
  530. static struct drm_driver *driver;
  531. static struct pci_driver *pdriver;
  532. #ifdef CONFIG_DRM_RADEON_UMS
  533. static struct pci_driver radeon_pci_driver = {
  534. .name = DRIVER_NAME,
  535. .id_table = pciidlist,
  536. };
  537. #endif
  538. static struct pci_driver radeon_kms_pci_driver = {
  539. .name = DRIVER_NAME,
  540. .id_table = pciidlist,
  541. .probe = radeon_pci_probe,
  542. .remove = radeon_pci_remove,
  543. .driver.pm = &radeon_pm_ops,
  544. };
  545. static int __init radeon_init(void)
  546. {
  547. #ifdef CONFIG_VGA_CONSOLE
  548. if (vgacon_text_force() && radeon_modeset == -1) {
  549. DRM_INFO("VGACON disable radeon kernel modesetting.\n");
  550. radeon_modeset = 0;
  551. }
  552. #endif
  553. /* set to modesetting by default if not nomodeset */
  554. if (radeon_modeset == -1)
  555. radeon_modeset = 1;
  556. if (radeon_modeset == 1) {
  557. DRM_INFO("radeon kernel modesetting enabled.\n");
  558. driver = &kms_driver;
  559. pdriver = &radeon_kms_pci_driver;
  560. driver->driver_features |= DRIVER_MODESET;
  561. driver->num_ioctls = radeon_max_kms_ioctl;
  562. radeon_register_atpx_handler();
  563. } else {
  564. #ifdef CONFIG_DRM_RADEON_UMS
  565. DRM_INFO("radeon userspace modesetting enabled.\n");
  566. driver = &driver_old;
  567. pdriver = &radeon_pci_driver;
  568. driver->driver_features &= ~DRIVER_MODESET;
  569. driver->num_ioctls = radeon_max_ioctl;
  570. #else
  571. DRM_ERROR("No UMS support in radeon module!\n");
  572. return -EINVAL;
  573. #endif
  574. }
  575. radeon_kfd_init();
  576. /* let modprobe override vga console setting */
  577. return drm_pci_init(driver, pdriver);
  578. }
  579. static void __exit radeon_exit(void)
  580. {
  581. radeon_kfd_fini();
  582. drm_pci_exit(driver, pdriver);
  583. radeon_unregister_atpx_handler();
  584. }
  585. module_init(radeon_init);
  586. module_exit(radeon_exit);
  587. MODULE_AUTHOR(DRIVER_AUTHOR);
  588. MODULE_DESCRIPTION(DRIVER_DESC);
  589. MODULE_LICENSE("GPL and additional rights");