radeon_mode.h 30 KB

1234567891011121314151617181920212223242526272829303132333435363738394041424344454647484950515253545556575859606162636465666768697071727374757677787980818283848586878889909192939495969798991001011021031041051061071081091101111121131141151161171181191201211221231241251261271281291301311321331341351361371381391401411421431441451461471481491501511521531541551561571581591601611621631641651661671681691701711721731741751761771781791801811821831841851861871881891901911921931941951961971981992002012022032042052062072082092102112122132142152162172182192202212222232242252262272282292302312322332342352362372382392402412422432442452462472482492502512522532542552562572582592602612622632642652662672682692702712722732742752762772782792802812822832842852862872882892902912922932942952962972982993003013023033043053063073083093103113123133143153163173183193203213223233243253263273283293303313323333343353363373383393403413423433443453463473483493503513523533543553563573583593603613623633643653663673683693703713723733743753763773783793803813823833843853863873883893903913923933943953963973983994004014024034044054064074084094104114124134144154164174184194204214224234244254264274284294304314324334344354364374384394404414424434444454464474484494504514524534544554564574584594604614624634644654664674684694704714724734744754764774784794804814824834844854864874884894904914924934944954964974984995005015025035045055065075085095105115125135145155165175185195205215225235245255265275285295305315325335345355365375385395405415425435445455465475485495505515525535545555565575585595605615625635645655665675685695705715725735745755765775785795805815825835845855865875885895905915925935945955965975985996006016026036046056066076086096106116126136146156166176186196206216226236246256266276286296306316326336346356366376386396406416426436446456466476486496506516526536546556566576586596606616626636646656666676686696706716726736746756766776786796806816826836846856866876886896906916926936946956966976986997007017027037047057067077087097107117127137147157167177187197207217227237247257267277287297307317327337347357367377387397407417427437447457467477487497507517527537547557567577587597607617627637647657667677687697707717727737747757767777787797807817827837847857867877887897907917927937947957967977987998008018028038048058068078088098108118128138148158168178188198208218228238248258268278288298308318328338348358368378388398408418428438448458468478488498508518528538548558568578588598608618628638648658668678688698708718728738748758768778788798808818828838848858868878888898908918928938948958968978988999009019029039049059069079089099109119129139149159169179189199209219229239249259269279289299309319329339349359369379389399409419429439449459469479489499509519529539549559569579589599609619629639649659669679689699709719729739749759769779789799809819829839849859869879889899909919929939949959969979989991000100110021003100410051006100710081009101010111012101310141015
  1. /*
  2. * Copyright 2000 ATI Technologies Inc., Markham, Ontario, and
  3. * VA Linux Systems Inc., Fremont, California.
  4. * Copyright 2008 Red Hat Inc.
  5. *
  6. * Permission is hereby granted, free of charge, to any person obtaining a
  7. * copy of this software and associated documentation files (the "Software"),
  8. * to deal in the Software without restriction, including without limitation
  9. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  10. * and/or sell copies of the Software, and to permit persons to whom the
  11. * Software is furnished to do so, subject to the following conditions:
  12. *
  13. * The above copyright notice and this permission notice shall be included in
  14. * all copies or substantial portions of the Software.
  15. *
  16. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  17. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  18. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  19. * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  20. * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  21. * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  22. * OTHER DEALINGS IN THE SOFTWARE.
  23. *
  24. * Original Authors:
  25. * Kevin E. Martin, Rickard E. Faith, Alan Hourihane
  26. *
  27. * Kernel port Author: Dave Airlie
  28. */
  29. #ifndef RADEON_MODE_H
  30. #define RADEON_MODE_H
  31. #include <drm/drm_crtc.h>
  32. #include <drm/drm_edid.h>
  33. #include <drm/drm_dp_helper.h>
  34. #include <drm/drm_dp_mst_helper.h>
  35. #include <drm/drm_fixed.h>
  36. #include <drm/drm_crtc_helper.h>
  37. #include <linux/i2c.h>
  38. #include <linux/i2c-algo-bit.h>
  39. struct radeon_bo;
  40. struct radeon_device;
  41. #define to_radeon_crtc(x) container_of(x, struct radeon_crtc, base)
  42. #define to_radeon_connector(x) container_of(x, struct radeon_connector, base)
  43. #define to_radeon_encoder(x) container_of(x, struct radeon_encoder, base)
  44. #define to_radeon_framebuffer(x) container_of(x, struct radeon_framebuffer, base)
  45. #define RADEON_MAX_HPD_PINS 7
  46. #define RADEON_MAX_CRTCS 6
  47. #define RADEON_MAX_AFMT_BLOCKS 7
  48. enum radeon_rmx_type {
  49. RMX_OFF,
  50. RMX_FULL,
  51. RMX_CENTER,
  52. RMX_ASPECT
  53. };
  54. enum radeon_tv_std {
  55. TV_STD_NTSC,
  56. TV_STD_PAL,
  57. TV_STD_PAL_M,
  58. TV_STD_PAL_60,
  59. TV_STD_NTSC_J,
  60. TV_STD_SCART_PAL,
  61. TV_STD_SECAM,
  62. TV_STD_PAL_CN,
  63. TV_STD_PAL_N,
  64. };
  65. enum radeon_underscan_type {
  66. UNDERSCAN_OFF,
  67. UNDERSCAN_ON,
  68. UNDERSCAN_AUTO,
  69. };
  70. enum radeon_hpd_id {
  71. RADEON_HPD_1 = 0,
  72. RADEON_HPD_2,
  73. RADEON_HPD_3,
  74. RADEON_HPD_4,
  75. RADEON_HPD_5,
  76. RADEON_HPD_6,
  77. RADEON_HPD_NONE = 0xff,
  78. };
  79. enum radeon_output_csc {
  80. RADEON_OUTPUT_CSC_BYPASS = 0,
  81. RADEON_OUTPUT_CSC_TVRGB = 1,
  82. RADEON_OUTPUT_CSC_YCBCR601 = 2,
  83. RADEON_OUTPUT_CSC_YCBCR709 = 3,
  84. };
  85. #define RADEON_MAX_I2C_BUS 16
  86. /* radeon gpio-based i2c
  87. * 1. "mask" reg and bits
  88. * grabs the gpio pins for software use
  89. * 0=not held 1=held
  90. * 2. "a" reg and bits
  91. * output pin value
  92. * 0=low 1=high
  93. * 3. "en" reg and bits
  94. * sets the pin direction
  95. * 0=input 1=output
  96. * 4. "y" reg and bits
  97. * input pin value
  98. * 0=low 1=high
  99. */
  100. struct radeon_i2c_bus_rec {
  101. bool valid;
  102. /* id used by atom */
  103. uint8_t i2c_id;
  104. /* id used by atom */
  105. enum radeon_hpd_id hpd;
  106. /* can be used with hw i2c engine */
  107. bool hw_capable;
  108. /* uses multi-media i2c engine */
  109. bool mm_i2c;
  110. /* regs and bits */
  111. uint32_t mask_clk_reg;
  112. uint32_t mask_data_reg;
  113. uint32_t a_clk_reg;
  114. uint32_t a_data_reg;
  115. uint32_t en_clk_reg;
  116. uint32_t en_data_reg;
  117. uint32_t y_clk_reg;
  118. uint32_t y_data_reg;
  119. uint32_t mask_clk_mask;
  120. uint32_t mask_data_mask;
  121. uint32_t a_clk_mask;
  122. uint32_t a_data_mask;
  123. uint32_t en_clk_mask;
  124. uint32_t en_data_mask;
  125. uint32_t y_clk_mask;
  126. uint32_t y_data_mask;
  127. };
  128. struct radeon_tmds_pll {
  129. uint32_t freq;
  130. uint32_t value;
  131. };
  132. #define RADEON_MAX_BIOS_CONNECTOR 16
  133. /* pll flags */
  134. #define RADEON_PLL_USE_BIOS_DIVS (1 << 0)
  135. #define RADEON_PLL_NO_ODD_POST_DIV (1 << 1)
  136. #define RADEON_PLL_USE_REF_DIV (1 << 2)
  137. #define RADEON_PLL_LEGACY (1 << 3)
  138. #define RADEON_PLL_PREFER_LOW_REF_DIV (1 << 4)
  139. #define RADEON_PLL_PREFER_HIGH_REF_DIV (1 << 5)
  140. #define RADEON_PLL_PREFER_LOW_FB_DIV (1 << 6)
  141. #define RADEON_PLL_PREFER_HIGH_FB_DIV (1 << 7)
  142. #define RADEON_PLL_PREFER_LOW_POST_DIV (1 << 8)
  143. #define RADEON_PLL_PREFER_HIGH_POST_DIV (1 << 9)
  144. #define RADEON_PLL_USE_FRAC_FB_DIV (1 << 10)
  145. #define RADEON_PLL_PREFER_CLOSEST_LOWER (1 << 11)
  146. #define RADEON_PLL_USE_POST_DIV (1 << 12)
  147. #define RADEON_PLL_IS_LCD (1 << 13)
  148. #define RADEON_PLL_PREFER_MINM_OVER_MAXP (1 << 14)
  149. struct radeon_pll {
  150. /* reference frequency */
  151. uint32_t reference_freq;
  152. /* fixed dividers */
  153. uint32_t reference_div;
  154. uint32_t post_div;
  155. /* pll in/out limits */
  156. uint32_t pll_in_min;
  157. uint32_t pll_in_max;
  158. uint32_t pll_out_min;
  159. uint32_t pll_out_max;
  160. uint32_t lcd_pll_out_min;
  161. uint32_t lcd_pll_out_max;
  162. uint32_t best_vco;
  163. /* divider limits */
  164. uint32_t min_ref_div;
  165. uint32_t max_ref_div;
  166. uint32_t min_post_div;
  167. uint32_t max_post_div;
  168. uint32_t min_feedback_div;
  169. uint32_t max_feedback_div;
  170. uint32_t min_frac_feedback_div;
  171. uint32_t max_frac_feedback_div;
  172. /* flags for the current clock */
  173. uint32_t flags;
  174. /* pll id */
  175. uint32_t id;
  176. };
  177. struct radeon_i2c_chan {
  178. struct i2c_adapter adapter;
  179. struct drm_device *dev;
  180. struct i2c_algo_bit_data bit;
  181. struct radeon_i2c_bus_rec rec;
  182. struct drm_dp_aux aux;
  183. bool has_aux;
  184. struct mutex mutex;
  185. };
  186. /* mostly for macs, but really any system without connector tables */
  187. enum radeon_connector_table {
  188. CT_NONE = 0,
  189. CT_GENERIC,
  190. CT_IBOOK,
  191. CT_POWERBOOK_EXTERNAL,
  192. CT_POWERBOOK_INTERNAL,
  193. CT_POWERBOOK_VGA,
  194. CT_MINI_EXTERNAL,
  195. CT_MINI_INTERNAL,
  196. CT_IMAC_G5_ISIGHT,
  197. CT_EMAC,
  198. CT_RN50_POWER,
  199. CT_MAC_X800,
  200. CT_MAC_G5_9600,
  201. CT_SAM440EP,
  202. CT_MAC_G4_SILVER
  203. };
  204. enum radeon_dvo_chip {
  205. DVO_SIL164,
  206. DVO_SIL1178,
  207. };
  208. struct radeon_fbdev;
  209. struct radeon_afmt {
  210. bool enabled;
  211. int offset;
  212. bool last_buffer_filled_status;
  213. int id;
  214. };
  215. struct radeon_mode_info {
  216. struct atom_context *atom_context;
  217. struct card_info *atom_card_info;
  218. enum radeon_connector_table connector_table;
  219. bool mode_config_initialized;
  220. struct radeon_crtc *crtcs[RADEON_MAX_CRTCS];
  221. struct radeon_afmt *afmt[RADEON_MAX_AFMT_BLOCKS];
  222. /* DVI-I properties */
  223. struct drm_property *coherent_mode_property;
  224. /* DAC enable load detect */
  225. struct drm_property *load_detect_property;
  226. /* TV standard */
  227. struct drm_property *tv_std_property;
  228. /* legacy TMDS PLL detect */
  229. struct drm_property *tmds_pll_property;
  230. /* underscan */
  231. struct drm_property *underscan_property;
  232. struct drm_property *underscan_hborder_property;
  233. struct drm_property *underscan_vborder_property;
  234. /* audio */
  235. struct drm_property *audio_property;
  236. /* FMT dithering */
  237. struct drm_property *dither_property;
  238. /* Output CSC */
  239. struct drm_property *output_csc_property;
  240. /* hardcoded DFP edid from BIOS */
  241. struct edid *bios_hardcoded_edid;
  242. int bios_hardcoded_edid_size;
  243. /* pointer to fbdev info structure */
  244. struct radeon_fbdev *rfbdev;
  245. /* firmware flags */
  246. u16 firmware_flags;
  247. /* pointer to backlight encoder */
  248. struct radeon_encoder *bl_encoder;
  249. /* bitmask for active encoder frontends */
  250. uint32_t active_encoders;
  251. };
  252. #define RADEON_MAX_BL_LEVEL 0xFF
  253. #if defined(CONFIG_BACKLIGHT_CLASS_DEVICE) || defined(CONFIG_BACKLIGHT_CLASS_DEVICE_MODULE)
  254. struct radeon_backlight_privdata {
  255. struct radeon_encoder *encoder;
  256. uint8_t negative;
  257. };
  258. #endif
  259. #define MAX_H_CODE_TIMING_LEN 32
  260. #define MAX_V_CODE_TIMING_LEN 32
  261. /* need to store these as reading
  262. back code tables is excessive */
  263. struct radeon_tv_regs {
  264. uint32_t tv_uv_adr;
  265. uint32_t timing_cntl;
  266. uint32_t hrestart;
  267. uint32_t vrestart;
  268. uint32_t frestart;
  269. uint16_t h_code_timing[MAX_H_CODE_TIMING_LEN];
  270. uint16_t v_code_timing[MAX_V_CODE_TIMING_LEN];
  271. };
  272. struct radeon_atom_ss {
  273. uint16_t percentage;
  274. uint16_t percentage_divider;
  275. uint8_t type;
  276. uint16_t step;
  277. uint8_t delay;
  278. uint8_t range;
  279. uint8_t refdiv;
  280. /* asic_ss */
  281. uint16_t rate;
  282. uint16_t amount;
  283. };
  284. enum radeon_flip_status {
  285. RADEON_FLIP_NONE,
  286. RADEON_FLIP_PENDING,
  287. RADEON_FLIP_SUBMITTED
  288. };
  289. struct radeon_crtc {
  290. struct drm_crtc base;
  291. int crtc_id;
  292. u16 lut_r[256], lut_g[256], lut_b[256];
  293. bool enabled;
  294. bool can_tile;
  295. bool cursor_out_of_bounds;
  296. uint32_t crtc_offset;
  297. struct drm_gem_object *cursor_bo;
  298. uint64_t cursor_addr;
  299. int cursor_x;
  300. int cursor_y;
  301. int cursor_hot_x;
  302. int cursor_hot_y;
  303. int cursor_width;
  304. int cursor_height;
  305. int max_cursor_width;
  306. int max_cursor_height;
  307. uint32_t legacy_display_base_addr;
  308. enum radeon_rmx_type rmx_type;
  309. u8 h_border;
  310. u8 v_border;
  311. fixed20_12 vsc;
  312. fixed20_12 hsc;
  313. struct drm_display_mode native_mode;
  314. int pll_id;
  315. /* page flipping */
  316. struct workqueue_struct *flip_queue;
  317. struct radeon_flip_work *flip_work;
  318. enum radeon_flip_status flip_status;
  319. /* pll sharing */
  320. struct radeon_atom_ss ss;
  321. bool ss_enabled;
  322. u32 adjusted_clock;
  323. int bpc;
  324. u32 pll_reference_div;
  325. u32 pll_post_div;
  326. u32 pll_flags;
  327. struct drm_encoder *encoder;
  328. struct drm_connector *connector;
  329. /* for dpm */
  330. u32 line_time;
  331. u32 wm_low;
  332. u32 wm_high;
  333. u32 lb_vblank_lead_lines;
  334. struct drm_display_mode hw_mode;
  335. enum radeon_output_csc output_csc;
  336. };
  337. struct radeon_encoder_primary_dac {
  338. /* legacy primary dac */
  339. uint32_t ps2_pdac_adj;
  340. };
  341. struct radeon_encoder_lvds {
  342. /* legacy lvds */
  343. uint16_t panel_vcc_delay;
  344. uint8_t panel_pwr_delay;
  345. uint8_t panel_digon_delay;
  346. uint8_t panel_blon_delay;
  347. uint16_t panel_ref_divider;
  348. uint8_t panel_post_divider;
  349. uint16_t panel_fb_divider;
  350. bool use_bios_dividers;
  351. uint32_t lvds_gen_cntl;
  352. /* panel mode */
  353. struct drm_display_mode native_mode;
  354. struct backlight_device *bl_dev;
  355. int dpms_mode;
  356. uint8_t backlight_level;
  357. };
  358. struct radeon_encoder_tv_dac {
  359. /* legacy tv dac */
  360. uint32_t ps2_tvdac_adj;
  361. uint32_t ntsc_tvdac_adj;
  362. uint32_t pal_tvdac_adj;
  363. int h_pos;
  364. int v_pos;
  365. int h_size;
  366. int supported_tv_stds;
  367. bool tv_on;
  368. enum radeon_tv_std tv_std;
  369. struct radeon_tv_regs tv;
  370. };
  371. struct radeon_encoder_int_tmds {
  372. /* legacy int tmds */
  373. struct radeon_tmds_pll tmds_pll[4];
  374. };
  375. struct radeon_encoder_ext_tmds {
  376. /* tmds over dvo */
  377. struct radeon_i2c_chan *i2c_bus;
  378. uint8_t slave_addr;
  379. enum radeon_dvo_chip dvo_chip;
  380. };
  381. /* spread spectrum */
  382. struct radeon_encoder_atom_dig {
  383. bool linkb;
  384. /* atom dig */
  385. bool coherent_mode;
  386. int dig_encoder; /* -1 disabled, 0 DIGA, 1 DIGB, etc. */
  387. /* atom lvds/edp */
  388. uint32_t lcd_misc;
  389. uint16_t panel_pwr_delay;
  390. uint32_t lcd_ss_id;
  391. /* panel mode */
  392. struct drm_display_mode native_mode;
  393. struct backlight_device *bl_dev;
  394. int dpms_mode;
  395. uint8_t backlight_level;
  396. int panel_mode;
  397. struct radeon_afmt *afmt;
  398. struct r600_audio_pin *pin;
  399. int active_mst_links;
  400. };
  401. struct radeon_encoder_atom_dac {
  402. enum radeon_tv_std tv_std;
  403. };
  404. struct radeon_encoder_mst {
  405. int crtc;
  406. struct radeon_encoder *primary;
  407. struct radeon_connector *connector;
  408. struct drm_dp_mst_port *port;
  409. int pbn;
  410. int fe;
  411. bool fe_from_be;
  412. bool enc_active;
  413. };
  414. struct radeon_encoder {
  415. struct drm_encoder base;
  416. uint32_t encoder_enum;
  417. uint32_t encoder_id;
  418. uint32_t devices;
  419. uint32_t active_device;
  420. uint32_t flags;
  421. uint32_t pixel_clock;
  422. enum radeon_rmx_type rmx_type;
  423. enum radeon_underscan_type underscan_type;
  424. uint32_t underscan_hborder;
  425. uint32_t underscan_vborder;
  426. struct drm_display_mode native_mode;
  427. void *enc_priv;
  428. int audio_polling_active;
  429. bool is_ext_encoder;
  430. u16 caps;
  431. struct radeon_audio_funcs *audio;
  432. enum radeon_output_csc output_csc;
  433. bool can_mst;
  434. uint32_t offset;
  435. bool is_mst_encoder;
  436. /* front end for this mst encoder */
  437. };
  438. struct radeon_connector_atom_dig {
  439. uint32_t igp_lane_info;
  440. /* displayport */
  441. u8 dpcd[DP_RECEIVER_CAP_SIZE];
  442. u8 dp_sink_type;
  443. int dp_clock;
  444. int dp_lane_count;
  445. bool edp_on;
  446. bool is_mst;
  447. };
  448. struct radeon_gpio_rec {
  449. bool valid;
  450. u8 id;
  451. u32 reg;
  452. u32 mask;
  453. u32 shift;
  454. };
  455. struct radeon_hpd {
  456. enum radeon_hpd_id hpd;
  457. u8 plugged_state;
  458. struct radeon_gpio_rec gpio;
  459. };
  460. struct radeon_router {
  461. u32 router_id;
  462. struct radeon_i2c_bus_rec i2c_info;
  463. u8 i2c_addr;
  464. /* i2c mux */
  465. bool ddc_valid;
  466. u8 ddc_mux_type;
  467. u8 ddc_mux_control_pin;
  468. u8 ddc_mux_state;
  469. /* clock/data mux */
  470. bool cd_valid;
  471. u8 cd_mux_type;
  472. u8 cd_mux_control_pin;
  473. u8 cd_mux_state;
  474. };
  475. enum radeon_connector_audio {
  476. RADEON_AUDIO_DISABLE = 0,
  477. RADEON_AUDIO_ENABLE = 1,
  478. RADEON_AUDIO_AUTO = 2
  479. };
  480. enum radeon_connector_dither {
  481. RADEON_FMT_DITHER_DISABLE = 0,
  482. RADEON_FMT_DITHER_ENABLE = 1,
  483. };
  484. struct stream_attribs {
  485. uint16_t fe;
  486. uint16_t slots;
  487. };
  488. struct radeon_connector {
  489. struct drm_connector base;
  490. uint32_t connector_id;
  491. uint32_t devices;
  492. struct radeon_i2c_chan *ddc_bus;
  493. /* some systems have an hdmi and vga port with a shared ddc line */
  494. bool shared_ddc;
  495. bool use_digital;
  496. /* we need to mind the EDID between detect
  497. and get modes due to analog/digital/tvencoder */
  498. struct edid *edid;
  499. void *con_priv;
  500. bool dac_load_detect;
  501. bool detected_by_load; /* if the connection status was determined by load */
  502. bool detected_hpd_without_ddc; /* if an HPD signal was detected on DVI, but ddc probing failed */
  503. uint16_t connector_object_id;
  504. struct radeon_hpd hpd;
  505. struct radeon_router router;
  506. struct radeon_i2c_chan *router_bus;
  507. enum radeon_connector_audio audio;
  508. enum radeon_connector_dither dither;
  509. int pixelclock_for_modeset;
  510. bool is_mst_connector;
  511. struct radeon_connector *mst_port;
  512. struct drm_dp_mst_port *port;
  513. struct drm_dp_mst_topology_mgr mst_mgr;
  514. struct radeon_encoder *mst_encoder;
  515. struct stream_attribs cur_stream_attribs[6];
  516. int enabled_attribs;
  517. };
  518. struct radeon_framebuffer {
  519. struct drm_framebuffer base;
  520. struct drm_gem_object *obj;
  521. };
  522. #define ENCODER_MODE_IS_DP(em) (((em) == ATOM_ENCODER_MODE_DP) || \
  523. ((em) == ATOM_ENCODER_MODE_DP_MST))
  524. struct atom_clock_dividers {
  525. u32 post_div;
  526. union {
  527. struct {
  528. #ifdef __BIG_ENDIAN
  529. u32 reserved : 6;
  530. u32 whole_fb_div : 12;
  531. u32 frac_fb_div : 14;
  532. #else
  533. u32 frac_fb_div : 14;
  534. u32 whole_fb_div : 12;
  535. u32 reserved : 6;
  536. #endif
  537. };
  538. u32 fb_div;
  539. };
  540. u32 ref_div;
  541. bool enable_post_div;
  542. bool enable_dithen;
  543. u32 vco_mode;
  544. u32 real_clock;
  545. /* added for CI */
  546. u32 post_divider;
  547. u32 flags;
  548. };
  549. struct atom_mpll_param {
  550. union {
  551. struct {
  552. #ifdef __BIG_ENDIAN
  553. u32 reserved : 8;
  554. u32 clkfrac : 12;
  555. u32 clkf : 12;
  556. #else
  557. u32 clkf : 12;
  558. u32 clkfrac : 12;
  559. u32 reserved : 8;
  560. #endif
  561. };
  562. u32 fb_div;
  563. };
  564. u32 post_div;
  565. u32 bwcntl;
  566. u32 dll_speed;
  567. u32 vco_mode;
  568. u32 yclk_sel;
  569. u32 qdr;
  570. u32 half_rate;
  571. };
  572. #define MEM_TYPE_GDDR5 0x50
  573. #define MEM_TYPE_GDDR4 0x40
  574. #define MEM_TYPE_GDDR3 0x30
  575. #define MEM_TYPE_DDR2 0x20
  576. #define MEM_TYPE_GDDR1 0x10
  577. #define MEM_TYPE_DDR3 0xb0
  578. #define MEM_TYPE_MASK 0xf0
  579. struct atom_memory_info {
  580. u8 mem_vendor;
  581. u8 mem_type;
  582. };
  583. #define MAX_AC_TIMING_ENTRIES 16
  584. struct atom_memory_clock_range_table
  585. {
  586. u8 num_entries;
  587. u8 rsv[3];
  588. u32 mclk[MAX_AC_TIMING_ENTRIES];
  589. };
  590. #define VBIOS_MC_REGISTER_ARRAY_SIZE 32
  591. #define VBIOS_MAX_AC_TIMING_ENTRIES 20
  592. struct atom_mc_reg_entry {
  593. u32 mclk_max;
  594. u32 mc_data[VBIOS_MC_REGISTER_ARRAY_SIZE];
  595. };
  596. struct atom_mc_register_address {
  597. u16 s1;
  598. u8 pre_reg_data;
  599. };
  600. struct atom_mc_reg_table {
  601. u8 last;
  602. u8 num_entries;
  603. struct atom_mc_reg_entry mc_reg_table_entry[VBIOS_MAX_AC_TIMING_ENTRIES];
  604. struct atom_mc_register_address mc_reg_address[VBIOS_MC_REGISTER_ARRAY_SIZE];
  605. };
  606. #define MAX_VOLTAGE_ENTRIES 32
  607. struct atom_voltage_table_entry
  608. {
  609. u16 value;
  610. u32 smio_low;
  611. };
  612. struct atom_voltage_table
  613. {
  614. u32 count;
  615. u32 mask_low;
  616. u32 phase_delay;
  617. struct atom_voltage_table_entry entries[MAX_VOLTAGE_ENTRIES];
  618. };
  619. /* Driver internal use only flags of radeon_get_crtc_scanoutpos() */
  620. #define USE_REAL_VBLANKSTART (1 << 30)
  621. #define GET_DISTANCE_TO_VBLANKSTART (1 << 31)
  622. extern void
  623. radeon_add_atom_connector(struct drm_device *dev,
  624. uint32_t connector_id,
  625. uint32_t supported_device,
  626. int connector_type,
  627. struct radeon_i2c_bus_rec *i2c_bus,
  628. uint32_t igp_lane_info,
  629. uint16_t connector_object_id,
  630. struct radeon_hpd *hpd,
  631. struct radeon_router *router);
  632. extern void
  633. radeon_add_legacy_connector(struct drm_device *dev,
  634. uint32_t connector_id,
  635. uint32_t supported_device,
  636. int connector_type,
  637. struct radeon_i2c_bus_rec *i2c_bus,
  638. uint16_t connector_object_id,
  639. struct radeon_hpd *hpd);
  640. extern uint32_t
  641. radeon_get_encoder_enum(struct drm_device *dev, uint32_t supported_device,
  642. uint8_t dac);
  643. extern void radeon_link_encoder_connector(struct drm_device *dev);
  644. extern enum radeon_tv_std
  645. radeon_combios_get_tv_info(struct radeon_device *rdev);
  646. extern enum radeon_tv_std
  647. radeon_atombios_get_tv_info(struct radeon_device *rdev);
  648. extern void radeon_atombios_get_default_voltages(struct radeon_device *rdev,
  649. u16 *vddc, u16 *vddci, u16 *mvdd);
  650. extern void
  651. radeon_combios_connected_scratch_regs(struct drm_connector *connector,
  652. struct drm_encoder *encoder,
  653. bool connected);
  654. extern void
  655. radeon_atombios_connected_scratch_regs(struct drm_connector *connector,
  656. struct drm_encoder *encoder,
  657. bool connected);
  658. extern struct drm_connector *
  659. radeon_get_connector_for_encoder(struct drm_encoder *encoder);
  660. extern struct drm_connector *
  661. radeon_get_connector_for_encoder_init(struct drm_encoder *encoder);
  662. extern bool radeon_dig_monitor_is_duallink(struct drm_encoder *encoder,
  663. u32 pixel_clock);
  664. extern u16 radeon_encoder_get_dp_bridge_encoder_id(struct drm_encoder *encoder);
  665. extern u16 radeon_connector_encoder_get_dp_bridge_encoder_id(struct drm_connector *connector);
  666. extern bool radeon_connector_is_dp12_capable(struct drm_connector *connector);
  667. extern int radeon_get_monitor_bpc(struct drm_connector *connector);
  668. extern struct edid *radeon_connector_edid(struct drm_connector *connector);
  669. extern void radeon_connector_hotplug(struct drm_connector *connector);
  670. extern int radeon_dp_mode_valid_helper(struct drm_connector *connector,
  671. struct drm_display_mode *mode);
  672. extern void radeon_dp_set_link_config(struct drm_connector *connector,
  673. const struct drm_display_mode *mode);
  674. extern void radeon_dp_link_train(struct drm_encoder *encoder,
  675. struct drm_connector *connector);
  676. extern bool radeon_dp_needs_link_train(struct radeon_connector *radeon_connector);
  677. extern u8 radeon_dp_getsinktype(struct radeon_connector *radeon_connector);
  678. extern bool radeon_dp_getdpcd(struct radeon_connector *radeon_connector);
  679. extern int radeon_dp_get_panel_mode(struct drm_encoder *encoder,
  680. struct drm_connector *connector);
  681. extern int radeon_dp_get_dp_link_config(struct drm_connector *connector,
  682. const u8 *dpcd,
  683. unsigned pix_clock,
  684. unsigned *dp_lanes, unsigned *dp_rate);
  685. extern void radeon_dp_set_rx_power_state(struct drm_connector *connector,
  686. u8 power_state);
  687. extern void radeon_dp_aux_init(struct radeon_connector *radeon_connector);
  688. extern ssize_t
  689. radeon_dp_aux_transfer_native(struct drm_dp_aux *aux, struct drm_dp_aux_msg *msg);
  690. extern void atombios_dig_encoder_setup(struct drm_encoder *encoder, int action, int panel_mode);
  691. extern void atombios_dig_encoder_setup2(struct drm_encoder *encoder, int action, int panel_mode, int enc_override);
  692. extern void radeon_atom_encoder_init(struct radeon_device *rdev);
  693. extern void radeon_atom_disp_eng_pll_init(struct radeon_device *rdev);
  694. extern void atombios_dig_transmitter_setup(struct drm_encoder *encoder,
  695. int action, uint8_t lane_num,
  696. uint8_t lane_set);
  697. extern void atombios_dig_transmitter_setup2(struct drm_encoder *encoder,
  698. int action, uint8_t lane_num,
  699. uint8_t lane_set, int fe);
  700. extern void atombios_set_mst_encoder_crtc_source(struct drm_encoder *encoder,
  701. int fe);
  702. extern void radeon_atom_ext_encoder_setup_ddc(struct drm_encoder *encoder);
  703. extern struct drm_encoder *radeon_get_external_encoder(struct drm_encoder *encoder);
  704. void radeon_atom_copy_swap(u8 *dst, u8 *src, u8 num_bytes, bool to_le);
  705. extern void radeon_i2c_init(struct radeon_device *rdev);
  706. extern void radeon_i2c_fini(struct radeon_device *rdev);
  707. extern void radeon_combios_i2c_init(struct radeon_device *rdev);
  708. extern void radeon_atombios_i2c_init(struct radeon_device *rdev);
  709. extern void radeon_i2c_add(struct radeon_device *rdev,
  710. struct radeon_i2c_bus_rec *rec,
  711. const char *name);
  712. extern struct radeon_i2c_chan *radeon_i2c_lookup(struct radeon_device *rdev,
  713. struct radeon_i2c_bus_rec *i2c_bus);
  714. extern struct radeon_i2c_chan *radeon_i2c_create(struct drm_device *dev,
  715. struct radeon_i2c_bus_rec *rec,
  716. const char *name);
  717. extern void radeon_i2c_destroy(struct radeon_i2c_chan *i2c);
  718. extern void radeon_i2c_get_byte(struct radeon_i2c_chan *i2c_bus,
  719. u8 slave_addr,
  720. u8 addr,
  721. u8 *val);
  722. extern void radeon_i2c_put_byte(struct radeon_i2c_chan *i2c,
  723. u8 slave_addr,
  724. u8 addr,
  725. u8 val);
  726. extern void radeon_router_select_ddc_port(struct radeon_connector *radeon_connector);
  727. extern void radeon_router_select_cd_port(struct radeon_connector *radeon_connector);
  728. extern bool radeon_ddc_probe(struct radeon_connector *radeon_connector, bool use_aux);
  729. extern bool radeon_atombios_get_ppll_ss_info(struct radeon_device *rdev,
  730. struct radeon_atom_ss *ss,
  731. int id);
  732. extern bool radeon_atombios_get_asic_ss_info(struct radeon_device *rdev,
  733. struct radeon_atom_ss *ss,
  734. int id, u32 clock);
  735. extern struct radeon_gpio_rec radeon_atombios_lookup_gpio(struct radeon_device *rdev,
  736. u8 id);
  737. extern void radeon_compute_pll_legacy(struct radeon_pll *pll,
  738. uint64_t freq,
  739. uint32_t *dot_clock_p,
  740. uint32_t *fb_div_p,
  741. uint32_t *frac_fb_div_p,
  742. uint32_t *ref_div_p,
  743. uint32_t *post_div_p);
  744. extern void radeon_compute_pll_avivo(struct radeon_pll *pll,
  745. u32 freq,
  746. u32 *dot_clock_p,
  747. u32 *fb_div_p,
  748. u32 *frac_fb_div_p,
  749. u32 *ref_div_p,
  750. u32 *post_div_p);
  751. extern void radeon_setup_encoder_clones(struct drm_device *dev);
  752. struct drm_encoder *radeon_encoder_legacy_lvds_add(struct drm_device *dev, int bios_index);
  753. struct drm_encoder *radeon_encoder_legacy_primary_dac_add(struct drm_device *dev, int bios_index, int with_tv);
  754. struct drm_encoder *radeon_encoder_legacy_tv_dac_add(struct drm_device *dev, int bios_index, int with_tv);
  755. struct drm_encoder *radeon_encoder_legacy_tmds_int_add(struct drm_device *dev, int bios_index);
  756. struct drm_encoder *radeon_encoder_legacy_tmds_ext_add(struct drm_device *dev, int bios_index);
  757. extern void atombios_dvo_setup(struct drm_encoder *encoder, int action);
  758. extern void atombios_digital_setup(struct drm_encoder *encoder, int action);
  759. extern int atombios_get_encoder_mode(struct drm_encoder *encoder);
  760. extern bool atombios_set_edp_panel_power(struct drm_connector *connector, int action);
  761. extern void radeon_encoder_set_active_device(struct drm_encoder *encoder);
  762. extern bool radeon_encoder_is_digital(struct drm_encoder *encoder);
  763. extern void radeon_crtc_load_lut(struct drm_crtc *crtc);
  764. extern int atombios_crtc_set_base(struct drm_crtc *crtc, int x, int y,
  765. struct drm_framebuffer *old_fb);
  766. extern int atombios_crtc_set_base_atomic(struct drm_crtc *crtc,
  767. struct drm_framebuffer *fb,
  768. int x, int y,
  769. enum mode_set_atomic state);
  770. extern int atombios_crtc_mode_set(struct drm_crtc *crtc,
  771. struct drm_display_mode *mode,
  772. struct drm_display_mode *adjusted_mode,
  773. int x, int y,
  774. struct drm_framebuffer *old_fb);
  775. extern void atombios_crtc_dpms(struct drm_crtc *crtc, int mode);
  776. extern int radeon_crtc_set_base(struct drm_crtc *crtc, int x, int y,
  777. struct drm_framebuffer *old_fb);
  778. extern int radeon_crtc_set_base_atomic(struct drm_crtc *crtc,
  779. struct drm_framebuffer *fb,
  780. int x, int y,
  781. enum mode_set_atomic state);
  782. extern int radeon_crtc_do_set_base(struct drm_crtc *crtc,
  783. struct drm_framebuffer *fb,
  784. int x, int y, int atomic);
  785. extern int radeon_crtc_cursor_set2(struct drm_crtc *crtc,
  786. struct drm_file *file_priv,
  787. uint32_t handle,
  788. uint32_t width,
  789. uint32_t height,
  790. int32_t hot_x,
  791. int32_t hot_y);
  792. extern int radeon_crtc_cursor_move(struct drm_crtc *crtc,
  793. int x, int y);
  794. extern void radeon_cursor_reset(struct drm_crtc *crtc);
  795. extern int radeon_get_crtc_scanoutpos(struct drm_device *dev, unsigned int pipe,
  796. unsigned int flags, int *vpos, int *hpos,
  797. ktime_t *stime, ktime_t *etime,
  798. const struct drm_display_mode *mode);
  799. extern bool radeon_combios_check_hardcoded_edid(struct radeon_device *rdev);
  800. extern struct edid *
  801. radeon_bios_get_hardcoded_edid(struct radeon_device *rdev);
  802. extern bool radeon_atom_get_clock_info(struct drm_device *dev);
  803. extern bool radeon_combios_get_clock_info(struct drm_device *dev);
  804. extern struct radeon_encoder_atom_dig *
  805. radeon_atombios_get_lvds_info(struct radeon_encoder *encoder);
  806. extern bool radeon_atombios_get_tmds_info(struct radeon_encoder *encoder,
  807. struct radeon_encoder_int_tmds *tmds);
  808. extern bool radeon_legacy_get_tmds_info_from_combios(struct radeon_encoder *encoder,
  809. struct radeon_encoder_int_tmds *tmds);
  810. extern bool radeon_legacy_get_tmds_info_from_table(struct radeon_encoder *encoder,
  811. struct radeon_encoder_int_tmds *tmds);
  812. extern bool radeon_legacy_get_ext_tmds_info_from_combios(struct radeon_encoder *encoder,
  813. struct radeon_encoder_ext_tmds *tmds);
  814. extern bool radeon_legacy_get_ext_tmds_info_from_table(struct radeon_encoder *encoder,
  815. struct radeon_encoder_ext_tmds *tmds);
  816. extern struct radeon_encoder_primary_dac *
  817. radeon_atombios_get_primary_dac_info(struct radeon_encoder *encoder);
  818. extern struct radeon_encoder_tv_dac *
  819. radeon_atombios_get_tv_dac_info(struct radeon_encoder *encoder);
  820. extern struct radeon_encoder_lvds *
  821. radeon_combios_get_lvds_info(struct radeon_encoder *encoder);
  822. extern void radeon_combios_get_ext_tmds_info(struct radeon_encoder *encoder);
  823. extern struct radeon_encoder_tv_dac *
  824. radeon_combios_get_tv_dac_info(struct radeon_encoder *encoder);
  825. extern struct radeon_encoder_primary_dac *
  826. radeon_combios_get_primary_dac_info(struct radeon_encoder *encoder);
  827. extern bool radeon_combios_external_tmds_setup(struct drm_encoder *encoder);
  828. extern void radeon_external_tmds_setup(struct drm_encoder *encoder);
  829. extern void radeon_combios_output_lock(struct drm_encoder *encoder, bool lock);
  830. extern void radeon_combios_initialize_bios_scratch_regs(struct drm_device *dev);
  831. extern void radeon_atom_output_lock(struct drm_encoder *encoder, bool lock);
  832. extern void radeon_atom_initialize_bios_scratch_regs(struct drm_device *dev);
  833. extern void radeon_save_bios_scratch_regs(struct radeon_device *rdev);
  834. extern void radeon_restore_bios_scratch_regs(struct radeon_device *rdev);
  835. extern void
  836. radeon_atombios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc);
  837. extern void
  838. radeon_atombios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on);
  839. extern void
  840. radeon_combios_encoder_crtc_scratch_regs(struct drm_encoder *encoder, int crtc);
  841. extern void
  842. radeon_combios_encoder_dpms_scratch_regs(struct drm_encoder *encoder, bool on);
  843. extern void radeon_crtc_fb_gamma_set(struct drm_crtc *crtc, u16 red, u16 green,
  844. u16 blue, int regno);
  845. extern void radeon_crtc_fb_gamma_get(struct drm_crtc *crtc, u16 *red, u16 *green,
  846. u16 *blue, int regno);
  847. int radeon_framebuffer_init(struct drm_device *dev,
  848. struct radeon_framebuffer *rfb,
  849. struct drm_mode_fb_cmd2 *mode_cmd,
  850. struct drm_gem_object *obj);
  851. int radeonfb_remove(struct drm_device *dev, struct drm_framebuffer *fb);
  852. bool radeon_get_legacy_connector_info_from_bios(struct drm_device *dev);
  853. bool radeon_get_legacy_connector_info_from_table(struct drm_device *dev);
  854. void radeon_atombios_init_crtc(struct drm_device *dev,
  855. struct radeon_crtc *radeon_crtc);
  856. void radeon_legacy_init_crtc(struct drm_device *dev,
  857. struct radeon_crtc *radeon_crtc);
  858. void radeon_get_clock_info(struct drm_device *dev);
  859. extern bool radeon_get_atom_connector_info_from_object_table(struct drm_device *dev);
  860. extern bool radeon_get_atom_connector_info_from_supported_devices_table(struct drm_device *dev);
  861. void radeon_enc_destroy(struct drm_encoder *encoder);
  862. void radeon_copy_fb(struct drm_device *dev, struct drm_gem_object *dst_obj);
  863. void radeon_combios_asic_init(struct drm_device *dev);
  864. bool radeon_crtc_scaling_mode_fixup(struct drm_crtc *crtc,
  865. const struct drm_display_mode *mode,
  866. struct drm_display_mode *adjusted_mode);
  867. void radeon_panel_mode_fixup(struct drm_encoder *encoder,
  868. struct drm_display_mode *adjusted_mode);
  869. void atom_rv515_force_tv_scaler(struct radeon_device *rdev, struct radeon_crtc *radeon_crtc);
  870. /* legacy tv */
  871. void radeon_legacy_tv_adjust_crtc_reg(struct drm_encoder *encoder,
  872. uint32_t *h_total_disp, uint32_t *h_sync_strt_wid,
  873. uint32_t *v_total_disp, uint32_t *v_sync_strt_wid);
  874. void radeon_legacy_tv_adjust_pll1(struct drm_encoder *encoder,
  875. uint32_t *htotal_cntl, uint32_t *ppll_ref_div,
  876. uint32_t *ppll_div_3, uint32_t *pixclks_cntl);
  877. void radeon_legacy_tv_adjust_pll2(struct drm_encoder *encoder,
  878. uint32_t *htotal2_cntl, uint32_t *p2pll_ref_div,
  879. uint32_t *p2pll_div_0, uint32_t *pixclks_cntl);
  880. void radeon_legacy_tv_mode_set(struct drm_encoder *encoder,
  881. struct drm_display_mode *mode,
  882. struct drm_display_mode *adjusted_mode);
  883. /* fmt blocks */
  884. void avivo_program_fmt(struct drm_encoder *encoder);
  885. void dce3_program_fmt(struct drm_encoder *encoder);
  886. void dce4_program_fmt(struct drm_encoder *encoder);
  887. void dce8_program_fmt(struct drm_encoder *encoder);
  888. /* fbdev layer */
  889. int radeon_fbdev_init(struct radeon_device *rdev);
  890. void radeon_fbdev_fini(struct radeon_device *rdev);
  891. void radeon_fbdev_set_suspend(struct radeon_device *rdev, int state);
  892. bool radeon_fbdev_robj_is_fb(struct radeon_device *rdev, struct radeon_bo *robj);
  893. void radeon_fbdev_restore_mode(struct radeon_device *rdev);
  894. void radeon_fb_output_poll_changed(struct radeon_device *rdev);
  895. void radeon_crtc_handle_vblank(struct radeon_device *rdev, int crtc_id);
  896. void radeon_fb_add_connector(struct radeon_device *rdev, struct drm_connector *connector);
  897. void radeon_fb_remove_connector(struct radeon_device *rdev, struct drm_connector *connector);
  898. void radeon_crtc_handle_flip(struct radeon_device *rdev, int crtc_id);
  899. int radeon_align_pitch(struct radeon_device *rdev, int width, int bpp, bool tiled);
  900. /* mst */
  901. int radeon_dp_mst_init(struct radeon_connector *radeon_connector);
  902. int radeon_dp_mst_probe(struct radeon_connector *radeon_connector);
  903. int radeon_dp_mst_check_status(struct radeon_connector *radeon_connector);
  904. int radeon_mst_debugfs_init(struct radeon_device *rdev);
  905. void radeon_dp_mst_prepare_pll(struct drm_crtc *crtc, struct drm_display_mode *mode);
  906. void radeon_setup_mst_connector(struct drm_device *dev);
  907. int radeon_atom_pick_dig_encoder(struct drm_encoder *encoder, int fe_idx);
  908. void radeon_atom_release_dig_encoder(struct radeon_device *rdev, int enc_idx);
  909. #endif