radeon_test.c 15 KB

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  1. /*
  2. * Copyright 2009 VMware, Inc.
  3. *
  4. * Permission is hereby granted, free of charge, to any person obtaining a
  5. * copy of this software and associated documentation files (the "Software"),
  6. * to deal in the Software without restriction, including without limitation
  7. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8. * and/or sell copies of the Software, and to permit persons to whom the
  9. * Software is furnished to do so, subject to the following conditions:
  10. *
  11. * The above copyright notice and this permission notice shall be included in
  12. * all copies or substantial portions of the Software.
  13. *
  14. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  17. * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18. * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19. * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20. * OTHER DEALINGS IN THE SOFTWARE.
  21. *
  22. * Authors: Michel Dänzer
  23. */
  24. #include <drm/drmP.h>
  25. #include <drm/radeon_drm.h>
  26. #include "radeon_reg.h"
  27. #include "radeon.h"
  28. #define RADEON_TEST_COPY_BLIT 1
  29. #define RADEON_TEST_COPY_DMA 0
  30. /* Test BO GTT->VRAM and VRAM->GTT GPU copies across the whole GTT aperture */
  31. static void radeon_do_test_moves(struct radeon_device *rdev, int flag)
  32. {
  33. struct radeon_bo *vram_obj = NULL;
  34. struct radeon_bo **gtt_obj = NULL;
  35. uint64_t gtt_addr, vram_addr;
  36. unsigned n, size;
  37. int i, r, ring;
  38. switch (flag) {
  39. case RADEON_TEST_COPY_DMA:
  40. ring = radeon_copy_dma_ring_index(rdev);
  41. break;
  42. case RADEON_TEST_COPY_BLIT:
  43. ring = radeon_copy_blit_ring_index(rdev);
  44. break;
  45. default:
  46. DRM_ERROR("Unknown copy method\n");
  47. return;
  48. }
  49. size = 1024 * 1024;
  50. /* Number of tests =
  51. * (Total GTT - IB pool - writeback page - ring buffers) / test size
  52. */
  53. n = rdev->mc.gtt_size - rdev->gart_pin_size;
  54. n /= size;
  55. gtt_obj = kzalloc(n * sizeof(*gtt_obj), GFP_KERNEL);
  56. if (!gtt_obj) {
  57. DRM_ERROR("Failed to allocate %d pointers\n", n);
  58. r = 1;
  59. goto out_cleanup;
  60. }
  61. r = radeon_bo_create(rdev, size, PAGE_SIZE, true, RADEON_GEM_DOMAIN_VRAM,
  62. 0, NULL, NULL, &vram_obj);
  63. if (r) {
  64. DRM_ERROR("Failed to create VRAM object\n");
  65. goto out_cleanup;
  66. }
  67. r = radeon_bo_reserve(vram_obj, false);
  68. if (unlikely(r != 0))
  69. goto out_unref;
  70. r = radeon_bo_pin(vram_obj, RADEON_GEM_DOMAIN_VRAM, &vram_addr);
  71. if (r) {
  72. DRM_ERROR("Failed to pin VRAM object\n");
  73. goto out_unres;
  74. }
  75. for (i = 0; i < n; i++) {
  76. void *gtt_map, *vram_map;
  77. void **gtt_start, **gtt_end;
  78. void **vram_start, **vram_end;
  79. struct radeon_fence *fence = NULL;
  80. r = radeon_bo_create(rdev, size, PAGE_SIZE, true,
  81. RADEON_GEM_DOMAIN_GTT, 0, NULL, NULL,
  82. gtt_obj + i);
  83. if (r) {
  84. DRM_ERROR("Failed to create GTT object %d\n", i);
  85. goto out_lclean;
  86. }
  87. r = radeon_bo_reserve(gtt_obj[i], false);
  88. if (unlikely(r != 0))
  89. goto out_lclean_unref;
  90. r = radeon_bo_pin(gtt_obj[i], RADEON_GEM_DOMAIN_GTT, &gtt_addr);
  91. if (r) {
  92. DRM_ERROR("Failed to pin GTT object %d\n", i);
  93. goto out_lclean_unres;
  94. }
  95. r = radeon_bo_kmap(gtt_obj[i], &gtt_map);
  96. if (r) {
  97. DRM_ERROR("Failed to map GTT object %d\n", i);
  98. goto out_lclean_unpin;
  99. }
  100. for (gtt_start = gtt_map, gtt_end = gtt_map + size;
  101. gtt_start < gtt_end;
  102. gtt_start++)
  103. *gtt_start = gtt_start;
  104. radeon_bo_kunmap(gtt_obj[i]);
  105. if (ring == R600_RING_TYPE_DMA_INDEX)
  106. fence = radeon_copy_dma(rdev, gtt_addr, vram_addr,
  107. size / RADEON_GPU_PAGE_SIZE,
  108. vram_obj->tbo.resv);
  109. else
  110. fence = radeon_copy_blit(rdev, gtt_addr, vram_addr,
  111. size / RADEON_GPU_PAGE_SIZE,
  112. vram_obj->tbo.resv);
  113. if (IS_ERR(fence)) {
  114. DRM_ERROR("Failed GTT->VRAM copy %d\n", i);
  115. r = PTR_ERR(fence);
  116. goto out_lclean_unpin;
  117. }
  118. r = radeon_fence_wait(fence, false);
  119. if (r) {
  120. DRM_ERROR("Failed to wait for GTT->VRAM fence %d\n", i);
  121. goto out_lclean_unpin;
  122. }
  123. radeon_fence_unref(&fence);
  124. r = radeon_bo_kmap(vram_obj, &vram_map);
  125. if (r) {
  126. DRM_ERROR("Failed to map VRAM object after copy %d\n", i);
  127. goto out_lclean_unpin;
  128. }
  129. for (gtt_start = gtt_map, gtt_end = gtt_map + size,
  130. vram_start = vram_map, vram_end = vram_map + size;
  131. vram_start < vram_end;
  132. gtt_start++, vram_start++) {
  133. if (*vram_start != gtt_start) {
  134. DRM_ERROR("Incorrect GTT->VRAM copy %d: Got 0x%p, "
  135. "expected 0x%p (GTT/VRAM offset "
  136. "0x%16llx/0x%16llx)\n",
  137. i, *vram_start, gtt_start,
  138. (unsigned long long)
  139. (gtt_addr - rdev->mc.gtt_start +
  140. (void*)gtt_start - gtt_map),
  141. (unsigned long long)
  142. (vram_addr - rdev->mc.vram_start +
  143. (void*)gtt_start - gtt_map));
  144. radeon_bo_kunmap(vram_obj);
  145. goto out_lclean_unpin;
  146. }
  147. *vram_start = vram_start;
  148. }
  149. radeon_bo_kunmap(vram_obj);
  150. if (ring == R600_RING_TYPE_DMA_INDEX)
  151. fence = radeon_copy_dma(rdev, vram_addr, gtt_addr,
  152. size / RADEON_GPU_PAGE_SIZE,
  153. vram_obj->tbo.resv);
  154. else
  155. fence = radeon_copy_blit(rdev, vram_addr, gtt_addr,
  156. size / RADEON_GPU_PAGE_SIZE,
  157. vram_obj->tbo.resv);
  158. if (IS_ERR(fence)) {
  159. DRM_ERROR("Failed VRAM->GTT copy %d\n", i);
  160. r = PTR_ERR(fence);
  161. goto out_lclean_unpin;
  162. }
  163. r = radeon_fence_wait(fence, false);
  164. if (r) {
  165. DRM_ERROR("Failed to wait for VRAM->GTT fence %d\n", i);
  166. goto out_lclean_unpin;
  167. }
  168. radeon_fence_unref(&fence);
  169. r = radeon_bo_kmap(gtt_obj[i], &gtt_map);
  170. if (r) {
  171. DRM_ERROR("Failed to map GTT object after copy %d\n", i);
  172. goto out_lclean_unpin;
  173. }
  174. for (gtt_start = gtt_map, gtt_end = gtt_map + size,
  175. vram_start = vram_map, vram_end = vram_map + size;
  176. gtt_start < gtt_end;
  177. gtt_start++, vram_start++) {
  178. if (*gtt_start != vram_start) {
  179. DRM_ERROR("Incorrect VRAM->GTT copy %d: Got 0x%p, "
  180. "expected 0x%p (VRAM/GTT offset "
  181. "0x%16llx/0x%16llx)\n",
  182. i, *gtt_start, vram_start,
  183. (unsigned long long)
  184. (vram_addr - rdev->mc.vram_start +
  185. (void*)vram_start - vram_map),
  186. (unsigned long long)
  187. (gtt_addr - rdev->mc.gtt_start +
  188. (void*)vram_start - vram_map));
  189. radeon_bo_kunmap(gtt_obj[i]);
  190. goto out_lclean_unpin;
  191. }
  192. }
  193. radeon_bo_kunmap(gtt_obj[i]);
  194. DRM_INFO("Tested GTT->VRAM and VRAM->GTT copy for GTT offset 0x%llx\n",
  195. gtt_addr - rdev->mc.gtt_start);
  196. continue;
  197. out_lclean_unpin:
  198. radeon_bo_unpin(gtt_obj[i]);
  199. out_lclean_unres:
  200. radeon_bo_unreserve(gtt_obj[i]);
  201. out_lclean_unref:
  202. radeon_bo_unref(&gtt_obj[i]);
  203. out_lclean:
  204. for (--i; i >= 0; --i) {
  205. radeon_bo_unpin(gtt_obj[i]);
  206. radeon_bo_unreserve(gtt_obj[i]);
  207. radeon_bo_unref(&gtt_obj[i]);
  208. }
  209. if (fence && !IS_ERR(fence))
  210. radeon_fence_unref(&fence);
  211. break;
  212. }
  213. radeon_bo_unpin(vram_obj);
  214. out_unres:
  215. radeon_bo_unreserve(vram_obj);
  216. out_unref:
  217. radeon_bo_unref(&vram_obj);
  218. out_cleanup:
  219. kfree(gtt_obj);
  220. if (r) {
  221. printk(KERN_WARNING "Error while testing BO move.\n");
  222. }
  223. }
  224. void radeon_test_moves(struct radeon_device *rdev)
  225. {
  226. if (rdev->asic->copy.dma)
  227. radeon_do_test_moves(rdev, RADEON_TEST_COPY_DMA);
  228. if (rdev->asic->copy.blit)
  229. radeon_do_test_moves(rdev, RADEON_TEST_COPY_BLIT);
  230. }
  231. static int radeon_test_create_and_emit_fence(struct radeon_device *rdev,
  232. struct radeon_ring *ring,
  233. struct radeon_fence **fence)
  234. {
  235. uint32_t handle = ring->idx ^ 0xdeafbeef;
  236. int r;
  237. if (ring->idx == R600_RING_TYPE_UVD_INDEX) {
  238. r = radeon_uvd_get_create_msg(rdev, ring->idx, handle, NULL);
  239. if (r) {
  240. DRM_ERROR("Failed to get dummy create msg\n");
  241. return r;
  242. }
  243. r = radeon_uvd_get_destroy_msg(rdev, ring->idx, handle, fence);
  244. if (r) {
  245. DRM_ERROR("Failed to get dummy destroy msg\n");
  246. return r;
  247. }
  248. } else if (ring->idx == TN_RING_TYPE_VCE1_INDEX ||
  249. ring->idx == TN_RING_TYPE_VCE2_INDEX) {
  250. r = radeon_vce_get_create_msg(rdev, ring->idx, handle, NULL);
  251. if (r) {
  252. DRM_ERROR("Failed to get dummy create msg\n");
  253. return r;
  254. }
  255. r = radeon_vce_get_destroy_msg(rdev, ring->idx, handle, fence);
  256. if (r) {
  257. DRM_ERROR("Failed to get dummy destroy msg\n");
  258. return r;
  259. }
  260. } else {
  261. r = radeon_ring_lock(rdev, ring, 64);
  262. if (r) {
  263. DRM_ERROR("Failed to lock ring A %d\n", ring->idx);
  264. return r;
  265. }
  266. radeon_fence_emit(rdev, fence, ring->idx);
  267. radeon_ring_unlock_commit(rdev, ring, false);
  268. }
  269. return 0;
  270. }
  271. void radeon_test_ring_sync(struct radeon_device *rdev,
  272. struct radeon_ring *ringA,
  273. struct radeon_ring *ringB)
  274. {
  275. struct radeon_fence *fence1 = NULL, *fence2 = NULL;
  276. struct radeon_semaphore *semaphore = NULL;
  277. int r;
  278. r = radeon_semaphore_create(rdev, &semaphore);
  279. if (r) {
  280. DRM_ERROR("Failed to create semaphore\n");
  281. goto out_cleanup;
  282. }
  283. r = radeon_ring_lock(rdev, ringA, 64);
  284. if (r) {
  285. DRM_ERROR("Failed to lock ring A %d\n", ringA->idx);
  286. goto out_cleanup;
  287. }
  288. radeon_semaphore_emit_wait(rdev, ringA->idx, semaphore);
  289. radeon_ring_unlock_commit(rdev, ringA, false);
  290. r = radeon_test_create_and_emit_fence(rdev, ringA, &fence1);
  291. if (r)
  292. goto out_cleanup;
  293. r = radeon_ring_lock(rdev, ringA, 64);
  294. if (r) {
  295. DRM_ERROR("Failed to lock ring A %d\n", ringA->idx);
  296. goto out_cleanup;
  297. }
  298. radeon_semaphore_emit_wait(rdev, ringA->idx, semaphore);
  299. radeon_ring_unlock_commit(rdev, ringA, false);
  300. r = radeon_test_create_and_emit_fence(rdev, ringA, &fence2);
  301. if (r)
  302. goto out_cleanup;
  303. mdelay(1000);
  304. if (radeon_fence_signaled(fence1)) {
  305. DRM_ERROR("Fence 1 signaled without waiting for semaphore.\n");
  306. goto out_cleanup;
  307. }
  308. r = radeon_ring_lock(rdev, ringB, 64);
  309. if (r) {
  310. DRM_ERROR("Failed to lock ring B %p\n", ringB);
  311. goto out_cleanup;
  312. }
  313. radeon_semaphore_emit_signal(rdev, ringB->idx, semaphore);
  314. radeon_ring_unlock_commit(rdev, ringB, false);
  315. r = radeon_fence_wait(fence1, false);
  316. if (r) {
  317. DRM_ERROR("Failed to wait for sync fence 1\n");
  318. goto out_cleanup;
  319. }
  320. mdelay(1000);
  321. if (radeon_fence_signaled(fence2)) {
  322. DRM_ERROR("Fence 2 signaled without waiting for semaphore.\n");
  323. goto out_cleanup;
  324. }
  325. r = radeon_ring_lock(rdev, ringB, 64);
  326. if (r) {
  327. DRM_ERROR("Failed to lock ring B %p\n", ringB);
  328. goto out_cleanup;
  329. }
  330. radeon_semaphore_emit_signal(rdev, ringB->idx, semaphore);
  331. radeon_ring_unlock_commit(rdev, ringB, false);
  332. r = radeon_fence_wait(fence2, false);
  333. if (r) {
  334. DRM_ERROR("Failed to wait for sync fence 1\n");
  335. goto out_cleanup;
  336. }
  337. out_cleanup:
  338. radeon_semaphore_free(rdev, &semaphore, NULL);
  339. if (fence1)
  340. radeon_fence_unref(&fence1);
  341. if (fence2)
  342. radeon_fence_unref(&fence2);
  343. if (r)
  344. printk(KERN_WARNING "Error while testing ring sync (%d).\n", r);
  345. }
  346. static void radeon_test_ring_sync2(struct radeon_device *rdev,
  347. struct radeon_ring *ringA,
  348. struct radeon_ring *ringB,
  349. struct radeon_ring *ringC)
  350. {
  351. struct radeon_fence *fenceA = NULL, *fenceB = NULL;
  352. struct radeon_semaphore *semaphore = NULL;
  353. bool sigA, sigB;
  354. int i, r;
  355. r = radeon_semaphore_create(rdev, &semaphore);
  356. if (r) {
  357. DRM_ERROR("Failed to create semaphore\n");
  358. goto out_cleanup;
  359. }
  360. r = radeon_ring_lock(rdev, ringA, 64);
  361. if (r) {
  362. DRM_ERROR("Failed to lock ring A %d\n", ringA->idx);
  363. goto out_cleanup;
  364. }
  365. radeon_semaphore_emit_wait(rdev, ringA->idx, semaphore);
  366. radeon_ring_unlock_commit(rdev, ringA, false);
  367. r = radeon_test_create_and_emit_fence(rdev, ringA, &fenceA);
  368. if (r)
  369. goto out_cleanup;
  370. r = radeon_ring_lock(rdev, ringB, 64);
  371. if (r) {
  372. DRM_ERROR("Failed to lock ring B %d\n", ringB->idx);
  373. goto out_cleanup;
  374. }
  375. radeon_semaphore_emit_wait(rdev, ringB->idx, semaphore);
  376. radeon_ring_unlock_commit(rdev, ringB, false);
  377. r = radeon_test_create_and_emit_fence(rdev, ringB, &fenceB);
  378. if (r)
  379. goto out_cleanup;
  380. mdelay(1000);
  381. if (radeon_fence_signaled(fenceA)) {
  382. DRM_ERROR("Fence A signaled without waiting for semaphore.\n");
  383. goto out_cleanup;
  384. }
  385. if (radeon_fence_signaled(fenceB)) {
  386. DRM_ERROR("Fence B signaled without waiting for semaphore.\n");
  387. goto out_cleanup;
  388. }
  389. r = radeon_ring_lock(rdev, ringC, 64);
  390. if (r) {
  391. DRM_ERROR("Failed to lock ring B %p\n", ringC);
  392. goto out_cleanup;
  393. }
  394. radeon_semaphore_emit_signal(rdev, ringC->idx, semaphore);
  395. radeon_ring_unlock_commit(rdev, ringC, false);
  396. for (i = 0; i < 30; ++i) {
  397. mdelay(100);
  398. sigA = radeon_fence_signaled(fenceA);
  399. sigB = radeon_fence_signaled(fenceB);
  400. if (sigA || sigB)
  401. break;
  402. }
  403. if (!sigA && !sigB) {
  404. DRM_ERROR("Neither fence A nor B has been signaled\n");
  405. goto out_cleanup;
  406. } else if (sigA && sigB) {
  407. DRM_ERROR("Both fence A and B has been signaled\n");
  408. goto out_cleanup;
  409. }
  410. DRM_INFO("Fence %c was first signaled\n", sigA ? 'A' : 'B');
  411. r = radeon_ring_lock(rdev, ringC, 64);
  412. if (r) {
  413. DRM_ERROR("Failed to lock ring B %p\n", ringC);
  414. goto out_cleanup;
  415. }
  416. radeon_semaphore_emit_signal(rdev, ringC->idx, semaphore);
  417. radeon_ring_unlock_commit(rdev, ringC, false);
  418. mdelay(1000);
  419. r = radeon_fence_wait(fenceA, false);
  420. if (r) {
  421. DRM_ERROR("Failed to wait for sync fence A\n");
  422. goto out_cleanup;
  423. }
  424. r = radeon_fence_wait(fenceB, false);
  425. if (r) {
  426. DRM_ERROR("Failed to wait for sync fence B\n");
  427. goto out_cleanup;
  428. }
  429. out_cleanup:
  430. radeon_semaphore_free(rdev, &semaphore, NULL);
  431. if (fenceA)
  432. radeon_fence_unref(&fenceA);
  433. if (fenceB)
  434. radeon_fence_unref(&fenceB);
  435. if (r)
  436. printk(KERN_WARNING "Error while testing ring sync (%d).\n", r);
  437. }
  438. static bool radeon_test_sync_possible(struct radeon_ring *ringA,
  439. struct radeon_ring *ringB)
  440. {
  441. if (ringA->idx == TN_RING_TYPE_VCE2_INDEX &&
  442. ringB->idx == TN_RING_TYPE_VCE1_INDEX)
  443. return false;
  444. return true;
  445. }
  446. void radeon_test_syncing(struct radeon_device *rdev)
  447. {
  448. int i, j, k;
  449. for (i = 1; i < RADEON_NUM_RINGS; ++i) {
  450. struct radeon_ring *ringA = &rdev->ring[i];
  451. if (!ringA->ready)
  452. continue;
  453. for (j = 0; j < i; ++j) {
  454. struct radeon_ring *ringB = &rdev->ring[j];
  455. if (!ringB->ready)
  456. continue;
  457. if (!radeon_test_sync_possible(ringA, ringB))
  458. continue;
  459. DRM_INFO("Testing syncing between rings %d and %d...\n", i, j);
  460. radeon_test_ring_sync(rdev, ringA, ringB);
  461. DRM_INFO("Testing syncing between rings %d and %d...\n", j, i);
  462. radeon_test_ring_sync(rdev, ringB, ringA);
  463. for (k = 0; k < j; ++k) {
  464. struct radeon_ring *ringC = &rdev->ring[k];
  465. if (!ringC->ready)
  466. continue;
  467. if (!radeon_test_sync_possible(ringA, ringC))
  468. continue;
  469. if (!radeon_test_sync_possible(ringB, ringC))
  470. continue;
  471. DRM_INFO("Testing syncing between rings %d, %d and %d...\n", i, j, k);
  472. radeon_test_ring_sync2(rdev, ringA, ringB, ringC);
  473. DRM_INFO("Testing syncing between rings %d, %d and %d...\n", i, k, j);
  474. radeon_test_ring_sync2(rdev, ringA, ringC, ringB);
  475. DRM_INFO("Testing syncing between rings %d, %d and %d...\n", j, i, k);
  476. radeon_test_ring_sync2(rdev, ringB, ringA, ringC);
  477. DRM_INFO("Testing syncing between rings %d, %d and %d...\n", j, k, i);
  478. radeon_test_ring_sync2(rdev, ringB, ringC, ringA);
  479. DRM_INFO("Testing syncing between rings %d, %d and %d...\n", k, i, j);
  480. radeon_test_ring_sync2(rdev, ringC, ringA, ringB);
  481. DRM_INFO("Testing syncing between rings %d, %d and %d...\n", k, j, i);
  482. radeon_test_ring_sync2(rdev, ringC, ringB, ringA);
  483. }
  484. }
  485. }
  486. }