radeon_ucode.h 8.0 KB

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  1. /*
  2. * Copyright 2012 Advanced Micro Devices, Inc.
  3. *
  4. * Permission is hereby granted, free of charge, to any person obtaining a
  5. * copy of this software and associated documentation files (the "Software"),
  6. * to deal in the Software without restriction, including without limitation
  7. * the rights to use, copy, modify, merge, publish, distribute, sublicense,
  8. * and/or sell copies of the Software, and to permit persons to whom the
  9. * Software is furnished to do so, subject to the following conditions:
  10. *
  11. * The above copyright notice and this permission notice shall be included in
  12. * all copies or substantial portions of the Software.
  13. *
  14. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  15. * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  16. * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
  17. * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
  18. * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
  19. * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
  20. * OTHER DEALINGS IN THE SOFTWARE.
  21. *
  22. */
  23. #ifndef __RADEON_UCODE_H__
  24. #define __RADEON_UCODE_H__
  25. /* CP */
  26. #define R600_PFP_UCODE_SIZE 576
  27. #define R600_PM4_UCODE_SIZE 1792
  28. #define R700_PFP_UCODE_SIZE 848
  29. #define R700_PM4_UCODE_SIZE 1360
  30. #define EVERGREEN_PFP_UCODE_SIZE 1120
  31. #define EVERGREEN_PM4_UCODE_SIZE 1376
  32. #define CAYMAN_PFP_UCODE_SIZE 2176
  33. #define CAYMAN_PM4_UCODE_SIZE 2176
  34. #define SI_PFP_UCODE_SIZE 2144
  35. #define SI_PM4_UCODE_SIZE 2144
  36. #define SI_CE_UCODE_SIZE 2144
  37. #define CIK_PFP_UCODE_SIZE 2144
  38. #define CIK_ME_UCODE_SIZE 2144
  39. #define CIK_CE_UCODE_SIZE 2144
  40. /* MEC */
  41. #define CIK_MEC_UCODE_SIZE 4192
  42. /* RLC */
  43. #define R600_RLC_UCODE_SIZE 768
  44. #define R700_RLC_UCODE_SIZE 1024
  45. #define EVERGREEN_RLC_UCODE_SIZE 768
  46. #define CAYMAN_RLC_UCODE_SIZE 1024
  47. #define ARUBA_RLC_UCODE_SIZE 1536
  48. #define SI_RLC_UCODE_SIZE 2048
  49. #define BONAIRE_RLC_UCODE_SIZE 2048
  50. #define KB_RLC_UCODE_SIZE 2560
  51. #define KV_RLC_UCODE_SIZE 2560
  52. #define ML_RLC_UCODE_SIZE 2560
  53. /* MC */
  54. #define BTC_MC_UCODE_SIZE 6024
  55. #define CAYMAN_MC_UCODE_SIZE 6037
  56. #define SI_MC_UCODE_SIZE 7769
  57. #define TAHITI_MC_UCODE_SIZE 7808
  58. #define PITCAIRN_MC_UCODE_SIZE 7775
  59. #define VERDE_MC_UCODE_SIZE 7875
  60. #define OLAND_MC_UCODE_SIZE 7863
  61. #define BONAIRE_MC_UCODE_SIZE 7866
  62. #define BONAIRE_MC2_UCODE_SIZE 7948
  63. #define HAWAII_MC_UCODE_SIZE 7933
  64. #define HAWAII_MC2_UCODE_SIZE 8091
  65. /* SDMA */
  66. #define CIK_SDMA_UCODE_SIZE 1050
  67. #define CIK_SDMA_UCODE_VERSION 64
  68. /* SMC */
  69. #define RV770_SMC_UCODE_START 0x0100
  70. #define RV770_SMC_UCODE_SIZE 0x410d
  71. #define RV770_SMC_INT_VECTOR_START 0xffc0
  72. #define RV770_SMC_INT_VECTOR_SIZE 0x0040
  73. #define RV730_SMC_UCODE_START 0x0100
  74. #define RV730_SMC_UCODE_SIZE 0x412c
  75. #define RV730_SMC_INT_VECTOR_START 0xffc0
  76. #define RV730_SMC_INT_VECTOR_SIZE 0x0040
  77. #define RV710_SMC_UCODE_START 0x0100
  78. #define RV710_SMC_UCODE_SIZE 0x3f1f
  79. #define RV710_SMC_INT_VECTOR_START 0xffc0
  80. #define RV710_SMC_INT_VECTOR_SIZE 0x0040
  81. #define RV740_SMC_UCODE_START 0x0100
  82. #define RV740_SMC_UCODE_SIZE 0x41c5
  83. #define RV740_SMC_INT_VECTOR_START 0xffc0
  84. #define RV740_SMC_INT_VECTOR_SIZE 0x0040
  85. #define CEDAR_SMC_UCODE_START 0x0100
  86. #define CEDAR_SMC_UCODE_SIZE 0x5d50
  87. #define CEDAR_SMC_INT_VECTOR_START 0xffc0
  88. #define CEDAR_SMC_INT_VECTOR_SIZE 0x0040
  89. #define REDWOOD_SMC_UCODE_START 0x0100
  90. #define REDWOOD_SMC_UCODE_SIZE 0x5f0a
  91. #define REDWOOD_SMC_INT_VECTOR_START 0xffc0
  92. #define REDWOOD_SMC_INT_VECTOR_SIZE 0x0040
  93. #define JUNIPER_SMC_UCODE_START 0x0100
  94. #define JUNIPER_SMC_UCODE_SIZE 0x5f1f
  95. #define JUNIPER_SMC_INT_VECTOR_START 0xffc0
  96. #define JUNIPER_SMC_INT_VECTOR_SIZE 0x0040
  97. #define CYPRESS_SMC_UCODE_START 0x0100
  98. #define CYPRESS_SMC_UCODE_SIZE 0x61f7
  99. #define CYPRESS_SMC_INT_VECTOR_START 0xffc0
  100. #define CYPRESS_SMC_INT_VECTOR_SIZE 0x0040
  101. #define BARTS_SMC_UCODE_START 0x0100
  102. #define BARTS_SMC_UCODE_SIZE 0x6107
  103. #define BARTS_SMC_INT_VECTOR_START 0xffc0
  104. #define BARTS_SMC_INT_VECTOR_SIZE 0x0040
  105. #define TURKS_SMC_UCODE_START 0x0100
  106. #define TURKS_SMC_UCODE_SIZE 0x605b
  107. #define TURKS_SMC_INT_VECTOR_START 0xffc0
  108. #define TURKS_SMC_INT_VECTOR_SIZE 0x0040
  109. #define CAICOS_SMC_UCODE_START 0x0100
  110. #define CAICOS_SMC_UCODE_SIZE 0x5fbd
  111. #define CAICOS_SMC_INT_VECTOR_START 0xffc0
  112. #define CAICOS_SMC_INT_VECTOR_SIZE 0x0040
  113. #define CAYMAN_SMC_UCODE_START 0x0100
  114. #define CAYMAN_SMC_UCODE_SIZE 0x79ec
  115. #define CAYMAN_SMC_INT_VECTOR_START 0xffc0
  116. #define CAYMAN_SMC_INT_VECTOR_SIZE 0x0040
  117. #define TAHITI_SMC_UCODE_START 0x10000
  118. #define TAHITI_SMC_UCODE_SIZE 0xf458
  119. #define PITCAIRN_SMC_UCODE_START 0x10000
  120. #define PITCAIRN_SMC_UCODE_SIZE 0xe9f4
  121. #define VERDE_SMC_UCODE_START 0x10000
  122. #define VERDE_SMC_UCODE_SIZE 0xebe4
  123. #define OLAND_SMC_UCODE_START 0x10000
  124. #define OLAND_SMC_UCODE_SIZE 0xe7b4
  125. #define HAINAN_SMC_UCODE_START 0x10000
  126. #define HAINAN_SMC_UCODE_SIZE 0xe67C
  127. #define BONAIRE_SMC_UCODE_START 0x20000
  128. #define BONAIRE_SMC_UCODE_SIZE 0x1FDEC
  129. #define HAWAII_SMC_UCODE_START 0x20000
  130. #define HAWAII_SMC_UCODE_SIZE 0x1FDEC
  131. struct common_firmware_header {
  132. uint32_t size_bytes; /* size of the entire header+image(s) in bytes */
  133. uint32_t header_size_bytes; /* size of just the header in bytes */
  134. uint16_t header_version_major; /* header version */
  135. uint16_t header_version_minor; /* header version */
  136. uint16_t ip_version_major; /* IP version */
  137. uint16_t ip_version_minor; /* IP version */
  138. uint32_t ucode_version;
  139. uint32_t ucode_size_bytes; /* size of ucode in bytes */
  140. uint32_t ucode_array_offset_bytes; /* payload offset from the start of the header */
  141. uint32_t crc32; /* crc32 checksum of the payload */
  142. };
  143. /* version_major=1, version_minor=0 */
  144. struct mc_firmware_header_v1_0 {
  145. struct common_firmware_header header;
  146. uint32_t io_debug_size_bytes; /* size of debug array in dwords */
  147. uint32_t io_debug_array_offset_bytes; /* payload offset from the start of the header */
  148. };
  149. /* version_major=1, version_minor=0 */
  150. struct smc_firmware_header_v1_0 {
  151. struct common_firmware_header header;
  152. uint32_t ucode_start_addr;
  153. };
  154. /* version_major=1, version_minor=0 */
  155. struct gfx_firmware_header_v1_0 {
  156. struct common_firmware_header header;
  157. uint32_t ucode_feature_version;
  158. uint32_t jt_offset; /* jt location */
  159. uint32_t jt_size; /* size of jt */
  160. };
  161. /* version_major=1, version_minor=0 */
  162. struct rlc_firmware_header_v1_0 {
  163. struct common_firmware_header header;
  164. uint32_t ucode_feature_version;
  165. uint32_t save_and_restore_offset;
  166. uint32_t clear_state_descriptor_offset;
  167. uint32_t avail_scratch_ram_locations;
  168. uint32_t master_pkt_description_offset;
  169. };
  170. /* version_major=1, version_minor=0 */
  171. struct sdma_firmware_header_v1_0 {
  172. struct common_firmware_header header;
  173. uint32_t ucode_feature_version;
  174. uint32_t ucode_change_version;
  175. uint32_t jt_offset; /* jt location */
  176. uint32_t jt_size; /* size of jt */
  177. };
  178. /* header is fixed size */
  179. union radeon_firmware_header {
  180. struct common_firmware_header common;
  181. struct mc_firmware_header_v1_0 mc;
  182. struct smc_firmware_header_v1_0 smc;
  183. struct gfx_firmware_header_v1_0 gfx;
  184. struct rlc_firmware_header_v1_0 rlc;
  185. struct sdma_firmware_header_v1_0 sdma;
  186. uint8_t raw[0x100];
  187. };
  188. void radeon_ucode_print_mc_hdr(const struct common_firmware_header *hdr);
  189. void radeon_ucode_print_smc_hdr(const struct common_firmware_header *hdr);
  190. void radeon_ucode_print_gfx_hdr(const struct common_firmware_header *hdr);
  191. void radeon_ucode_print_rlc_hdr(const struct common_firmware_header *hdr);
  192. void radeon_ucode_print_sdma_hdr(const struct common_firmware_header *hdr);
  193. int radeon_ucode_validate(const struct firmware *fw);
  194. #endif