rcar_du_lvdsenc.c 4.6 KB

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  1. /*
  2. * rcar_du_lvdsenc.c -- R-Car Display Unit LVDS Encoder
  3. *
  4. * Copyright (C) 2013-2014 Renesas Electronics Corporation
  5. *
  6. * Contact: Laurent Pinchart (laurent.pinchart@ideasonboard.com)
  7. *
  8. * This program is free software; you can redistribute it and/or modify
  9. * it under the terms of the GNU General Public License as published by
  10. * the Free Software Foundation; either version 2 of the License, or
  11. * (at your option) any later version.
  12. */
  13. #include <linux/clk.h>
  14. #include <linux/delay.h>
  15. #include <linux/io.h>
  16. #include <linux/platform_device.h>
  17. #include <linux/slab.h>
  18. #include "rcar_du_drv.h"
  19. #include "rcar_du_encoder.h"
  20. #include "rcar_du_lvdsenc.h"
  21. #include "rcar_lvds_regs.h"
  22. struct rcar_du_lvdsenc {
  23. struct rcar_du_device *dev;
  24. unsigned int index;
  25. void __iomem *mmio;
  26. struct clk *clock;
  27. bool enabled;
  28. enum rcar_lvds_input input;
  29. };
  30. static void rcar_lvds_write(struct rcar_du_lvdsenc *lvds, u32 reg, u32 data)
  31. {
  32. iowrite32(data, lvds->mmio + reg);
  33. }
  34. static int rcar_du_lvdsenc_start(struct rcar_du_lvdsenc *lvds,
  35. struct rcar_du_crtc *rcrtc)
  36. {
  37. const struct drm_display_mode *mode = &rcrtc->crtc.mode;
  38. unsigned int freq = mode->clock;
  39. u32 lvdcr0;
  40. u32 lvdhcr;
  41. u32 pllcr;
  42. int ret;
  43. if (lvds->enabled)
  44. return 0;
  45. ret = clk_prepare_enable(lvds->clock);
  46. if (ret < 0)
  47. return ret;
  48. /* PLL clock configuration */
  49. if (freq < 39000)
  50. pllcr = LVDPLLCR_CEEN | LVDPLLCR_COSEL | LVDPLLCR_PLLDLYCNT_38M;
  51. else if (freq < 61000)
  52. pllcr = LVDPLLCR_CEEN | LVDPLLCR_COSEL | LVDPLLCR_PLLDLYCNT_60M;
  53. else if (freq < 121000)
  54. pllcr = LVDPLLCR_CEEN | LVDPLLCR_COSEL | LVDPLLCR_PLLDLYCNT_121M;
  55. else
  56. pllcr = LVDPLLCR_PLLDLYCNT_150M;
  57. rcar_lvds_write(lvds, LVDPLLCR, pllcr);
  58. /* Hardcode the channels and control signals routing for now.
  59. *
  60. * HSYNC -> CTRL0
  61. * VSYNC -> CTRL1
  62. * DISP -> CTRL2
  63. * 0 -> CTRL3
  64. */
  65. rcar_lvds_write(lvds, LVDCTRCR, LVDCTRCR_CTR3SEL_ZERO |
  66. LVDCTRCR_CTR2SEL_DISP | LVDCTRCR_CTR1SEL_VSYNC |
  67. LVDCTRCR_CTR0SEL_HSYNC);
  68. if (rcar_du_needs(lvds->dev, RCAR_DU_QUIRK_LVDS_LANES))
  69. lvdhcr = LVDCHCR_CHSEL_CH(0, 0) | LVDCHCR_CHSEL_CH(1, 3)
  70. | LVDCHCR_CHSEL_CH(2, 2) | LVDCHCR_CHSEL_CH(3, 1);
  71. else
  72. lvdhcr = LVDCHCR_CHSEL_CH(0, 0) | LVDCHCR_CHSEL_CH(1, 1)
  73. | LVDCHCR_CHSEL_CH(2, 2) | LVDCHCR_CHSEL_CH(3, 3);
  74. rcar_lvds_write(lvds, LVDCHCR, lvdhcr);
  75. /* Select the input, hardcode mode 0, enable LVDS operation and turn
  76. * bias circuitry on.
  77. */
  78. lvdcr0 = LVDCR0_BEN | LVDCR0_LVEN;
  79. if (rcrtc->index == 2)
  80. lvdcr0 |= LVDCR0_DUSEL;
  81. rcar_lvds_write(lvds, LVDCR0, lvdcr0);
  82. /* Turn all the channels on. */
  83. rcar_lvds_write(lvds, LVDCR1, LVDCR1_CHSTBY(3) | LVDCR1_CHSTBY(2) |
  84. LVDCR1_CHSTBY(1) | LVDCR1_CHSTBY(0) | LVDCR1_CLKSTBY);
  85. /* Turn the PLL on, wait for the startup delay, and turn the output
  86. * on.
  87. */
  88. lvdcr0 |= LVDCR0_PLLON;
  89. rcar_lvds_write(lvds, LVDCR0, lvdcr0);
  90. usleep_range(100, 150);
  91. lvdcr0 |= LVDCR0_LVRES;
  92. rcar_lvds_write(lvds, LVDCR0, lvdcr0);
  93. lvds->enabled = true;
  94. return 0;
  95. }
  96. static void rcar_du_lvdsenc_stop(struct rcar_du_lvdsenc *lvds)
  97. {
  98. if (!lvds->enabled)
  99. return;
  100. rcar_lvds_write(lvds, LVDCR0, 0);
  101. rcar_lvds_write(lvds, LVDCR1, 0);
  102. clk_disable_unprepare(lvds->clock);
  103. lvds->enabled = false;
  104. }
  105. int rcar_du_lvdsenc_enable(struct rcar_du_lvdsenc *lvds, struct drm_crtc *crtc,
  106. bool enable)
  107. {
  108. if (!enable) {
  109. rcar_du_lvdsenc_stop(lvds);
  110. return 0;
  111. } else if (crtc) {
  112. struct rcar_du_crtc *rcrtc = to_rcar_crtc(crtc);
  113. return rcar_du_lvdsenc_start(lvds, rcrtc);
  114. } else
  115. return -EINVAL;
  116. }
  117. static int rcar_du_lvdsenc_get_resources(struct rcar_du_lvdsenc *lvds,
  118. struct platform_device *pdev)
  119. {
  120. struct resource *mem;
  121. char name[7];
  122. sprintf(name, "lvds.%u", lvds->index);
  123. mem = platform_get_resource_byname(pdev, IORESOURCE_MEM, name);
  124. lvds->mmio = devm_ioremap_resource(&pdev->dev, mem);
  125. if (IS_ERR(lvds->mmio))
  126. return PTR_ERR(lvds->mmio);
  127. lvds->clock = devm_clk_get(&pdev->dev, name);
  128. if (IS_ERR(lvds->clock)) {
  129. dev_err(&pdev->dev, "failed to get clock for %s\n", name);
  130. return PTR_ERR(lvds->clock);
  131. }
  132. return 0;
  133. }
  134. int rcar_du_lvdsenc_init(struct rcar_du_device *rcdu)
  135. {
  136. struct platform_device *pdev = to_platform_device(rcdu->dev);
  137. struct rcar_du_lvdsenc *lvds;
  138. unsigned int i;
  139. int ret;
  140. for (i = 0; i < rcdu->info->num_lvds; ++i) {
  141. lvds = devm_kzalloc(&pdev->dev, sizeof(*lvds), GFP_KERNEL);
  142. if (lvds == NULL) {
  143. dev_err(&pdev->dev, "failed to allocate private data\n");
  144. return -ENOMEM;
  145. }
  146. lvds->dev = rcdu;
  147. lvds->index = i;
  148. lvds->input = i ? RCAR_LVDS_INPUT_DU1 : RCAR_LVDS_INPUT_DU0;
  149. lvds->enabled = false;
  150. ret = rcar_du_lvdsenc_get_resources(lvds, pdev);
  151. if (ret < 0)
  152. return ret;
  153. rcdu->lvds[i] = lvds;
  154. }
  155. return 0;
  156. }