sti_hdmi.c 24 KB

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  1. /*
  2. * Copyright (C) STMicroelectronics SA 2014
  3. * Author: Vincent Abriou <vincent.abriou@st.com> for STMicroelectronics.
  4. * License terms: GNU General Public License (GPL), version 2
  5. */
  6. #include <linux/clk.h>
  7. #include <linux/component.h>
  8. #include <linux/hdmi.h>
  9. #include <linux/module.h>
  10. #include <linux/of_gpio.h>
  11. #include <linux/platform_device.h>
  12. #include <linux/reset.h>
  13. #include <drm/drmP.h>
  14. #include <drm/drm_atomic_helper.h>
  15. #include <drm/drm_crtc_helper.h>
  16. #include <drm/drm_edid.h>
  17. #include "sti_hdmi.h"
  18. #include "sti_hdmi_tx3g4c28phy.h"
  19. #include "sti_hdmi_tx3g0c55phy.h"
  20. #include "sti_vtg.h"
  21. #define HDMI_CFG 0x0000
  22. #define HDMI_INT_EN 0x0004
  23. #define HDMI_INT_STA 0x0008
  24. #define HDMI_INT_CLR 0x000C
  25. #define HDMI_STA 0x0010
  26. #define HDMI_ACTIVE_VID_XMIN 0x0100
  27. #define HDMI_ACTIVE_VID_XMAX 0x0104
  28. #define HDMI_ACTIVE_VID_YMIN 0x0108
  29. #define HDMI_ACTIVE_VID_YMAX 0x010C
  30. #define HDMI_DFLT_CHL0_DAT 0x0110
  31. #define HDMI_DFLT_CHL1_DAT 0x0114
  32. #define HDMI_DFLT_CHL2_DAT 0x0118
  33. #define HDMI_SW_DI_1_HEAD_WORD 0x0210
  34. #define HDMI_SW_DI_1_PKT_WORD0 0x0214
  35. #define HDMI_SW_DI_1_PKT_WORD1 0x0218
  36. #define HDMI_SW_DI_1_PKT_WORD2 0x021C
  37. #define HDMI_SW_DI_1_PKT_WORD3 0x0220
  38. #define HDMI_SW_DI_1_PKT_WORD4 0x0224
  39. #define HDMI_SW_DI_1_PKT_WORD5 0x0228
  40. #define HDMI_SW_DI_1_PKT_WORD6 0x022C
  41. #define HDMI_SW_DI_CFG 0x0230
  42. #define HDMI_SW_DI_2_HEAD_WORD 0x0600
  43. #define HDMI_SW_DI_2_PKT_WORD0 0x0604
  44. #define HDMI_SW_DI_2_PKT_WORD1 0x0608
  45. #define HDMI_SW_DI_2_PKT_WORD2 0x060C
  46. #define HDMI_SW_DI_2_PKT_WORD3 0x0610
  47. #define HDMI_SW_DI_2_PKT_WORD4 0x0614
  48. #define HDMI_SW_DI_2_PKT_WORD5 0x0618
  49. #define HDMI_SW_DI_2_PKT_WORD6 0x061C
  50. #define HDMI_IFRAME_SLOT_AVI 1
  51. #define HDMI_IFRAME_SLOT_AUDIO 2
  52. #define XCAT(prefix, x, suffix) prefix ## x ## suffix
  53. #define HDMI_SW_DI_N_HEAD_WORD(x) XCAT(HDMI_SW_DI_, x, _HEAD_WORD)
  54. #define HDMI_SW_DI_N_PKT_WORD0(x) XCAT(HDMI_SW_DI_, x, _PKT_WORD0)
  55. #define HDMI_SW_DI_N_PKT_WORD1(x) XCAT(HDMI_SW_DI_, x, _PKT_WORD1)
  56. #define HDMI_SW_DI_N_PKT_WORD2(x) XCAT(HDMI_SW_DI_, x, _PKT_WORD2)
  57. #define HDMI_SW_DI_N_PKT_WORD3(x) XCAT(HDMI_SW_DI_, x, _PKT_WORD3)
  58. #define HDMI_SW_DI_N_PKT_WORD4(x) XCAT(HDMI_SW_DI_, x, _PKT_WORD4)
  59. #define HDMI_SW_DI_N_PKT_WORD5(x) XCAT(HDMI_SW_DI_, x, _PKT_WORD5)
  60. #define HDMI_SW_DI_N_PKT_WORD6(x) XCAT(HDMI_SW_DI_, x, _PKT_WORD6)
  61. #define HDMI_IFRAME_DISABLED 0x0
  62. #define HDMI_IFRAME_SINGLE_SHOT 0x1
  63. #define HDMI_IFRAME_FIELD 0x2
  64. #define HDMI_IFRAME_FRAME 0x3
  65. #define HDMI_IFRAME_MASK 0x3
  66. #define HDMI_IFRAME_CFG_DI_N(x, n) ((x) << ((n-1)*4)) /* n from 1 to 6 */
  67. #define HDMI_CFG_DEVICE_EN BIT(0)
  68. #define HDMI_CFG_HDMI_NOT_DVI BIT(1)
  69. #define HDMI_CFG_HDCP_EN BIT(2)
  70. #define HDMI_CFG_ESS_NOT_OESS BIT(3)
  71. #define HDMI_CFG_H_SYNC_POL_NEG BIT(4)
  72. #define HDMI_CFG_SINK_TERM_DET_EN BIT(5)
  73. #define HDMI_CFG_V_SYNC_POL_NEG BIT(6)
  74. #define HDMI_CFG_422_EN BIT(8)
  75. #define HDMI_CFG_FIFO_OVERRUN_CLR BIT(12)
  76. #define HDMI_CFG_FIFO_UNDERRUN_CLR BIT(13)
  77. #define HDMI_CFG_SW_RST_EN BIT(31)
  78. #define HDMI_INT_GLOBAL BIT(0)
  79. #define HDMI_INT_SW_RST BIT(1)
  80. #define HDMI_INT_PIX_CAP BIT(3)
  81. #define HDMI_INT_HOT_PLUG BIT(4)
  82. #define HDMI_INT_DLL_LCK BIT(5)
  83. #define HDMI_INT_NEW_FRAME BIT(6)
  84. #define HDMI_INT_GENCTRL_PKT BIT(7)
  85. #define HDMI_INT_SINK_TERM_PRESENT BIT(11)
  86. #define HDMI_DEFAULT_INT (HDMI_INT_SINK_TERM_PRESENT \
  87. | HDMI_INT_DLL_LCK \
  88. | HDMI_INT_HOT_PLUG \
  89. | HDMI_INT_GLOBAL)
  90. #define HDMI_WORKING_INT (HDMI_INT_SINK_TERM_PRESENT \
  91. | HDMI_INT_GENCTRL_PKT \
  92. | HDMI_INT_NEW_FRAME \
  93. | HDMI_INT_DLL_LCK \
  94. | HDMI_INT_HOT_PLUG \
  95. | HDMI_INT_PIX_CAP \
  96. | HDMI_INT_SW_RST \
  97. | HDMI_INT_GLOBAL)
  98. #define HDMI_STA_SW_RST BIT(1)
  99. #define HDMI_INFOFRAME_HEADER_TYPE(x) (((x) & 0xff) << 0)
  100. #define HDMI_INFOFRAME_HEADER_VERSION(x) (((x) & 0xff) << 8)
  101. #define HDMI_INFOFRAME_HEADER_LEN(x) (((x) & 0x0f) << 16)
  102. struct sti_hdmi_connector {
  103. struct drm_connector drm_connector;
  104. struct drm_encoder *encoder;
  105. struct sti_hdmi *hdmi;
  106. };
  107. #define to_sti_hdmi_connector(x) \
  108. container_of(x, struct sti_hdmi_connector, drm_connector)
  109. u32 hdmi_read(struct sti_hdmi *hdmi, int offset)
  110. {
  111. return readl(hdmi->regs + offset);
  112. }
  113. void hdmi_write(struct sti_hdmi *hdmi, u32 val, int offset)
  114. {
  115. writel(val, hdmi->regs + offset);
  116. }
  117. /**
  118. * HDMI interrupt handler threaded
  119. *
  120. * @irq: irq number
  121. * @arg: connector structure
  122. */
  123. static irqreturn_t hdmi_irq_thread(int irq, void *arg)
  124. {
  125. struct sti_hdmi *hdmi = arg;
  126. /* Hot plug/unplug IRQ */
  127. if (hdmi->irq_status & HDMI_INT_HOT_PLUG) {
  128. hdmi->hpd = readl(hdmi->regs + HDMI_STA) & HDMI_STA_HOT_PLUG;
  129. if (hdmi->drm_dev)
  130. drm_helper_hpd_irq_event(hdmi->drm_dev);
  131. }
  132. /* Sw reset and PLL lock are exclusive so we can use the same
  133. * event to signal them
  134. */
  135. if (hdmi->irq_status & (HDMI_INT_SW_RST | HDMI_INT_DLL_LCK)) {
  136. hdmi->event_received = true;
  137. wake_up_interruptible(&hdmi->wait_event);
  138. }
  139. return IRQ_HANDLED;
  140. }
  141. /**
  142. * HDMI interrupt handler
  143. *
  144. * @irq: irq number
  145. * @arg: connector structure
  146. */
  147. static irqreturn_t hdmi_irq(int irq, void *arg)
  148. {
  149. struct sti_hdmi *hdmi = arg;
  150. /* read interrupt status */
  151. hdmi->irq_status = hdmi_read(hdmi, HDMI_INT_STA);
  152. /* clear interrupt status */
  153. hdmi_write(hdmi, hdmi->irq_status, HDMI_INT_CLR);
  154. /* force sync bus write */
  155. hdmi_read(hdmi, HDMI_INT_STA);
  156. return IRQ_WAKE_THREAD;
  157. }
  158. /**
  159. * Set hdmi active area depending on the drm display mode selected
  160. *
  161. * @hdmi: pointer on the hdmi internal structure
  162. */
  163. static void hdmi_active_area(struct sti_hdmi *hdmi)
  164. {
  165. u32 xmin, xmax;
  166. u32 ymin, ymax;
  167. xmin = sti_vtg_get_pixel_number(hdmi->mode, 1);
  168. xmax = sti_vtg_get_pixel_number(hdmi->mode, hdmi->mode.hdisplay);
  169. ymin = sti_vtg_get_line_number(hdmi->mode, 0);
  170. ymax = sti_vtg_get_line_number(hdmi->mode, hdmi->mode.vdisplay - 1);
  171. hdmi_write(hdmi, xmin, HDMI_ACTIVE_VID_XMIN);
  172. hdmi_write(hdmi, xmax, HDMI_ACTIVE_VID_XMAX);
  173. hdmi_write(hdmi, ymin, HDMI_ACTIVE_VID_YMIN);
  174. hdmi_write(hdmi, ymax, HDMI_ACTIVE_VID_YMAX);
  175. }
  176. /**
  177. * Overall hdmi configuration
  178. *
  179. * @hdmi: pointer on the hdmi internal structure
  180. */
  181. static void hdmi_config(struct sti_hdmi *hdmi)
  182. {
  183. u32 conf;
  184. DRM_DEBUG_DRIVER("\n");
  185. /* Clear overrun and underrun fifo */
  186. conf = HDMI_CFG_FIFO_OVERRUN_CLR | HDMI_CFG_FIFO_UNDERRUN_CLR;
  187. /* Enable HDMI mode not DVI */
  188. conf |= HDMI_CFG_HDMI_NOT_DVI | HDMI_CFG_ESS_NOT_OESS;
  189. /* Enable sink term detection */
  190. conf |= HDMI_CFG_SINK_TERM_DET_EN;
  191. /* Set Hsync polarity */
  192. if (hdmi->mode.flags & DRM_MODE_FLAG_NHSYNC) {
  193. DRM_DEBUG_DRIVER("H Sync Negative\n");
  194. conf |= HDMI_CFG_H_SYNC_POL_NEG;
  195. }
  196. /* Set Vsync polarity */
  197. if (hdmi->mode.flags & DRM_MODE_FLAG_NVSYNC) {
  198. DRM_DEBUG_DRIVER("V Sync Negative\n");
  199. conf |= HDMI_CFG_V_SYNC_POL_NEG;
  200. }
  201. /* Enable HDMI */
  202. conf |= HDMI_CFG_DEVICE_EN;
  203. hdmi_write(hdmi, conf, HDMI_CFG);
  204. }
  205. /**
  206. * Helper to concatenate infoframe in 32 bits word
  207. *
  208. * @ptr: pointer on the hdmi internal structure
  209. * @data: infoframe to write
  210. * @size: size to write
  211. */
  212. static inline unsigned int hdmi_infoframe_subpack(const u8 *ptr, size_t size)
  213. {
  214. unsigned long value = 0;
  215. size_t i;
  216. for (i = size; i > 0; i--)
  217. value = (value << 8) | ptr[i - 1];
  218. return value;
  219. }
  220. /**
  221. * Helper to write info frame
  222. *
  223. * @hdmi: pointer on the hdmi internal structure
  224. * @data: infoframe to write
  225. * @size: size to write
  226. */
  227. static void hdmi_infoframe_write_infopack(struct sti_hdmi *hdmi, const u8 *data)
  228. {
  229. const u8 *ptr = data;
  230. u32 val, slot, mode, i;
  231. u32 head_offset, pack_offset;
  232. size_t size;
  233. switch (*ptr) {
  234. case HDMI_INFOFRAME_TYPE_AVI:
  235. slot = HDMI_IFRAME_SLOT_AVI;
  236. mode = HDMI_IFRAME_FIELD;
  237. head_offset = HDMI_SW_DI_N_HEAD_WORD(HDMI_IFRAME_SLOT_AVI);
  238. pack_offset = HDMI_SW_DI_N_PKT_WORD0(HDMI_IFRAME_SLOT_AVI);
  239. size = HDMI_AVI_INFOFRAME_SIZE;
  240. break;
  241. case HDMI_INFOFRAME_TYPE_AUDIO:
  242. slot = HDMI_IFRAME_SLOT_AUDIO;
  243. mode = HDMI_IFRAME_FRAME;
  244. head_offset = HDMI_SW_DI_N_HEAD_WORD(HDMI_IFRAME_SLOT_AUDIO);
  245. pack_offset = HDMI_SW_DI_N_PKT_WORD0(HDMI_IFRAME_SLOT_AUDIO);
  246. size = HDMI_AUDIO_INFOFRAME_SIZE;
  247. break;
  248. default:
  249. DRM_ERROR("unsupported infoframe type: %#x\n", *ptr);
  250. return;
  251. }
  252. /* Disable transmission slot for updated infoframe */
  253. val = hdmi_read(hdmi, HDMI_SW_DI_CFG);
  254. val &= ~HDMI_IFRAME_CFG_DI_N(HDMI_IFRAME_MASK, slot);
  255. hdmi_write(hdmi, val, HDMI_SW_DI_CFG);
  256. val = HDMI_INFOFRAME_HEADER_TYPE(*ptr++);
  257. val |= HDMI_INFOFRAME_HEADER_VERSION(*ptr++);
  258. val |= HDMI_INFOFRAME_HEADER_LEN(*ptr++);
  259. writel(val, hdmi->regs + head_offset);
  260. /*
  261. * Each subpack contains 4 bytes
  262. * The First Bytes of the first subpacket must contain the checksum
  263. * Packet size in increase by one.
  264. */
  265. for (i = 0; i < size; i += sizeof(u32)) {
  266. size_t num;
  267. num = min_t(size_t, size - i, sizeof(u32));
  268. val = hdmi_infoframe_subpack(ptr, num);
  269. ptr += sizeof(u32);
  270. writel(val, hdmi->regs + pack_offset + i);
  271. }
  272. /* Enable transmission slot for updated infoframe */
  273. val = hdmi_read(hdmi, HDMI_SW_DI_CFG);
  274. val |= HDMI_IFRAME_CFG_DI_N(HDMI_IFRAME_FIELD, slot);
  275. hdmi_write(hdmi, val, HDMI_SW_DI_CFG);
  276. }
  277. /**
  278. * Prepare and configure the AVI infoframe
  279. *
  280. * AVI infoframe are transmitted at least once per two video field and
  281. * contains information about HDMI transmission mode such as color space,
  282. * colorimetry, ...
  283. *
  284. * @hdmi: pointer on the hdmi internal structure
  285. *
  286. * Return negative value if error occurs
  287. */
  288. static int hdmi_avi_infoframe_config(struct sti_hdmi *hdmi)
  289. {
  290. struct drm_display_mode *mode = &hdmi->mode;
  291. struct hdmi_avi_infoframe infoframe;
  292. u8 buffer[HDMI_INFOFRAME_SIZE(AVI)];
  293. int ret;
  294. DRM_DEBUG_DRIVER("\n");
  295. ret = drm_hdmi_avi_infoframe_from_display_mode(&infoframe, mode);
  296. if (ret < 0) {
  297. DRM_ERROR("failed to setup AVI infoframe: %d\n", ret);
  298. return ret;
  299. }
  300. /* fixed infoframe configuration not linked to the mode */
  301. infoframe.colorspace = HDMI_COLORSPACE_RGB;
  302. infoframe.quantization_range = HDMI_QUANTIZATION_RANGE_DEFAULT;
  303. infoframe.colorimetry = HDMI_COLORIMETRY_NONE;
  304. ret = hdmi_avi_infoframe_pack(&infoframe, buffer, sizeof(buffer));
  305. if (ret < 0) {
  306. DRM_ERROR("failed to pack AVI infoframe: %d\n", ret);
  307. return ret;
  308. }
  309. hdmi_infoframe_write_infopack(hdmi, buffer);
  310. return 0;
  311. }
  312. /**
  313. * Prepare and configure the AUDIO infoframe
  314. *
  315. * AUDIO infoframe are transmitted once per frame and
  316. * contains information about HDMI transmission mode such as audio codec,
  317. * sample size, ...
  318. *
  319. * @hdmi: pointer on the hdmi internal structure
  320. *
  321. * Return negative value if error occurs
  322. */
  323. static int hdmi_audio_infoframe_config(struct sti_hdmi *hdmi)
  324. {
  325. struct hdmi_audio_infoframe infofame;
  326. u8 buffer[HDMI_INFOFRAME_SIZE(AUDIO)];
  327. int ret;
  328. ret = hdmi_audio_infoframe_init(&infofame);
  329. if (ret < 0) {
  330. DRM_ERROR("failed to setup audio infoframe: %d\n", ret);
  331. return ret;
  332. }
  333. infofame.channels = 2;
  334. ret = hdmi_audio_infoframe_pack(&infofame, buffer, sizeof(buffer));
  335. if (ret < 0) {
  336. DRM_ERROR("failed to pack audio infoframe: %d\n", ret);
  337. return ret;
  338. }
  339. hdmi_infoframe_write_infopack(hdmi, buffer);
  340. return 0;
  341. }
  342. /**
  343. * Software reset of the hdmi subsystem
  344. *
  345. * @hdmi: pointer on the hdmi internal structure
  346. *
  347. */
  348. #define HDMI_TIMEOUT_SWRESET 100 /*milliseconds */
  349. static void hdmi_swreset(struct sti_hdmi *hdmi)
  350. {
  351. u32 val;
  352. DRM_DEBUG_DRIVER("\n");
  353. /* Enable hdmi_audio clock only during hdmi reset */
  354. if (clk_prepare_enable(hdmi->clk_audio))
  355. DRM_INFO("Failed to prepare/enable hdmi_audio clk\n");
  356. /* Sw reset */
  357. hdmi->event_received = false;
  358. val = hdmi_read(hdmi, HDMI_CFG);
  359. val |= HDMI_CFG_SW_RST_EN;
  360. hdmi_write(hdmi, val, HDMI_CFG);
  361. /* Wait reset completed */
  362. wait_event_interruptible_timeout(hdmi->wait_event,
  363. hdmi->event_received == true,
  364. msecs_to_jiffies
  365. (HDMI_TIMEOUT_SWRESET));
  366. /*
  367. * HDMI_STA_SW_RST bit is set to '1' when SW_RST bit in HDMI_CFG is
  368. * set to '1' and clk_audio is running.
  369. */
  370. if ((hdmi_read(hdmi, HDMI_STA) & HDMI_STA_SW_RST) == 0)
  371. DRM_DEBUG_DRIVER("Warning: HDMI sw reset timeout occurs\n");
  372. val = hdmi_read(hdmi, HDMI_CFG);
  373. val &= ~HDMI_CFG_SW_RST_EN;
  374. hdmi_write(hdmi, val, HDMI_CFG);
  375. /* Disable hdmi_audio clock. Not used anymore for drm purpose */
  376. clk_disable_unprepare(hdmi->clk_audio);
  377. }
  378. static void sti_hdmi_disable(struct drm_bridge *bridge)
  379. {
  380. struct sti_hdmi *hdmi = bridge->driver_private;
  381. u32 val = hdmi_read(hdmi, HDMI_CFG);
  382. if (!hdmi->enabled)
  383. return;
  384. DRM_DEBUG_DRIVER("\n");
  385. /* Disable HDMI */
  386. val &= ~HDMI_CFG_DEVICE_EN;
  387. hdmi_write(hdmi, val, HDMI_CFG);
  388. hdmi_write(hdmi, 0xffffffff, HDMI_INT_CLR);
  389. /* Stop the phy */
  390. hdmi->phy_ops->stop(hdmi);
  391. /* Set the default channel data to be a dark red */
  392. hdmi_write(hdmi, 0x0000, HDMI_DFLT_CHL0_DAT);
  393. hdmi_write(hdmi, 0x0000, HDMI_DFLT_CHL1_DAT);
  394. hdmi_write(hdmi, 0x0060, HDMI_DFLT_CHL2_DAT);
  395. /* Disable/unprepare hdmi clock */
  396. clk_disable_unprepare(hdmi->clk_phy);
  397. clk_disable_unprepare(hdmi->clk_tmds);
  398. clk_disable_unprepare(hdmi->clk_pix);
  399. hdmi->enabled = false;
  400. }
  401. static void sti_hdmi_pre_enable(struct drm_bridge *bridge)
  402. {
  403. struct sti_hdmi *hdmi = bridge->driver_private;
  404. DRM_DEBUG_DRIVER("\n");
  405. if (hdmi->enabled)
  406. return;
  407. /* Prepare/enable clocks */
  408. if (clk_prepare_enable(hdmi->clk_pix))
  409. DRM_ERROR("Failed to prepare/enable hdmi_pix clk\n");
  410. if (clk_prepare_enable(hdmi->clk_tmds))
  411. DRM_ERROR("Failed to prepare/enable hdmi_tmds clk\n");
  412. if (clk_prepare_enable(hdmi->clk_phy))
  413. DRM_ERROR("Failed to prepare/enable hdmi_rejec_pll clk\n");
  414. hdmi->enabled = true;
  415. /* Program hdmi serializer and start phy */
  416. if (!hdmi->phy_ops->start(hdmi)) {
  417. DRM_ERROR("Unable to start hdmi phy\n");
  418. return;
  419. }
  420. /* Program hdmi active area */
  421. hdmi_active_area(hdmi);
  422. /* Enable working interrupts */
  423. hdmi_write(hdmi, HDMI_WORKING_INT, HDMI_INT_EN);
  424. /* Program hdmi config */
  425. hdmi_config(hdmi);
  426. /* Program AVI infoframe */
  427. if (hdmi_avi_infoframe_config(hdmi))
  428. DRM_ERROR("Unable to configure AVI infoframe\n");
  429. /* Program AUDIO infoframe */
  430. if (hdmi_audio_infoframe_config(hdmi))
  431. DRM_ERROR("Unable to configure AUDIO infoframe\n");
  432. /* Sw reset */
  433. hdmi_swreset(hdmi);
  434. }
  435. static void sti_hdmi_set_mode(struct drm_bridge *bridge,
  436. struct drm_display_mode *mode,
  437. struct drm_display_mode *adjusted_mode)
  438. {
  439. struct sti_hdmi *hdmi = bridge->driver_private;
  440. int ret;
  441. DRM_DEBUG_DRIVER("\n");
  442. /* Copy the drm display mode in the connector local structure */
  443. memcpy(&hdmi->mode, mode, sizeof(struct drm_display_mode));
  444. /* Update clock framerate according to the selected mode */
  445. ret = clk_set_rate(hdmi->clk_pix, mode->clock * 1000);
  446. if (ret < 0) {
  447. DRM_ERROR("Cannot set rate (%dHz) for hdmi_pix clk\n",
  448. mode->clock * 1000);
  449. return;
  450. }
  451. ret = clk_set_rate(hdmi->clk_phy, mode->clock * 1000);
  452. if (ret < 0) {
  453. DRM_ERROR("Cannot set rate (%dHz) for hdmi_rejection_pll clk\n",
  454. mode->clock * 1000);
  455. return;
  456. }
  457. }
  458. static void sti_hdmi_bridge_nope(struct drm_bridge *bridge)
  459. {
  460. /* do nothing */
  461. }
  462. static const struct drm_bridge_funcs sti_hdmi_bridge_funcs = {
  463. .pre_enable = sti_hdmi_pre_enable,
  464. .enable = sti_hdmi_bridge_nope,
  465. .disable = sti_hdmi_disable,
  466. .post_disable = sti_hdmi_bridge_nope,
  467. .mode_set = sti_hdmi_set_mode,
  468. };
  469. static int sti_hdmi_connector_get_modes(struct drm_connector *connector)
  470. {
  471. struct sti_hdmi_connector *hdmi_connector
  472. = to_sti_hdmi_connector(connector);
  473. struct sti_hdmi *hdmi = hdmi_connector->hdmi;
  474. struct edid *edid;
  475. int count;
  476. DRM_DEBUG_DRIVER("\n");
  477. edid = drm_get_edid(connector, hdmi->ddc_adapt);
  478. if (!edid)
  479. goto fail;
  480. count = drm_add_edid_modes(connector, edid);
  481. drm_mode_connector_update_edid_property(connector, edid);
  482. kfree(edid);
  483. return count;
  484. fail:
  485. DRM_ERROR("Can't read HDMI EDID\n");
  486. return 0;
  487. }
  488. #define CLK_TOLERANCE_HZ 50
  489. static int sti_hdmi_connector_mode_valid(struct drm_connector *connector,
  490. struct drm_display_mode *mode)
  491. {
  492. int target = mode->clock * 1000;
  493. int target_min = target - CLK_TOLERANCE_HZ;
  494. int target_max = target + CLK_TOLERANCE_HZ;
  495. int result;
  496. struct sti_hdmi_connector *hdmi_connector
  497. = to_sti_hdmi_connector(connector);
  498. struct sti_hdmi *hdmi = hdmi_connector->hdmi;
  499. result = clk_round_rate(hdmi->clk_pix, target);
  500. DRM_DEBUG_DRIVER("target rate = %d => available rate = %d\n",
  501. target, result);
  502. if ((result < target_min) || (result > target_max)) {
  503. DRM_DEBUG_DRIVER("hdmi pixclk=%d not supported\n", target);
  504. return MODE_BAD;
  505. }
  506. return MODE_OK;
  507. }
  508. struct drm_encoder *sti_hdmi_best_encoder(struct drm_connector *connector)
  509. {
  510. struct sti_hdmi_connector *hdmi_connector
  511. = to_sti_hdmi_connector(connector);
  512. /* Best encoder is the one associated during connector creation */
  513. return hdmi_connector->encoder;
  514. }
  515. static const
  516. struct drm_connector_helper_funcs sti_hdmi_connector_helper_funcs = {
  517. .get_modes = sti_hdmi_connector_get_modes,
  518. .mode_valid = sti_hdmi_connector_mode_valid,
  519. .best_encoder = sti_hdmi_best_encoder,
  520. };
  521. /* get detection status of display device */
  522. static enum drm_connector_status
  523. sti_hdmi_connector_detect(struct drm_connector *connector, bool force)
  524. {
  525. struct sti_hdmi_connector *hdmi_connector
  526. = to_sti_hdmi_connector(connector);
  527. struct sti_hdmi *hdmi = hdmi_connector->hdmi;
  528. DRM_DEBUG_DRIVER("\n");
  529. if (hdmi->hpd) {
  530. DRM_DEBUG_DRIVER("hdmi cable connected\n");
  531. return connector_status_connected;
  532. }
  533. DRM_DEBUG_DRIVER("hdmi cable disconnected\n");
  534. return connector_status_disconnected;
  535. }
  536. static void sti_hdmi_connector_destroy(struct drm_connector *connector)
  537. {
  538. struct sti_hdmi_connector *hdmi_connector
  539. = to_sti_hdmi_connector(connector);
  540. drm_connector_unregister(connector);
  541. drm_connector_cleanup(connector);
  542. kfree(hdmi_connector);
  543. }
  544. static const struct drm_connector_funcs sti_hdmi_connector_funcs = {
  545. .dpms = drm_atomic_helper_connector_dpms,
  546. .fill_modes = drm_helper_probe_single_connector_modes,
  547. .detect = sti_hdmi_connector_detect,
  548. .destroy = sti_hdmi_connector_destroy,
  549. .reset = drm_atomic_helper_connector_reset,
  550. .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
  551. .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
  552. };
  553. static struct drm_encoder *sti_hdmi_find_encoder(struct drm_device *dev)
  554. {
  555. struct drm_encoder *encoder;
  556. list_for_each_entry(encoder, &dev->mode_config.encoder_list, head) {
  557. if (encoder->encoder_type == DRM_MODE_ENCODER_TMDS)
  558. return encoder;
  559. }
  560. return NULL;
  561. }
  562. static int sti_hdmi_bind(struct device *dev, struct device *master, void *data)
  563. {
  564. struct sti_hdmi *hdmi = dev_get_drvdata(dev);
  565. struct drm_device *drm_dev = data;
  566. struct drm_encoder *encoder;
  567. struct sti_hdmi_connector *connector;
  568. struct drm_connector *drm_connector;
  569. struct drm_bridge *bridge;
  570. int err;
  571. /* Set the drm device handle */
  572. hdmi->drm_dev = drm_dev;
  573. encoder = sti_hdmi_find_encoder(drm_dev);
  574. if (!encoder)
  575. return -EINVAL;
  576. connector = devm_kzalloc(dev, sizeof(*connector), GFP_KERNEL);
  577. if (!connector)
  578. return -EINVAL;
  579. connector->hdmi = hdmi;
  580. bridge = devm_kzalloc(dev, sizeof(*bridge), GFP_KERNEL);
  581. if (!bridge)
  582. return -EINVAL;
  583. bridge->driver_private = hdmi;
  584. bridge->funcs = &sti_hdmi_bridge_funcs;
  585. drm_bridge_attach(drm_dev, bridge);
  586. encoder->bridge = bridge;
  587. connector->encoder = encoder;
  588. drm_connector = (struct drm_connector *)connector;
  589. drm_connector->polled = DRM_CONNECTOR_POLL_HPD;
  590. drm_connector_init(drm_dev, drm_connector,
  591. &sti_hdmi_connector_funcs, DRM_MODE_CONNECTOR_HDMIA);
  592. drm_connector_helper_add(drm_connector,
  593. &sti_hdmi_connector_helper_funcs);
  594. err = drm_connector_register(drm_connector);
  595. if (err)
  596. goto err_connector;
  597. err = drm_mode_connector_attach_encoder(drm_connector, encoder);
  598. if (err) {
  599. DRM_ERROR("Failed to attach a connector to a encoder\n");
  600. goto err_sysfs;
  601. }
  602. /* Enable default interrupts */
  603. hdmi_write(hdmi, HDMI_DEFAULT_INT, HDMI_INT_EN);
  604. return 0;
  605. err_sysfs:
  606. drm_connector_unregister(drm_connector);
  607. err_connector:
  608. drm_connector_cleanup(drm_connector);
  609. return -EINVAL;
  610. }
  611. static void sti_hdmi_unbind(struct device *dev,
  612. struct device *master, void *data)
  613. {
  614. /* do nothing */
  615. }
  616. static const struct component_ops sti_hdmi_ops = {
  617. .bind = sti_hdmi_bind,
  618. .unbind = sti_hdmi_unbind,
  619. };
  620. static const struct of_device_id hdmi_of_match[] = {
  621. {
  622. .compatible = "st,stih416-hdmi",
  623. .data = &tx3g0c55phy_ops,
  624. }, {
  625. .compatible = "st,stih407-hdmi",
  626. .data = &tx3g4c28phy_ops,
  627. }, {
  628. /* end node */
  629. }
  630. };
  631. MODULE_DEVICE_TABLE(of, hdmi_of_match);
  632. static int sti_hdmi_probe(struct platform_device *pdev)
  633. {
  634. struct device *dev = &pdev->dev;
  635. struct sti_hdmi *hdmi;
  636. struct device_node *np = dev->of_node;
  637. struct resource *res;
  638. struct device_node *ddc;
  639. int ret;
  640. DRM_INFO("%s\n", __func__);
  641. hdmi = devm_kzalloc(dev, sizeof(*hdmi), GFP_KERNEL);
  642. if (!hdmi)
  643. return -ENOMEM;
  644. ddc = of_parse_phandle(pdev->dev.of_node, "ddc", 0);
  645. if (ddc) {
  646. hdmi->ddc_adapt = of_get_i2c_adapter_by_node(ddc);
  647. of_node_put(ddc);
  648. if (!hdmi->ddc_adapt)
  649. return -EPROBE_DEFER;
  650. }
  651. hdmi->dev = pdev->dev;
  652. /* Get resources */
  653. res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "hdmi-reg");
  654. if (!res) {
  655. DRM_ERROR("Invalid hdmi resource\n");
  656. ret = -ENOMEM;
  657. goto release_adapter;
  658. }
  659. hdmi->regs = devm_ioremap_nocache(dev, res->start, resource_size(res));
  660. if (!hdmi->regs) {
  661. ret = -ENOMEM;
  662. goto release_adapter;
  663. }
  664. if (of_device_is_compatible(np, "st,stih416-hdmi")) {
  665. res = platform_get_resource_byname(pdev, IORESOURCE_MEM,
  666. "syscfg");
  667. if (!res) {
  668. DRM_ERROR("Invalid syscfg resource\n");
  669. ret = -ENOMEM;
  670. goto release_adapter;
  671. }
  672. hdmi->syscfg = devm_ioremap_nocache(dev, res->start,
  673. resource_size(res));
  674. if (!hdmi->syscfg) {
  675. ret = -ENOMEM;
  676. goto release_adapter;
  677. }
  678. }
  679. hdmi->phy_ops = (struct hdmi_phy_ops *)
  680. of_match_node(hdmi_of_match, np)->data;
  681. /* Get clock resources */
  682. hdmi->clk_pix = devm_clk_get(dev, "pix");
  683. if (IS_ERR(hdmi->clk_pix)) {
  684. DRM_ERROR("Cannot get hdmi_pix clock\n");
  685. ret = PTR_ERR(hdmi->clk_pix);
  686. goto release_adapter;
  687. }
  688. hdmi->clk_tmds = devm_clk_get(dev, "tmds");
  689. if (IS_ERR(hdmi->clk_tmds)) {
  690. DRM_ERROR("Cannot get hdmi_tmds clock\n");
  691. ret = PTR_ERR(hdmi->clk_tmds);
  692. goto release_adapter;
  693. }
  694. hdmi->clk_phy = devm_clk_get(dev, "phy");
  695. if (IS_ERR(hdmi->clk_phy)) {
  696. DRM_ERROR("Cannot get hdmi_phy clock\n");
  697. ret = PTR_ERR(hdmi->clk_phy);
  698. goto release_adapter;
  699. }
  700. hdmi->clk_audio = devm_clk_get(dev, "audio");
  701. if (IS_ERR(hdmi->clk_audio)) {
  702. DRM_ERROR("Cannot get hdmi_audio clock\n");
  703. ret = PTR_ERR(hdmi->clk_audio);
  704. goto release_adapter;
  705. }
  706. hdmi->hpd = readl(hdmi->regs + HDMI_STA) & HDMI_STA_HOT_PLUG;
  707. init_waitqueue_head(&hdmi->wait_event);
  708. hdmi->irq = platform_get_irq_byname(pdev, "irq");
  709. ret = devm_request_threaded_irq(dev, hdmi->irq, hdmi_irq,
  710. hdmi_irq_thread, IRQF_ONESHOT, dev_name(dev), hdmi);
  711. if (ret) {
  712. DRM_ERROR("Failed to register HDMI interrupt\n");
  713. goto release_adapter;
  714. }
  715. hdmi->reset = devm_reset_control_get(dev, "hdmi");
  716. /* Take hdmi out of reset */
  717. if (!IS_ERR(hdmi->reset))
  718. reset_control_deassert(hdmi->reset);
  719. platform_set_drvdata(pdev, hdmi);
  720. return component_add(&pdev->dev, &sti_hdmi_ops);
  721. release_adapter:
  722. i2c_put_adapter(hdmi->ddc_adapt);
  723. return ret;
  724. }
  725. static int sti_hdmi_remove(struct platform_device *pdev)
  726. {
  727. struct sti_hdmi *hdmi = dev_get_drvdata(&pdev->dev);
  728. i2c_put_adapter(hdmi->ddc_adapt);
  729. component_del(&pdev->dev, &sti_hdmi_ops);
  730. return 0;
  731. }
  732. struct platform_driver sti_hdmi_driver = {
  733. .driver = {
  734. .name = "sti-hdmi",
  735. .owner = THIS_MODULE,
  736. .of_match_table = hdmi_of_match,
  737. },
  738. .probe = sti_hdmi_probe,
  739. .remove = sti_hdmi_remove,
  740. };
  741. MODULE_AUTHOR("Benjamin Gaignard <benjamin.gaignard@st.com>");
  742. MODULE_DESCRIPTION("STMicroelectronics SoC DRM driver");
  743. MODULE_LICENSE("GPL");