jc42.c 15 KB

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  1. /*
  2. * jc42.c - driver for Jedec JC42.4 compliant temperature sensors
  3. *
  4. * Copyright (c) 2010 Ericsson AB.
  5. *
  6. * Derived from lm77.c by Andras BALI <drewie@freemail.hu>.
  7. *
  8. * JC42.4 compliant temperature sensors are typically used on memory modules.
  9. *
  10. * This program is free software; you can redistribute it and/or modify
  11. * it under the terms of the GNU General Public License as published by
  12. * the Free Software Foundation; either version 2 of the License, or
  13. * (at your option) any later version.
  14. *
  15. * This program is distributed in the hope that it will be useful,
  16. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  18. * GNU General Public License for more details.
  19. *
  20. * You should have received a copy of the GNU General Public License
  21. * along with this program; if not, write to the Free Software
  22. * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  23. */
  24. #include <linux/module.h>
  25. #include <linux/init.h>
  26. #include <linux/slab.h>
  27. #include <linux/jiffies.h>
  28. #include <linux/i2c.h>
  29. #include <linux/hwmon.h>
  30. #include <linux/hwmon-sysfs.h>
  31. #include <linux/err.h>
  32. #include <linux/mutex.h>
  33. /* Addresses to scan */
  34. static const unsigned short normal_i2c[] = {
  35. 0x18, 0x19, 0x1a, 0x1b, 0x1c, 0x1d, 0x1e, 0x1f, I2C_CLIENT_END };
  36. /* JC42 registers. All registers are 16 bit. */
  37. #define JC42_REG_CAP 0x00
  38. #define JC42_REG_CONFIG 0x01
  39. #define JC42_REG_TEMP_UPPER 0x02
  40. #define JC42_REG_TEMP_LOWER 0x03
  41. #define JC42_REG_TEMP_CRITICAL 0x04
  42. #define JC42_REG_TEMP 0x05
  43. #define JC42_REG_MANID 0x06
  44. #define JC42_REG_DEVICEID 0x07
  45. /* Status bits in temperature register */
  46. #define JC42_ALARM_CRIT_BIT 15
  47. #define JC42_ALARM_MAX_BIT 14
  48. #define JC42_ALARM_MIN_BIT 13
  49. /* Configuration register defines */
  50. #define JC42_CFG_CRIT_ONLY (1 << 2)
  51. #define JC42_CFG_TCRIT_LOCK (1 << 6)
  52. #define JC42_CFG_EVENT_LOCK (1 << 7)
  53. #define JC42_CFG_SHUTDOWN (1 << 8)
  54. #define JC42_CFG_HYST_SHIFT 9
  55. #define JC42_CFG_HYST_MASK (0x03 << 9)
  56. /* Capabilities */
  57. #define JC42_CAP_RANGE (1 << 2)
  58. /* Manufacturer IDs */
  59. #define ADT_MANID 0x11d4 /* Analog Devices */
  60. #define ATMEL_MANID 0x001f /* Atmel */
  61. #define ATMEL_MANID2 0x1114 /* Atmel */
  62. #define MAX_MANID 0x004d /* Maxim */
  63. #define IDT_MANID 0x00b3 /* IDT */
  64. #define MCP_MANID 0x0054 /* Microchip */
  65. #define NXP_MANID 0x1131 /* NXP Semiconductors */
  66. #define ONS_MANID 0x1b09 /* ON Semiconductor */
  67. #define STM_MANID 0x104a /* ST Microelectronics */
  68. /* Supported chips */
  69. /* Analog Devices */
  70. #define ADT7408_DEVID 0x0801
  71. #define ADT7408_DEVID_MASK 0xffff
  72. /* Atmel */
  73. #define AT30TS00_DEVID 0x8201
  74. #define AT30TS00_DEVID_MASK 0xffff
  75. #define AT30TSE004_DEVID 0x2200
  76. #define AT30TSE004_DEVID_MASK 0xffff
  77. /* IDT */
  78. #define TSE2004_DEVID 0x2200
  79. #define TSE2004_DEVID_MASK 0xff00
  80. #define TS3000_DEVID 0x2900 /* Also matches TSE2002 */
  81. #define TS3000_DEVID_MASK 0xff00
  82. #define TS3001_DEVID 0x3000
  83. #define TS3001_DEVID_MASK 0xff00
  84. /* Maxim */
  85. #define MAX6604_DEVID 0x3e00
  86. #define MAX6604_DEVID_MASK 0xffff
  87. /* Microchip */
  88. #define MCP9804_DEVID 0x0200
  89. #define MCP9804_DEVID_MASK 0xfffc
  90. #define MCP98242_DEVID 0x2000
  91. #define MCP98242_DEVID_MASK 0xfffc
  92. #define MCP98243_DEVID 0x2100
  93. #define MCP98243_DEVID_MASK 0xfffc
  94. #define MCP98244_DEVID 0x2200
  95. #define MCP98244_DEVID_MASK 0xfffc
  96. #define MCP9843_DEVID 0x0000 /* Also matches mcp9805 */
  97. #define MCP9843_DEVID_MASK 0xfffe
  98. /* NXP */
  99. #define SE97_DEVID 0xa200
  100. #define SE97_DEVID_MASK 0xfffc
  101. #define SE98_DEVID 0xa100
  102. #define SE98_DEVID_MASK 0xfffc
  103. /* ON Semiconductor */
  104. #define CAT6095_DEVID 0x0800 /* Also matches CAT34TS02 */
  105. #define CAT6095_DEVID_MASK 0xffe0
  106. /* ST Microelectronics */
  107. #define STTS424_DEVID 0x0101
  108. #define STTS424_DEVID_MASK 0xffff
  109. #define STTS424E_DEVID 0x0000
  110. #define STTS424E_DEVID_MASK 0xfffe
  111. #define STTS2002_DEVID 0x0300
  112. #define STTS2002_DEVID_MASK 0xffff
  113. #define STTS2004_DEVID 0x2201
  114. #define STTS2004_DEVID_MASK 0xffff
  115. #define STTS3000_DEVID 0x0200
  116. #define STTS3000_DEVID_MASK 0xffff
  117. static u16 jc42_hysteresis[] = { 0, 1500, 3000, 6000 };
  118. struct jc42_chips {
  119. u16 manid;
  120. u16 devid;
  121. u16 devid_mask;
  122. };
  123. static struct jc42_chips jc42_chips[] = {
  124. { ADT_MANID, ADT7408_DEVID, ADT7408_DEVID_MASK },
  125. { ATMEL_MANID, AT30TS00_DEVID, AT30TS00_DEVID_MASK },
  126. { ATMEL_MANID2, AT30TSE004_DEVID, AT30TSE004_DEVID_MASK },
  127. { IDT_MANID, TSE2004_DEVID, TSE2004_DEVID_MASK },
  128. { IDT_MANID, TS3000_DEVID, TS3000_DEVID_MASK },
  129. { IDT_MANID, TS3001_DEVID, TS3001_DEVID_MASK },
  130. { MAX_MANID, MAX6604_DEVID, MAX6604_DEVID_MASK },
  131. { MCP_MANID, MCP9804_DEVID, MCP9804_DEVID_MASK },
  132. { MCP_MANID, MCP98242_DEVID, MCP98242_DEVID_MASK },
  133. { MCP_MANID, MCP98243_DEVID, MCP98243_DEVID_MASK },
  134. { MCP_MANID, MCP98244_DEVID, MCP98244_DEVID_MASK },
  135. { MCP_MANID, MCP9843_DEVID, MCP9843_DEVID_MASK },
  136. { NXP_MANID, SE97_DEVID, SE97_DEVID_MASK },
  137. { ONS_MANID, CAT6095_DEVID, CAT6095_DEVID_MASK },
  138. { NXP_MANID, SE98_DEVID, SE98_DEVID_MASK },
  139. { STM_MANID, STTS424_DEVID, STTS424_DEVID_MASK },
  140. { STM_MANID, STTS424E_DEVID, STTS424E_DEVID_MASK },
  141. { STM_MANID, STTS2002_DEVID, STTS2002_DEVID_MASK },
  142. { STM_MANID, STTS2004_DEVID, STTS2004_DEVID_MASK },
  143. { STM_MANID, STTS3000_DEVID, STTS3000_DEVID_MASK },
  144. };
  145. enum temp_index {
  146. t_input = 0,
  147. t_crit,
  148. t_min,
  149. t_max,
  150. t_num_temp
  151. };
  152. static const u8 temp_regs[t_num_temp] = {
  153. [t_input] = JC42_REG_TEMP,
  154. [t_crit] = JC42_REG_TEMP_CRITICAL,
  155. [t_min] = JC42_REG_TEMP_LOWER,
  156. [t_max] = JC42_REG_TEMP_UPPER,
  157. };
  158. /* Each client has this additional data */
  159. struct jc42_data {
  160. struct i2c_client *client;
  161. struct mutex update_lock; /* protect register access */
  162. bool extended; /* true if extended range supported */
  163. bool valid;
  164. unsigned long last_updated; /* In jiffies */
  165. u16 orig_config; /* original configuration */
  166. u16 config; /* current configuration */
  167. u16 temp[t_num_temp];/* Temperatures */
  168. };
  169. #define JC42_TEMP_MIN_EXTENDED (-40000)
  170. #define JC42_TEMP_MIN 0
  171. #define JC42_TEMP_MAX 125000
  172. static u16 jc42_temp_to_reg(long temp, bool extended)
  173. {
  174. int ntemp = clamp_val(temp,
  175. extended ? JC42_TEMP_MIN_EXTENDED :
  176. JC42_TEMP_MIN, JC42_TEMP_MAX);
  177. /* convert from 0.001 to 0.0625 resolution */
  178. return (ntemp * 2 / 125) & 0x1fff;
  179. }
  180. static int jc42_temp_from_reg(s16 reg)
  181. {
  182. reg = sign_extend32(reg, 12);
  183. /* convert from 0.0625 to 0.001 resolution */
  184. return reg * 125 / 2;
  185. }
  186. static struct jc42_data *jc42_update_device(struct device *dev)
  187. {
  188. struct jc42_data *data = dev_get_drvdata(dev);
  189. struct i2c_client *client = data->client;
  190. struct jc42_data *ret = data;
  191. int i, val;
  192. mutex_lock(&data->update_lock);
  193. if (time_after(jiffies, data->last_updated + HZ) || !data->valid) {
  194. for (i = 0; i < t_num_temp; i++) {
  195. val = i2c_smbus_read_word_swapped(client, temp_regs[i]);
  196. if (val < 0) {
  197. ret = ERR_PTR(val);
  198. goto abort;
  199. }
  200. data->temp[i] = val;
  201. }
  202. data->last_updated = jiffies;
  203. data->valid = true;
  204. }
  205. abort:
  206. mutex_unlock(&data->update_lock);
  207. return ret;
  208. }
  209. /* sysfs functions */
  210. static ssize_t show_temp(struct device *dev, struct device_attribute *devattr,
  211. char *buf)
  212. {
  213. struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr);
  214. struct jc42_data *data = jc42_update_device(dev);
  215. if (IS_ERR(data))
  216. return PTR_ERR(data);
  217. return sprintf(buf, "%d\n",
  218. jc42_temp_from_reg(data->temp[attr->index]));
  219. }
  220. static ssize_t show_temp_hyst(struct device *dev,
  221. struct device_attribute *devattr, char *buf)
  222. {
  223. struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr);
  224. struct jc42_data *data = jc42_update_device(dev);
  225. int temp, hyst;
  226. if (IS_ERR(data))
  227. return PTR_ERR(data);
  228. temp = jc42_temp_from_reg(data->temp[attr->index]);
  229. hyst = jc42_hysteresis[(data->config & JC42_CFG_HYST_MASK)
  230. >> JC42_CFG_HYST_SHIFT];
  231. return sprintf(buf, "%d\n", temp - hyst);
  232. }
  233. static ssize_t set_temp(struct device *dev, struct device_attribute *devattr,
  234. const char *buf, size_t count)
  235. {
  236. struct sensor_device_attribute *attr = to_sensor_dev_attr(devattr);
  237. struct jc42_data *data = dev_get_drvdata(dev);
  238. int err, ret = count;
  239. int nr = attr->index;
  240. long val;
  241. if (kstrtol(buf, 10, &val) < 0)
  242. return -EINVAL;
  243. mutex_lock(&data->update_lock);
  244. data->temp[nr] = jc42_temp_to_reg(val, data->extended);
  245. err = i2c_smbus_write_word_swapped(data->client, temp_regs[nr],
  246. data->temp[nr]);
  247. if (err < 0)
  248. ret = err;
  249. mutex_unlock(&data->update_lock);
  250. return ret;
  251. }
  252. /*
  253. * JC42.4 compliant chips only support four hysteresis values.
  254. * Pick best choice and go from there.
  255. */
  256. static ssize_t set_temp_crit_hyst(struct device *dev,
  257. struct device_attribute *attr,
  258. const char *buf, size_t count)
  259. {
  260. struct jc42_data *data = dev_get_drvdata(dev);
  261. long val;
  262. int diff, hyst;
  263. int err;
  264. int ret = count;
  265. if (kstrtol(buf, 10, &val) < 0)
  266. return -EINVAL;
  267. val = clamp_val(val, (data->extended ? JC42_TEMP_MIN_EXTENDED :
  268. JC42_TEMP_MIN) - 6000, JC42_TEMP_MAX);
  269. diff = jc42_temp_from_reg(data->temp[t_crit]) - val;
  270. hyst = 0;
  271. if (diff > 0) {
  272. if (diff < 2250)
  273. hyst = 1; /* 1.5 degrees C */
  274. else if (diff < 4500)
  275. hyst = 2; /* 3.0 degrees C */
  276. else
  277. hyst = 3; /* 6.0 degrees C */
  278. }
  279. mutex_lock(&data->update_lock);
  280. data->config = (data->config & ~JC42_CFG_HYST_MASK)
  281. | (hyst << JC42_CFG_HYST_SHIFT);
  282. err = i2c_smbus_write_word_swapped(data->client, JC42_REG_CONFIG,
  283. data->config);
  284. if (err < 0)
  285. ret = err;
  286. mutex_unlock(&data->update_lock);
  287. return ret;
  288. }
  289. static ssize_t show_alarm(struct device *dev,
  290. struct device_attribute *attr, char *buf)
  291. {
  292. u16 bit = to_sensor_dev_attr(attr)->index;
  293. struct jc42_data *data = jc42_update_device(dev);
  294. u16 val;
  295. if (IS_ERR(data))
  296. return PTR_ERR(data);
  297. val = data->temp[t_input];
  298. if (bit != JC42_ALARM_CRIT_BIT && (data->config & JC42_CFG_CRIT_ONLY))
  299. val = 0;
  300. return sprintf(buf, "%u\n", (val >> bit) & 1);
  301. }
  302. static SENSOR_DEVICE_ATTR(temp1_input, S_IRUGO, show_temp, NULL, t_input);
  303. static SENSOR_DEVICE_ATTR(temp1_crit, S_IRUGO, show_temp, set_temp, t_crit);
  304. static SENSOR_DEVICE_ATTR(temp1_min, S_IRUGO, show_temp, set_temp, t_min);
  305. static SENSOR_DEVICE_ATTR(temp1_max, S_IRUGO, show_temp, set_temp, t_max);
  306. static SENSOR_DEVICE_ATTR(temp1_crit_hyst, S_IRUGO, show_temp_hyst,
  307. set_temp_crit_hyst, t_crit);
  308. static SENSOR_DEVICE_ATTR(temp1_max_hyst, S_IRUGO, show_temp_hyst, NULL, t_max);
  309. static SENSOR_DEVICE_ATTR(temp1_crit_alarm, S_IRUGO, show_alarm, NULL,
  310. JC42_ALARM_CRIT_BIT);
  311. static SENSOR_DEVICE_ATTR(temp1_min_alarm, S_IRUGO, show_alarm, NULL,
  312. JC42_ALARM_MIN_BIT);
  313. static SENSOR_DEVICE_ATTR(temp1_max_alarm, S_IRUGO, show_alarm, NULL,
  314. JC42_ALARM_MAX_BIT);
  315. static struct attribute *jc42_attributes[] = {
  316. &sensor_dev_attr_temp1_input.dev_attr.attr,
  317. &sensor_dev_attr_temp1_crit.dev_attr.attr,
  318. &sensor_dev_attr_temp1_min.dev_attr.attr,
  319. &sensor_dev_attr_temp1_max.dev_attr.attr,
  320. &sensor_dev_attr_temp1_crit_hyst.dev_attr.attr,
  321. &sensor_dev_attr_temp1_max_hyst.dev_attr.attr,
  322. &sensor_dev_attr_temp1_crit_alarm.dev_attr.attr,
  323. &sensor_dev_attr_temp1_min_alarm.dev_attr.attr,
  324. &sensor_dev_attr_temp1_max_alarm.dev_attr.attr,
  325. NULL
  326. };
  327. static umode_t jc42_attribute_mode(struct kobject *kobj,
  328. struct attribute *attr, int index)
  329. {
  330. struct device *dev = container_of(kobj, struct device, kobj);
  331. struct jc42_data *data = dev_get_drvdata(dev);
  332. unsigned int config = data->config;
  333. bool readonly;
  334. if (attr == &sensor_dev_attr_temp1_crit.dev_attr.attr)
  335. readonly = config & JC42_CFG_TCRIT_LOCK;
  336. else if (attr == &sensor_dev_attr_temp1_min.dev_attr.attr ||
  337. attr == &sensor_dev_attr_temp1_max.dev_attr.attr)
  338. readonly = config & JC42_CFG_EVENT_LOCK;
  339. else if (attr == &sensor_dev_attr_temp1_crit_hyst.dev_attr.attr)
  340. readonly = config & (JC42_CFG_EVENT_LOCK | JC42_CFG_TCRIT_LOCK);
  341. else
  342. readonly = true;
  343. return S_IRUGO | (readonly ? 0 : S_IWUSR);
  344. }
  345. static const struct attribute_group jc42_group = {
  346. .attrs = jc42_attributes,
  347. .is_visible = jc42_attribute_mode,
  348. };
  349. __ATTRIBUTE_GROUPS(jc42);
  350. /* Return 0 if detection is successful, -ENODEV otherwise */
  351. static int jc42_detect(struct i2c_client *client, struct i2c_board_info *info)
  352. {
  353. struct i2c_adapter *adapter = client->adapter;
  354. int i, config, cap, manid, devid;
  355. if (!i2c_check_functionality(adapter, I2C_FUNC_SMBUS_BYTE_DATA |
  356. I2C_FUNC_SMBUS_WORD_DATA))
  357. return -ENODEV;
  358. cap = i2c_smbus_read_word_swapped(client, JC42_REG_CAP);
  359. config = i2c_smbus_read_word_swapped(client, JC42_REG_CONFIG);
  360. manid = i2c_smbus_read_word_swapped(client, JC42_REG_MANID);
  361. devid = i2c_smbus_read_word_swapped(client, JC42_REG_DEVICEID);
  362. if (cap < 0 || config < 0 || manid < 0 || devid < 0)
  363. return -ENODEV;
  364. if ((cap & 0xff00) || (config & 0xf800))
  365. return -ENODEV;
  366. for (i = 0; i < ARRAY_SIZE(jc42_chips); i++) {
  367. struct jc42_chips *chip = &jc42_chips[i];
  368. if (manid == chip->manid &&
  369. (devid & chip->devid_mask) == chip->devid) {
  370. strlcpy(info->type, "jc42", I2C_NAME_SIZE);
  371. return 0;
  372. }
  373. }
  374. return -ENODEV;
  375. }
  376. static int jc42_probe(struct i2c_client *client, const struct i2c_device_id *id)
  377. {
  378. struct device *dev = &client->dev;
  379. struct device *hwmon_dev;
  380. struct jc42_data *data;
  381. int config, cap;
  382. data = devm_kzalloc(dev, sizeof(struct jc42_data), GFP_KERNEL);
  383. if (!data)
  384. return -ENOMEM;
  385. data->client = client;
  386. i2c_set_clientdata(client, data);
  387. mutex_init(&data->update_lock);
  388. cap = i2c_smbus_read_word_swapped(client, JC42_REG_CAP);
  389. if (cap < 0)
  390. return cap;
  391. data->extended = !!(cap & JC42_CAP_RANGE);
  392. config = i2c_smbus_read_word_swapped(client, JC42_REG_CONFIG);
  393. if (config < 0)
  394. return config;
  395. data->orig_config = config;
  396. if (config & JC42_CFG_SHUTDOWN) {
  397. config &= ~JC42_CFG_SHUTDOWN;
  398. i2c_smbus_write_word_swapped(client, JC42_REG_CONFIG, config);
  399. }
  400. data->config = config;
  401. hwmon_dev = devm_hwmon_device_register_with_groups(dev, client->name,
  402. data,
  403. jc42_groups);
  404. return PTR_ERR_OR_ZERO(hwmon_dev);
  405. }
  406. static int jc42_remove(struct i2c_client *client)
  407. {
  408. struct jc42_data *data = i2c_get_clientdata(client);
  409. /* Restore original configuration except hysteresis */
  410. if ((data->config & ~JC42_CFG_HYST_MASK) !=
  411. (data->orig_config & ~JC42_CFG_HYST_MASK)) {
  412. int config;
  413. config = (data->orig_config & ~JC42_CFG_HYST_MASK)
  414. | (data->config & JC42_CFG_HYST_MASK);
  415. i2c_smbus_write_word_swapped(client, JC42_REG_CONFIG, config);
  416. }
  417. return 0;
  418. }
  419. #ifdef CONFIG_PM
  420. static int jc42_suspend(struct device *dev)
  421. {
  422. struct jc42_data *data = dev_get_drvdata(dev);
  423. data->config |= JC42_CFG_SHUTDOWN;
  424. i2c_smbus_write_word_swapped(data->client, JC42_REG_CONFIG,
  425. data->config);
  426. return 0;
  427. }
  428. static int jc42_resume(struct device *dev)
  429. {
  430. struct jc42_data *data = dev_get_drvdata(dev);
  431. data->config &= ~JC42_CFG_SHUTDOWN;
  432. i2c_smbus_write_word_swapped(data->client, JC42_REG_CONFIG,
  433. data->config);
  434. return 0;
  435. }
  436. static const struct dev_pm_ops jc42_dev_pm_ops = {
  437. .suspend = jc42_suspend,
  438. .resume = jc42_resume,
  439. };
  440. #define JC42_DEV_PM_OPS (&jc42_dev_pm_ops)
  441. #else
  442. #define JC42_DEV_PM_OPS NULL
  443. #endif /* CONFIG_PM */
  444. static const struct i2c_device_id jc42_id[] = {
  445. { "jc42", 0 },
  446. { }
  447. };
  448. MODULE_DEVICE_TABLE(i2c, jc42_id);
  449. static struct i2c_driver jc42_driver = {
  450. .class = I2C_CLASS_SPD,
  451. .driver = {
  452. .name = "jc42",
  453. .pm = JC42_DEV_PM_OPS,
  454. },
  455. .probe = jc42_probe,
  456. .remove = jc42_remove,
  457. .id_table = jc42_id,
  458. .detect = jc42_detect,
  459. .address_list = normal_i2c,
  460. };
  461. module_i2c_driver(jc42_driver);
  462. MODULE_AUTHOR("Guenter Roeck <linux@roeck-us.net>");
  463. MODULE_DESCRIPTION("JC42 driver");
  464. MODULE_LICENSE("GPL");