i2c-iop3xx.c 12 KB

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  1. /* ------------------------------------------------------------------------- */
  2. /* i2c-iop3xx.c i2c driver algorithms for Intel XScale IOP3xx & IXP46x */
  3. /* ------------------------------------------------------------------------- */
  4. /* Copyright (C) 2003 Peter Milne, D-TACQ Solutions Ltd
  5. * <Peter dot Milne at D hyphen TACQ dot com>
  6. *
  7. * With acknowledgements to i2c-algo-ibm_ocp.c by
  8. * Ian DaSilva, MontaVista Software, Inc. idasilva@mvista.com
  9. *
  10. * And i2c-algo-pcf.c, which was created by Simon G. Vogl and Hans Berglund:
  11. *
  12. * Copyright (C) 1995-1997 Simon G. Vogl, 1998-2000 Hans Berglund
  13. *
  14. * And which acknowledged Kyösti Mälkki <kmalkki@cc.hut.fi>,
  15. * Frodo Looijaard <frodol@dds.nl>, Martin Bailey<mbailey@littlefeet-inc.com>
  16. *
  17. * Major cleanup by Deepak Saxena <dsaxena@plexity.net>, 01/2005:
  18. *
  19. * - Use driver model to pass per-chip info instead of hardcoding and #ifdefs
  20. * - Use ioremap/__raw_readl/__raw_writel instead of direct dereference
  21. * - Make it work with IXP46x chips
  22. * - Cleanup function names, coding style, etc
  23. *
  24. * - writing to slave address causes latchup on iop331.
  25. * fix: driver refuses to address self.
  26. *
  27. * This program is free software; you can redistribute it and/or modify
  28. * it under the terms of the GNU General Public License as published by
  29. * the Free Software Foundation, version 2.
  30. */
  31. #include <linux/interrupt.h>
  32. #include <linux/kernel.h>
  33. #include <linux/module.h>
  34. #include <linux/delay.h>
  35. #include <linux/slab.h>
  36. #include <linux/errno.h>
  37. #include <linux/platform_device.h>
  38. #include <linux/i2c.h>
  39. #include <linux/io.h>
  40. #include <linux/gpio.h>
  41. #include "i2c-iop3xx.h"
  42. /* global unit counter */
  43. static int i2c_id;
  44. static inline unsigned char
  45. iic_cook_addr(struct i2c_msg *msg)
  46. {
  47. unsigned char addr;
  48. addr = (msg->addr << 1);
  49. if (msg->flags & I2C_M_RD)
  50. addr |= 1;
  51. return addr;
  52. }
  53. static void
  54. iop3xx_i2c_reset(struct i2c_algo_iop3xx_data *iop3xx_adap)
  55. {
  56. /* Follows devman 9.3 */
  57. __raw_writel(IOP3XX_ICR_UNIT_RESET, iop3xx_adap->ioaddr + CR_OFFSET);
  58. __raw_writel(IOP3XX_ISR_CLEARBITS, iop3xx_adap->ioaddr + SR_OFFSET);
  59. __raw_writel(0, iop3xx_adap->ioaddr + CR_OFFSET);
  60. }
  61. static void
  62. iop3xx_i2c_enable(struct i2c_algo_iop3xx_data *iop3xx_adap)
  63. {
  64. u32 cr = IOP3XX_ICR_GCD | IOP3XX_ICR_SCLEN | IOP3XX_ICR_UE;
  65. /*
  66. * Every time unit enable is asserted, GPOD needs to be cleared
  67. * on IOP3XX to avoid data corruption on the bus.
  68. */
  69. #if defined(CONFIG_ARCH_IOP32X) || defined(CONFIG_ARCH_IOP33X)
  70. if (iop3xx_adap->id == 0) {
  71. gpio_set_value(7, 0);
  72. gpio_set_value(6, 0);
  73. } else {
  74. gpio_set_value(5, 0);
  75. gpio_set_value(4, 0);
  76. }
  77. #endif
  78. /* NB SR bits not same position as CR IE bits :-( */
  79. iop3xx_adap->SR_enabled =
  80. IOP3XX_ISR_ALD | IOP3XX_ISR_BERRD |
  81. IOP3XX_ISR_RXFULL | IOP3XX_ISR_TXEMPTY;
  82. cr |= IOP3XX_ICR_ALD_IE | IOP3XX_ICR_BERR_IE |
  83. IOP3XX_ICR_RXFULL_IE | IOP3XX_ICR_TXEMPTY_IE;
  84. __raw_writel(cr, iop3xx_adap->ioaddr + CR_OFFSET);
  85. }
  86. static void
  87. iop3xx_i2c_transaction_cleanup(struct i2c_algo_iop3xx_data *iop3xx_adap)
  88. {
  89. unsigned long cr = __raw_readl(iop3xx_adap->ioaddr + CR_OFFSET);
  90. cr &= ~(IOP3XX_ICR_MSTART | IOP3XX_ICR_TBYTE |
  91. IOP3XX_ICR_MSTOP | IOP3XX_ICR_SCLEN);
  92. __raw_writel(cr, iop3xx_adap->ioaddr + CR_OFFSET);
  93. }
  94. /*
  95. * NB: the handler has to clear the source of the interrupt!
  96. * Then it passes the SR flags of interest to BH via adap data
  97. */
  98. static irqreturn_t
  99. iop3xx_i2c_irq_handler(int this_irq, void *dev_id)
  100. {
  101. struct i2c_algo_iop3xx_data *iop3xx_adap = dev_id;
  102. u32 sr = __raw_readl(iop3xx_adap->ioaddr + SR_OFFSET);
  103. if ((sr &= iop3xx_adap->SR_enabled)) {
  104. __raw_writel(sr, iop3xx_adap->ioaddr + SR_OFFSET);
  105. iop3xx_adap->SR_received |= sr;
  106. wake_up_interruptible(&iop3xx_adap->waitq);
  107. }
  108. return IRQ_HANDLED;
  109. }
  110. /* check all error conditions, clear them , report most important */
  111. static int
  112. iop3xx_i2c_error(u32 sr)
  113. {
  114. int rc = 0;
  115. if ((sr & IOP3XX_ISR_BERRD)) {
  116. if ( !rc ) rc = -I2C_ERR_BERR;
  117. }
  118. if ((sr & IOP3XX_ISR_ALD)) {
  119. if ( !rc ) rc = -I2C_ERR_ALD;
  120. }
  121. return rc;
  122. }
  123. static inline u32
  124. iop3xx_i2c_get_srstat(struct i2c_algo_iop3xx_data *iop3xx_adap)
  125. {
  126. unsigned long flags;
  127. u32 sr;
  128. spin_lock_irqsave(&iop3xx_adap->lock, flags);
  129. sr = iop3xx_adap->SR_received;
  130. iop3xx_adap->SR_received = 0;
  131. spin_unlock_irqrestore(&iop3xx_adap->lock, flags);
  132. return sr;
  133. }
  134. /*
  135. * sleep until interrupted, then recover and analyse the SR
  136. * saved by handler
  137. */
  138. typedef int (* compare_func)(unsigned test, unsigned mask);
  139. /* returns 1 on correct comparison */
  140. static int
  141. iop3xx_i2c_wait_event(struct i2c_algo_iop3xx_data *iop3xx_adap,
  142. unsigned flags, unsigned* status,
  143. compare_func compare)
  144. {
  145. unsigned sr = 0;
  146. int interrupted;
  147. int done;
  148. int rc = 0;
  149. do {
  150. interrupted = wait_event_interruptible_timeout (
  151. iop3xx_adap->waitq,
  152. (done = compare( sr = iop3xx_i2c_get_srstat(iop3xx_adap) ,flags )),
  153. 1 * HZ
  154. );
  155. if ((rc = iop3xx_i2c_error(sr)) < 0) {
  156. *status = sr;
  157. return rc;
  158. } else if (!interrupted) {
  159. *status = sr;
  160. return -ETIMEDOUT;
  161. }
  162. } while(!done);
  163. *status = sr;
  164. return 0;
  165. }
  166. /*
  167. * Concrete compare_funcs
  168. */
  169. static int
  170. all_bits_clear(unsigned test, unsigned mask)
  171. {
  172. return (test & mask) == 0;
  173. }
  174. static int
  175. any_bits_set(unsigned test, unsigned mask)
  176. {
  177. return (test & mask) != 0;
  178. }
  179. static int
  180. iop3xx_i2c_wait_tx_done(struct i2c_algo_iop3xx_data *iop3xx_adap, int *status)
  181. {
  182. return iop3xx_i2c_wait_event(
  183. iop3xx_adap,
  184. IOP3XX_ISR_TXEMPTY | IOP3XX_ISR_ALD | IOP3XX_ISR_BERRD,
  185. status, any_bits_set);
  186. }
  187. static int
  188. iop3xx_i2c_wait_rx_done(struct i2c_algo_iop3xx_data *iop3xx_adap, int *status)
  189. {
  190. return iop3xx_i2c_wait_event(
  191. iop3xx_adap,
  192. IOP3XX_ISR_RXFULL | IOP3XX_ISR_ALD | IOP3XX_ISR_BERRD,
  193. status, any_bits_set);
  194. }
  195. static int
  196. iop3xx_i2c_wait_idle(struct i2c_algo_iop3xx_data *iop3xx_adap, int *status)
  197. {
  198. return iop3xx_i2c_wait_event(
  199. iop3xx_adap, IOP3XX_ISR_UNITBUSY, status, all_bits_clear);
  200. }
  201. static int
  202. iop3xx_i2c_send_target_addr(struct i2c_algo_iop3xx_data *iop3xx_adap,
  203. struct i2c_msg* msg)
  204. {
  205. unsigned long cr = __raw_readl(iop3xx_adap->ioaddr + CR_OFFSET);
  206. int status;
  207. int rc;
  208. /* avoid writing to my slave address (hangs on 80331),
  209. * forbidden in Intel developer manual
  210. */
  211. if (msg->addr == MYSAR) {
  212. return -EBUSY;
  213. }
  214. __raw_writel(iic_cook_addr(msg), iop3xx_adap->ioaddr + DBR_OFFSET);
  215. cr &= ~(IOP3XX_ICR_MSTOP | IOP3XX_ICR_NACK);
  216. cr |= IOP3XX_ICR_MSTART | IOP3XX_ICR_TBYTE;
  217. __raw_writel(cr, iop3xx_adap->ioaddr + CR_OFFSET);
  218. rc = iop3xx_i2c_wait_tx_done(iop3xx_adap, &status);
  219. return rc;
  220. }
  221. static int
  222. iop3xx_i2c_write_byte(struct i2c_algo_iop3xx_data *iop3xx_adap, char byte,
  223. int stop)
  224. {
  225. unsigned long cr = __raw_readl(iop3xx_adap->ioaddr + CR_OFFSET);
  226. int status;
  227. int rc = 0;
  228. __raw_writel(byte, iop3xx_adap->ioaddr + DBR_OFFSET);
  229. cr &= ~IOP3XX_ICR_MSTART;
  230. if (stop) {
  231. cr |= IOP3XX_ICR_MSTOP;
  232. } else {
  233. cr &= ~IOP3XX_ICR_MSTOP;
  234. }
  235. cr |= IOP3XX_ICR_TBYTE;
  236. __raw_writel(cr, iop3xx_adap->ioaddr + CR_OFFSET);
  237. rc = iop3xx_i2c_wait_tx_done(iop3xx_adap, &status);
  238. return rc;
  239. }
  240. static int
  241. iop3xx_i2c_read_byte(struct i2c_algo_iop3xx_data *iop3xx_adap, char* byte,
  242. int stop)
  243. {
  244. unsigned long cr = __raw_readl(iop3xx_adap->ioaddr + CR_OFFSET);
  245. int status;
  246. int rc = 0;
  247. cr &= ~IOP3XX_ICR_MSTART;
  248. if (stop) {
  249. cr |= IOP3XX_ICR_MSTOP | IOP3XX_ICR_NACK;
  250. } else {
  251. cr &= ~(IOP3XX_ICR_MSTOP | IOP3XX_ICR_NACK);
  252. }
  253. cr |= IOP3XX_ICR_TBYTE;
  254. __raw_writel(cr, iop3xx_adap->ioaddr + CR_OFFSET);
  255. rc = iop3xx_i2c_wait_rx_done(iop3xx_adap, &status);
  256. *byte = __raw_readl(iop3xx_adap->ioaddr + DBR_OFFSET);
  257. return rc;
  258. }
  259. static int
  260. iop3xx_i2c_writebytes(struct i2c_adapter *i2c_adap, const char *buf, int count)
  261. {
  262. struct i2c_algo_iop3xx_data *iop3xx_adap = i2c_adap->algo_data;
  263. int ii;
  264. int rc = 0;
  265. for (ii = 0; rc == 0 && ii != count; ++ii)
  266. rc = iop3xx_i2c_write_byte(iop3xx_adap, buf[ii], ii==count-1);
  267. return rc;
  268. }
  269. static int
  270. iop3xx_i2c_readbytes(struct i2c_adapter *i2c_adap, char *buf, int count)
  271. {
  272. struct i2c_algo_iop3xx_data *iop3xx_adap = i2c_adap->algo_data;
  273. int ii;
  274. int rc = 0;
  275. for (ii = 0; rc == 0 && ii != count; ++ii)
  276. rc = iop3xx_i2c_read_byte(iop3xx_adap, &buf[ii], ii==count-1);
  277. return rc;
  278. }
  279. /*
  280. * Description: This function implements combined transactions. Combined
  281. * transactions consist of combinations of reading and writing blocks of data.
  282. * FROM THE SAME ADDRESS
  283. * Each transfer (i.e. a read or a write) is separated by a repeated start
  284. * condition.
  285. */
  286. static int
  287. iop3xx_i2c_handle_msg(struct i2c_adapter *i2c_adap, struct i2c_msg* pmsg)
  288. {
  289. struct i2c_algo_iop3xx_data *iop3xx_adap = i2c_adap->algo_data;
  290. int rc;
  291. rc = iop3xx_i2c_send_target_addr(iop3xx_adap, pmsg);
  292. if (rc < 0) {
  293. return rc;
  294. }
  295. if ((pmsg->flags&I2C_M_RD)) {
  296. return iop3xx_i2c_readbytes(i2c_adap, pmsg->buf, pmsg->len);
  297. } else {
  298. return iop3xx_i2c_writebytes(i2c_adap, pmsg->buf, pmsg->len);
  299. }
  300. }
  301. /*
  302. * master_xfer() - main read/write entry
  303. */
  304. static int
  305. iop3xx_i2c_master_xfer(struct i2c_adapter *i2c_adap, struct i2c_msg *msgs,
  306. int num)
  307. {
  308. struct i2c_algo_iop3xx_data *iop3xx_adap = i2c_adap->algo_data;
  309. int im = 0;
  310. int ret = 0;
  311. int status;
  312. iop3xx_i2c_wait_idle(iop3xx_adap, &status);
  313. iop3xx_i2c_reset(iop3xx_adap);
  314. iop3xx_i2c_enable(iop3xx_adap);
  315. for (im = 0; ret == 0 && im != num; im++) {
  316. ret = iop3xx_i2c_handle_msg(i2c_adap, &msgs[im]);
  317. }
  318. iop3xx_i2c_transaction_cleanup(iop3xx_adap);
  319. if(ret)
  320. return ret;
  321. return im;
  322. }
  323. static u32
  324. iop3xx_i2c_func(struct i2c_adapter *adap)
  325. {
  326. return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL;
  327. }
  328. static const struct i2c_algorithm iop3xx_i2c_algo = {
  329. .master_xfer = iop3xx_i2c_master_xfer,
  330. .functionality = iop3xx_i2c_func,
  331. };
  332. static int
  333. iop3xx_i2c_remove(struct platform_device *pdev)
  334. {
  335. struct i2c_adapter *padapter = platform_get_drvdata(pdev);
  336. struct i2c_algo_iop3xx_data *adapter_data =
  337. (struct i2c_algo_iop3xx_data *)padapter->algo_data;
  338. struct resource *res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  339. unsigned long cr = __raw_readl(adapter_data->ioaddr + CR_OFFSET);
  340. /*
  341. * Disable the actual HW unit
  342. */
  343. cr &= ~(IOP3XX_ICR_ALD_IE | IOP3XX_ICR_BERR_IE |
  344. IOP3XX_ICR_RXFULL_IE | IOP3XX_ICR_TXEMPTY_IE);
  345. __raw_writel(cr, adapter_data->ioaddr + CR_OFFSET);
  346. iounmap(adapter_data->ioaddr);
  347. release_mem_region(res->start, IOP3XX_I2C_IO_SIZE);
  348. kfree(adapter_data);
  349. kfree(padapter);
  350. return 0;
  351. }
  352. static int
  353. iop3xx_i2c_probe(struct platform_device *pdev)
  354. {
  355. struct resource *res;
  356. int ret, irq;
  357. struct i2c_adapter *new_adapter;
  358. struct i2c_algo_iop3xx_data *adapter_data;
  359. new_adapter = kzalloc(sizeof(struct i2c_adapter), GFP_KERNEL);
  360. if (!new_adapter) {
  361. ret = -ENOMEM;
  362. goto out;
  363. }
  364. adapter_data = kzalloc(sizeof(struct i2c_algo_iop3xx_data), GFP_KERNEL);
  365. if (!adapter_data) {
  366. ret = -ENOMEM;
  367. goto free_adapter;
  368. }
  369. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  370. if (!res) {
  371. ret = -ENODEV;
  372. goto free_both;
  373. }
  374. if (!request_mem_region(res->start, IOP3XX_I2C_IO_SIZE, pdev->name)) {
  375. ret = -EBUSY;
  376. goto free_both;
  377. }
  378. /* set the adapter enumeration # */
  379. adapter_data->id = i2c_id++;
  380. adapter_data->ioaddr = ioremap(res->start, IOP3XX_I2C_IO_SIZE);
  381. if (!adapter_data->ioaddr) {
  382. ret = -ENOMEM;
  383. goto release_region;
  384. }
  385. irq = platform_get_irq(pdev, 0);
  386. if (irq < 0) {
  387. ret = -ENXIO;
  388. goto unmap;
  389. }
  390. ret = request_irq(irq, iop3xx_i2c_irq_handler, 0,
  391. pdev->name, adapter_data);
  392. if (ret) {
  393. ret = -EIO;
  394. goto unmap;
  395. }
  396. memcpy(new_adapter->name, pdev->name, strlen(pdev->name));
  397. new_adapter->owner = THIS_MODULE;
  398. new_adapter->class = I2C_CLASS_HWMON | I2C_CLASS_SPD;
  399. new_adapter->dev.parent = &pdev->dev;
  400. new_adapter->nr = pdev->id;
  401. /*
  402. * Default values...should these come in from board code?
  403. */
  404. new_adapter->timeout = HZ;
  405. new_adapter->algo = &iop3xx_i2c_algo;
  406. init_waitqueue_head(&adapter_data->waitq);
  407. spin_lock_init(&adapter_data->lock);
  408. iop3xx_i2c_reset(adapter_data);
  409. iop3xx_i2c_enable(adapter_data);
  410. platform_set_drvdata(pdev, new_adapter);
  411. new_adapter->algo_data = adapter_data;
  412. i2c_add_numbered_adapter(new_adapter);
  413. return 0;
  414. unmap:
  415. iounmap(adapter_data->ioaddr);
  416. release_region:
  417. release_mem_region(res->start, IOP3XX_I2C_IO_SIZE);
  418. free_both:
  419. kfree(adapter_data);
  420. free_adapter:
  421. kfree(new_adapter);
  422. out:
  423. return ret;
  424. }
  425. static struct platform_driver iop3xx_i2c_driver = {
  426. .probe = iop3xx_i2c_probe,
  427. .remove = iop3xx_i2c_remove,
  428. .driver = {
  429. .name = "IOP3xx-I2C",
  430. },
  431. };
  432. module_platform_driver(iop3xx_i2c_driver);
  433. MODULE_AUTHOR("D-TACQ Solutions Ltd <www.d-tacq.com>");
  434. MODULE_DESCRIPTION("IOP3xx iic algorithm and driver");
  435. MODULE_LICENSE("GPL");
  436. MODULE_ALIAS("platform:IOP3xx-I2C");