i2c-nforce2.c 13 KB

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  1. /*
  2. SMBus driver for nVidia nForce2 MCP
  3. Added nForce3 Pro 150 Thomas Leibold <thomas@plx.com>,
  4. Ported to 2.5 Patrick Dreker <patrick@dreker.de>,
  5. Copyright (c) 2003 Hans-Frieder Vogt <hfvogt@arcor.de>,
  6. Based on
  7. SMBus 2.0 driver for AMD-8111 IO-Hub
  8. Copyright (c) 2002 Vojtech Pavlik
  9. This program is free software; you can redistribute it and/or modify
  10. it under the terms of the GNU General Public License as published by
  11. the Free Software Foundation; either version 2 of the License, or
  12. (at your option) any later version.
  13. This program is distributed in the hope that it will be useful,
  14. but WITHOUT ANY WARRANTY; without even the implied warranty of
  15. MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16. GNU General Public License for more details.
  17. */
  18. /*
  19. SUPPORTED DEVICES PCI ID
  20. nForce2 MCP 0064
  21. nForce2 Ultra 400 MCP 0084
  22. nForce3 Pro150 MCP 00D4
  23. nForce3 250Gb MCP 00E4
  24. nForce4 MCP 0052
  25. nForce4 MCP-04 0034
  26. nForce MCP51 0264
  27. nForce MCP55 0368
  28. nForce MCP61 03EB
  29. nForce MCP65 0446
  30. nForce MCP67 0542
  31. nForce MCP73 07D8
  32. nForce MCP78S 0752
  33. nForce MCP79 0AA2
  34. This driver supports the 2 SMBuses that are included in the MCP of the
  35. nForce2/3/4/5xx chipsets.
  36. */
  37. /* Note: we assume there can only be one nForce2, with two SMBus interfaces */
  38. #include <linux/module.h>
  39. #include <linux/pci.h>
  40. #include <linux/kernel.h>
  41. #include <linux/stddef.h>
  42. #include <linux/ioport.h>
  43. #include <linux/i2c.h>
  44. #include <linux/delay.h>
  45. #include <linux/dmi.h>
  46. #include <linux/acpi.h>
  47. #include <linux/slab.h>
  48. #include <linux/io.h>
  49. MODULE_LICENSE("GPL");
  50. MODULE_AUTHOR("Hans-Frieder Vogt <hfvogt@gmx.net>");
  51. MODULE_DESCRIPTION("nForce2/3/4/5xx SMBus driver");
  52. struct nforce2_smbus {
  53. struct i2c_adapter adapter;
  54. int base;
  55. int size;
  56. int blockops;
  57. int can_abort;
  58. };
  59. /*
  60. * nVidia nForce2 SMBus control register definitions
  61. * (Newer incarnations use standard BARs 4 and 5 instead)
  62. */
  63. #define NFORCE_PCI_SMB1 0x50
  64. #define NFORCE_PCI_SMB2 0x54
  65. /*
  66. * ACPI 2.0 chapter 13 SMBus 2.0 EC register model
  67. */
  68. #define NVIDIA_SMB_PRTCL (smbus->base + 0x00) /* protocol, PEC */
  69. #define NVIDIA_SMB_STS (smbus->base + 0x01) /* status */
  70. #define NVIDIA_SMB_ADDR (smbus->base + 0x02) /* address */
  71. #define NVIDIA_SMB_CMD (smbus->base + 0x03) /* command */
  72. #define NVIDIA_SMB_DATA (smbus->base + 0x04) /* 32 data registers */
  73. #define NVIDIA_SMB_BCNT (smbus->base + 0x24) /* number of data
  74. bytes */
  75. #define NVIDIA_SMB_STATUS_ABRT (smbus->base + 0x3c) /* register used to
  76. check the status of
  77. the abort command */
  78. #define NVIDIA_SMB_CTRL (smbus->base + 0x3e) /* control register */
  79. #define NVIDIA_SMB_STATUS_ABRT_STS 0x01 /* Bit to notify that
  80. abort succeeded */
  81. #define NVIDIA_SMB_CTRL_ABORT 0x20
  82. #define NVIDIA_SMB_STS_DONE 0x80
  83. #define NVIDIA_SMB_STS_ALRM 0x40
  84. #define NVIDIA_SMB_STS_RES 0x20
  85. #define NVIDIA_SMB_STS_STATUS 0x1f
  86. #define NVIDIA_SMB_PRTCL_WRITE 0x00
  87. #define NVIDIA_SMB_PRTCL_READ 0x01
  88. #define NVIDIA_SMB_PRTCL_QUICK 0x02
  89. #define NVIDIA_SMB_PRTCL_BYTE 0x04
  90. #define NVIDIA_SMB_PRTCL_BYTE_DATA 0x06
  91. #define NVIDIA_SMB_PRTCL_WORD_DATA 0x08
  92. #define NVIDIA_SMB_PRTCL_BLOCK_DATA 0x0a
  93. #define NVIDIA_SMB_PRTCL_PEC 0x80
  94. /* Misc definitions */
  95. #define MAX_TIMEOUT 100
  96. /* We disable the second SMBus channel on these boards */
  97. static const struct dmi_system_id nforce2_dmi_blacklist2[] = {
  98. {
  99. .ident = "DFI Lanparty NF4 Expert",
  100. .matches = {
  101. DMI_MATCH(DMI_BOARD_VENDOR, "DFI Corp,LTD"),
  102. DMI_MATCH(DMI_BOARD_NAME, "LP UT NF4 Expert"),
  103. },
  104. },
  105. { }
  106. };
  107. static struct pci_driver nforce2_driver;
  108. /* For multiplexing support, we need a global reference to the 1st
  109. SMBus channel */
  110. #if defined CONFIG_I2C_NFORCE2_S4985 || defined CONFIG_I2C_NFORCE2_S4985_MODULE
  111. struct i2c_adapter *nforce2_smbus;
  112. EXPORT_SYMBOL_GPL(nforce2_smbus);
  113. static void nforce2_set_reference(struct i2c_adapter *adap)
  114. {
  115. nforce2_smbus = adap;
  116. }
  117. #else
  118. static inline void nforce2_set_reference(struct i2c_adapter *adap) { }
  119. #endif
  120. static void nforce2_abort(struct i2c_adapter *adap)
  121. {
  122. struct nforce2_smbus *smbus = adap->algo_data;
  123. int timeout = 0;
  124. unsigned char temp;
  125. dev_dbg(&adap->dev, "Aborting current transaction\n");
  126. outb_p(NVIDIA_SMB_CTRL_ABORT, NVIDIA_SMB_CTRL);
  127. do {
  128. msleep(1);
  129. temp = inb_p(NVIDIA_SMB_STATUS_ABRT);
  130. } while (!(temp & NVIDIA_SMB_STATUS_ABRT_STS) &&
  131. (timeout++ < MAX_TIMEOUT));
  132. if (!(temp & NVIDIA_SMB_STATUS_ABRT_STS))
  133. dev_err(&adap->dev, "Can't reset the smbus\n");
  134. outb_p(NVIDIA_SMB_STATUS_ABRT_STS, NVIDIA_SMB_STATUS_ABRT);
  135. }
  136. static int nforce2_check_status(struct i2c_adapter *adap)
  137. {
  138. struct nforce2_smbus *smbus = adap->algo_data;
  139. int timeout = 0;
  140. unsigned char temp;
  141. do {
  142. msleep(1);
  143. temp = inb_p(NVIDIA_SMB_STS);
  144. } while ((!temp) && (timeout++ < MAX_TIMEOUT));
  145. if (timeout > MAX_TIMEOUT) {
  146. dev_dbg(&adap->dev, "SMBus Timeout!\n");
  147. if (smbus->can_abort)
  148. nforce2_abort(adap);
  149. return -ETIMEDOUT;
  150. }
  151. if (!(temp & NVIDIA_SMB_STS_DONE) || (temp & NVIDIA_SMB_STS_STATUS)) {
  152. dev_dbg(&adap->dev, "Transaction failed (0x%02x)!\n", temp);
  153. return -EIO;
  154. }
  155. return 0;
  156. }
  157. /* Return negative errno on error */
  158. static s32 nforce2_access(struct i2c_adapter *adap, u16 addr,
  159. unsigned short flags, char read_write,
  160. u8 command, int size, union i2c_smbus_data *data)
  161. {
  162. struct nforce2_smbus *smbus = adap->algo_data;
  163. unsigned char protocol, pec;
  164. u8 len;
  165. int i, status;
  166. protocol = (read_write == I2C_SMBUS_READ) ? NVIDIA_SMB_PRTCL_READ :
  167. NVIDIA_SMB_PRTCL_WRITE;
  168. pec = (flags & I2C_CLIENT_PEC) ? NVIDIA_SMB_PRTCL_PEC : 0;
  169. switch (size) {
  170. case I2C_SMBUS_QUICK:
  171. protocol |= NVIDIA_SMB_PRTCL_QUICK;
  172. read_write = I2C_SMBUS_WRITE;
  173. break;
  174. case I2C_SMBUS_BYTE:
  175. if (read_write == I2C_SMBUS_WRITE)
  176. outb_p(command, NVIDIA_SMB_CMD);
  177. protocol |= NVIDIA_SMB_PRTCL_BYTE;
  178. break;
  179. case I2C_SMBUS_BYTE_DATA:
  180. outb_p(command, NVIDIA_SMB_CMD);
  181. if (read_write == I2C_SMBUS_WRITE)
  182. outb_p(data->byte, NVIDIA_SMB_DATA);
  183. protocol |= NVIDIA_SMB_PRTCL_BYTE_DATA;
  184. break;
  185. case I2C_SMBUS_WORD_DATA:
  186. outb_p(command, NVIDIA_SMB_CMD);
  187. if (read_write == I2C_SMBUS_WRITE) {
  188. outb_p(data->word, NVIDIA_SMB_DATA);
  189. outb_p(data->word >> 8, NVIDIA_SMB_DATA + 1);
  190. }
  191. protocol |= NVIDIA_SMB_PRTCL_WORD_DATA | pec;
  192. break;
  193. case I2C_SMBUS_BLOCK_DATA:
  194. outb_p(command, NVIDIA_SMB_CMD);
  195. if (read_write == I2C_SMBUS_WRITE) {
  196. len = data->block[0];
  197. if ((len == 0) || (len > I2C_SMBUS_BLOCK_MAX)) {
  198. dev_err(&adap->dev,
  199. "Transaction failed (requested block size: %d)\n",
  200. len);
  201. return -EINVAL;
  202. }
  203. outb_p(len, NVIDIA_SMB_BCNT);
  204. for (i = 0; i < I2C_SMBUS_BLOCK_MAX; i++)
  205. outb_p(data->block[i + 1],
  206. NVIDIA_SMB_DATA + i);
  207. }
  208. protocol |= NVIDIA_SMB_PRTCL_BLOCK_DATA | pec;
  209. break;
  210. default:
  211. dev_err(&adap->dev, "Unsupported transaction %d\n", size);
  212. return -EOPNOTSUPP;
  213. }
  214. outb_p((addr & 0x7f) << 1, NVIDIA_SMB_ADDR);
  215. outb_p(protocol, NVIDIA_SMB_PRTCL);
  216. status = nforce2_check_status(adap);
  217. if (status)
  218. return status;
  219. if (read_write == I2C_SMBUS_WRITE)
  220. return 0;
  221. switch (size) {
  222. case I2C_SMBUS_BYTE:
  223. case I2C_SMBUS_BYTE_DATA:
  224. data->byte = inb_p(NVIDIA_SMB_DATA);
  225. break;
  226. case I2C_SMBUS_WORD_DATA:
  227. data->word = inb_p(NVIDIA_SMB_DATA) |
  228. (inb_p(NVIDIA_SMB_DATA + 1) << 8);
  229. break;
  230. case I2C_SMBUS_BLOCK_DATA:
  231. len = inb_p(NVIDIA_SMB_BCNT);
  232. if ((len <= 0) || (len > I2C_SMBUS_BLOCK_MAX)) {
  233. dev_err(&adap->dev,
  234. "Transaction failed (received block size: 0x%02x)\n",
  235. len);
  236. return -EPROTO;
  237. }
  238. for (i = 0; i < len; i++)
  239. data->block[i + 1] = inb_p(NVIDIA_SMB_DATA + i);
  240. data->block[0] = len;
  241. break;
  242. }
  243. return 0;
  244. }
  245. static u32 nforce2_func(struct i2c_adapter *adapter)
  246. {
  247. /* other functionality might be possible, but is not tested */
  248. return I2C_FUNC_SMBUS_QUICK | I2C_FUNC_SMBUS_BYTE |
  249. I2C_FUNC_SMBUS_BYTE_DATA | I2C_FUNC_SMBUS_WORD_DATA |
  250. I2C_FUNC_SMBUS_PEC |
  251. (((struct nforce2_smbus *)adapter->algo_data)->blockops ?
  252. I2C_FUNC_SMBUS_BLOCK_DATA : 0);
  253. }
  254. static struct i2c_algorithm smbus_algorithm = {
  255. .smbus_xfer = nforce2_access,
  256. .functionality = nforce2_func,
  257. };
  258. static const struct pci_device_id nforce2_ids[] = {
  259. { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE2_SMBUS) },
  260. { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE2S_SMBUS) },
  261. { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE3_SMBUS) },
  262. { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE3S_SMBUS) },
  263. { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE4_SMBUS) },
  264. { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP04_SMBUS) },
  265. { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP51_SMBUS) },
  266. { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP55_SMBUS) },
  267. { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP61_SMBUS) },
  268. { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP65_SMBUS) },
  269. { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP67_SMBUS) },
  270. { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP73_SMBUS) },
  271. { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP78S_SMBUS) },
  272. { PCI_DEVICE(PCI_VENDOR_ID_NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP79_SMBUS) },
  273. { 0 }
  274. };
  275. MODULE_DEVICE_TABLE(pci, nforce2_ids);
  276. static int nforce2_probe_smb(struct pci_dev *dev, int bar, int alt_reg,
  277. struct nforce2_smbus *smbus, const char *name)
  278. {
  279. int error;
  280. smbus->base = pci_resource_start(dev, bar);
  281. if (smbus->base) {
  282. smbus->size = pci_resource_len(dev, bar);
  283. } else {
  284. /* Older incarnations of the device used non-standard BARs */
  285. u16 iobase;
  286. if (pci_read_config_word(dev, alt_reg, &iobase)
  287. != PCIBIOS_SUCCESSFUL) {
  288. dev_err(&dev->dev, "Error reading PCI config for %s\n",
  289. name);
  290. return -EIO;
  291. }
  292. smbus->base = iobase & PCI_BASE_ADDRESS_IO_MASK;
  293. smbus->size = 64;
  294. }
  295. error = acpi_check_region(smbus->base, smbus->size,
  296. nforce2_driver.name);
  297. if (error)
  298. return error;
  299. if (!request_region(smbus->base, smbus->size, nforce2_driver.name)) {
  300. dev_err(&smbus->adapter.dev, "Error requesting region %02x .. %02X for %s\n",
  301. smbus->base, smbus->base+smbus->size-1, name);
  302. return -EBUSY;
  303. }
  304. smbus->adapter.owner = THIS_MODULE;
  305. smbus->adapter.class = I2C_CLASS_HWMON | I2C_CLASS_SPD;
  306. smbus->adapter.algo = &smbus_algorithm;
  307. smbus->adapter.algo_data = smbus;
  308. smbus->adapter.dev.parent = &dev->dev;
  309. snprintf(smbus->adapter.name, sizeof(smbus->adapter.name),
  310. "SMBus nForce2 adapter at %04x", smbus->base);
  311. error = i2c_add_adapter(&smbus->adapter);
  312. if (error) {
  313. dev_err(&smbus->adapter.dev, "Failed to register adapter.\n");
  314. release_region(smbus->base, smbus->size);
  315. return error;
  316. }
  317. dev_info(&smbus->adapter.dev, "nForce2 SMBus adapter at %#x\n",
  318. smbus->base);
  319. return 0;
  320. }
  321. static int nforce2_probe(struct pci_dev *dev, const struct pci_device_id *id)
  322. {
  323. struct nforce2_smbus *smbuses;
  324. int res1, res2;
  325. /* we support 2 SMBus adapters */
  326. smbuses = kzalloc(2 * sizeof(struct nforce2_smbus), GFP_KERNEL);
  327. if (!smbuses)
  328. return -ENOMEM;
  329. pci_set_drvdata(dev, smbuses);
  330. switch (dev->device) {
  331. case PCI_DEVICE_ID_NVIDIA_NFORCE2_SMBUS:
  332. case PCI_DEVICE_ID_NVIDIA_NFORCE_MCP51_SMBUS:
  333. case PCI_DEVICE_ID_NVIDIA_NFORCE_MCP55_SMBUS:
  334. smbuses[0].blockops = 1;
  335. smbuses[1].blockops = 1;
  336. smbuses[0].can_abort = 1;
  337. smbuses[1].can_abort = 1;
  338. }
  339. /* SMBus adapter 1 */
  340. res1 = nforce2_probe_smb(dev, 4, NFORCE_PCI_SMB1, &smbuses[0], "SMB1");
  341. if (res1 < 0)
  342. smbuses[0].base = 0; /* to have a check value */
  343. /* SMBus adapter 2 */
  344. if (dmi_check_system(nforce2_dmi_blacklist2)) {
  345. dev_err(&dev->dev, "Disabling SMB2 for safety reasons.\n");
  346. res2 = -EPERM;
  347. smbuses[1].base = 0;
  348. } else {
  349. res2 = nforce2_probe_smb(dev, 5, NFORCE_PCI_SMB2, &smbuses[1],
  350. "SMB2");
  351. if (res2 < 0)
  352. smbuses[1].base = 0; /* to have a check value */
  353. }
  354. if ((res1 < 0) && (res2 < 0)) {
  355. /* we did not find even one of the SMBuses, so we give up */
  356. kfree(smbuses);
  357. return -ENODEV;
  358. }
  359. nforce2_set_reference(&smbuses[0].adapter);
  360. return 0;
  361. }
  362. static void nforce2_remove(struct pci_dev *dev)
  363. {
  364. struct nforce2_smbus *smbuses = pci_get_drvdata(dev);
  365. nforce2_set_reference(NULL);
  366. if (smbuses[0].base) {
  367. i2c_del_adapter(&smbuses[0].adapter);
  368. release_region(smbuses[0].base, smbuses[0].size);
  369. }
  370. if (smbuses[1].base) {
  371. i2c_del_adapter(&smbuses[1].adapter);
  372. release_region(smbuses[1].base, smbuses[1].size);
  373. }
  374. kfree(smbuses);
  375. }
  376. static struct pci_driver nforce2_driver = {
  377. .name = "nForce2_smbus",
  378. .id_table = nforce2_ids,
  379. .probe = nforce2_probe,
  380. .remove = nforce2_remove,
  381. };
  382. module_pci_driver(nforce2_driver);