i2c-sh7760.c 13 KB

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  1. /*
  2. * I2C bus driver for the SH7760 I2C Interfaces.
  3. *
  4. * (c) 2005-2008 MSC Vertriebsges.m.b.H, Manuel Lauss <mlau@msc-ge.com>
  5. *
  6. * licensed under the terms outlined in the file COPYING.
  7. *
  8. */
  9. #include <linux/completion.h>
  10. #include <linux/delay.h>
  11. #include <linux/err.h>
  12. #include <linux/i2c.h>
  13. #include <linux/interrupt.h>
  14. #include <linux/ioport.h>
  15. #include <linux/platform_device.h>
  16. #include <linux/slab.h>
  17. #include <linux/io.h>
  18. #include <linux/module.h>
  19. #include <asm/clock.h>
  20. #include <asm/i2c-sh7760.h>
  21. /* register offsets */
  22. #define I2CSCR 0x0 /* slave ctrl */
  23. #define I2CMCR 0x4 /* master ctrl */
  24. #define I2CSSR 0x8 /* slave status */
  25. #define I2CMSR 0xC /* master status */
  26. #define I2CSIER 0x10 /* slave irq enable */
  27. #define I2CMIER 0x14 /* master irq enable */
  28. #define I2CCCR 0x18 /* clock dividers */
  29. #define I2CSAR 0x1c /* slave address */
  30. #define I2CMAR 0x20 /* master address */
  31. #define I2CRXTX 0x24 /* data port */
  32. #define I2CFCR 0x28 /* fifo control */
  33. #define I2CFSR 0x2C /* fifo status */
  34. #define I2CFIER 0x30 /* fifo irq enable */
  35. #define I2CRFDR 0x34 /* rx fifo count */
  36. #define I2CTFDR 0x38 /* tx fifo count */
  37. #define REGSIZE 0x3C
  38. #define MCR_MDBS 0x80 /* non-fifo mode switch */
  39. #define MCR_FSCL 0x40 /* override SCL pin */
  40. #define MCR_FSDA 0x20 /* override SDA pin */
  41. #define MCR_OBPC 0x10 /* override pins */
  42. #define MCR_MIE 0x08 /* master if enable */
  43. #define MCR_TSBE 0x04
  44. #define MCR_FSB 0x02 /* force stop bit */
  45. #define MCR_ESG 0x01 /* en startbit gen. */
  46. #define MSR_MNR 0x40 /* nack received */
  47. #define MSR_MAL 0x20 /* arbitration lost */
  48. #define MSR_MST 0x10 /* sent a stop */
  49. #define MSR_MDE 0x08
  50. #define MSR_MDT 0x04
  51. #define MSR_MDR 0x02
  52. #define MSR_MAT 0x01 /* slave addr xfer done */
  53. #define MIE_MNRE 0x40 /* nack irq en */
  54. #define MIE_MALE 0x20 /* arblos irq en */
  55. #define MIE_MSTE 0x10 /* stop irq en */
  56. #define MIE_MDEE 0x08
  57. #define MIE_MDTE 0x04
  58. #define MIE_MDRE 0x02
  59. #define MIE_MATE 0x01 /* address sent irq en */
  60. #define FCR_RFRST 0x02 /* reset rx fifo */
  61. #define FCR_TFRST 0x01 /* reset tx fifo */
  62. #define FSR_TEND 0x04 /* last byte sent */
  63. #define FSR_RDF 0x02 /* rx fifo trigger */
  64. #define FSR_TDFE 0x01 /* tx fifo empty */
  65. #define FIER_TEIE 0x04 /* tx fifo empty irq en */
  66. #define FIER_RXIE 0x02 /* rx fifo trig irq en */
  67. #define FIER_TXIE 0x01 /* tx fifo trig irq en */
  68. #define FIFO_SIZE 16
  69. struct cami2c {
  70. void __iomem *iobase;
  71. struct i2c_adapter adap;
  72. /* message processing */
  73. struct i2c_msg *msg;
  74. #define IDF_SEND 1
  75. #define IDF_RECV 2
  76. #define IDF_STOP 4
  77. int flags;
  78. #define IDS_DONE 1
  79. #define IDS_ARBLOST 2
  80. #define IDS_NACK 4
  81. int status;
  82. struct completion xfer_done;
  83. int irq;
  84. struct resource *ioarea;
  85. };
  86. static inline void OUT32(struct cami2c *cam, int reg, unsigned long val)
  87. {
  88. __raw_writel(val, (unsigned long)cam->iobase + reg);
  89. }
  90. static inline unsigned long IN32(struct cami2c *cam, int reg)
  91. {
  92. return __raw_readl((unsigned long)cam->iobase + reg);
  93. }
  94. static irqreturn_t sh7760_i2c_irq(int irq, void *ptr)
  95. {
  96. struct cami2c *id = ptr;
  97. struct i2c_msg *msg = id->msg;
  98. char *data = msg->buf;
  99. unsigned long msr, fsr, fier, len;
  100. msr = IN32(id, I2CMSR);
  101. fsr = IN32(id, I2CFSR);
  102. /* arbitration lost */
  103. if (msr & MSR_MAL) {
  104. OUT32(id, I2CMCR, 0);
  105. OUT32(id, I2CSCR, 0);
  106. OUT32(id, I2CSAR, 0);
  107. id->status |= IDS_DONE | IDS_ARBLOST;
  108. goto out;
  109. }
  110. if (msr & MSR_MNR) {
  111. /* NACK handling is very screwed up. After receiving a
  112. * NAK IRQ one has to wait a bit before writing to any
  113. * registers, or the ctl will lock up. After that delay
  114. * do a normal i2c stop. Then wait at least 1 ms before
  115. * attempting another transfer or ctl will stop working
  116. */
  117. udelay(100); /* wait or risk ctl hang */
  118. OUT32(id, I2CFCR, FCR_RFRST | FCR_TFRST);
  119. OUT32(id, I2CMCR, MCR_MIE | MCR_FSB);
  120. OUT32(id, I2CFIER, 0);
  121. OUT32(id, I2CMIER, MIE_MSTE);
  122. OUT32(id, I2CSCR, 0);
  123. OUT32(id, I2CSAR, 0);
  124. id->status |= IDS_NACK;
  125. msr &= ~MSR_MAT;
  126. fsr = 0;
  127. /* In some cases the MST bit is also set. */
  128. }
  129. /* i2c-stop was sent */
  130. if (msr & MSR_MST) {
  131. id->status |= IDS_DONE;
  132. goto out;
  133. }
  134. /* i2c slave addr was sent; set to "normal" operation */
  135. if (msr & MSR_MAT)
  136. OUT32(id, I2CMCR, MCR_MIE);
  137. fier = IN32(id, I2CFIER);
  138. if (fsr & FSR_RDF) {
  139. len = IN32(id, I2CRFDR);
  140. if (msg->len <= len) {
  141. if (id->flags & IDF_STOP) {
  142. OUT32(id, I2CMCR, MCR_MIE | MCR_FSB);
  143. OUT32(id, I2CFIER, 0);
  144. /* manual says: wait >= 0.5 SCL times */
  145. udelay(5);
  146. /* next int should be MST */
  147. } else {
  148. id->status |= IDS_DONE;
  149. /* keep the RDF bit: ctrl holds SCL low
  150. * until the setup for the next i2c_msg
  151. * clears this bit.
  152. */
  153. fsr &= ~FSR_RDF;
  154. }
  155. }
  156. while (msg->len && len) {
  157. *data++ = IN32(id, I2CRXTX);
  158. msg->len--;
  159. len--;
  160. }
  161. if (msg->len) {
  162. len = (msg->len >= FIFO_SIZE) ? FIFO_SIZE - 1
  163. : msg->len - 1;
  164. OUT32(id, I2CFCR, FCR_TFRST | ((len & 0xf) << 4));
  165. }
  166. } else if (id->flags & IDF_SEND) {
  167. if ((fsr & FSR_TEND) && (msg->len < 1)) {
  168. if (id->flags & IDF_STOP) {
  169. OUT32(id, I2CMCR, MCR_MIE | MCR_FSB);
  170. } else {
  171. id->status |= IDS_DONE;
  172. /* keep the TEND bit: ctl holds SCL low
  173. * until the setup for the next i2c_msg
  174. * clears this bit.
  175. */
  176. fsr &= ~FSR_TEND;
  177. }
  178. }
  179. if (fsr & FSR_TDFE) {
  180. while (msg->len && (IN32(id, I2CTFDR) < FIFO_SIZE)) {
  181. OUT32(id, I2CRXTX, *data++);
  182. msg->len--;
  183. }
  184. if (msg->len < 1) {
  185. fier &= ~FIER_TXIE;
  186. OUT32(id, I2CFIER, fier);
  187. } else {
  188. len = (msg->len >= FIFO_SIZE) ? 2 : 0;
  189. OUT32(id, I2CFCR,
  190. FCR_RFRST | ((len & 3) << 2));
  191. }
  192. }
  193. }
  194. out:
  195. if (id->status & IDS_DONE) {
  196. OUT32(id, I2CMIER, 0);
  197. OUT32(id, I2CFIER, 0);
  198. id->msg = NULL;
  199. complete(&id->xfer_done);
  200. }
  201. /* clear status flags and ctrl resumes work */
  202. OUT32(id, I2CMSR, ~msr);
  203. OUT32(id, I2CFSR, ~fsr);
  204. OUT32(id, I2CSSR, 0);
  205. return IRQ_HANDLED;
  206. }
  207. /* prepare and start a master receive operation */
  208. static void sh7760_i2c_mrecv(struct cami2c *id)
  209. {
  210. int len;
  211. id->flags |= IDF_RECV;
  212. /* set the slave addr reg; otherwise rcv wont work! */
  213. OUT32(id, I2CSAR, 0xfe);
  214. OUT32(id, I2CMAR, (id->msg->addr << 1) | 1);
  215. /* adjust rx fifo trigger */
  216. if (id->msg->len >= FIFO_SIZE)
  217. len = FIFO_SIZE - 1; /* trigger at fifo full */
  218. else
  219. len = id->msg->len - 1; /* trigger before all received */
  220. OUT32(id, I2CFCR, FCR_RFRST | FCR_TFRST);
  221. OUT32(id, I2CFCR, FCR_TFRST | ((len & 0xF) << 4));
  222. OUT32(id, I2CMSR, 0);
  223. OUT32(id, I2CMCR, MCR_MIE | MCR_ESG);
  224. OUT32(id, I2CMIER, MIE_MNRE | MIE_MALE | MIE_MSTE | MIE_MATE);
  225. OUT32(id, I2CFIER, FIER_RXIE);
  226. }
  227. /* prepare and start a master send operation */
  228. static void sh7760_i2c_msend(struct cami2c *id)
  229. {
  230. int len;
  231. id->flags |= IDF_SEND;
  232. /* set the slave addr reg; otherwise xmit wont work! */
  233. OUT32(id, I2CSAR, 0xfe);
  234. OUT32(id, I2CMAR, (id->msg->addr << 1) | 0);
  235. /* adjust tx fifo trigger */
  236. if (id->msg->len >= FIFO_SIZE)
  237. len = 2; /* trig: 2 bytes left in TX fifo */
  238. else
  239. len = 0; /* trig: 8 bytes left in TX fifo */
  240. OUT32(id, I2CFCR, FCR_RFRST | FCR_TFRST);
  241. OUT32(id, I2CFCR, FCR_RFRST | ((len & 3) << 2));
  242. while (id->msg->len && IN32(id, I2CTFDR) < FIFO_SIZE) {
  243. OUT32(id, I2CRXTX, *(id->msg->buf));
  244. (id->msg->len)--;
  245. (id->msg->buf)++;
  246. }
  247. OUT32(id, I2CMSR, 0);
  248. OUT32(id, I2CMCR, MCR_MIE | MCR_ESG);
  249. OUT32(id, I2CFSR, 0);
  250. OUT32(id, I2CMIER, MIE_MNRE | MIE_MALE | MIE_MSTE | MIE_MATE);
  251. OUT32(id, I2CFIER, FIER_TEIE | (id->msg->len ? FIER_TXIE : 0));
  252. }
  253. static inline int sh7760_i2c_busy_check(struct cami2c *id)
  254. {
  255. return (IN32(id, I2CMCR) & MCR_FSDA);
  256. }
  257. static int sh7760_i2c_master_xfer(struct i2c_adapter *adap,
  258. struct i2c_msg *msgs,
  259. int num)
  260. {
  261. struct cami2c *id = adap->algo_data;
  262. int i, retr;
  263. if (sh7760_i2c_busy_check(id)) {
  264. dev_err(&adap->dev, "sh7760-i2c%d: bus busy!\n", adap->nr);
  265. return -EBUSY;
  266. }
  267. i = 0;
  268. while (i < num) {
  269. retr = adap->retries;
  270. retry:
  271. id->flags = ((i == (num-1)) ? IDF_STOP : 0);
  272. id->status = 0;
  273. id->msg = msgs;
  274. init_completion(&id->xfer_done);
  275. if (msgs->flags & I2C_M_RD)
  276. sh7760_i2c_mrecv(id);
  277. else
  278. sh7760_i2c_msend(id);
  279. wait_for_completion(&id->xfer_done);
  280. if (id->status == 0) {
  281. num = -EIO;
  282. break;
  283. }
  284. if (id->status & IDS_NACK) {
  285. /* wait a bit or i2c module stops working */
  286. mdelay(1);
  287. num = -EREMOTEIO;
  288. break;
  289. }
  290. if (id->status & IDS_ARBLOST) {
  291. if (retr--) {
  292. mdelay(2);
  293. goto retry;
  294. }
  295. num = -EREMOTEIO;
  296. break;
  297. }
  298. msgs++;
  299. i++;
  300. }
  301. id->msg = NULL;
  302. id->flags = 0;
  303. id->status = 0;
  304. OUT32(id, I2CMCR, 0);
  305. OUT32(id, I2CMSR, 0);
  306. OUT32(id, I2CMIER, 0);
  307. OUT32(id, I2CFIER, 0);
  308. /* reset slave module registers too: master mode enables slave
  309. * module for receive ops (ack, data). Without this reset,
  310. * eternal bus activity might be reported after NACK / ARBLOST.
  311. */
  312. OUT32(id, I2CSCR, 0);
  313. OUT32(id, I2CSAR, 0);
  314. OUT32(id, I2CSSR, 0);
  315. return num;
  316. }
  317. static u32 sh7760_i2c_func(struct i2c_adapter *adap)
  318. {
  319. return I2C_FUNC_I2C | (I2C_FUNC_SMBUS_EMUL & ~I2C_FUNC_SMBUS_QUICK);
  320. }
  321. static const struct i2c_algorithm sh7760_i2c_algo = {
  322. .master_xfer = sh7760_i2c_master_xfer,
  323. .functionality = sh7760_i2c_func,
  324. };
  325. /* calculate CCR register setting for a desired scl clock. SCL clock is
  326. * derived from I2C module clock (iclk) which in turn is derived from
  327. * peripheral module clock (mclk, usually around 33MHz):
  328. * iclk = mclk/(CDF + 1). iclk must be < 20MHz.
  329. * scl = iclk/(SCGD*8 + 20).
  330. */
  331. static int calc_CCR(unsigned long scl_hz)
  332. {
  333. struct clk *mclk;
  334. unsigned long mck, m1, dff, odff, iclk;
  335. signed char cdf, cdfm;
  336. int scgd, scgdm, scgds;
  337. mclk = clk_get(NULL, "peripheral_clk");
  338. if (IS_ERR(mclk)) {
  339. return PTR_ERR(mclk);
  340. } else {
  341. mck = mclk->rate;
  342. clk_put(mclk);
  343. }
  344. odff = scl_hz;
  345. scgdm = cdfm = m1 = 0;
  346. for (cdf = 3; cdf >= 0; cdf--) {
  347. iclk = mck / (1 + cdf);
  348. if (iclk >= 20000000)
  349. continue;
  350. scgds = ((iclk / scl_hz) - 20) >> 3;
  351. for (scgd = scgds; (scgd < 63) && scgd <= scgds + 1; scgd++) {
  352. m1 = iclk / (20 + (scgd << 3));
  353. dff = abs(scl_hz - m1);
  354. if (dff < odff) {
  355. odff = dff;
  356. cdfm = cdf;
  357. scgdm = scgd;
  358. }
  359. }
  360. }
  361. /* fail if more than 25% off of requested SCL */
  362. if (odff > (scl_hz >> 2))
  363. return -EINVAL;
  364. /* create a CCR register value */
  365. return ((scgdm << 2) | cdfm);
  366. }
  367. static int sh7760_i2c_probe(struct platform_device *pdev)
  368. {
  369. struct sh7760_i2c_platdata *pd;
  370. struct resource *res;
  371. struct cami2c *id;
  372. int ret;
  373. pd = dev_get_platdata(&pdev->dev);
  374. if (!pd) {
  375. dev_err(&pdev->dev, "no platform_data!\n");
  376. ret = -ENODEV;
  377. goto out0;
  378. }
  379. id = kzalloc(sizeof(struct cami2c), GFP_KERNEL);
  380. if (!id) {
  381. dev_err(&pdev->dev, "no mem for private data\n");
  382. ret = -ENOMEM;
  383. goto out0;
  384. }
  385. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  386. if (!res) {
  387. dev_err(&pdev->dev, "no mmio resources\n");
  388. ret = -ENODEV;
  389. goto out1;
  390. }
  391. id->ioarea = request_mem_region(res->start, REGSIZE, pdev->name);
  392. if (!id->ioarea) {
  393. dev_err(&pdev->dev, "mmio already reserved\n");
  394. ret = -EBUSY;
  395. goto out1;
  396. }
  397. id->iobase = ioremap(res->start, REGSIZE);
  398. if (!id->iobase) {
  399. dev_err(&pdev->dev, "cannot ioremap\n");
  400. ret = -ENODEV;
  401. goto out2;
  402. }
  403. id->irq = platform_get_irq(pdev, 0);
  404. id->adap.nr = pdev->id;
  405. id->adap.algo = &sh7760_i2c_algo;
  406. id->adap.class = I2C_CLASS_HWMON | I2C_CLASS_SPD;
  407. id->adap.retries = 3;
  408. id->adap.algo_data = id;
  409. id->adap.dev.parent = &pdev->dev;
  410. snprintf(id->adap.name, sizeof(id->adap.name),
  411. "SH7760 I2C at %08lx", (unsigned long)res->start);
  412. OUT32(id, I2CMCR, 0);
  413. OUT32(id, I2CMSR, 0);
  414. OUT32(id, I2CMIER, 0);
  415. OUT32(id, I2CMAR, 0);
  416. OUT32(id, I2CSIER, 0);
  417. OUT32(id, I2CSAR, 0);
  418. OUT32(id, I2CSCR, 0);
  419. OUT32(id, I2CSSR, 0);
  420. OUT32(id, I2CFIER, 0);
  421. OUT32(id, I2CFCR, FCR_RFRST | FCR_TFRST);
  422. OUT32(id, I2CFSR, 0);
  423. ret = calc_CCR(pd->speed_khz * 1000);
  424. if (ret < 0) {
  425. dev_err(&pdev->dev, "invalid SCL clock: %dkHz\n",
  426. pd->speed_khz);
  427. goto out3;
  428. }
  429. OUT32(id, I2CCCR, ret);
  430. if (request_irq(id->irq, sh7760_i2c_irq, 0,
  431. SH7760_I2C_DEVNAME, id)) {
  432. dev_err(&pdev->dev, "cannot get irq %d\n", id->irq);
  433. ret = -EBUSY;
  434. goto out3;
  435. }
  436. ret = i2c_add_numbered_adapter(&id->adap);
  437. if (ret < 0) {
  438. dev_err(&pdev->dev, "reg adap failed: %d\n", ret);
  439. goto out4;
  440. }
  441. platform_set_drvdata(pdev, id);
  442. dev_info(&pdev->dev, "%d kHz mmio %08x irq %d\n",
  443. pd->speed_khz, res->start, id->irq);
  444. return 0;
  445. out4:
  446. free_irq(id->irq, id);
  447. out3:
  448. iounmap(id->iobase);
  449. out2:
  450. release_resource(id->ioarea);
  451. kfree(id->ioarea);
  452. out1:
  453. kfree(id);
  454. out0:
  455. return ret;
  456. }
  457. static int sh7760_i2c_remove(struct platform_device *pdev)
  458. {
  459. struct cami2c *id = platform_get_drvdata(pdev);
  460. i2c_del_adapter(&id->adap);
  461. free_irq(id->irq, id);
  462. iounmap(id->iobase);
  463. release_resource(id->ioarea);
  464. kfree(id->ioarea);
  465. kfree(id);
  466. return 0;
  467. }
  468. static struct platform_driver sh7760_i2c_drv = {
  469. .driver = {
  470. .name = SH7760_I2C_DEVNAME,
  471. },
  472. .probe = sh7760_i2c_probe,
  473. .remove = sh7760_i2c_remove,
  474. };
  475. module_platform_driver(sh7760_i2c_drv);
  476. MODULE_LICENSE("GPL");
  477. MODULE_DESCRIPTION("SH7760 I2C bus driver");
  478. MODULE_AUTHOR("Manuel Lauss <mano@roarinelk.homelinux.net>");