i2c-wmt.c 11 KB

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  1. /*
  2. * Wondermedia I2C Master Mode Driver
  3. *
  4. * Copyright (C) 2012 Tony Prisk <linux@prisktech.co.nz>
  5. *
  6. * Derived from GPLv2+ licensed source:
  7. * - Copyright (C) 2008 WonderMedia Technologies, Inc.
  8. *
  9. * This program is free software; you can redistribute it and/or modify
  10. * it under the terms of the GNU General Public License version 2, or
  11. * (at your option) any later version. as published by the Free Software
  12. * Foundation
  13. */
  14. #include <linux/clk.h>
  15. #include <linux/delay.h>
  16. #include <linux/err.h>
  17. #include <linux/i2c.h>
  18. #include <linux/interrupt.h>
  19. #include <linux/io.h>
  20. #include <linux/module.h>
  21. #include <linux/of.h>
  22. #include <linux/of_address.h>
  23. #include <linux/of_irq.h>
  24. #include <linux/platform_device.h>
  25. #define REG_CR 0x00
  26. #define REG_TCR 0x02
  27. #define REG_CSR 0x04
  28. #define REG_ISR 0x06
  29. #define REG_IMR 0x08
  30. #define REG_CDR 0x0A
  31. #define REG_TR 0x0C
  32. #define REG_MCR 0x0E
  33. #define REG_SLAVE_CR 0x10
  34. #define REG_SLAVE_SR 0x12
  35. #define REG_SLAVE_ISR 0x14
  36. #define REG_SLAVE_IMR 0x16
  37. #define REG_SLAVE_DR 0x18
  38. #define REG_SLAVE_TR 0x1A
  39. /* REG_CR Bit fields */
  40. #define CR_TX_NEXT_ACK 0x0000
  41. #define CR_ENABLE 0x0001
  42. #define CR_TX_NEXT_NO_ACK 0x0002
  43. #define CR_TX_END 0x0004
  44. #define CR_CPU_RDY 0x0008
  45. #define SLAV_MODE_SEL 0x8000
  46. /* REG_TCR Bit fields */
  47. #define TCR_STANDARD_MODE 0x0000
  48. #define TCR_MASTER_WRITE 0x0000
  49. #define TCR_HS_MODE 0x2000
  50. #define TCR_MASTER_READ 0x4000
  51. #define TCR_FAST_MODE 0x8000
  52. #define TCR_SLAVE_ADDR_MASK 0x007F
  53. /* REG_ISR Bit fields */
  54. #define ISR_NACK_ADDR 0x0001
  55. #define ISR_BYTE_END 0x0002
  56. #define ISR_SCL_TIMEOUT 0x0004
  57. #define ISR_WRITE_ALL 0x0007
  58. /* REG_IMR Bit fields */
  59. #define IMR_ENABLE_ALL 0x0007
  60. /* REG_CSR Bit fields */
  61. #define CSR_RCV_NOT_ACK 0x0001
  62. #define CSR_RCV_ACK_MASK 0x0001
  63. #define CSR_READY_MASK 0x0002
  64. /* REG_TR */
  65. #define SCL_TIMEOUT(x) (((x) & 0xFF) << 8)
  66. #define TR_STD 0x0064
  67. #define TR_HS 0x0019
  68. /* REG_MCR */
  69. #define MCR_APB_96M 7
  70. #define MCR_APB_166M 12
  71. #define I2C_MODE_STANDARD 0
  72. #define I2C_MODE_FAST 1
  73. #define WMT_I2C_TIMEOUT (msecs_to_jiffies(1000))
  74. struct wmt_i2c_dev {
  75. struct i2c_adapter adapter;
  76. struct completion complete;
  77. struct device *dev;
  78. void __iomem *base;
  79. struct clk *clk;
  80. int mode;
  81. int irq;
  82. u16 cmd_status;
  83. };
  84. static int wmt_i2c_wait_bus_not_busy(struct wmt_i2c_dev *i2c_dev)
  85. {
  86. unsigned long timeout;
  87. timeout = jiffies + WMT_I2C_TIMEOUT;
  88. while (!(readw(i2c_dev->base + REG_CSR) & CSR_READY_MASK)) {
  89. if (time_after(jiffies, timeout)) {
  90. dev_warn(i2c_dev->dev, "timeout waiting for bus ready\n");
  91. return -EBUSY;
  92. }
  93. msleep(20);
  94. }
  95. return 0;
  96. }
  97. static int wmt_check_status(struct wmt_i2c_dev *i2c_dev)
  98. {
  99. int ret = 0;
  100. if (i2c_dev->cmd_status & ISR_NACK_ADDR)
  101. ret = -EIO;
  102. if (i2c_dev->cmd_status & ISR_SCL_TIMEOUT)
  103. ret = -ETIMEDOUT;
  104. return ret;
  105. }
  106. static int wmt_i2c_write(struct i2c_adapter *adap, struct i2c_msg *pmsg,
  107. int last)
  108. {
  109. struct wmt_i2c_dev *i2c_dev = i2c_get_adapdata(adap);
  110. u16 val, tcr_val;
  111. int ret;
  112. unsigned long wait_result;
  113. int xfer_len = 0;
  114. if (!(pmsg->flags & I2C_M_NOSTART)) {
  115. ret = wmt_i2c_wait_bus_not_busy(i2c_dev);
  116. if (ret < 0)
  117. return ret;
  118. }
  119. if (pmsg->len == 0) {
  120. /*
  121. * We still need to run through the while (..) once, so
  122. * start at -1 and break out early from the loop
  123. */
  124. xfer_len = -1;
  125. writew(0, i2c_dev->base + REG_CDR);
  126. } else {
  127. writew(pmsg->buf[0] & 0xFF, i2c_dev->base + REG_CDR);
  128. }
  129. if (!(pmsg->flags & I2C_M_NOSTART)) {
  130. val = readw(i2c_dev->base + REG_CR);
  131. val &= ~CR_TX_END;
  132. writew(val, i2c_dev->base + REG_CR);
  133. val = readw(i2c_dev->base + REG_CR);
  134. val |= CR_CPU_RDY;
  135. writew(val, i2c_dev->base + REG_CR);
  136. }
  137. reinit_completion(&i2c_dev->complete);
  138. if (i2c_dev->mode == I2C_MODE_STANDARD)
  139. tcr_val = TCR_STANDARD_MODE;
  140. else
  141. tcr_val = TCR_FAST_MODE;
  142. tcr_val |= (TCR_MASTER_WRITE | (pmsg->addr & TCR_SLAVE_ADDR_MASK));
  143. writew(tcr_val, i2c_dev->base + REG_TCR);
  144. if (pmsg->flags & I2C_M_NOSTART) {
  145. val = readw(i2c_dev->base + REG_CR);
  146. val |= CR_CPU_RDY;
  147. writew(val, i2c_dev->base + REG_CR);
  148. }
  149. while (xfer_len < pmsg->len) {
  150. wait_result = wait_for_completion_timeout(&i2c_dev->complete,
  151. msecs_to_jiffies(500));
  152. if (wait_result == 0)
  153. return -ETIMEDOUT;
  154. ret = wmt_check_status(i2c_dev);
  155. if (ret)
  156. return ret;
  157. xfer_len++;
  158. val = readw(i2c_dev->base + REG_CSR);
  159. if ((val & CSR_RCV_ACK_MASK) == CSR_RCV_NOT_ACK) {
  160. dev_dbg(i2c_dev->dev, "write RCV NACK error\n");
  161. return -EIO;
  162. }
  163. if (pmsg->len == 0) {
  164. val = CR_TX_END | CR_CPU_RDY | CR_ENABLE;
  165. writew(val, i2c_dev->base + REG_CR);
  166. break;
  167. }
  168. if (xfer_len == pmsg->len) {
  169. if (last != 1)
  170. writew(CR_ENABLE, i2c_dev->base + REG_CR);
  171. } else {
  172. writew(pmsg->buf[xfer_len] & 0xFF, i2c_dev->base +
  173. REG_CDR);
  174. writew(CR_CPU_RDY | CR_ENABLE, i2c_dev->base + REG_CR);
  175. }
  176. }
  177. return 0;
  178. }
  179. static int wmt_i2c_read(struct i2c_adapter *adap, struct i2c_msg *pmsg,
  180. int last)
  181. {
  182. struct wmt_i2c_dev *i2c_dev = i2c_get_adapdata(adap);
  183. u16 val, tcr_val;
  184. int ret;
  185. unsigned long wait_result;
  186. u32 xfer_len = 0;
  187. if (!(pmsg->flags & I2C_M_NOSTART)) {
  188. ret = wmt_i2c_wait_bus_not_busy(i2c_dev);
  189. if (ret < 0)
  190. return ret;
  191. }
  192. val = readw(i2c_dev->base + REG_CR);
  193. val &= ~CR_TX_END;
  194. writew(val, i2c_dev->base + REG_CR);
  195. val = readw(i2c_dev->base + REG_CR);
  196. val &= ~CR_TX_NEXT_NO_ACK;
  197. writew(val, i2c_dev->base + REG_CR);
  198. if (!(pmsg->flags & I2C_M_NOSTART)) {
  199. val = readw(i2c_dev->base + REG_CR);
  200. val |= CR_CPU_RDY;
  201. writew(val, i2c_dev->base + REG_CR);
  202. }
  203. if (pmsg->len == 1) {
  204. val = readw(i2c_dev->base + REG_CR);
  205. val |= CR_TX_NEXT_NO_ACK;
  206. writew(val, i2c_dev->base + REG_CR);
  207. }
  208. reinit_completion(&i2c_dev->complete);
  209. if (i2c_dev->mode == I2C_MODE_STANDARD)
  210. tcr_val = TCR_STANDARD_MODE;
  211. else
  212. tcr_val = TCR_FAST_MODE;
  213. tcr_val |= TCR_MASTER_READ | (pmsg->addr & TCR_SLAVE_ADDR_MASK);
  214. writew(tcr_val, i2c_dev->base + REG_TCR);
  215. if (pmsg->flags & I2C_M_NOSTART) {
  216. val = readw(i2c_dev->base + REG_CR);
  217. val |= CR_CPU_RDY;
  218. writew(val, i2c_dev->base + REG_CR);
  219. }
  220. while (xfer_len < pmsg->len) {
  221. wait_result = wait_for_completion_timeout(&i2c_dev->complete,
  222. msecs_to_jiffies(500));
  223. if (!wait_result)
  224. return -ETIMEDOUT;
  225. ret = wmt_check_status(i2c_dev);
  226. if (ret)
  227. return ret;
  228. pmsg->buf[xfer_len] = readw(i2c_dev->base + REG_CDR) >> 8;
  229. xfer_len++;
  230. if (xfer_len == pmsg->len - 1) {
  231. val = readw(i2c_dev->base + REG_CR);
  232. val |= (CR_TX_NEXT_NO_ACK | CR_CPU_RDY);
  233. writew(val, i2c_dev->base + REG_CR);
  234. } else {
  235. val = readw(i2c_dev->base + REG_CR);
  236. val |= CR_CPU_RDY;
  237. writew(val, i2c_dev->base + REG_CR);
  238. }
  239. }
  240. return 0;
  241. }
  242. static int wmt_i2c_xfer(struct i2c_adapter *adap,
  243. struct i2c_msg msgs[],
  244. int num)
  245. {
  246. struct i2c_msg *pmsg;
  247. int i, is_last;
  248. int ret = 0;
  249. for (i = 0; ret >= 0 && i < num; i++) {
  250. is_last = ((i + 1) == num);
  251. pmsg = &msgs[i];
  252. if (pmsg->flags & I2C_M_RD)
  253. ret = wmt_i2c_read(adap, pmsg, is_last);
  254. else
  255. ret = wmt_i2c_write(adap, pmsg, is_last);
  256. }
  257. return (ret < 0) ? ret : i;
  258. }
  259. static u32 wmt_i2c_func(struct i2c_adapter *adap)
  260. {
  261. return I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL | I2C_FUNC_NOSTART;
  262. }
  263. static const struct i2c_algorithm wmt_i2c_algo = {
  264. .master_xfer = wmt_i2c_xfer,
  265. .functionality = wmt_i2c_func,
  266. };
  267. static irqreturn_t wmt_i2c_isr(int irq, void *data)
  268. {
  269. struct wmt_i2c_dev *i2c_dev = data;
  270. /* save the status and write-clear it */
  271. i2c_dev->cmd_status = readw(i2c_dev->base + REG_ISR);
  272. writew(i2c_dev->cmd_status, i2c_dev->base + REG_ISR);
  273. complete(&i2c_dev->complete);
  274. return IRQ_HANDLED;
  275. }
  276. static int wmt_i2c_reset_hardware(struct wmt_i2c_dev *i2c_dev)
  277. {
  278. int err;
  279. err = clk_prepare_enable(i2c_dev->clk);
  280. if (err) {
  281. dev_err(i2c_dev->dev, "failed to enable clock\n");
  282. return err;
  283. }
  284. err = clk_set_rate(i2c_dev->clk, 20000000);
  285. if (err) {
  286. dev_err(i2c_dev->dev, "failed to set clock = 20Mhz\n");
  287. clk_disable_unprepare(i2c_dev->clk);
  288. return err;
  289. }
  290. writew(0, i2c_dev->base + REG_CR);
  291. writew(MCR_APB_166M, i2c_dev->base + REG_MCR);
  292. writew(ISR_WRITE_ALL, i2c_dev->base + REG_ISR);
  293. writew(IMR_ENABLE_ALL, i2c_dev->base + REG_IMR);
  294. writew(CR_ENABLE, i2c_dev->base + REG_CR);
  295. readw(i2c_dev->base + REG_CSR); /* read clear */
  296. writew(ISR_WRITE_ALL, i2c_dev->base + REG_ISR);
  297. if (i2c_dev->mode == I2C_MODE_STANDARD)
  298. writew(SCL_TIMEOUT(128) | TR_STD, i2c_dev->base + REG_TR);
  299. else
  300. writew(SCL_TIMEOUT(128) | TR_HS, i2c_dev->base + REG_TR);
  301. return 0;
  302. }
  303. static int wmt_i2c_probe(struct platform_device *pdev)
  304. {
  305. struct device_node *np = pdev->dev.of_node;
  306. struct wmt_i2c_dev *i2c_dev;
  307. struct i2c_adapter *adap;
  308. struct resource *res;
  309. int err;
  310. u32 clk_rate;
  311. i2c_dev = devm_kzalloc(&pdev->dev, sizeof(*i2c_dev), GFP_KERNEL);
  312. if (!i2c_dev)
  313. return -ENOMEM;
  314. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  315. i2c_dev->base = devm_ioremap_resource(&pdev->dev, res);
  316. if (IS_ERR(i2c_dev->base))
  317. return PTR_ERR(i2c_dev->base);
  318. i2c_dev->irq = irq_of_parse_and_map(np, 0);
  319. if (!i2c_dev->irq) {
  320. dev_err(&pdev->dev, "irq missing or invalid\n");
  321. return -EINVAL;
  322. }
  323. i2c_dev->clk = of_clk_get(np, 0);
  324. if (IS_ERR(i2c_dev->clk)) {
  325. dev_err(&pdev->dev, "unable to request clock\n");
  326. return PTR_ERR(i2c_dev->clk);
  327. }
  328. i2c_dev->mode = I2C_MODE_STANDARD;
  329. err = of_property_read_u32(np, "clock-frequency", &clk_rate);
  330. if ((!err) && (clk_rate == 400000))
  331. i2c_dev->mode = I2C_MODE_FAST;
  332. i2c_dev->dev = &pdev->dev;
  333. err = devm_request_irq(&pdev->dev, i2c_dev->irq, wmt_i2c_isr, 0,
  334. "i2c", i2c_dev);
  335. if (err) {
  336. dev_err(&pdev->dev, "failed to request irq %i\n", i2c_dev->irq);
  337. return err;
  338. }
  339. adap = &i2c_dev->adapter;
  340. i2c_set_adapdata(adap, i2c_dev);
  341. strlcpy(adap->name, "WMT I2C adapter", sizeof(adap->name));
  342. adap->owner = THIS_MODULE;
  343. adap->algo = &wmt_i2c_algo;
  344. adap->dev.parent = &pdev->dev;
  345. adap->dev.of_node = pdev->dev.of_node;
  346. init_completion(&i2c_dev->complete);
  347. err = wmt_i2c_reset_hardware(i2c_dev);
  348. if (err) {
  349. dev_err(&pdev->dev, "error initializing hardware\n");
  350. return err;
  351. }
  352. err = i2c_add_adapter(adap);
  353. if (err) {
  354. dev_err(&pdev->dev, "failed to add adapter\n");
  355. return err;
  356. }
  357. platform_set_drvdata(pdev, i2c_dev);
  358. return 0;
  359. }
  360. static int wmt_i2c_remove(struct platform_device *pdev)
  361. {
  362. struct wmt_i2c_dev *i2c_dev = platform_get_drvdata(pdev);
  363. /* Disable interrupts, clock and delete adapter */
  364. writew(0, i2c_dev->base + REG_IMR);
  365. clk_disable_unprepare(i2c_dev->clk);
  366. i2c_del_adapter(&i2c_dev->adapter);
  367. return 0;
  368. }
  369. static const struct of_device_id wmt_i2c_dt_ids[] = {
  370. { .compatible = "wm,wm8505-i2c" },
  371. { /* Sentinel */ },
  372. };
  373. static struct platform_driver wmt_i2c_driver = {
  374. .probe = wmt_i2c_probe,
  375. .remove = wmt_i2c_remove,
  376. .driver = {
  377. .name = "wmt-i2c",
  378. .of_match_table = wmt_i2c_dt_ids,
  379. },
  380. };
  381. module_platform_driver(wmt_i2c_driver);
  382. MODULE_DESCRIPTION("Wondermedia I2C master-mode bus adapter");
  383. MODULE_AUTHOR("Tony Prisk <linux@prisktech.co.nz>");
  384. MODULE_LICENSE("GPL");
  385. MODULE_DEVICE_TABLE(of, wmt_i2c_dt_ids);