cy82c693.c 6.3 KB

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  1. /*
  2. * Copyright (C) 1998-2000 Andreas S. Krebs (akrebs@altavista.net), Maintainer
  3. * Copyright (C) 1998-2002 Andre Hedrick <andre@linux-ide.org>, Integrator
  4. * Copyright (C) 2007-2011 Bartlomiej Zolnierkiewicz
  5. *
  6. * CYPRESS CY82C693 chipset IDE controller
  7. *
  8. * The CY82C693 chipset is used on Digital's PC-Alpha 164SX boards.
  9. */
  10. #include <linux/module.h>
  11. #include <linux/types.h>
  12. #include <linux/pci.h>
  13. #include <linux/ide.h>
  14. #include <linux/init.h>
  15. #include <asm/io.h>
  16. #define DRV_NAME "cy82c693"
  17. /*
  18. * NOTE: the value for busmaster timeout is tricky and I got it by
  19. * trial and error! By using a to low value will cause DMA timeouts
  20. * and drop IDE performance, and by using a to high value will cause
  21. * audio playback to scatter.
  22. * If you know a better value or how to calc it, please let me know.
  23. */
  24. /* twice the value written in cy82c693ub datasheet */
  25. #define BUSMASTER_TIMEOUT 0x50
  26. /*
  27. * the value above was tested on my machine and it seems to work okay
  28. */
  29. /* here are the offset definitions for the registers */
  30. #define CY82_IDE_CMDREG 0x04
  31. #define CY82_IDE_ADDRSETUP 0x48
  32. #define CY82_IDE_MASTER_IOR 0x4C
  33. #define CY82_IDE_MASTER_IOW 0x4D
  34. #define CY82_IDE_SLAVE_IOR 0x4E
  35. #define CY82_IDE_SLAVE_IOW 0x4F
  36. #define CY82_IDE_MASTER_8BIT 0x50
  37. #define CY82_IDE_SLAVE_8BIT 0x51
  38. #define CY82_INDEX_PORT 0x22
  39. #define CY82_DATA_PORT 0x23
  40. #define CY82_INDEX_CHANNEL0 0x30
  41. #define CY82_INDEX_CHANNEL1 0x31
  42. #define CY82_INDEX_TIMEOUT 0x32
  43. /*
  44. * set DMA mode a specific channel for CY82C693
  45. */
  46. static void cy82c693_set_dma_mode(ide_hwif_t *hwif, ide_drive_t *drive)
  47. {
  48. const u8 mode = drive->dma_mode;
  49. u8 single = (mode & 0x10) >> 4, index = 0, data = 0;
  50. index = hwif->channel ? CY82_INDEX_CHANNEL1 : CY82_INDEX_CHANNEL0;
  51. data = (mode & 3) | (single << 2);
  52. outb(index, CY82_INDEX_PORT);
  53. outb(data, CY82_DATA_PORT);
  54. /*
  55. * note: below we set the value for Bus Master IDE TimeOut Register
  56. * I'm not absolutely sure what this does, but it solved my problem
  57. * with IDE DMA and sound, so I now can play sound and work with
  58. * my IDE driver at the same time :-)
  59. *
  60. * If you know the correct (best) value for this register please
  61. * let me know - ASK
  62. */
  63. data = BUSMASTER_TIMEOUT;
  64. outb(CY82_INDEX_TIMEOUT, CY82_INDEX_PORT);
  65. outb(data, CY82_DATA_PORT);
  66. }
  67. static void cy82c693_set_pio_mode(ide_hwif_t *hwif, ide_drive_t *drive)
  68. {
  69. struct pci_dev *dev = to_pci_dev(hwif->dev);
  70. int bus_speed = ide_pci_clk ? ide_pci_clk : 33;
  71. const unsigned long T = 1000000 / bus_speed;
  72. unsigned int addrCtrl;
  73. struct ide_timing t;
  74. u8 time_16, time_8;
  75. /* select primary or secondary channel */
  76. if (drive->dn > 1) { /* drive is on the secondary channel */
  77. dev = pci_get_slot(dev->bus, dev->devfn+1);
  78. if (!dev) {
  79. printk(KERN_ERR "%s: tune_drive: "
  80. "Cannot find secondary interface!\n",
  81. drive->name);
  82. return;
  83. }
  84. }
  85. ide_timing_compute(drive, drive->pio_mode, &t, T, 1);
  86. time_16 = clamp_val(t.recover - 1, 0, 15) |
  87. (clamp_val(t.active - 1, 0, 15) << 4);
  88. time_8 = clamp_val(t.act8b - 1, 0, 15) |
  89. (clamp_val(t.rec8b - 1, 0, 15) << 4);
  90. /* now let's write the clocks registers */
  91. if ((drive->dn & 1) == 0) {
  92. /*
  93. * set master drive
  94. * address setup control register
  95. * is 32 bit !!!
  96. */
  97. pci_read_config_dword(dev, CY82_IDE_ADDRSETUP, &addrCtrl);
  98. addrCtrl &= (~0xF);
  99. addrCtrl |= clamp_val(t.setup - 1, 0, 15);
  100. pci_write_config_dword(dev, CY82_IDE_ADDRSETUP, addrCtrl);
  101. /* now let's set the remaining registers */
  102. pci_write_config_byte(dev, CY82_IDE_MASTER_IOR, time_16);
  103. pci_write_config_byte(dev, CY82_IDE_MASTER_IOW, time_16);
  104. pci_write_config_byte(dev, CY82_IDE_MASTER_8BIT, time_8);
  105. } else {
  106. /*
  107. * set slave drive
  108. * address setup control register
  109. * is 32 bit !!!
  110. */
  111. pci_read_config_dword(dev, CY82_IDE_ADDRSETUP, &addrCtrl);
  112. addrCtrl &= (~0xF0);
  113. addrCtrl |= (clamp_val(t.setup - 1, 0, 15) << 4);
  114. pci_write_config_dword(dev, CY82_IDE_ADDRSETUP, addrCtrl);
  115. /* now let's set the remaining registers */
  116. pci_write_config_byte(dev, CY82_IDE_SLAVE_IOR, time_16);
  117. pci_write_config_byte(dev, CY82_IDE_SLAVE_IOW, time_16);
  118. pci_write_config_byte(dev, CY82_IDE_SLAVE_8BIT, time_8);
  119. }
  120. if (drive->dn > 1)
  121. pci_dev_put(dev);
  122. }
  123. static void init_iops_cy82c693(ide_hwif_t *hwif)
  124. {
  125. static ide_hwif_t *primary;
  126. struct pci_dev *dev = to_pci_dev(hwif->dev);
  127. if (PCI_FUNC(dev->devfn) == 1)
  128. primary = hwif;
  129. else {
  130. hwif->mate = primary;
  131. hwif->channel = 1;
  132. }
  133. }
  134. static const struct ide_port_ops cy82c693_port_ops = {
  135. .set_pio_mode = cy82c693_set_pio_mode,
  136. .set_dma_mode = cy82c693_set_dma_mode,
  137. };
  138. static const struct ide_port_info cy82c693_chipset = {
  139. .name = DRV_NAME,
  140. .init_iops = init_iops_cy82c693,
  141. .port_ops = &cy82c693_port_ops,
  142. .host_flags = IDE_HFLAG_SINGLE,
  143. .pio_mask = ATA_PIO4,
  144. .swdma_mask = ATA_SWDMA2,
  145. .mwdma_mask = ATA_MWDMA2,
  146. };
  147. static int cy82c693_init_one(struct pci_dev *dev,
  148. const struct pci_device_id *id)
  149. {
  150. struct pci_dev *dev2;
  151. int ret = -ENODEV;
  152. /* CY82C693 is more than only a IDE controller.
  153. Function 1 is primary IDE channel, function 2 - secondary. */
  154. if ((dev->class >> 8) == PCI_CLASS_STORAGE_IDE &&
  155. PCI_FUNC(dev->devfn) == 1) {
  156. dev2 = pci_get_slot(dev->bus, dev->devfn + 1);
  157. ret = ide_pci_init_two(dev, dev2, &cy82c693_chipset, NULL);
  158. if (ret)
  159. pci_dev_put(dev2);
  160. }
  161. return ret;
  162. }
  163. static void cy82c693_remove(struct pci_dev *dev)
  164. {
  165. struct ide_host *host = pci_get_drvdata(dev);
  166. struct pci_dev *dev2 = host->dev[1] ? to_pci_dev(host->dev[1]) : NULL;
  167. ide_pci_remove(dev);
  168. pci_dev_put(dev2);
  169. }
  170. static const struct pci_device_id cy82c693_pci_tbl[] = {
  171. { PCI_VDEVICE(CONTAQ, PCI_DEVICE_ID_CONTAQ_82C693), 0 },
  172. { 0, },
  173. };
  174. MODULE_DEVICE_TABLE(pci, cy82c693_pci_tbl);
  175. static struct pci_driver cy82c693_pci_driver = {
  176. .name = "Cypress_IDE",
  177. .id_table = cy82c693_pci_tbl,
  178. .probe = cy82c693_init_one,
  179. .remove = cy82c693_remove,
  180. .suspend = ide_pci_suspend,
  181. .resume = ide_pci_resume,
  182. };
  183. static int __init cy82c693_ide_init(void)
  184. {
  185. return ide_pci_register_driver(&cy82c693_pci_driver);
  186. }
  187. static void __exit cy82c693_ide_exit(void)
  188. {
  189. pci_unregister_driver(&cy82c693_pci_driver);
  190. }
  191. module_init(cy82c693_ide_init);
  192. module_exit(cy82c693_ide_exit);
  193. MODULE_AUTHOR("Andreas Krebs, Andre Hedrick, Bartlomiej Zolnierkiewicz");
  194. MODULE_DESCRIPTION("PCI driver module for the Cypress CY82C693 IDE");
  195. MODULE_LICENSE("GPL");