main.c 78 KB

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  1. /*
  2. * Copyright (c) 2006, 2007 Cisco Systems, Inc. All rights reserved.
  3. * Copyright (c) 2007, 2008 Mellanox Technologies. All rights reserved.
  4. *
  5. * This software is available to you under a choice of one of two
  6. * licenses. You may choose to be licensed under the terms of the GNU
  7. * General Public License (GPL) Version 2, available from the file
  8. * COPYING in the main directory of this source tree, or the
  9. * OpenIB.org BSD license below:
  10. *
  11. * Redistribution and use in source and binary forms, with or
  12. * without modification, are permitted provided that the following
  13. * conditions are met:
  14. *
  15. * - Redistributions of source code must retain the above
  16. * copyright notice, this list of conditions and the following
  17. * disclaimer.
  18. *
  19. * - Redistributions in binary form must reproduce the above
  20. * copyright notice, this list of conditions and the following
  21. * disclaimer in the documentation and/or other materials
  22. * provided with the distribution.
  23. *
  24. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  25. * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  26. * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  27. * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  28. * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  29. * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  30. * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  31. * SOFTWARE.
  32. */
  33. #include <linux/module.h>
  34. #include <linux/init.h>
  35. #include <linux/slab.h>
  36. #include <linux/errno.h>
  37. #include <linux/netdevice.h>
  38. #include <linux/inetdevice.h>
  39. #include <linux/rtnetlink.h>
  40. #include <linux/if_vlan.h>
  41. #include <net/ipv6.h>
  42. #include <net/addrconf.h>
  43. #include <rdma/ib_smi.h>
  44. #include <rdma/ib_user_verbs.h>
  45. #include <rdma/ib_addr.h>
  46. #include <rdma/ib_cache.h>
  47. #include <net/bonding.h>
  48. #include <linux/mlx4/driver.h>
  49. #include <linux/mlx4/cmd.h>
  50. #include <linux/mlx4/qp.h>
  51. #include "mlx4_ib.h"
  52. #include "user.h"
  53. #define DRV_NAME MLX4_IB_DRV_NAME
  54. #define DRV_VERSION "2.2-1"
  55. #define DRV_RELDATE "Feb 2014"
  56. #define MLX4_IB_FLOW_MAX_PRIO 0xFFF
  57. #define MLX4_IB_FLOW_QPN_MASK 0xFFFFFF
  58. #define MLX4_IB_CARD_REV_A0 0xA0
  59. MODULE_AUTHOR("Roland Dreier");
  60. MODULE_DESCRIPTION("Mellanox ConnectX HCA InfiniBand driver");
  61. MODULE_LICENSE("Dual BSD/GPL");
  62. MODULE_VERSION(DRV_VERSION);
  63. int mlx4_ib_sm_guid_assign = 0;
  64. module_param_named(sm_guid_assign, mlx4_ib_sm_guid_assign, int, 0444);
  65. MODULE_PARM_DESC(sm_guid_assign, "Enable SM alias_GUID assignment if sm_guid_assign > 0 (Default: 0)");
  66. static const char mlx4_ib_version[] =
  67. DRV_NAME ": Mellanox ConnectX InfiniBand driver v"
  68. DRV_VERSION " (" DRV_RELDATE ")\n";
  69. static void do_slave_init(struct mlx4_ib_dev *ibdev, int slave, int do_init);
  70. static struct workqueue_struct *wq;
  71. static void init_query_mad(struct ib_smp *mad)
  72. {
  73. mad->base_version = 1;
  74. mad->mgmt_class = IB_MGMT_CLASS_SUBN_LID_ROUTED;
  75. mad->class_version = 1;
  76. mad->method = IB_MGMT_METHOD_GET;
  77. }
  78. static int check_flow_steering_support(struct mlx4_dev *dev)
  79. {
  80. int eth_num_ports = 0;
  81. int ib_num_ports = 0;
  82. int dmfs = dev->caps.steering_mode == MLX4_STEERING_MODE_DEVICE_MANAGED;
  83. if (dmfs) {
  84. int i;
  85. mlx4_foreach_port(i, dev, MLX4_PORT_TYPE_ETH)
  86. eth_num_ports++;
  87. mlx4_foreach_port(i, dev, MLX4_PORT_TYPE_IB)
  88. ib_num_ports++;
  89. dmfs &= (!ib_num_ports ||
  90. (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_DMFS_IPOIB)) &&
  91. (!eth_num_ports ||
  92. (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_FS_EN));
  93. if (ib_num_ports && mlx4_is_mfunc(dev)) {
  94. pr_warn("Device managed flow steering is unavailable for IB port in multifunction env.\n");
  95. dmfs = 0;
  96. }
  97. }
  98. return dmfs;
  99. }
  100. static int num_ib_ports(struct mlx4_dev *dev)
  101. {
  102. int ib_ports = 0;
  103. int i;
  104. mlx4_foreach_port(i, dev, MLX4_PORT_TYPE_IB)
  105. ib_ports++;
  106. return ib_ports;
  107. }
  108. static struct net_device *mlx4_ib_get_netdev(struct ib_device *device, u8 port_num)
  109. {
  110. struct mlx4_ib_dev *ibdev = to_mdev(device);
  111. struct net_device *dev;
  112. rcu_read_lock();
  113. dev = mlx4_get_protocol_dev(ibdev->dev, MLX4_PROT_ETH, port_num);
  114. if (dev) {
  115. if (mlx4_is_bonded(ibdev->dev)) {
  116. struct net_device *upper = NULL;
  117. upper = netdev_master_upper_dev_get_rcu(dev);
  118. if (upper) {
  119. struct net_device *active;
  120. active = bond_option_active_slave_get_rcu(netdev_priv(upper));
  121. if (active)
  122. dev = active;
  123. }
  124. }
  125. }
  126. if (dev)
  127. dev_hold(dev);
  128. rcu_read_unlock();
  129. return dev;
  130. }
  131. static int mlx4_ib_update_gids(struct gid_entry *gids,
  132. struct mlx4_ib_dev *ibdev,
  133. u8 port_num)
  134. {
  135. struct mlx4_cmd_mailbox *mailbox;
  136. int err;
  137. struct mlx4_dev *dev = ibdev->dev;
  138. int i;
  139. union ib_gid *gid_tbl;
  140. mailbox = mlx4_alloc_cmd_mailbox(dev);
  141. if (IS_ERR(mailbox))
  142. return -ENOMEM;
  143. gid_tbl = mailbox->buf;
  144. for (i = 0; i < MLX4_MAX_PORT_GIDS; ++i)
  145. memcpy(&gid_tbl[i], &gids[i].gid, sizeof(union ib_gid));
  146. err = mlx4_cmd(dev, mailbox->dma,
  147. MLX4_SET_PORT_GID_TABLE << 8 | port_num,
  148. 1, MLX4_CMD_SET_PORT, MLX4_CMD_TIME_CLASS_B,
  149. MLX4_CMD_WRAPPED);
  150. if (mlx4_is_bonded(dev))
  151. err += mlx4_cmd(dev, mailbox->dma,
  152. MLX4_SET_PORT_GID_TABLE << 8 | 2,
  153. 1, MLX4_CMD_SET_PORT, MLX4_CMD_TIME_CLASS_B,
  154. MLX4_CMD_WRAPPED);
  155. mlx4_free_cmd_mailbox(dev, mailbox);
  156. return err;
  157. }
  158. static int mlx4_ib_add_gid(struct ib_device *device,
  159. u8 port_num,
  160. unsigned int index,
  161. const union ib_gid *gid,
  162. const struct ib_gid_attr *attr,
  163. void **context)
  164. {
  165. struct mlx4_ib_dev *ibdev = to_mdev(device);
  166. struct mlx4_ib_iboe *iboe = &ibdev->iboe;
  167. struct mlx4_port_gid_table *port_gid_table;
  168. int free = -1, found = -1;
  169. int ret = 0;
  170. int hw_update = 0;
  171. int i;
  172. struct gid_entry *gids = NULL;
  173. if (!rdma_cap_roce_gid_table(device, port_num))
  174. return -EINVAL;
  175. if (port_num > MLX4_MAX_PORTS)
  176. return -EINVAL;
  177. if (!context)
  178. return -EINVAL;
  179. port_gid_table = &iboe->gids[port_num - 1];
  180. spin_lock_bh(&iboe->lock);
  181. for (i = 0; i < MLX4_MAX_PORT_GIDS; ++i) {
  182. if (!memcmp(&port_gid_table->gids[i].gid, gid, sizeof(*gid))) {
  183. found = i;
  184. break;
  185. }
  186. if (free < 0 && !memcmp(&port_gid_table->gids[i].gid, &zgid, sizeof(*gid)))
  187. free = i; /* HW has space */
  188. }
  189. if (found < 0) {
  190. if (free < 0) {
  191. ret = -ENOSPC;
  192. } else {
  193. port_gid_table->gids[free].ctx = kmalloc(sizeof(*port_gid_table->gids[free].ctx), GFP_ATOMIC);
  194. if (!port_gid_table->gids[free].ctx) {
  195. ret = -ENOMEM;
  196. } else {
  197. *context = port_gid_table->gids[free].ctx;
  198. memcpy(&port_gid_table->gids[free].gid, gid, sizeof(*gid));
  199. port_gid_table->gids[free].ctx->real_index = free;
  200. port_gid_table->gids[free].ctx->refcount = 1;
  201. hw_update = 1;
  202. }
  203. }
  204. } else {
  205. struct gid_cache_context *ctx = port_gid_table->gids[found].ctx;
  206. *context = ctx;
  207. ctx->refcount++;
  208. }
  209. if (!ret && hw_update) {
  210. gids = kmalloc(sizeof(*gids) * MLX4_MAX_PORT_GIDS, GFP_ATOMIC);
  211. if (!gids) {
  212. ret = -ENOMEM;
  213. } else {
  214. for (i = 0; i < MLX4_MAX_PORT_GIDS; i++)
  215. memcpy(&gids[i].gid, &port_gid_table->gids[i].gid, sizeof(union ib_gid));
  216. }
  217. }
  218. spin_unlock_bh(&iboe->lock);
  219. if (!ret && hw_update) {
  220. ret = mlx4_ib_update_gids(gids, ibdev, port_num);
  221. kfree(gids);
  222. }
  223. return ret;
  224. }
  225. static int mlx4_ib_del_gid(struct ib_device *device,
  226. u8 port_num,
  227. unsigned int index,
  228. void **context)
  229. {
  230. struct gid_cache_context *ctx = *context;
  231. struct mlx4_ib_dev *ibdev = to_mdev(device);
  232. struct mlx4_ib_iboe *iboe = &ibdev->iboe;
  233. struct mlx4_port_gid_table *port_gid_table;
  234. int ret = 0;
  235. int hw_update = 0;
  236. struct gid_entry *gids = NULL;
  237. if (!rdma_cap_roce_gid_table(device, port_num))
  238. return -EINVAL;
  239. if (port_num > MLX4_MAX_PORTS)
  240. return -EINVAL;
  241. port_gid_table = &iboe->gids[port_num - 1];
  242. spin_lock_bh(&iboe->lock);
  243. if (ctx) {
  244. ctx->refcount--;
  245. if (!ctx->refcount) {
  246. unsigned int real_index = ctx->real_index;
  247. memcpy(&port_gid_table->gids[real_index].gid, &zgid, sizeof(zgid));
  248. kfree(port_gid_table->gids[real_index].ctx);
  249. port_gid_table->gids[real_index].ctx = NULL;
  250. hw_update = 1;
  251. }
  252. }
  253. if (!ret && hw_update) {
  254. int i;
  255. gids = kmalloc(sizeof(*gids) * MLX4_MAX_PORT_GIDS, GFP_ATOMIC);
  256. if (!gids) {
  257. ret = -ENOMEM;
  258. } else {
  259. for (i = 0; i < MLX4_MAX_PORT_GIDS; i++)
  260. memcpy(&gids[i].gid, &port_gid_table->gids[i].gid, sizeof(union ib_gid));
  261. }
  262. }
  263. spin_unlock_bh(&iboe->lock);
  264. if (!ret && hw_update) {
  265. ret = mlx4_ib_update_gids(gids, ibdev, port_num);
  266. kfree(gids);
  267. }
  268. return ret;
  269. }
  270. int mlx4_ib_gid_index_to_real_index(struct mlx4_ib_dev *ibdev,
  271. u8 port_num, int index)
  272. {
  273. struct mlx4_ib_iboe *iboe = &ibdev->iboe;
  274. struct gid_cache_context *ctx = NULL;
  275. union ib_gid gid;
  276. struct mlx4_port_gid_table *port_gid_table;
  277. int real_index = -EINVAL;
  278. int i;
  279. int ret;
  280. unsigned long flags;
  281. if (port_num > MLX4_MAX_PORTS)
  282. return -EINVAL;
  283. if (mlx4_is_bonded(ibdev->dev))
  284. port_num = 1;
  285. if (!rdma_cap_roce_gid_table(&ibdev->ib_dev, port_num))
  286. return index;
  287. ret = ib_get_cached_gid(&ibdev->ib_dev, port_num, index, &gid, NULL);
  288. if (ret)
  289. return ret;
  290. if (!memcmp(&gid, &zgid, sizeof(gid)))
  291. return -EINVAL;
  292. spin_lock_irqsave(&iboe->lock, flags);
  293. port_gid_table = &iboe->gids[port_num - 1];
  294. for (i = 0; i < MLX4_MAX_PORT_GIDS; ++i)
  295. if (!memcmp(&port_gid_table->gids[i].gid, &gid, sizeof(gid))) {
  296. ctx = port_gid_table->gids[i].ctx;
  297. break;
  298. }
  299. if (ctx)
  300. real_index = ctx->real_index;
  301. spin_unlock_irqrestore(&iboe->lock, flags);
  302. return real_index;
  303. }
  304. static int mlx4_ib_query_device(struct ib_device *ibdev,
  305. struct ib_device_attr *props,
  306. struct ib_udata *uhw)
  307. {
  308. struct mlx4_ib_dev *dev = to_mdev(ibdev);
  309. struct ib_smp *in_mad = NULL;
  310. struct ib_smp *out_mad = NULL;
  311. int err = -ENOMEM;
  312. int have_ib_ports;
  313. struct mlx4_uverbs_ex_query_device cmd;
  314. struct mlx4_uverbs_ex_query_device_resp resp = {.comp_mask = 0};
  315. struct mlx4_clock_params clock_params;
  316. if (uhw->inlen) {
  317. if (uhw->inlen < sizeof(cmd))
  318. return -EINVAL;
  319. err = ib_copy_from_udata(&cmd, uhw, sizeof(cmd));
  320. if (err)
  321. return err;
  322. if (cmd.comp_mask)
  323. return -EINVAL;
  324. if (cmd.reserved)
  325. return -EINVAL;
  326. }
  327. resp.response_length = offsetof(typeof(resp), response_length) +
  328. sizeof(resp.response_length);
  329. in_mad = kzalloc(sizeof *in_mad, GFP_KERNEL);
  330. out_mad = kmalloc(sizeof *out_mad, GFP_KERNEL);
  331. if (!in_mad || !out_mad)
  332. goto out;
  333. init_query_mad(in_mad);
  334. in_mad->attr_id = IB_SMP_ATTR_NODE_INFO;
  335. err = mlx4_MAD_IFC(to_mdev(ibdev), MLX4_MAD_IFC_IGNORE_KEYS,
  336. 1, NULL, NULL, in_mad, out_mad);
  337. if (err)
  338. goto out;
  339. memset(props, 0, sizeof *props);
  340. have_ib_ports = num_ib_ports(dev->dev);
  341. props->fw_ver = dev->dev->caps.fw_ver;
  342. props->device_cap_flags = IB_DEVICE_CHANGE_PHY_PORT |
  343. IB_DEVICE_PORT_ACTIVE_EVENT |
  344. IB_DEVICE_SYS_IMAGE_GUID |
  345. IB_DEVICE_RC_RNR_NAK_GEN |
  346. IB_DEVICE_BLOCK_MULTICAST_LOOPBACK;
  347. if (dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_BAD_PKEY_CNTR)
  348. props->device_cap_flags |= IB_DEVICE_BAD_PKEY_CNTR;
  349. if (dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_BAD_QKEY_CNTR)
  350. props->device_cap_flags |= IB_DEVICE_BAD_QKEY_CNTR;
  351. if (dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_APM && have_ib_ports)
  352. props->device_cap_flags |= IB_DEVICE_AUTO_PATH_MIG;
  353. if (dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_UD_AV_PORT)
  354. props->device_cap_flags |= IB_DEVICE_UD_AV_PORT_ENFORCE;
  355. if (dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_IPOIB_CSUM)
  356. props->device_cap_flags |= IB_DEVICE_UD_IP_CSUM;
  357. if (dev->dev->caps.max_gso_sz &&
  358. (dev->dev->rev_id != MLX4_IB_CARD_REV_A0) &&
  359. (dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_BLH))
  360. props->device_cap_flags |= IB_DEVICE_UD_TSO;
  361. if (dev->dev->caps.bmme_flags & MLX4_BMME_FLAG_RESERVED_LKEY)
  362. props->device_cap_flags |= IB_DEVICE_LOCAL_DMA_LKEY;
  363. if ((dev->dev->caps.bmme_flags & MLX4_BMME_FLAG_LOCAL_INV) &&
  364. (dev->dev->caps.bmme_flags & MLX4_BMME_FLAG_REMOTE_INV) &&
  365. (dev->dev->caps.bmme_flags & MLX4_BMME_FLAG_FAST_REG_WR))
  366. props->device_cap_flags |= IB_DEVICE_MEM_MGT_EXTENSIONS;
  367. if (dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_XRC)
  368. props->device_cap_flags |= IB_DEVICE_XRC;
  369. if (dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_MEM_WINDOW)
  370. props->device_cap_flags |= IB_DEVICE_MEM_WINDOW;
  371. if (dev->dev->caps.bmme_flags & MLX4_BMME_FLAG_TYPE_2_WIN) {
  372. if (dev->dev->caps.bmme_flags & MLX4_BMME_FLAG_WIN_TYPE_2B)
  373. props->device_cap_flags |= IB_DEVICE_MEM_WINDOW_TYPE_2B;
  374. else
  375. props->device_cap_flags |= IB_DEVICE_MEM_WINDOW_TYPE_2A;
  376. if (dev->steering_support == MLX4_STEERING_MODE_DEVICE_MANAGED)
  377. props->device_cap_flags |= IB_DEVICE_MANAGED_FLOW_STEERING;
  378. }
  379. props->device_cap_flags |= IB_DEVICE_RAW_IP_CSUM;
  380. props->vendor_id = be32_to_cpup((__be32 *) (out_mad->data + 36)) &
  381. 0xffffff;
  382. props->vendor_part_id = dev->dev->persist->pdev->device;
  383. props->hw_ver = be32_to_cpup((__be32 *) (out_mad->data + 32));
  384. memcpy(&props->sys_image_guid, out_mad->data + 4, 8);
  385. props->max_mr_size = ~0ull;
  386. props->page_size_cap = dev->dev->caps.page_size_cap;
  387. props->max_qp = dev->dev->quotas.qp;
  388. props->max_qp_wr = dev->dev->caps.max_wqes - MLX4_IB_SQ_MAX_SPARE;
  389. props->max_sge = min(dev->dev->caps.max_sq_sg,
  390. dev->dev->caps.max_rq_sg);
  391. props->max_sge_rd = MLX4_MAX_SGE_RD;
  392. props->max_cq = dev->dev->quotas.cq;
  393. props->max_cqe = dev->dev->caps.max_cqes;
  394. props->max_mr = dev->dev->quotas.mpt;
  395. props->max_pd = dev->dev->caps.num_pds - dev->dev->caps.reserved_pds;
  396. props->max_qp_rd_atom = dev->dev->caps.max_qp_dest_rdma;
  397. props->max_qp_init_rd_atom = dev->dev->caps.max_qp_init_rdma;
  398. props->max_res_rd_atom = props->max_qp_rd_atom * props->max_qp;
  399. props->max_srq = dev->dev->quotas.srq;
  400. props->max_srq_wr = dev->dev->caps.max_srq_wqes - 1;
  401. props->max_srq_sge = dev->dev->caps.max_srq_sge;
  402. props->max_fast_reg_page_list_len = MLX4_MAX_FAST_REG_PAGES;
  403. props->local_ca_ack_delay = dev->dev->caps.local_ca_ack_delay;
  404. props->atomic_cap = dev->dev->caps.flags & MLX4_DEV_CAP_FLAG_ATOMIC ?
  405. IB_ATOMIC_HCA : IB_ATOMIC_NONE;
  406. props->masked_atomic_cap = props->atomic_cap;
  407. props->max_pkeys = dev->dev->caps.pkey_table_len[1];
  408. props->max_mcast_grp = dev->dev->caps.num_mgms + dev->dev->caps.num_amgms;
  409. props->max_mcast_qp_attach = dev->dev->caps.num_qp_per_mgm;
  410. props->max_total_mcast_qp_attach = props->max_mcast_qp_attach *
  411. props->max_mcast_grp;
  412. props->max_map_per_fmr = dev->dev->caps.max_fmr_maps;
  413. props->hca_core_clock = dev->dev->caps.hca_core_clock * 1000UL;
  414. props->timestamp_mask = 0xFFFFFFFFFFFFULL;
  415. if (!mlx4_is_slave(dev->dev))
  416. err = mlx4_get_internal_clock_params(dev->dev, &clock_params);
  417. if (uhw->outlen >= resp.response_length + sizeof(resp.hca_core_clock_offset)) {
  418. resp.response_length += sizeof(resp.hca_core_clock_offset);
  419. if (!err && !mlx4_is_slave(dev->dev)) {
  420. resp.comp_mask |= QUERY_DEVICE_RESP_MASK_TIMESTAMP;
  421. resp.hca_core_clock_offset = clock_params.offset % PAGE_SIZE;
  422. }
  423. }
  424. if (uhw->outlen) {
  425. err = ib_copy_to_udata(uhw, &resp, resp.response_length);
  426. if (err)
  427. goto out;
  428. }
  429. out:
  430. kfree(in_mad);
  431. kfree(out_mad);
  432. return err;
  433. }
  434. static enum rdma_link_layer
  435. mlx4_ib_port_link_layer(struct ib_device *device, u8 port_num)
  436. {
  437. struct mlx4_dev *dev = to_mdev(device)->dev;
  438. return dev->caps.port_mask[port_num] == MLX4_PORT_TYPE_IB ?
  439. IB_LINK_LAYER_INFINIBAND : IB_LINK_LAYER_ETHERNET;
  440. }
  441. static int ib_link_query_port(struct ib_device *ibdev, u8 port,
  442. struct ib_port_attr *props, int netw_view)
  443. {
  444. struct ib_smp *in_mad = NULL;
  445. struct ib_smp *out_mad = NULL;
  446. int ext_active_speed;
  447. int mad_ifc_flags = MLX4_MAD_IFC_IGNORE_KEYS;
  448. int err = -ENOMEM;
  449. in_mad = kzalloc(sizeof *in_mad, GFP_KERNEL);
  450. out_mad = kmalloc(sizeof *out_mad, GFP_KERNEL);
  451. if (!in_mad || !out_mad)
  452. goto out;
  453. init_query_mad(in_mad);
  454. in_mad->attr_id = IB_SMP_ATTR_PORT_INFO;
  455. in_mad->attr_mod = cpu_to_be32(port);
  456. if (mlx4_is_mfunc(to_mdev(ibdev)->dev) && netw_view)
  457. mad_ifc_flags |= MLX4_MAD_IFC_NET_VIEW;
  458. err = mlx4_MAD_IFC(to_mdev(ibdev), mad_ifc_flags, port, NULL, NULL,
  459. in_mad, out_mad);
  460. if (err)
  461. goto out;
  462. props->lid = be16_to_cpup((__be16 *) (out_mad->data + 16));
  463. props->lmc = out_mad->data[34] & 0x7;
  464. props->sm_lid = be16_to_cpup((__be16 *) (out_mad->data + 18));
  465. props->sm_sl = out_mad->data[36] & 0xf;
  466. props->state = out_mad->data[32] & 0xf;
  467. props->phys_state = out_mad->data[33] >> 4;
  468. props->port_cap_flags = be32_to_cpup((__be32 *) (out_mad->data + 20));
  469. if (netw_view)
  470. props->gid_tbl_len = out_mad->data[50];
  471. else
  472. props->gid_tbl_len = to_mdev(ibdev)->dev->caps.gid_table_len[port];
  473. props->max_msg_sz = to_mdev(ibdev)->dev->caps.max_msg_sz;
  474. props->pkey_tbl_len = to_mdev(ibdev)->dev->caps.pkey_table_len[port];
  475. props->bad_pkey_cntr = be16_to_cpup((__be16 *) (out_mad->data + 46));
  476. props->qkey_viol_cntr = be16_to_cpup((__be16 *) (out_mad->data + 48));
  477. props->active_width = out_mad->data[31] & 0xf;
  478. props->active_speed = out_mad->data[35] >> 4;
  479. props->max_mtu = out_mad->data[41] & 0xf;
  480. props->active_mtu = out_mad->data[36] >> 4;
  481. props->subnet_timeout = out_mad->data[51] & 0x1f;
  482. props->max_vl_num = out_mad->data[37] >> 4;
  483. props->init_type_reply = out_mad->data[41] >> 4;
  484. /* Check if extended speeds (EDR/FDR/...) are supported */
  485. if (props->port_cap_flags & IB_PORT_EXTENDED_SPEEDS_SUP) {
  486. ext_active_speed = out_mad->data[62] >> 4;
  487. switch (ext_active_speed) {
  488. case 1:
  489. props->active_speed = IB_SPEED_FDR;
  490. break;
  491. case 2:
  492. props->active_speed = IB_SPEED_EDR;
  493. break;
  494. }
  495. }
  496. /* If reported active speed is QDR, check if is FDR-10 */
  497. if (props->active_speed == IB_SPEED_QDR) {
  498. init_query_mad(in_mad);
  499. in_mad->attr_id = MLX4_ATTR_EXTENDED_PORT_INFO;
  500. in_mad->attr_mod = cpu_to_be32(port);
  501. err = mlx4_MAD_IFC(to_mdev(ibdev), mad_ifc_flags, port,
  502. NULL, NULL, in_mad, out_mad);
  503. if (err)
  504. goto out;
  505. /* Checking LinkSpeedActive for FDR-10 */
  506. if (out_mad->data[15] & 0x1)
  507. props->active_speed = IB_SPEED_FDR10;
  508. }
  509. /* Avoid wrong speed value returned by FW if the IB link is down. */
  510. if (props->state == IB_PORT_DOWN)
  511. props->active_speed = IB_SPEED_SDR;
  512. out:
  513. kfree(in_mad);
  514. kfree(out_mad);
  515. return err;
  516. }
  517. static u8 state_to_phys_state(enum ib_port_state state)
  518. {
  519. return state == IB_PORT_ACTIVE ? 5 : 3;
  520. }
  521. static int eth_link_query_port(struct ib_device *ibdev, u8 port,
  522. struct ib_port_attr *props, int netw_view)
  523. {
  524. struct mlx4_ib_dev *mdev = to_mdev(ibdev);
  525. struct mlx4_ib_iboe *iboe = &mdev->iboe;
  526. struct net_device *ndev;
  527. enum ib_mtu tmp;
  528. struct mlx4_cmd_mailbox *mailbox;
  529. int err = 0;
  530. int is_bonded = mlx4_is_bonded(mdev->dev);
  531. mailbox = mlx4_alloc_cmd_mailbox(mdev->dev);
  532. if (IS_ERR(mailbox))
  533. return PTR_ERR(mailbox);
  534. err = mlx4_cmd_box(mdev->dev, 0, mailbox->dma, port, 0,
  535. MLX4_CMD_QUERY_PORT, MLX4_CMD_TIME_CLASS_B,
  536. MLX4_CMD_WRAPPED);
  537. if (err)
  538. goto out;
  539. props->active_width = (((u8 *)mailbox->buf)[5] == 0x40) ||
  540. (((u8 *)mailbox->buf)[5] == 0x20 /*56Gb*/) ?
  541. IB_WIDTH_4X : IB_WIDTH_1X;
  542. props->active_speed = (((u8 *)mailbox->buf)[5] == 0x20 /*56Gb*/) ?
  543. IB_SPEED_FDR : IB_SPEED_QDR;
  544. props->port_cap_flags = IB_PORT_CM_SUP | IB_PORT_IP_BASED_GIDS;
  545. props->gid_tbl_len = mdev->dev->caps.gid_table_len[port];
  546. props->max_msg_sz = mdev->dev->caps.max_msg_sz;
  547. props->pkey_tbl_len = 1;
  548. props->max_mtu = IB_MTU_4096;
  549. props->max_vl_num = 2;
  550. props->state = IB_PORT_DOWN;
  551. props->phys_state = state_to_phys_state(props->state);
  552. props->active_mtu = IB_MTU_256;
  553. spin_lock_bh(&iboe->lock);
  554. ndev = iboe->netdevs[port - 1];
  555. if (ndev && is_bonded) {
  556. rcu_read_lock(); /* required to get upper dev */
  557. ndev = netdev_master_upper_dev_get_rcu(ndev);
  558. rcu_read_unlock();
  559. }
  560. if (!ndev)
  561. goto out_unlock;
  562. tmp = iboe_get_mtu(ndev->mtu);
  563. props->active_mtu = tmp ? min(props->max_mtu, tmp) : IB_MTU_256;
  564. props->state = (netif_running(ndev) && netif_carrier_ok(ndev)) ?
  565. IB_PORT_ACTIVE : IB_PORT_DOWN;
  566. props->phys_state = state_to_phys_state(props->state);
  567. out_unlock:
  568. spin_unlock_bh(&iboe->lock);
  569. out:
  570. mlx4_free_cmd_mailbox(mdev->dev, mailbox);
  571. return err;
  572. }
  573. int __mlx4_ib_query_port(struct ib_device *ibdev, u8 port,
  574. struct ib_port_attr *props, int netw_view)
  575. {
  576. int err;
  577. memset(props, 0, sizeof *props);
  578. err = mlx4_ib_port_link_layer(ibdev, port) == IB_LINK_LAYER_INFINIBAND ?
  579. ib_link_query_port(ibdev, port, props, netw_view) :
  580. eth_link_query_port(ibdev, port, props, netw_view);
  581. return err;
  582. }
  583. static int mlx4_ib_query_port(struct ib_device *ibdev, u8 port,
  584. struct ib_port_attr *props)
  585. {
  586. /* returns host view */
  587. return __mlx4_ib_query_port(ibdev, port, props, 0);
  588. }
  589. int __mlx4_ib_query_gid(struct ib_device *ibdev, u8 port, int index,
  590. union ib_gid *gid, int netw_view)
  591. {
  592. struct ib_smp *in_mad = NULL;
  593. struct ib_smp *out_mad = NULL;
  594. int err = -ENOMEM;
  595. struct mlx4_ib_dev *dev = to_mdev(ibdev);
  596. int clear = 0;
  597. int mad_ifc_flags = MLX4_MAD_IFC_IGNORE_KEYS;
  598. in_mad = kzalloc(sizeof *in_mad, GFP_KERNEL);
  599. out_mad = kmalloc(sizeof *out_mad, GFP_KERNEL);
  600. if (!in_mad || !out_mad)
  601. goto out;
  602. init_query_mad(in_mad);
  603. in_mad->attr_id = IB_SMP_ATTR_PORT_INFO;
  604. in_mad->attr_mod = cpu_to_be32(port);
  605. if (mlx4_is_mfunc(dev->dev) && netw_view)
  606. mad_ifc_flags |= MLX4_MAD_IFC_NET_VIEW;
  607. err = mlx4_MAD_IFC(dev, mad_ifc_flags, port, NULL, NULL, in_mad, out_mad);
  608. if (err)
  609. goto out;
  610. memcpy(gid->raw, out_mad->data + 8, 8);
  611. if (mlx4_is_mfunc(dev->dev) && !netw_view) {
  612. if (index) {
  613. /* For any index > 0, return the null guid */
  614. err = 0;
  615. clear = 1;
  616. goto out;
  617. }
  618. }
  619. init_query_mad(in_mad);
  620. in_mad->attr_id = IB_SMP_ATTR_GUID_INFO;
  621. in_mad->attr_mod = cpu_to_be32(index / 8);
  622. err = mlx4_MAD_IFC(dev, mad_ifc_flags, port,
  623. NULL, NULL, in_mad, out_mad);
  624. if (err)
  625. goto out;
  626. memcpy(gid->raw + 8, out_mad->data + (index % 8) * 8, 8);
  627. out:
  628. if (clear)
  629. memset(gid->raw + 8, 0, 8);
  630. kfree(in_mad);
  631. kfree(out_mad);
  632. return err;
  633. }
  634. static int mlx4_ib_query_gid(struct ib_device *ibdev, u8 port, int index,
  635. union ib_gid *gid)
  636. {
  637. int ret;
  638. if (rdma_protocol_ib(ibdev, port))
  639. return __mlx4_ib_query_gid(ibdev, port, index, gid, 0);
  640. if (!rdma_protocol_roce(ibdev, port))
  641. return -ENODEV;
  642. if (!rdma_cap_roce_gid_table(ibdev, port))
  643. return -ENODEV;
  644. ret = ib_get_cached_gid(ibdev, port, index, gid, NULL);
  645. if (ret == -EAGAIN) {
  646. memcpy(gid, &zgid, sizeof(*gid));
  647. return 0;
  648. }
  649. return ret;
  650. }
  651. int __mlx4_ib_query_pkey(struct ib_device *ibdev, u8 port, u16 index,
  652. u16 *pkey, int netw_view)
  653. {
  654. struct ib_smp *in_mad = NULL;
  655. struct ib_smp *out_mad = NULL;
  656. int mad_ifc_flags = MLX4_MAD_IFC_IGNORE_KEYS;
  657. int err = -ENOMEM;
  658. in_mad = kzalloc(sizeof *in_mad, GFP_KERNEL);
  659. out_mad = kmalloc(sizeof *out_mad, GFP_KERNEL);
  660. if (!in_mad || !out_mad)
  661. goto out;
  662. init_query_mad(in_mad);
  663. in_mad->attr_id = IB_SMP_ATTR_PKEY_TABLE;
  664. in_mad->attr_mod = cpu_to_be32(index / 32);
  665. if (mlx4_is_mfunc(to_mdev(ibdev)->dev) && netw_view)
  666. mad_ifc_flags |= MLX4_MAD_IFC_NET_VIEW;
  667. err = mlx4_MAD_IFC(to_mdev(ibdev), mad_ifc_flags, port, NULL, NULL,
  668. in_mad, out_mad);
  669. if (err)
  670. goto out;
  671. *pkey = be16_to_cpu(((__be16 *) out_mad->data)[index % 32]);
  672. out:
  673. kfree(in_mad);
  674. kfree(out_mad);
  675. return err;
  676. }
  677. static int mlx4_ib_query_pkey(struct ib_device *ibdev, u8 port, u16 index, u16 *pkey)
  678. {
  679. return __mlx4_ib_query_pkey(ibdev, port, index, pkey, 0);
  680. }
  681. static int mlx4_ib_modify_device(struct ib_device *ibdev, int mask,
  682. struct ib_device_modify *props)
  683. {
  684. struct mlx4_cmd_mailbox *mailbox;
  685. unsigned long flags;
  686. if (mask & ~IB_DEVICE_MODIFY_NODE_DESC)
  687. return -EOPNOTSUPP;
  688. if (!(mask & IB_DEVICE_MODIFY_NODE_DESC))
  689. return 0;
  690. if (mlx4_is_slave(to_mdev(ibdev)->dev))
  691. return -EOPNOTSUPP;
  692. spin_lock_irqsave(&to_mdev(ibdev)->sm_lock, flags);
  693. memcpy(ibdev->node_desc, props->node_desc, 64);
  694. spin_unlock_irqrestore(&to_mdev(ibdev)->sm_lock, flags);
  695. /*
  696. * If possible, pass node desc to FW, so it can generate
  697. * a 144 trap. If cmd fails, just ignore.
  698. */
  699. mailbox = mlx4_alloc_cmd_mailbox(to_mdev(ibdev)->dev);
  700. if (IS_ERR(mailbox))
  701. return 0;
  702. memcpy(mailbox->buf, props->node_desc, 64);
  703. mlx4_cmd(to_mdev(ibdev)->dev, mailbox->dma, 1, 0,
  704. MLX4_CMD_SET_NODE, MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE);
  705. mlx4_free_cmd_mailbox(to_mdev(ibdev)->dev, mailbox);
  706. return 0;
  707. }
  708. static int mlx4_ib_SET_PORT(struct mlx4_ib_dev *dev, u8 port, int reset_qkey_viols,
  709. u32 cap_mask)
  710. {
  711. struct mlx4_cmd_mailbox *mailbox;
  712. int err;
  713. mailbox = mlx4_alloc_cmd_mailbox(dev->dev);
  714. if (IS_ERR(mailbox))
  715. return PTR_ERR(mailbox);
  716. if (dev->dev->flags & MLX4_FLAG_OLD_PORT_CMDS) {
  717. *(u8 *) mailbox->buf = !!reset_qkey_viols << 6;
  718. ((__be32 *) mailbox->buf)[2] = cpu_to_be32(cap_mask);
  719. } else {
  720. ((u8 *) mailbox->buf)[3] = !!reset_qkey_viols;
  721. ((__be32 *) mailbox->buf)[1] = cpu_to_be32(cap_mask);
  722. }
  723. err = mlx4_cmd(dev->dev, mailbox->dma, port, MLX4_SET_PORT_IB_OPCODE,
  724. MLX4_CMD_SET_PORT, MLX4_CMD_TIME_CLASS_B,
  725. MLX4_CMD_WRAPPED);
  726. mlx4_free_cmd_mailbox(dev->dev, mailbox);
  727. return err;
  728. }
  729. static int mlx4_ib_modify_port(struct ib_device *ibdev, u8 port, int mask,
  730. struct ib_port_modify *props)
  731. {
  732. struct mlx4_ib_dev *mdev = to_mdev(ibdev);
  733. u8 is_eth = mdev->dev->caps.port_type[port] == MLX4_PORT_TYPE_ETH;
  734. struct ib_port_attr attr;
  735. u32 cap_mask;
  736. int err;
  737. /* return OK if this is RoCE. CM calls ib_modify_port() regardless
  738. * of whether port link layer is ETH or IB. For ETH ports, qkey
  739. * violations and port capabilities are not meaningful.
  740. */
  741. if (is_eth)
  742. return 0;
  743. mutex_lock(&mdev->cap_mask_mutex);
  744. err = mlx4_ib_query_port(ibdev, port, &attr);
  745. if (err)
  746. goto out;
  747. cap_mask = (attr.port_cap_flags | props->set_port_cap_mask) &
  748. ~props->clr_port_cap_mask;
  749. err = mlx4_ib_SET_PORT(mdev, port,
  750. !!(mask & IB_PORT_RESET_QKEY_CNTR),
  751. cap_mask);
  752. out:
  753. mutex_unlock(&to_mdev(ibdev)->cap_mask_mutex);
  754. return err;
  755. }
  756. static struct ib_ucontext *mlx4_ib_alloc_ucontext(struct ib_device *ibdev,
  757. struct ib_udata *udata)
  758. {
  759. struct mlx4_ib_dev *dev = to_mdev(ibdev);
  760. struct mlx4_ib_ucontext *context;
  761. struct mlx4_ib_alloc_ucontext_resp_v3 resp_v3;
  762. struct mlx4_ib_alloc_ucontext_resp resp;
  763. int err;
  764. if (!dev->ib_active)
  765. return ERR_PTR(-EAGAIN);
  766. if (ibdev->uverbs_abi_ver == MLX4_IB_UVERBS_NO_DEV_CAPS_ABI_VERSION) {
  767. resp_v3.qp_tab_size = dev->dev->caps.num_qps;
  768. resp_v3.bf_reg_size = dev->dev->caps.bf_reg_size;
  769. resp_v3.bf_regs_per_page = dev->dev->caps.bf_regs_per_page;
  770. } else {
  771. resp.dev_caps = dev->dev->caps.userspace_caps;
  772. resp.qp_tab_size = dev->dev->caps.num_qps;
  773. resp.bf_reg_size = dev->dev->caps.bf_reg_size;
  774. resp.bf_regs_per_page = dev->dev->caps.bf_regs_per_page;
  775. resp.cqe_size = dev->dev->caps.cqe_size;
  776. }
  777. context = kzalloc(sizeof(*context), GFP_KERNEL);
  778. if (!context)
  779. return ERR_PTR(-ENOMEM);
  780. err = mlx4_uar_alloc(to_mdev(ibdev)->dev, &context->uar);
  781. if (err) {
  782. kfree(context);
  783. return ERR_PTR(err);
  784. }
  785. INIT_LIST_HEAD(&context->db_page_list);
  786. mutex_init(&context->db_page_mutex);
  787. if (ibdev->uverbs_abi_ver == MLX4_IB_UVERBS_NO_DEV_CAPS_ABI_VERSION)
  788. err = ib_copy_to_udata(udata, &resp_v3, sizeof(resp_v3));
  789. else
  790. err = ib_copy_to_udata(udata, &resp, sizeof(resp));
  791. if (err) {
  792. mlx4_uar_free(to_mdev(ibdev)->dev, &context->uar);
  793. kfree(context);
  794. return ERR_PTR(-EFAULT);
  795. }
  796. return &context->ibucontext;
  797. }
  798. static int mlx4_ib_dealloc_ucontext(struct ib_ucontext *ibcontext)
  799. {
  800. struct mlx4_ib_ucontext *context = to_mucontext(ibcontext);
  801. mlx4_uar_free(to_mdev(ibcontext->device)->dev, &context->uar);
  802. kfree(context);
  803. return 0;
  804. }
  805. static void mlx4_ib_vma_open(struct vm_area_struct *area)
  806. {
  807. /* vma_open is called when a new VMA is created on top of our VMA.
  808. * This is done through either mremap flow or split_vma (usually due
  809. * to mlock, madvise, munmap, etc.). We do not support a clone of the
  810. * vma, as this VMA is strongly hardware related. Therefore we set the
  811. * vm_ops of the newly created/cloned VMA to NULL, to prevent it from
  812. * calling us again and trying to do incorrect actions. We assume that
  813. * the original vma size is exactly a single page that there will be no
  814. * "splitting" operations on.
  815. */
  816. area->vm_ops = NULL;
  817. }
  818. static void mlx4_ib_vma_close(struct vm_area_struct *area)
  819. {
  820. struct mlx4_ib_vma_private_data *mlx4_ib_vma_priv_data;
  821. /* It's guaranteed that all VMAs opened on a FD are closed before the
  822. * file itself is closed, therefore no sync is needed with the regular
  823. * closing flow. (e.g. mlx4_ib_dealloc_ucontext) However need a sync
  824. * with accessing the vma as part of mlx4_ib_disassociate_ucontext.
  825. * The close operation is usually called under mm->mmap_sem except when
  826. * process is exiting. The exiting case is handled explicitly as part
  827. * of mlx4_ib_disassociate_ucontext.
  828. */
  829. mlx4_ib_vma_priv_data = (struct mlx4_ib_vma_private_data *)
  830. area->vm_private_data;
  831. /* set the vma context pointer to null in the mlx4_ib driver's private
  832. * data to protect against a race condition in mlx4_ib_dissassociate_ucontext().
  833. */
  834. mlx4_ib_vma_priv_data->vma = NULL;
  835. }
  836. static const struct vm_operations_struct mlx4_ib_vm_ops = {
  837. .open = mlx4_ib_vma_open,
  838. .close = mlx4_ib_vma_close
  839. };
  840. static void mlx4_ib_disassociate_ucontext(struct ib_ucontext *ibcontext)
  841. {
  842. int i;
  843. int ret = 0;
  844. struct vm_area_struct *vma;
  845. struct mlx4_ib_ucontext *context = to_mucontext(ibcontext);
  846. struct task_struct *owning_process = NULL;
  847. struct mm_struct *owning_mm = NULL;
  848. owning_process = get_pid_task(ibcontext->tgid, PIDTYPE_PID);
  849. if (!owning_process)
  850. return;
  851. owning_mm = get_task_mm(owning_process);
  852. if (!owning_mm) {
  853. pr_info("no mm, disassociate ucontext is pending task termination\n");
  854. while (1) {
  855. /* make sure that task is dead before returning, it may
  856. * prevent a rare case of module down in parallel to a
  857. * call to mlx4_ib_vma_close.
  858. */
  859. put_task_struct(owning_process);
  860. msleep(1);
  861. owning_process = get_pid_task(ibcontext->tgid,
  862. PIDTYPE_PID);
  863. if (!owning_process ||
  864. owning_process->state == TASK_DEAD) {
  865. pr_info("disassociate ucontext done, task was terminated\n");
  866. /* in case task was dead need to release the task struct */
  867. if (owning_process)
  868. put_task_struct(owning_process);
  869. return;
  870. }
  871. }
  872. }
  873. /* need to protect from a race on closing the vma as part of
  874. * mlx4_ib_vma_close().
  875. */
  876. down_write(&owning_mm->mmap_sem);
  877. for (i = 0; i < HW_BAR_COUNT; i++) {
  878. vma = context->hw_bar_info[i].vma;
  879. if (!vma)
  880. continue;
  881. ret = zap_vma_ptes(context->hw_bar_info[i].vma,
  882. context->hw_bar_info[i].vma->vm_start,
  883. PAGE_SIZE);
  884. if (ret) {
  885. pr_err("Error: zap_vma_ptes failed for index=%d, ret=%d\n", i, ret);
  886. BUG_ON(1);
  887. }
  888. context->hw_bar_info[i].vma->vm_flags &=
  889. ~(VM_SHARED | VM_MAYSHARE);
  890. /* context going to be destroyed, should not access ops any more */
  891. context->hw_bar_info[i].vma->vm_ops = NULL;
  892. }
  893. up_write(&owning_mm->mmap_sem);
  894. mmput(owning_mm);
  895. put_task_struct(owning_process);
  896. }
  897. static void mlx4_ib_set_vma_data(struct vm_area_struct *vma,
  898. struct mlx4_ib_vma_private_data *vma_private_data)
  899. {
  900. vma_private_data->vma = vma;
  901. vma->vm_private_data = vma_private_data;
  902. vma->vm_ops = &mlx4_ib_vm_ops;
  903. }
  904. static int mlx4_ib_mmap(struct ib_ucontext *context, struct vm_area_struct *vma)
  905. {
  906. struct mlx4_ib_dev *dev = to_mdev(context->device);
  907. struct mlx4_ib_ucontext *mucontext = to_mucontext(context);
  908. if (vma->vm_end - vma->vm_start != PAGE_SIZE)
  909. return -EINVAL;
  910. if (vma->vm_pgoff == 0) {
  911. /* We prevent double mmaping on same context */
  912. if (mucontext->hw_bar_info[HW_BAR_DB].vma)
  913. return -EINVAL;
  914. vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
  915. if (io_remap_pfn_range(vma, vma->vm_start,
  916. to_mucontext(context)->uar.pfn,
  917. PAGE_SIZE, vma->vm_page_prot))
  918. return -EAGAIN;
  919. mlx4_ib_set_vma_data(vma, &mucontext->hw_bar_info[HW_BAR_DB]);
  920. } else if (vma->vm_pgoff == 1 && dev->dev->caps.bf_reg_size != 0) {
  921. /* We prevent double mmaping on same context */
  922. if (mucontext->hw_bar_info[HW_BAR_BF].vma)
  923. return -EINVAL;
  924. vma->vm_page_prot = pgprot_writecombine(vma->vm_page_prot);
  925. if (io_remap_pfn_range(vma, vma->vm_start,
  926. to_mucontext(context)->uar.pfn +
  927. dev->dev->caps.num_uars,
  928. PAGE_SIZE, vma->vm_page_prot))
  929. return -EAGAIN;
  930. mlx4_ib_set_vma_data(vma, &mucontext->hw_bar_info[HW_BAR_BF]);
  931. } else if (vma->vm_pgoff == 3) {
  932. struct mlx4_clock_params params;
  933. int ret;
  934. /* We prevent double mmaping on same context */
  935. if (mucontext->hw_bar_info[HW_BAR_CLOCK].vma)
  936. return -EINVAL;
  937. ret = mlx4_get_internal_clock_params(dev->dev, &params);
  938. if (ret)
  939. return ret;
  940. vma->vm_page_prot = pgprot_noncached(vma->vm_page_prot);
  941. if (io_remap_pfn_range(vma, vma->vm_start,
  942. (pci_resource_start(dev->dev->persist->pdev,
  943. params.bar) +
  944. params.offset)
  945. >> PAGE_SHIFT,
  946. PAGE_SIZE, vma->vm_page_prot))
  947. return -EAGAIN;
  948. mlx4_ib_set_vma_data(vma,
  949. &mucontext->hw_bar_info[HW_BAR_CLOCK]);
  950. } else {
  951. return -EINVAL;
  952. }
  953. return 0;
  954. }
  955. static struct ib_pd *mlx4_ib_alloc_pd(struct ib_device *ibdev,
  956. struct ib_ucontext *context,
  957. struct ib_udata *udata)
  958. {
  959. struct mlx4_ib_pd *pd;
  960. int err;
  961. pd = kmalloc(sizeof *pd, GFP_KERNEL);
  962. if (!pd)
  963. return ERR_PTR(-ENOMEM);
  964. err = mlx4_pd_alloc(to_mdev(ibdev)->dev, &pd->pdn);
  965. if (err) {
  966. kfree(pd);
  967. return ERR_PTR(err);
  968. }
  969. if (context)
  970. if (ib_copy_to_udata(udata, &pd->pdn, sizeof (__u32))) {
  971. mlx4_pd_free(to_mdev(ibdev)->dev, pd->pdn);
  972. kfree(pd);
  973. return ERR_PTR(-EFAULT);
  974. }
  975. return &pd->ibpd;
  976. }
  977. static int mlx4_ib_dealloc_pd(struct ib_pd *pd)
  978. {
  979. mlx4_pd_free(to_mdev(pd->device)->dev, to_mpd(pd)->pdn);
  980. kfree(pd);
  981. return 0;
  982. }
  983. static struct ib_xrcd *mlx4_ib_alloc_xrcd(struct ib_device *ibdev,
  984. struct ib_ucontext *context,
  985. struct ib_udata *udata)
  986. {
  987. struct mlx4_ib_xrcd *xrcd;
  988. struct ib_cq_init_attr cq_attr = {};
  989. int err;
  990. if (!(to_mdev(ibdev)->dev->caps.flags & MLX4_DEV_CAP_FLAG_XRC))
  991. return ERR_PTR(-ENOSYS);
  992. xrcd = kmalloc(sizeof *xrcd, GFP_KERNEL);
  993. if (!xrcd)
  994. return ERR_PTR(-ENOMEM);
  995. err = mlx4_xrcd_alloc(to_mdev(ibdev)->dev, &xrcd->xrcdn);
  996. if (err)
  997. goto err1;
  998. xrcd->pd = ib_alloc_pd(ibdev);
  999. if (IS_ERR(xrcd->pd)) {
  1000. err = PTR_ERR(xrcd->pd);
  1001. goto err2;
  1002. }
  1003. cq_attr.cqe = 1;
  1004. xrcd->cq = ib_create_cq(ibdev, NULL, NULL, xrcd, &cq_attr);
  1005. if (IS_ERR(xrcd->cq)) {
  1006. err = PTR_ERR(xrcd->cq);
  1007. goto err3;
  1008. }
  1009. return &xrcd->ibxrcd;
  1010. err3:
  1011. ib_dealloc_pd(xrcd->pd);
  1012. err2:
  1013. mlx4_xrcd_free(to_mdev(ibdev)->dev, xrcd->xrcdn);
  1014. err1:
  1015. kfree(xrcd);
  1016. return ERR_PTR(err);
  1017. }
  1018. static int mlx4_ib_dealloc_xrcd(struct ib_xrcd *xrcd)
  1019. {
  1020. ib_destroy_cq(to_mxrcd(xrcd)->cq);
  1021. ib_dealloc_pd(to_mxrcd(xrcd)->pd);
  1022. mlx4_xrcd_free(to_mdev(xrcd->device)->dev, to_mxrcd(xrcd)->xrcdn);
  1023. kfree(xrcd);
  1024. return 0;
  1025. }
  1026. static int add_gid_entry(struct ib_qp *ibqp, union ib_gid *gid)
  1027. {
  1028. struct mlx4_ib_qp *mqp = to_mqp(ibqp);
  1029. struct mlx4_ib_dev *mdev = to_mdev(ibqp->device);
  1030. struct mlx4_ib_gid_entry *ge;
  1031. ge = kzalloc(sizeof *ge, GFP_KERNEL);
  1032. if (!ge)
  1033. return -ENOMEM;
  1034. ge->gid = *gid;
  1035. if (mlx4_ib_add_mc(mdev, mqp, gid)) {
  1036. ge->port = mqp->port;
  1037. ge->added = 1;
  1038. }
  1039. mutex_lock(&mqp->mutex);
  1040. list_add_tail(&ge->list, &mqp->gid_list);
  1041. mutex_unlock(&mqp->mutex);
  1042. return 0;
  1043. }
  1044. static void mlx4_ib_delete_counters_table(struct mlx4_ib_dev *ibdev,
  1045. struct mlx4_ib_counters *ctr_table)
  1046. {
  1047. struct counter_index *counter, *tmp_count;
  1048. mutex_lock(&ctr_table->mutex);
  1049. list_for_each_entry_safe(counter, tmp_count, &ctr_table->counters_list,
  1050. list) {
  1051. if (counter->allocated)
  1052. mlx4_counter_free(ibdev->dev, counter->index);
  1053. list_del(&counter->list);
  1054. kfree(counter);
  1055. }
  1056. mutex_unlock(&ctr_table->mutex);
  1057. }
  1058. int mlx4_ib_add_mc(struct mlx4_ib_dev *mdev, struct mlx4_ib_qp *mqp,
  1059. union ib_gid *gid)
  1060. {
  1061. struct net_device *ndev;
  1062. int ret = 0;
  1063. if (!mqp->port)
  1064. return 0;
  1065. spin_lock_bh(&mdev->iboe.lock);
  1066. ndev = mdev->iboe.netdevs[mqp->port - 1];
  1067. if (ndev)
  1068. dev_hold(ndev);
  1069. spin_unlock_bh(&mdev->iboe.lock);
  1070. if (ndev) {
  1071. ret = 1;
  1072. dev_put(ndev);
  1073. }
  1074. return ret;
  1075. }
  1076. struct mlx4_ib_steering {
  1077. struct list_head list;
  1078. struct mlx4_flow_reg_id reg_id;
  1079. union ib_gid gid;
  1080. };
  1081. static int parse_flow_attr(struct mlx4_dev *dev,
  1082. u32 qp_num,
  1083. union ib_flow_spec *ib_spec,
  1084. struct _rule_hw *mlx4_spec)
  1085. {
  1086. enum mlx4_net_trans_rule_id type;
  1087. switch (ib_spec->type) {
  1088. case IB_FLOW_SPEC_ETH:
  1089. type = MLX4_NET_TRANS_RULE_ID_ETH;
  1090. memcpy(mlx4_spec->eth.dst_mac, ib_spec->eth.val.dst_mac,
  1091. ETH_ALEN);
  1092. memcpy(mlx4_spec->eth.dst_mac_msk, ib_spec->eth.mask.dst_mac,
  1093. ETH_ALEN);
  1094. mlx4_spec->eth.vlan_tag = ib_spec->eth.val.vlan_tag;
  1095. mlx4_spec->eth.vlan_tag_msk = ib_spec->eth.mask.vlan_tag;
  1096. break;
  1097. case IB_FLOW_SPEC_IB:
  1098. type = MLX4_NET_TRANS_RULE_ID_IB;
  1099. mlx4_spec->ib.l3_qpn =
  1100. cpu_to_be32(qp_num);
  1101. mlx4_spec->ib.qpn_mask =
  1102. cpu_to_be32(MLX4_IB_FLOW_QPN_MASK);
  1103. break;
  1104. case IB_FLOW_SPEC_IPV4:
  1105. type = MLX4_NET_TRANS_RULE_ID_IPV4;
  1106. mlx4_spec->ipv4.src_ip = ib_spec->ipv4.val.src_ip;
  1107. mlx4_spec->ipv4.src_ip_msk = ib_spec->ipv4.mask.src_ip;
  1108. mlx4_spec->ipv4.dst_ip = ib_spec->ipv4.val.dst_ip;
  1109. mlx4_spec->ipv4.dst_ip_msk = ib_spec->ipv4.mask.dst_ip;
  1110. break;
  1111. case IB_FLOW_SPEC_TCP:
  1112. case IB_FLOW_SPEC_UDP:
  1113. type = ib_spec->type == IB_FLOW_SPEC_TCP ?
  1114. MLX4_NET_TRANS_RULE_ID_TCP :
  1115. MLX4_NET_TRANS_RULE_ID_UDP;
  1116. mlx4_spec->tcp_udp.dst_port = ib_spec->tcp_udp.val.dst_port;
  1117. mlx4_spec->tcp_udp.dst_port_msk = ib_spec->tcp_udp.mask.dst_port;
  1118. mlx4_spec->tcp_udp.src_port = ib_spec->tcp_udp.val.src_port;
  1119. mlx4_spec->tcp_udp.src_port_msk = ib_spec->tcp_udp.mask.src_port;
  1120. break;
  1121. default:
  1122. return -EINVAL;
  1123. }
  1124. if (mlx4_map_sw_to_hw_steering_id(dev, type) < 0 ||
  1125. mlx4_hw_rule_sz(dev, type) < 0)
  1126. return -EINVAL;
  1127. mlx4_spec->id = cpu_to_be16(mlx4_map_sw_to_hw_steering_id(dev, type));
  1128. mlx4_spec->size = mlx4_hw_rule_sz(dev, type) >> 2;
  1129. return mlx4_hw_rule_sz(dev, type);
  1130. }
  1131. struct default_rules {
  1132. __u32 mandatory_fields[IB_FLOW_SPEC_SUPPORT_LAYERS];
  1133. __u32 mandatory_not_fields[IB_FLOW_SPEC_SUPPORT_LAYERS];
  1134. __u32 rules_create_list[IB_FLOW_SPEC_SUPPORT_LAYERS];
  1135. __u8 link_layer;
  1136. };
  1137. static const struct default_rules default_table[] = {
  1138. {
  1139. .mandatory_fields = {IB_FLOW_SPEC_IPV4},
  1140. .mandatory_not_fields = {IB_FLOW_SPEC_ETH},
  1141. .rules_create_list = {IB_FLOW_SPEC_IB},
  1142. .link_layer = IB_LINK_LAYER_INFINIBAND
  1143. }
  1144. };
  1145. static int __mlx4_ib_default_rules_match(struct ib_qp *qp,
  1146. struct ib_flow_attr *flow_attr)
  1147. {
  1148. int i, j, k;
  1149. void *ib_flow;
  1150. const struct default_rules *pdefault_rules = default_table;
  1151. u8 link_layer = rdma_port_get_link_layer(qp->device, flow_attr->port);
  1152. for (i = 0; i < ARRAY_SIZE(default_table); i++, pdefault_rules++) {
  1153. __u32 field_types[IB_FLOW_SPEC_SUPPORT_LAYERS];
  1154. memset(&field_types, 0, sizeof(field_types));
  1155. if (link_layer != pdefault_rules->link_layer)
  1156. continue;
  1157. ib_flow = flow_attr + 1;
  1158. /* we assume the specs are sorted */
  1159. for (j = 0, k = 0; k < IB_FLOW_SPEC_SUPPORT_LAYERS &&
  1160. j < flow_attr->num_of_specs; k++) {
  1161. union ib_flow_spec *current_flow =
  1162. (union ib_flow_spec *)ib_flow;
  1163. /* same layer but different type */
  1164. if (((current_flow->type & IB_FLOW_SPEC_LAYER_MASK) ==
  1165. (pdefault_rules->mandatory_fields[k] &
  1166. IB_FLOW_SPEC_LAYER_MASK)) &&
  1167. (current_flow->type !=
  1168. pdefault_rules->mandatory_fields[k]))
  1169. goto out;
  1170. /* same layer, try match next one */
  1171. if (current_flow->type ==
  1172. pdefault_rules->mandatory_fields[k]) {
  1173. j++;
  1174. ib_flow +=
  1175. ((union ib_flow_spec *)ib_flow)->size;
  1176. }
  1177. }
  1178. ib_flow = flow_attr + 1;
  1179. for (j = 0; j < flow_attr->num_of_specs;
  1180. j++, ib_flow += ((union ib_flow_spec *)ib_flow)->size)
  1181. for (k = 0; k < IB_FLOW_SPEC_SUPPORT_LAYERS; k++)
  1182. /* same layer and same type */
  1183. if (((union ib_flow_spec *)ib_flow)->type ==
  1184. pdefault_rules->mandatory_not_fields[k])
  1185. goto out;
  1186. return i;
  1187. }
  1188. out:
  1189. return -1;
  1190. }
  1191. static int __mlx4_ib_create_default_rules(
  1192. struct mlx4_ib_dev *mdev,
  1193. struct ib_qp *qp,
  1194. const struct default_rules *pdefault_rules,
  1195. struct _rule_hw *mlx4_spec) {
  1196. int size = 0;
  1197. int i;
  1198. for (i = 0; i < ARRAY_SIZE(pdefault_rules->rules_create_list); i++) {
  1199. int ret;
  1200. union ib_flow_spec ib_spec;
  1201. switch (pdefault_rules->rules_create_list[i]) {
  1202. case 0:
  1203. /* no rule */
  1204. continue;
  1205. case IB_FLOW_SPEC_IB:
  1206. ib_spec.type = IB_FLOW_SPEC_IB;
  1207. ib_spec.size = sizeof(struct ib_flow_spec_ib);
  1208. break;
  1209. default:
  1210. /* invalid rule */
  1211. return -EINVAL;
  1212. }
  1213. /* We must put empty rule, qpn is being ignored */
  1214. ret = parse_flow_attr(mdev->dev, 0, &ib_spec,
  1215. mlx4_spec);
  1216. if (ret < 0) {
  1217. pr_info("invalid parsing\n");
  1218. return -EINVAL;
  1219. }
  1220. mlx4_spec = (void *)mlx4_spec + ret;
  1221. size += ret;
  1222. }
  1223. return size;
  1224. }
  1225. static int __mlx4_ib_create_flow(struct ib_qp *qp, struct ib_flow_attr *flow_attr,
  1226. int domain,
  1227. enum mlx4_net_trans_promisc_mode flow_type,
  1228. u64 *reg_id)
  1229. {
  1230. int ret, i;
  1231. int size = 0;
  1232. void *ib_flow;
  1233. struct mlx4_ib_dev *mdev = to_mdev(qp->device);
  1234. struct mlx4_cmd_mailbox *mailbox;
  1235. struct mlx4_net_trans_rule_hw_ctrl *ctrl;
  1236. int default_flow;
  1237. static const u16 __mlx4_domain[] = {
  1238. [IB_FLOW_DOMAIN_USER] = MLX4_DOMAIN_UVERBS,
  1239. [IB_FLOW_DOMAIN_ETHTOOL] = MLX4_DOMAIN_ETHTOOL,
  1240. [IB_FLOW_DOMAIN_RFS] = MLX4_DOMAIN_RFS,
  1241. [IB_FLOW_DOMAIN_NIC] = MLX4_DOMAIN_NIC,
  1242. };
  1243. if (flow_attr->priority > MLX4_IB_FLOW_MAX_PRIO) {
  1244. pr_err("Invalid priority value %d\n", flow_attr->priority);
  1245. return -EINVAL;
  1246. }
  1247. if (domain >= IB_FLOW_DOMAIN_NUM) {
  1248. pr_err("Invalid domain value %d\n", domain);
  1249. return -EINVAL;
  1250. }
  1251. if (mlx4_map_sw_to_hw_steering_mode(mdev->dev, flow_type) < 0)
  1252. return -EINVAL;
  1253. mailbox = mlx4_alloc_cmd_mailbox(mdev->dev);
  1254. if (IS_ERR(mailbox))
  1255. return PTR_ERR(mailbox);
  1256. ctrl = mailbox->buf;
  1257. ctrl->prio = cpu_to_be16(__mlx4_domain[domain] |
  1258. flow_attr->priority);
  1259. ctrl->type = mlx4_map_sw_to_hw_steering_mode(mdev->dev, flow_type);
  1260. ctrl->port = flow_attr->port;
  1261. ctrl->qpn = cpu_to_be32(qp->qp_num);
  1262. ib_flow = flow_attr + 1;
  1263. size += sizeof(struct mlx4_net_trans_rule_hw_ctrl);
  1264. /* Add default flows */
  1265. default_flow = __mlx4_ib_default_rules_match(qp, flow_attr);
  1266. if (default_flow >= 0) {
  1267. ret = __mlx4_ib_create_default_rules(
  1268. mdev, qp, default_table + default_flow,
  1269. mailbox->buf + size);
  1270. if (ret < 0) {
  1271. mlx4_free_cmd_mailbox(mdev->dev, mailbox);
  1272. return -EINVAL;
  1273. }
  1274. size += ret;
  1275. }
  1276. for (i = 0; i < flow_attr->num_of_specs; i++) {
  1277. ret = parse_flow_attr(mdev->dev, qp->qp_num, ib_flow,
  1278. mailbox->buf + size);
  1279. if (ret < 0) {
  1280. mlx4_free_cmd_mailbox(mdev->dev, mailbox);
  1281. return -EINVAL;
  1282. }
  1283. ib_flow += ((union ib_flow_spec *) ib_flow)->size;
  1284. size += ret;
  1285. }
  1286. ret = mlx4_cmd_imm(mdev->dev, mailbox->dma, reg_id, size >> 2, 0,
  1287. MLX4_QP_FLOW_STEERING_ATTACH, MLX4_CMD_TIME_CLASS_A,
  1288. MLX4_CMD_WRAPPED);
  1289. if (ret == -ENOMEM)
  1290. pr_err("mcg table is full. Fail to register network rule.\n");
  1291. else if (ret == -ENXIO)
  1292. pr_err("Device managed flow steering is disabled. Fail to register network rule.\n");
  1293. else if (ret)
  1294. pr_err("Invalid argumant. Fail to register network rule.\n");
  1295. mlx4_free_cmd_mailbox(mdev->dev, mailbox);
  1296. return ret;
  1297. }
  1298. static int __mlx4_ib_destroy_flow(struct mlx4_dev *dev, u64 reg_id)
  1299. {
  1300. int err;
  1301. err = mlx4_cmd(dev, reg_id, 0, 0,
  1302. MLX4_QP_FLOW_STEERING_DETACH, MLX4_CMD_TIME_CLASS_A,
  1303. MLX4_CMD_WRAPPED);
  1304. if (err)
  1305. pr_err("Fail to detach network rule. registration id = 0x%llx\n",
  1306. reg_id);
  1307. return err;
  1308. }
  1309. static int mlx4_ib_tunnel_steer_add(struct ib_qp *qp, struct ib_flow_attr *flow_attr,
  1310. u64 *reg_id)
  1311. {
  1312. void *ib_flow;
  1313. union ib_flow_spec *ib_spec;
  1314. struct mlx4_dev *dev = to_mdev(qp->device)->dev;
  1315. int err = 0;
  1316. if (dev->caps.tunnel_offload_mode != MLX4_TUNNEL_OFFLOAD_MODE_VXLAN ||
  1317. dev->caps.dmfs_high_steer_mode == MLX4_STEERING_DMFS_A0_STATIC)
  1318. return 0; /* do nothing */
  1319. ib_flow = flow_attr + 1;
  1320. ib_spec = (union ib_flow_spec *)ib_flow;
  1321. if (ib_spec->type != IB_FLOW_SPEC_ETH || flow_attr->num_of_specs != 1)
  1322. return 0; /* do nothing */
  1323. err = mlx4_tunnel_steer_add(to_mdev(qp->device)->dev, ib_spec->eth.val.dst_mac,
  1324. flow_attr->port, qp->qp_num,
  1325. MLX4_DOMAIN_UVERBS | (flow_attr->priority & 0xff),
  1326. reg_id);
  1327. return err;
  1328. }
  1329. static struct ib_flow *mlx4_ib_create_flow(struct ib_qp *qp,
  1330. struct ib_flow_attr *flow_attr,
  1331. int domain)
  1332. {
  1333. int err = 0, i = 0, j = 0;
  1334. struct mlx4_ib_flow *mflow;
  1335. enum mlx4_net_trans_promisc_mode type[2];
  1336. struct mlx4_dev *dev = (to_mdev(qp->device))->dev;
  1337. int is_bonded = mlx4_is_bonded(dev);
  1338. memset(type, 0, sizeof(type));
  1339. mflow = kzalloc(sizeof(*mflow), GFP_KERNEL);
  1340. if (!mflow) {
  1341. err = -ENOMEM;
  1342. goto err_free;
  1343. }
  1344. switch (flow_attr->type) {
  1345. case IB_FLOW_ATTR_NORMAL:
  1346. type[0] = MLX4_FS_REGULAR;
  1347. break;
  1348. case IB_FLOW_ATTR_ALL_DEFAULT:
  1349. type[0] = MLX4_FS_ALL_DEFAULT;
  1350. break;
  1351. case IB_FLOW_ATTR_MC_DEFAULT:
  1352. type[0] = MLX4_FS_MC_DEFAULT;
  1353. break;
  1354. case IB_FLOW_ATTR_SNIFFER:
  1355. type[0] = MLX4_FS_UC_SNIFFER;
  1356. type[1] = MLX4_FS_MC_SNIFFER;
  1357. break;
  1358. default:
  1359. err = -EINVAL;
  1360. goto err_free;
  1361. }
  1362. while (i < ARRAY_SIZE(type) && type[i]) {
  1363. err = __mlx4_ib_create_flow(qp, flow_attr, domain, type[i],
  1364. &mflow->reg_id[i].id);
  1365. if (err)
  1366. goto err_create_flow;
  1367. if (is_bonded) {
  1368. /* Application always sees one port so the mirror rule
  1369. * must be on port #2
  1370. */
  1371. flow_attr->port = 2;
  1372. err = __mlx4_ib_create_flow(qp, flow_attr,
  1373. domain, type[j],
  1374. &mflow->reg_id[j].mirror);
  1375. flow_attr->port = 1;
  1376. if (err)
  1377. goto err_create_flow;
  1378. j++;
  1379. }
  1380. i++;
  1381. }
  1382. if (i < ARRAY_SIZE(type) && flow_attr->type == IB_FLOW_ATTR_NORMAL) {
  1383. err = mlx4_ib_tunnel_steer_add(qp, flow_attr,
  1384. &mflow->reg_id[i].id);
  1385. if (err)
  1386. goto err_create_flow;
  1387. if (is_bonded) {
  1388. flow_attr->port = 2;
  1389. err = mlx4_ib_tunnel_steer_add(qp, flow_attr,
  1390. &mflow->reg_id[j].mirror);
  1391. flow_attr->port = 1;
  1392. if (err)
  1393. goto err_create_flow;
  1394. j++;
  1395. }
  1396. /* function to create mirror rule */
  1397. i++;
  1398. }
  1399. return &mflow->ibflow;
  1400. err_create_flow:
  1401. while (i) {
  1402. (void)__mlx4_ib_destroy_flow(to_mdev(qp->device)->dev,
  1403. mflow->reg_id[i].id);
  1404. i--;
  1405. }
  1406. while (j) {
  1407. (void)__mlx4_ib_destroy_flow(to_mdev(qp->device)->dev,
  1408. mflow->reg_id[j].mirror);
  1409. j--;
  1410. }
  1411. err_free:
  1412. kfree(mflow);
  1413. return ERR_PTR(err);
  1414. }
  1415. static int mlx4_ib_destroy_flow(struct ib_flow *flow_id)
  1416. {
  1417. int err, ret = 0;
  1418. int i = 0;
  1419. struct mlx4_ib_dev *mdev = to_mdev(flow_id->qp->device);
  1420. struct mlx4_ib_flow *mflow = to_mflow(flow_id);
  1421. while (i < ARRAY_SIZE(mflow->reg_id) && mflow->reg_id[i].id) {
  1422. err = __mlx4_ib_destroy_flow(mdev->dev, mflow->reg_id[i].id);
  1423. if (err)
  1424. ret = err;
  1425. if (mflow->reg_id[i].mirror) {
  1426. err = __mlx4_ib_destroy_flow(mdev->dev,
  1427. mflow->reg_id[i].mirror);
  1428. if (err)
  1429. ret = err;
  1430. }
  1431. i++;
  1432. }
  1433. kfree(mflow);
  1434. return ret;
  1435. }
  1436. static int mlx4_ib_mcg_attach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid)
  1437. {
  1438. int err;
  1439. struct mlx4_ib_dev *mdev = to_mdev(ibqp->device);
  1440. struct mlx4_dev *dev = mdev->dev;
  1441. struct mlx4_ib_qp *mqp = to_mqp(ibqp);
  1442. struct mlx4_ib_steering *ib_steering = NULL;
  1443. enum mlx4_protocol prot = MLX4_PROT_IB_IPV6;
  1444. struct mlx4_flow_reg_id reg_id;
  1445. if (mdev->dev->caps.steering_mode ==
  1446. MLX4_STEERING_MODE_DEVICE_MANAGED) {
  1447. ib_steering = kmalloc(sizeof(*ib_steering), GFP_KERNEL);
  1448. if (!ib_steering)
  1449. return -ENOMEM;
  1450. }
  1451. err = mlx4_multicast_attach(mdev->dev, &mqp->mqp, gid->raw, mqp->port,
  1452. !!(mqp->flags &
  1453. MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK),
  1454. prot, &reg_id.id);
  1455. if (err) {
  1456. pr_err("multicast attach op failed, err %d\n", err);
  1457. goto err_malloc;
  1458. }
  1459. reg_id.mirror = 0;
  1460. if (mlx4_is_bonded(dev)) {
  1461. err = mlx4_multicast_attach(mdev->dev, &mqp->mqp, gid->raw,
  1462. (mqp->port == 1) ? 2 : 1,
  1463. !!(mqp->flags &
  1464. MLX4_IB_QP_BLOCK_MULTICAST_LOOPBACK),
  1465. prot, &reg_id.mirror);
  1466. if (err)
  1467. goto err_add;
  1468. }
  1469. err = add_gid_entry(ibqp, gid);
  1470. if (err)
  1471. goto err_add;
  1472. if (ib_steering) {
  1473. memcpy(ib_steering->gid.raw, gid->raw, 16);
  1474. ib_steering->reg_id = reg_id;
  1475. mutex_lock(&mqp->mutex);
  1476. list_add(&ib_steering->list, &mqp->steering_rules);
  1477. mutex_unlock(&mqp->mutex);
  1478. }
  1479. return 0;
  1480. err_add:
  1481. mlx4_multicast_detach(mdev->dev, &mqp->mqp, gid->raw,
  1482. prot, reg_id.id);
  1483. if (reg_id.mirror)
  1484. mlx4_multicast_detach(mdev->dev, &mqp->mqp, gid->raw,
  1485. prot, reg_id.mirror);
  1486. err_malloc:
  1487. kfree(ib_steering);
  1488. return err;
  1489. }
  1490. static struct mlx4_ib_gid_entry *find_gid_entry(struct mlx4_ib_qp *qp, u8 *raw)
  1491. {
  1492. struct mlx4_ib_gid_entry *ge;
  1493. struct mlx4_ib_gid_entry *tmp;
  1494. struct mlx4_ib_gid_entry *ret = NULL;
  1495. list_for_each_entry_safe(ge, tmp, &qp->gid_list, list) {
  1496. if (!memcmp(raw, ge->gid.raw, 16)) {
  1497. ret = ge;
  1498. break;
  1499. }
  1500. }
  1501. return ret;
  1502. }
  1503. static int mlx4_ib_mcg_detach(struct ib_qp *ibqp, union ib_gid *gid, u16 lid)
  1504. {
  1505. int err;
  1506. struct mlx4_ib_dev *mdev = to_mdev(ibqp->device);
  1507. struct mlx4_dev *dev = mdev->dev;
  1508. struct mlx4_ib_qp *mqp = to_mqp(ibqp);
  1509. struct net_device *ndev;
  1510. struct mlx4_ib_gid_entry *ge;
  1511. struct mlx4_flow_reg_id reg_id = {0, 0};
  1512. enum mlx4_protocol prot = MLX4_PROT_IB_IPV6;
  1513. if (mdev->dev->caps.steering_mode ==
  1514. MLX4_STEERING_MODE_DEVICE_MANAGED) {
  1515. struct mlx4_ib_steering *ib_steering;
  1516. mutex_lock(&mqp->mutex);
  1517. list_for_each_entry(ib_steering, &mqp->steering_rules, list) {
  1518. if (!memcmp(ib_steering->gid.raw, gid->raw, 16)) {
  1519. list_del(&ib_steering->list);
  1520. break;
  1521. }
  1522. }
  1523. mutex_unlock(&mqp->mutex);
  1524. if (&ib_steering->list == &mqp->steering_rules) {
  1525. pr_err("Couldn't find reg_id for mgid. Steering rule is left attached\n");
  1526. return -EINVAL;
  1527. }
  1528. reg_id = ib_steering->reg_id;
  1529. kfree(ib_steering);
  1530. }
  1531. err = mlx4_multicast_detach(mdev->dev, &mqp->mqp, gid->raw,
  1532. prot, reg_id.id);
  1533. if (err)
  1534. return err;
  1535. if (mlx4_is_bonded(dev)) {
  1536. err = mlx4_multicast_detach(mdev->dev, &mqp->mqp, gid->raw,
  1537. prot, reg_id.mirror);
  1538. if (err)
  1539. return err;
  1540. }
  1541. mutex_lock(&mqp->mutex);
  1542. ge = find_gid_entry(mqp, gid->raw);
  1543. if (ge) {
  1544. spin_lock_bh(&mdev->iboe.lock);
  1545. ndev = ge->added ? mdev->iboe.netdevs[ge->port - 1] : NULL;
  1546. if (ndev)
  1547. dev_hold(ndev);
  1548. spin_unlock_bh(&mdev->iboe.lock);
  1549. if (ndev)
  1550. dev_put(ndev);
  1551. list_del(&ge->list);
  1552. kfree(ge);
  1553. } else
  1554. pr_warn("could not find mgid entry\n");
  1555. mutex_unlock(&mqp->mutex);
  1556. return 0;
  1557. }
  1558. static int init_node_data(struct mlx4_ib_dev *dev)
  1559. {
  1560. struct ib_smp *in_mad = NULL;
  1561. struct ib_smp *out_mad = NULL;
  1562. int mad_ifc_flags = MLX4_MAD_IFC_IGNORE_KEYS;
  1563. int err = -ENOMEM;
  1564. in_mad = kzalloc(sizeof *in_mad, GFP_KERNEL);
  1565. out_mad = kmalloc(sizeof *out_mad, GFP_KERNEL);
  1566. if (!in_mad || !out_mad)
  1567. goto out;
  1568. init_query_mad(in_mad);
  1569. in_mad->attr_id = IB_SMP_ATTR_NODE_DESC;
  1570. if (mlx4_is_master(dev->dev))
  1571. mad_ifc_flags |= MLX4_MAD_IFC_NET_VIEW;
  1572. err = mlx4_MAD_IFC(dev, mad_ifc_flags, 1, NULL, NULL, in_mad, out_mad);
  1573. if (err)
  1574. goto out;
  1575. memcpy(dev->ib_dev.node_desc, out_mad->data, 64);
  1576. in_mad->attr_id = IB_SMP_ATTR_NODE_INFO;
  1577. err = mlx4_MAD_IFC(dev, mad_ifc_flags, 1, NULL, NULL, in_mad, out_mad);
  1578. if (err)
  1579. goto out;
  1580. dev->dev->rev_id = be32_to_cpup((__be32 *) (out_mad->data + 32));
  1581. memcpy(&dev->ib_dev.node_guid, out_mad->data + 12, 8);
  1582. out:
  1583. kfree(in_mad);
  1584. kfree(out_mad);
  1585. return err;
  1586. }
  1587. static ssize_t show_hca(struct device *device, struct device_attribute *attr,
  1588. char *buf)
  1589. {
  1590. struct mlx4_ib_dev *dev =
  1591. container_of(device, struct mlx4_ib_dev, ib_dev.dev);
  1592. return sprintf(buf, "MT%d\n", dev->dev->persist->pdev->device);
  1593. }
  1594. static ssize_t show_fw_ver(struct device *device, struct device_attribute *attr,
  1595. char *buf)
  1596. {
  1597. struct mlx4_ib_dev *dev =
  1598. container_of(device, struct mlx4_ib_dev, ib_dev.dev);
  1599. return sprintf(buf, "%d.%d.%d\n", (int) (dev->dev->caps.fw_ver >> 32),
  1600. (int) (dev->dev->caps.fw_ver >> 16) & 0xffff,
  1601. (int) dev->dev->caps.fw_ver & 0xffff);
  1602. }
  1603. static ssize_t show_rev(struct device *device, struct device_attribute *attr,
  1604. char *buf)
  1605. {
  1606. struct mlx4_ib_dev *dev =
  1607. container_of(device, struct mlx4_ib_dev, ib_dev.dev);
  1608. return sprintf(buf, "%x\n", dev->dev->rev_id);
  1609. }
  1610. static ssize_t show_board(struct device *device, struct device_attribute *attr,
  1611. char *buf)
  1612. {
  1613. struct mlx4_ib_dev *dev =
  1614. container_of(device, struct mlx4_ib_dev, ib_dev.dev);
  1615. return sprintf(buf, "%.*s\n", MLX4_BOARD_ID_LEN,
  1616. dev->dev->board_id);
  1617. }
  1618. static DEVICE_ATTR(hw_rev, S_IRUGO, show_rev, NULL);
  1619. static DEVICE_ATTR(fw_ver, S_IRUGO, show_fw_ver, NULL);
  1620. static DEVICE_ATTR(hca_type, S_IRUGO, show_hca, NULL);
  1621. static DEVICE_ATTR(board_id, S_IRUGO, show_board, NULL);
  1622. static struct device_attribute *mlx4_class_attributes[] = {
  1623. &dev_attr_hw_rev,
  1624. &dev_attr_fw_ver,
  1625. &dev_attr_hca_type,
  1626. &dev_attr_board_id
  1627. };
  1628. #define MLX4_IB_INVALID_MAC ((u64)-1)
  1629. static void mlx4_ib_update_qps(struct mlx4_ib_dev *ibdev,
  1630. struct net_device *dev,
  1631. int port)
  1632. {
  1633. u64 new_smac = 0;
  1634. u64 release_mac = MLX4_IB_INVALID_MAC;
  1635. struct mlx4_ib_qp *qp;
  1636. read_lock(&dev_base_lock);
  1637. new_smac = mlx4_mac_to_u64(dev->dev_addr);
  1638. read_unlock(&dev_base_lock);
  1639. atomic64_set(&ibdev->iboe.mac[port - 1], new_smac);
  1640. /* no need for update QP1 and mac registration in non-SRIOV */
  1641. if (!mlx4_is_mfunc(ibdev->dev))
  1642. return;
  1643. mutex_lock(&ibdev->qp1_proxy_lock[port - 1]);
  1644. qp = ibdev->qp1_proxy[port - 1];
  1645. if (qp) {
  1646. int new_smac_index;
  1647. u64 old_smac;
  1648. struct mlx4_update_qp_params update_params;
  1649. mutex_lock(&qp->mutex);
  1650. old_smac = qp->pri.smac;
  1651. if (new_smac == old_smac)
  1652. goto unlock;
  1653. new_smac_index = mlx4_register_mac(ibdev->dev, port, new_smac);
  1654. if (new_smac_index < 0)
  1655. goto unlock;
  1656. update_params.smac_index = new_smac_index;
  1657. if (mlx4_update_qp(ibdev->dev, qp->mqp.qpn, MLX4_UPDATE_QP_SMAC,
  1658. &update_params)) {
  1659. release_mac = new_smac;
  1660. goto unlock;
  1661. }
  1662. /* if old port was zero, no mac was yet registered for this QP */
  1663. if (qp->pri.smac_port)
  1664. release_mac = old_smac;
  1665. qp->pri.smac = new_smac;
  1666. qp->pri.smac_port = port;
  1667. qp->pri.smac_index = new_smac_index;
  1668. }
  1669. unlock:
  1670. if (release_mac != MLX4_IB_INVALID_MAC)
  1671. mlx4_unregister_mac(ibdev->dev, port, release_mac);
  1672. if (qp)
  1673. mutex_unlock(&qp->mutex);
  1674. mutex_unlock(&ibdev->qp1_proxy_lock[port - 1]);
  1675. }
  1676. static void mlx4_ib_scan_netdevs(struct mlx4_ib_dev *ibdev,
  1677. struct net_device *dev,
  1678. unsigned long event)
  1679. {
  1680. struct mlx4_ib_iboe *iboe;
  1681. int update_qps_port = -1;
  1682. int port;
  1683. ASSERT_RTNL();
  1684. iboe = &ibdev->iboe;
  1685. spin_lock_bh(&iboe->lock);
  1686. mlx4_foreach_ib_transport_port(port, ibdev->dev) {
  1687. iboe->netdevs[port - 1] =
  1688. mlx4_get_protocol_dev(ibdev->dev, MLX4_PROT_ETH, port);
  1689. if (dev == iboe->netdevs[port - 1] &&
  1690. (event == NETDEV_CHANGEADDR || event == NETDEV_REGISTER ||
  1691. event == NETDEV_UP || event == NETDEV_CHANGE))
  1692. update_qps_port = port;
  1693. }
  1694. spin_unlock_bh(&iboe->lock);
  1695. if (update_qps_port > 0)
  1696. mlx4_ib_update_qps(ibdev, dev, update_qps_port);
  1697. }
  1698. static int mlx4_ib_netdev_event(struct notifier_block *this,
  1699. unsigned long event, void *ptr)
  1700. {
  1701. struct net_device *dev = netdev_notifier_info_to_dev(ptr);
  1702. struct mlx4_ib_dev *ibdev;
  1703. if (!net_eq(dev_net(dev), &init_net))
  1704. return NOTIFY_DONE;
  1705. ibdev = container_of(this, struct mlx4_ib_dev, iboe.nb);
  1706. mlx4_ib_scan_netdevs(ibdev, dev, event);
  1707. return NOTIFY_DONE;
  1708. }
  1709. static void init_pkeys(struct mlx4_ib_dev *ibdev)
  1710. {
  1711. int port;
  1712. int slave;
  1713. int i;
  1714. if (mlx4_is_master(ibdev->dev)) {
  1715. for (slave = 0; slave <= ibdev->dev->persist->num_vfs;
  1716. ++slave) {
  1717. for (port = 1; port <= ibdev->dev->caps.num_ports; ++port) {
  1718. for (i = 0;
  1719. i < ibdev->dev->phys_caps.pkey_phys_table_len[port];
  1720. ++i) {
  1721. ibdev->pkeys.virt2phys_pkey[slave][port - 1][i] =
  1722. /* master has the identity virt2phys pkey mapping */
  1723. (slave == mlx4_master_func_num(ibdev->dev) || !i) ? i :
  1724. ibdev->dev->phys_caps.pkey_phys_table_len[port] - 1;
  1725. mlx4_sync_pkey_table(ibdev->dev, slave, port, i,
  1726. ibdev->pkeys.virt2phys_pkey[slave][port - 1][i]);
  1727. }
  1728. }
  1729. }
  1730. /* initialize pkey cache */
  1731. for (port = 1; port <= ibdev->dev->caps.num_ports; ++port) {
  1732. for (i = 0;
  1733. i < ibdev->dev->phys_caps.pkey_phys_table_len[port];
  1734. ++i)
  1735. ibdev->pkeys.phys_pkey_cache[port-1][i] =
  1736. (i) ? 0 : 0xFFFF;
  1737. }
  1738. }
  1739. }
  1740. static void mlx4_ib_alloc_eqs(struct mlx4_dev *dev, struct mlx4_ib_dev *ibdev)
  1741. {
  1742. int i, j, eq = 0, total_eqs = 0;
  1743. ibdev->eq_table = kcalloc(dev->caps.num_comp_vectors,
  1744. sizeof(ibdev->eq_table[0]), GFP_KERNEL);
  1745. if (!ibdev->eq_table)
  1746. return;
  1747. for (i = 1; i <= dev->caps.num_ports; i++) {
  1748. for (j = 0; j < mlx4_get_eqs_per_port(dev, i);
  1749. j++, total_eqs++) {
  1750. if (i > 1 && mlx4_is_eq_shared(dev, total_eqs))
  1751. continue;
  1752. ibdev->eq_table[eq] = total_eqs;
  1753. if (!mlx4_assign_eq(dev, i,
  1754. &ibdev->eq_table[eq]))
  1755. eq++;
  1756. else
  1757. ibdev->eq_table[eq] = -1;
  1758. }
  1759. }
  1760. for (i = eq; i < dev->caps.num_comp_vectors;
  1761. ibdev->eq_table[i++] = -1)
  1762. ;
  1763. /* Advertise the new number of EQs to clients */
  1764. ibdev->ib_dev.num_comp_vectors = eq;
  1765. }
  1766. static void mlx4_ib_free_eqs(struct mlx4_dev *dev, struct mlx4_ib_dev *ibdev)
  1767. {
  1768. int i;
  1769. int total_eqs = ibdev->ib_dev.num_comp_vectors;
  1770. /* no eqs were allocated */
  1771. if (!ibdev->eq_table)
  1772. return;
  1773. /* Reset the advertised EQ number */
  1774. ibdev->ib_dev.num_comp_vectors = 0;
  1775. for (i = 0; i < total_eqs; i++)
  1776. mlx4_release_eq(dev, ibdev->eq_table[i]);
  1777. kfree(ibdev->eq_table);
  1778. ibdev->eq_table = NULL;
  1779. }
  1780. static int mlx4_port_immutable(struct ib_device *ibdev, u8 port_num,
  1781. struct ib_port_immutable *immutable)
  1782. {
  1783. struct ib_port_attr attr;
  1784. int err;
  1785. err = mlx4_ib_query_port(ibdev, port_num, &attr);
  1786. if (err)
  1787. return err;
  1788. immutable->pkey_tbl_len = attr.pkey_tbl_len;
  1789. immutable->gid_tbl_len = attr.gid_tbl_len;
  1790. if (mlx4_ib_port_link_layer(ibdev, port_num) == IB_LINK_LAYER_INFINIBAND)
  1791. immutable->core_cap_flags = RDMA_CORE_PORT_IBA_IB;
  1792. else
  1793. immutable->core_cap_flags = RDMA_CORE_PORT_IBA_ROCE;
  1794. immutable->max_mad_size = IB_MGMT_MAD_SIZE;
  1795. return 0;
  1796. }
  1797. static void *mlx4_ib_add(struct mlx4_dev *dev)
  1798. {
  1799. struct mlx4_ib_dev *ibdev;
  1800. int num_ports = 0;
  1801. int i, j;
  1802. int err;
  1803. struct mlx4_ib_iboe *iboe;
  1804. int ib_num_ports = 0;
  1805. int num_req_counters;
  1806. int allocated;
  1807. u32 counter_index;
  1808. struct counter_index *new_counter_index = NULL;
  1809. pr_info_once("%s", mlx4_ib_version);
  1810. num_ports = 0;
  1811. mlx4_foreach_ib_transport_port(i, dev)
  1812. num_ports++;
  1813. /* No point in registering a device with no ports... */
  1814. if (num_ports == 0)
  1815. return NULL;
  1816. ibdev = (struct mlx4_ib_dev *) ib_alloc_device(sizeof *ibdev);
  1817. if (!ibdev) {
  1818. dev_err(&dev->persist->pdev->dev,
  1819. "Device struct alloc failed\n");
  1820. return NULL;
  1821. }
  1822. iboe = &ibdev->iboe;
  1823. if (mlx4_pd_alloc(dev, &ibdev->priv_pdn))
  1824. goto err_dealloc;
  1825. if (mlx4_uar_alloc(dev, &ibdev->priv_uar))
  1826. goto err_pd;
  1827. ibdev->uar_map = ioremap((phys_addr_t) ibdev->priv_uar.pfn << PAGE_SHIFT,
  1828. PAGE_SIZE);
  1829. if (!ibdev->uar_map)
  1830. goto err_uar;
  1831. MLX4_INIT_DOORBELL_LOCK(&ibdev->uar_lock);
  1832. ibdev->dev = dev;
  1833. ibdev->bond_next_port = 0;
  1834. strlcpy(ibdev->ib_dev.name, "mlx4_%d", IB_DEVICE_NAME_MAX);
  1835. ibdev->ib_dev.owner = THIS_MODULE;
  1836. ibdev->ib_dev.node_type = RDMA_NODE_IB_CA;
  1837. ibdev->ib_dev.local_dma_lkey = dev->caps.reserved_lkey;
  1838. ibdev->num_ports = num_ports;
  1839. ibdev->ib_dev.phys_port_cnt = mlx4_is_bonded(dev) ?
  1840. 1 : ibdev->num_ports;
  1841. ibdev->ib_dev.num_comp_vectors = dev->caps.num_comp_vectors;
  1842. ibdev->ib_dev.dma_device = &dev->persist->pdev->dev;
  1843. ibdev->ib_dev.get_netdev = mlx4_ib_get_netdev;
  1844. ibdev->ib_dev.add_gid = mlx4_ib_add_gid;
  1845. ibdev->ib_dev.del_gid = mlx4_ib_del_gid;
  1846. if (dev->caps.userspace_caps)
  1847. ibdev->ib_dev.uverbs_abi_ver = MLX4_IB_UVERBS_ABI_VERSION;
  1848. else
  1849. ibdev->ib_dev.uverbs_abi_ver = MLX4_IB_UVERBS_NO_DEV_CAPS_ABI_VERSION;
  1850. ibdev->ib_dev.uverbs_cmd_mask =
  1851. (1ull << IB_USER_VERBS_CMD_GET_CONTEXT) |
  1852. (1ull << IB_USER_VERBS_CMD_QUERY_DEVICE) |
  1853. (1ull << IB_USER_VERBS_CMD_QUERY_PORT) |
  1854. (1ull << IB_USER_VERBS_CMD_ALLOC_PD) |
  1855. (1ull << IB_USER_VERBS_CMD_DEALLOC_PD) |
  1856. (1ull << IB_USER_VERBS_CMD_REG_MR) |
  1857. (1ull << IB_USER_VERBS_CMD_REREG_MR) |
  1858. (1ull << IB_USER_VERBS_CMD_DEREG_MR) |
  1859. (1ull << IB_USER_VERBS_CMD_CREATE_COMP_CHANNEL) |
  1860. (1ull << IB_USER_VERBS_CMD_CREATE_CQ) |
  1861. (1ull << IB_USER_VERBS_CMD_RESIZE_CQ) |
  1862. (1ull << IB_USER_VERBS_CMD_DESTROY_CQ) |
  1863. (1ull << IB_USER_VERBS_CMD_CREATE_QP) |
  1864. (1ull << IB_USER_VERBS_CMD_MODIFY_QP) |
  1865. (1ull << IB_USER_VERBS_CMD_QUERY_QP) |
  1866. (1ull << IB_USER_VERBS_CMD_DESTROY_QP) |
  1867. (1ull << IB_USER_VERBS_CMD_ATTACH_MCAST) |
  1868. (1ull << IB_USER_VERBS_CMD_DETACH_MCAST) |
  1869. (1ull << IB_USER_VERBS_CMD_CREATE_SRQ) |
  1870. (1ull << IB_USER_VERBS_CMD_MODIFY_SRQ) |
  1871. (1ull << IB_USER_VERBS_CMD_QUERY_SRQ) |
  1872. (1ull << IB_USER_VERBS_CMD_DESTROY_SRQ) |
  1873. (1ull << IB_USER_VERBS_CMD_CREATE_XSRQ) |
  1874. (1ull << IB_USER_VERBS_CMD_OPEN_QP);
  1875. ibdev->ib_dev.query_device = mlx4_ib_query_device;
  1876. ibdev->ib_dev.query_port = mlx4_ib_query_port;
  1877. ibdev->ib_dev.get_link_layer = mlx4_ib_port_link_layer;
  1878. ibdev->ib_dev.query_gid = mlx4_ib_query_gid;
  1879. ibdev->ib_dev.query_pkey = mlx4_ib_query_pkey;
  1880. ibdev->ib_dev.modify_device = mlx4_ib_modify_device;
  1881. ibdev->ib_dev.modify_port = mlx4_ib_modify_port;
  1882. ibdev->ib_dev.alloc_ucontext = mlx4_ib_alloc_ucontext;
  1883. ibdev->ib_dev.dealloc_ucontext = mlx4_ib_dealloc_ucontext;
  1884. ibdev->ib_dev.mmap = mlx4_ib_mmap;
  1885. ibdev->ib_dev.alloc_pd = mlx4_ib_alloc_pd;
  1886. ibdev->ib_dev.dealloc_pd = mlx4_ib_dealloc_pd;
  1887. ibdev->ib_dev.create_ah = mlx4_ib_create_ah;
  1888. ibdev->ib_dev.query_ah = mlx4_ib_query_ah;
  1889. ibdev->ib_dev.destroy_ah = mlx4_ib_destroy_ah;
  1890. ibdev->ib_dev.create_srq = mlx4_ib_create_srq;
  1891. ibdev->ib_dev.modify_srq = mlx4_ib_modify_srq;
  1892. ibdev->ib_dev.query_srq = mlx4_ib_query_srq;
  1893. ibdev->ib_dev.destroy_srq = mlx4_ib_destroy_srq;
  1894. ibdev->ib_dev.post_srq_recv = mlx4_ib_post_srq_recv;
  1895. ibdev->ib_dev.create_qp = mlx4_ib_create_qp;
  1896. ibdev->ib_dev.modify_qp = mlx4_ib_modify_qp;
  1897. ibdev->ib_dev.query_qp = mlx4_ib_query_qp;
  1898. ibdev->ib_dev.destroy_qp = mlx4_ib_destroy_qp;
  1899. ibdev->ib_dev.post_send = mlx4_ib_post_send;
  1900. ibdev->ib_dev.post_recv = mlx4_ib_post_recv;
  1901. ibdev->ib_dev.create_cq = mlx4_ib_create_cq;
  1902. ibdev->ib_dev.modify_cq = mlx4_ib_modify_cq;
  1903. ibdev->ib_dev.resize_cq = mlx4_ib_resize_cq;
  1904. ibdev->ib_dev.destroy_cq = mlx4_ib_destroy_cq;
  1905. ibdev->ib_dev.poll_cq = mlx4_ib_poll_cq;
  1906. ibdev->ib_dev.req_notify_cq = mlx4_ib_arm_cq;
  1907. ibdev->ib_dev.get_dma_mr = mlx4_ib_get_dma_mr;
  1908. ibdev->ib_dev.reg_user_mr = mlx4_ib_reg_user_mr;
  1909. ibdev->ib_dev.rereg_user_mr = mlx4_ib_rereg_user_mr;
  1910. ibdev->ib_dev.dereg_mr = mlx4_ib_dereg_mr;
  1911. ibdev->ib_dev.alloc_mr = mlx4_ib_alloc_mr;
  1912. ibdev->ib_dev.map_mr_sg = mlx4_ib_map_mr_sg;
  1913. ibdev->ib_dev.attach_mcast = mlx4_ib_mcg_attach;
  1914. ibdev->ib_dev.detach_mcast = mlx4_ib_mcg_detach;
  1915. ibdev->ib_dev.process_mad = mlx4_ib_process_mad;
  1916. ibdev->ib_dev.get_port_immutable = mlx4_port_immutable;
  1917. ibdev->ib_dev.disassociate_ucontext = mlx4_ib_disassociate_ucontext;
  1918. if (!mlx4_is_slave(ibdev->dev)) {
  1919. ibdev->ib_dev.alloc_fmr = mlx4_ib_fmr_alloc;
  1920. ibdev->ib_dev.map_phys_fmr = mlx4_ib_map_phys_fmr;
  1921. ibdev->ib_dev.unmap_fmr = mlx4_ib_unmap_fmr;
  1922. ibdev->ib_dev.dealloc_fmr = mlx4_ib_fmr_dealloc;
  1923. }
  1924. if (dev->caps.flags & MLX4_DEV_CAP_FLAG_MEM_WINDOW ||
  1925. dev->caps.bmme_flags & MLX4_BMME_FLAG_TYPE_2_WIN) {
  1926. ibdev->ib_dev.alloc_mw = mlx4_ib_alloc_mw;
  1927. ibdev->ib_dev.bind_mw = mlx4_ib_bind_mw;
  1928. ibdev->ib_dev.dealloc_mw = mlx4_ib_dealloc_mw;
  1929. ibdev->ib_dev.uverbs_cmd_mask |=
  1930. (1ull << IB_USER_VERBS_CMD_ALLOC_MW) |
  1931. (1ull << IB_USER_VERBS_CMD_DEALLOC_MW);
  1932. }
  1933. if (dev->caps.flags & MLX4_DEV_CAP_FLAG_XRC) {
  1934. ibdev->ib_dev.alloc_xrcd = mlx4_ib_alloc_xrcd;
  1935. ibdev->ib_dev.dealloc_xrcd = mlx4_ib_dealloc_xrcd;
  1936. ibdev->ib_dev.uverbs_cmd_mask |=
  1937. (1ull << IB_USER_VERBS_CMD_OPEN_XRCD) |
  1938. (1ull << IB_USER_VERBS_CMD_CLOSE_XRCD);
  1939. }
  1940. if (check_flow_steering_support(dev)) {
  1941. ibdev->steering_support = MLX4_STEERING_MODE_DEVICE_MANAGED;
  1942. ibdev->ib_dev.create_flow = mlx4_ib_create_flow;
  1943. ibdev->ib_dev.destroy_flow = mlx4_ib_destroy_flow;
  1944. ibdev->ib_dev.uverbs_ex_cmd_mask |=
  1945. (1ull << IB_USER_VERBS_EX_CMD_CREATE_FLOW) |
  1946. (1ull << IB_USER_VERBS_EX_CMD_DESTROY_FLOW);
  1947. }
  1948. ibdev->ib_dev.uverbs_ex_cmd_mask |=
  1949. (1ull << IB_USER_VERBS_EX_CMD_QUERY_DEVICE) |
  1950. (1ull << IB_USER_VERBS_EX_CMD_CREATE_CQ) |
  1951. (1ull << IB_USER_VERBS_EX_CMD_CREATE_QP);
  1952. mlx4_ib_alloc_eqs(dev, ibdev);
  1953. spin_lock_init(&iboe->lock);
  1954. if (init_node_data(ibdev))
  1955. goto err_map;
  1956. for (i = 0; i < ibdev->num_ports; ++i) {
  1957. mutex_init(&ibdev->counters_table[i].mutex);
  1958. INIT_LIST_HEAD(&ibdev->counters_table[i].counters_list);
  1959. }
  1960. num_req_counters = mlx4_is_bonded(dev) ? 1 : ibdev->num_ports;
  1961. for (i = 0; i < num_req_counters; ++i) {
  1962. mutex_init(&ibdev->qp1_proxy_lock[i]);
  1963. allocated = 0;
  1964. if (mlx4_ib_port_link_layer(&ibdev->ib_dev, i + 1) ==
  1965. IB_LINK_LAYER_ETHERNET) {
  1966. err = mlx4_counter_alloc(ibdev->dev, &counter_index);
  1967. /* if failed to allocate a new counter, use default */
  1968. if (err)
  1969. counter_index =
  1970. mlx4_get_default_counter_index(dev,
  1971. i + 1);
  1972. else
  1973. allocated = 1;
  1974. } else { /* IB_LINK_LAYER_INFINIBAND use the default counter */
  1975. counter_index = mlx4_get_default_counter_index(dev,
  1976. i + 1);
  1977. }
  1978. new_counter_index = kmalloc(sizeof(*new_counter_index),
  1979. GFP_KERNEL);
  1980. if (!new_counter_index) {
  1981. if (allocated)
  1982. mlx4_counter_free(ibdev->dev, counter_index);
  1983. goto err_counter;
  1984. }
  1985. new_counter_index->index = counter_index;
  1986. new_counter_index->allocated = allocated;
  1987. list_add_tail(&new_counter_index->list,
  1988. &ibdev->counters_table[i].counters_list);
  1989. ibdev->counters_table[i].default_counter = counter_index;
  1990. pr_info("counter index %d for port %d allocated %d\n",
  1991. counter_index, i + 1, allocated);
  1992. }
  1993. if (mlx4_is_bonded(dev))
  1994. for (i = 1; i < ibdev->num_ports ; ++i) {
  1995. new_counter_index =
  1996. kmalloc(sizeof(struct counter_index),
  1997. GFP_KERNEL);
  1998. if (!new_counter_index)
  1999. goto err_counter;
  2000. new_counter_index->index = counter_index;
  2001. new_counter_index->allocated = 0;
  2002. list_add_tail(&new_counter_index->list,
  2003. &ibdev->counters_table[i].counters_list);
  2004. ibdev->counters_table[i].default_counter =
  2005. counter_index;
  2006. }
  2007. mlx4_foreach_port(i, dev, MLX4_PORT_TYPE_IB)
  2008. ib_num_ports++;
  2009. spin_lock_init(&ibdev->sm_lock);
  2010. mutex_init(&ibdev->cap_mask_mutex);
  2011. INIT_LIST_HEAD(&ibdev->qp_list);
  2012. spin_lock_init(&ibdev->reset_flow_resource_lock);
  2013. if (ibdev->steering_support == MLX4_STEERING_MODE_DEVICE_MANAGED &&
  2014. ib_num_ports) {
  2015. ibdev->steer_qpn_count = MLX4_IB_UC_MAX_NUM_QPS;
  2016. err = mlx4_qp_reserve_range(dev, ibdev->steer_qpn_count,
  2017. MLX4_IB_UC_STEER_QPN_ALIGN,
  2018. &ibdev->steer_qpn_base, 0);
  2019. if (err)
  2020. goto err_counter;
  2021. ibdev->ib_uc_qpns_bitmap =
  2022. kmalloc(BITS_TO_LONGS(ibdev->steer_qpn_count) *
  2023. sizeof(long),
  2024. GFP_KERNEL);
  2025. if (!ibdev->ib_uc_qpns_bitmap) {
  2026. dev_err(&dev->persist->pdev->dev,
  2027. "bit map alloc failed\n");
  2028. goto err_steer_qp_release;
  2029. }
  2030. if (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_DMFS_IPOIB) {
  2031. bitmap_zero(ibdev->ib_uc_qpns_bitmap,
  2032. ibdev->steer_qpn_count);
  2033. err = mlx4_FLOW_STEERING_IB_UC_QP_RANGE(
  2034. dev, ibdev->steer_qpn_base,
  2035. ibdev->steer_qpn_base +
  2036. ibdev->steer_qpn_count - 1);
  2037. if (err)
  2038. goto err_steer_free_bitmap;
  2039. } else {
  2040. bitmap_fill(ibdev->ib_uc_qpns_bitmap,
  2041. ibdev->steer_qpn_count);
  2042. }
  2043. }
  2044. for (j = 1; j <= ibdev->dev->caps.num_ports; j++)
  2045. atomic64_set(&iboe->mac[j - 1], ibdev->dev->caps.def_mac[j]);
  2046. if (ib_register_device(&ibdev->ib_dev, NULL))
  2047. goto err_steer_free_bitmap;
  2048. if (mlx4_ib_mad_init(ibdev))
  2049. goto err_reg;
  2050. if (mlx4_ib_init_sriov(ibdev))
  2051. goto err_mad;
  2052. if (dev->caps.flags & MLX4_DEV_CAP_FLAG_IBOE) {
  2053. if (!iboe->nb.notifier_call) {
  2054. iboe->nb.notifier_call = mlx4_ib_netdev_event;
  2055. err = register_netdevice_notifier(&iboe->nb);
  2056. if (err) {
  2057. iboe->nb.notifier_call = NULL;
  2058. goto err_notif;
  2059. }
  2060. }
  2061. }
  2062. for (j = 0; j < ARRAY_SIZE(mlx4_class_attributes); ++j) {
  2063. if (device_create_file(&ibdev->ib_dev.dev,
  2064. mlx4_class_attributes[j]))
  2065. goto err_notif;
  2066. }
  2067. ibdev->ib_active = true;
  2068. if (mlx4_is_mfunc(ibdev->dev))
  2069. init_pkeys(ibdev);
  2070. /* create paravirt contexts for any VFs which are active */
  2071. if (mlx4_is_master(ibdev->dev)) {
  2072. for (j = 0; j < MLX4_MFUNC_MAX; j++) {
  2073. if (j == mlx4_master_func_num(ibdev->dev))
  2074. continue;
  2075. if (mlx4_is_slave_active(ibdev->dev, j))
  2076. do_slave_init(ibdev, j, 1);
  2077. }
  2078. }
  2079. return ibdev;
  2080. err_notif:
  2081. if (ibdev->iboe.nb.notifier_call) {
  2082. if (unregister_netdevice_notifier(&ibdev->iboe.nb))
  2083. pr_warn("failure unregistering notifier\n");
  2084. ibdev->iboe.nb.notifier_call = NULL;
  2085. }
  2086. flush_workqueue(wq);
  2087. mlx4_ib_close_sriov(ibdev);
  2088. err_mad:
  2089. mlx4_ib_mad_cleanup(ibdev);
  2090. err_reg:
  2091. ib_unregister_device(&ibdev->ib_dev);
  2092. err_steer_free_bitmap:
  2093. kfree(ibdev->ib_uc_qpns_bitmap);
  2094. err_steer_qp_release:
  2095. mlx4_qp_release_range(dev, ibdev->steer_qpn_base,
  2096. ibdev->steer_qpn_count);
  2097. err_counter:
  2098. for (i = 0; i < ibdev->num_ports; ++i)
  2099. mlx4_ib_delete_counters_table(ibdev, &ibdev->counters_table[i]);
  2100. err_map:
  2101. mlx4_ib_free_eqs(dev, ibdev);
  2102. iounmap(ibdev->uar_map);
  2103. err_uar:
  2104. mlx4_uar_free(dev, &ibdev->priv_uar);
  2105. err_pd:
  2106. mlx4_pd_free(dev, ibdev->priv_pdn);
  2107. err_dealloc:
  2108. ib_dealloc_device(&ibdev->ib_dev);
  2109. return NULL;
  2110. }
  2111. int mlx4_ib_steer_qp_alloc(struct mlx4_ib_dev *dev, int count, int *qpn)
  2112. {
  2113. int offset;
  2114. WARN_ON(!dev->ib_uc_qpns_bitmap);
  2115. offset = bitmap_find_free_region(dev->ib_uc_qpns_bitmap,
  2116. dev->steer_qpn_count,
  2117. get_count_order(count));
  2118. if (offset < 0)
  2119. return offset;
  2120. *qpn = dev->steer_qpn_base + offset;
  2121. return 0;
  2122. }
  2123. void mlx4_ib_steer_qp_free(struct mlx4_ib_dev *dev, u32 qpn, int count)
  2124. {
  2125. if (!qpn ||
  2126. dev->steering_support != MLX4_STEERING_MODE_DEVICE_MANAGED)
  2127. return;
  2128. BUG_ON(qpn < dev->steer_qpn_base);
  2129. bitmap_release_region(dev->ib_uc_qpns_bitmap,
  2130. qpn - dev->steer_qpn_base,
  2131. get_count_order(count));
  2132. }
  2133. int mlx4_ib_steer_qp_reg(struct mlx4_ib_dev *mdev, struct mlx4_ib_qp *mqp,
  2134. int is_attach)
  2135. {
  2136. int err;
  2137. size_t flow_size;
  2138. struct ib_flow_attr *flow = NULL;
  2139. struct ib_flow_spec_ib *ib_spec;
  2140. if (is_attach) {
  2141. flow_size = sizeof(struct ib_flow_attr) +
  2142. sizeof(struct ib_flow_spec_ib);
  2143. flow = kzalloc(flow_size, GFP_KERNEL);
  2144. if (!flow)
  2145. return -ENOMEM;
  2146. flow->port = mqp->port;
  2147. flow->num_of_specs = 1;
  2148. flow->size = flow_size;
  2149. ib_spec = (struct ib_flow_spec_ib *)(flow + 1);
  2150. ib_spec->type = IB_FLOW_SPEC_IB;
  2151. ib_spec->size = sizeof(struct ib_flow_spec_ib);
  2152. /* Add an empty rule for IB L2 */
  2153. memset(&ib_spec->mask, 0, sizeof(ib_spec->mask));
  2154. err = __mlx4_ib_create_flow(&mqp->ibqp, flow,
  2155. IB_FLOW_DOMAIN_NIC,
  2156. MLX4_FS_REGULAR,
  2157. &mqp->reg_id);
  2158. } else {
  2159. err = __mlx4_ib_destroy_flow(mdev->dev, mqp->reg_id);
  2160. }
  2161. kfree(flow);
  2162. return err;
  2163. }
  2164. static void mlx4_ib_remove(struct mlx4_dev *dev, void *ibdev_ptr)
  2165. {
  2166. struct mlx4_ib_dev *ibdev = ibdev_ptr;
  2167. int p;
  2168. ibdev->ib_active = false;
  2169. flush_workqueue(wq);
  2170. mlx4_ib_close_sriov(ibdev);
  2171. mlx4_ib_mad_cleanup(ibdev);
  2172. ib_unregister_device(&ibdev->ib_dev);
  2173. if (ibdev->iboe.nb.notifier_call) {
  2174. if (unregister_netdevice_notifier(&ibdev->iboe.nb))
  2175. pr_warn("failure unregistering notifier\n");
  2176. ibdev->iboe.nb.notifier_call = NULL;
  2177. }
  2178. mlx4_qp_release_range(dev, ibdev->steer_qpn_base,
  2179. ibdev->steer_qpn_count);
  2180. kfree(ibdev->ib_uc_qpns_bitmap);
  2181. iounmap(ibdev->uar_map);
  2182. for (p = 0; p < ibdev->num_ports; ++p)
  2183. mlx4_ib_delete_counters_table(ibdev, &ibdev->counters_table[p]);
  2184. mlx4_foreach_port(p, dev, MLX4_PORT_TYPE_IB)
  2185. mlx4_CLOSE_PORT(dev, p);
  2186. mlx4_ib_free_eqs(dev, ibdev);
  2187. mlx4_uar_free(dev, &ibdev->priv_uar);
  2188. mlx4_pd_free(dev, ibdev->priv_pdn);
  2189. ib_dealloc_device(&ibdev->ib_dev);
  2190. }
  2191. static void do_slave_init(struct mlx4_ib_dev *ibdev, int slave, int do_init)
  2192. {
  2193. struct mlx4_ib_demux_work **dm = NULL;
  2194. struct mlx4_dev *dev = ibdev->dev;
  2195. int i;
  2196. unsigned long flags;
  2197. struct mlx4_active_ports actv_ports;
  2198. unsigned int ports;
  2199. unsigned int first_port;
  2200. if (!mlx4_is_master(dev))
  2201. return;
  2202. actv_ports = mlx4_get_active_ports(dev, slave);
  2203. ports = bitmap_weight(actv_ports.ports, dev->caps.num_ports);
  2204. first_port = find_first_bit(actv_ports.ports, dev->caps.num_ports);
  2205. dm = kcalloc(ports, sizeof(*dm), GFP_ATOMIC);
  2206. if (!dm) {
  2207. pr_err("failed to allocate memory for tunneling qp update\n");
  2208. return;
  2209. }
  2210. for (i = 0; i < ports; i++) {
  2211. dm[i] = kmalloc(sizeof (struct mlx4_ib_demux_work), GFP_ATOMIC);
  2212. if (!dm[i]) {
  2213. pr_err("failed to allocate memory for tunneling qp update work struct\n");
  2214. while (--i >= 0)
  2215. kfree(dm[i]);
  2216. goto out;
  2217. }
  2218. INIT_WORK(&dm[i]->work, mlx4_ib_tunnels_update_work);
  2219. dm[i]->port = first_port + i + 1;
  2220. dm[i]->slave = slave;
  2221. dm[i]->do_init = do_init;
  2222. dm[i]->dev = ibdev;
  2223. }
  2224. /* initialize or tear down tunnel QPs for the slave */
  2225. spin_lock_irqsave(&ibdev->sriov.going_down_lock, flags);
  2226. if (!ibdev->sriov.is_going_down) {
  2227. for (i = 0; i < ports; i++)
  2228. queue_work(ibdev->sriov.demux[i].ud_wq, &dm[i]->work);
  2229. spin_unlock_irqrestore(&ibdev->sriov.going_down_lock, flags);
  2230. } else {
  2231. spin_unlock_irqrestore(&ibdev->sriov.going_down_lock, flags);
  2232. for (i = 0; i < ports; i++)
  2233. kfree(dm[i]);
  2234. }
  2235. out:
  2236. kfree(dm);
  2237. return;
  2238. }
  2239. static void mlx4_ib_handle_catas_error(struct mlx4_ib_dev *ibdev)
  2240. {
  2241. struct mlx4_ib_qp *mqp;
  2242. unsigned long flags_qp;
  2243. unsigned long flags_cq;
  2244. struct mlx4_ib_cq *send_mcq, *recv_mcq;
  2245. struct list_head cq_notify_list;
  2246. struct mlx4_cq *mcq;
  2247. unsigned long flags;
  2248. pr_warn("mlx4_ib_handle_catas_error was started\n");
  2249. INIT_LIST_HEAD(&cq_notify_list);
  2250. /* Go over qp list reside on that ibdev, sync with create/destroy qp.*/
  2251. spin_lock_irqsave(&ibdev->reset_flow_resource_lock, flags);
  2252. list_for_each_entry(mqp, &ibdev->qp_list, qps_list) {
  2253. spin_lock_irqsave(&mqp->sq.lock, flags_qp);
  2254. if (mqp->sq.tail != mqp->sq.head) {
  2255. send_mcq = to_mcq(mqp->ibqp.send_cq);
  2256. spin_lock_irqsave(&send_mcq->lock, flags_cq);
  2257. if (send_mcq->mcq.comp &&
  2258. mqp->ibqp.send_cq->comp_handler) {
  2259. if (!send_mcq->mcq.reset_notify_added) {
  2260. send_mcq->mcq.reset_notify_added = 1;
  2261. list_add_tail(&send_mcq->mcq.reset_notify,
  2262. &cq_notify_list);
  2263. }
  2264. }
  2265. spin_unlock_irqrestore(&send_mcq->lock, flags_cq);
  2266. }
  2267. spin_unlock_irqrestore(&mqp->sq.lock, flags_qp);
  2268. /* Now, handle the QP's receive queue */
  2269. spin_lock_irqsave(&mqp->rq.lock, flags_qp);
  2270. /* no handling is needed for SRQ */
  2271. if (!mqp->ibqp.srq) {
  2272. if (mqp->rq.tail != mqp->rq.head) {
  2273. recv_mcq = to_mcq(mqp->ibqp.recv_cq);
  2274. spin_lock_irqsave(&recv_mcq->lock, flags_cq);
  2275. if (recv_mcq->mcq.comp &&
  2276. mqp->ibqp.recv_cq->comp_handler) {
  2277. if (!recv_mcq->mcq.reset_notify_added) {
  2278. recv_mcq->mcq.reset_notify_added = 1;
  2279. list_add_tail(&recv_mcq->mcq.reset_notify,
  2280. &cq_notify_list);
  2281. }
  2282. }
  2283. spin_unlock_irqrestore(&recv_mcq->lock,
  2284. flags_cq);
  2285. }
  2286. }
  2287. spin_unlock_irqrestore(&mqp->rq.lock, flags_qp);
  2288. }
  2289. list_for_each_entry(mcq, &cq_notify_list, reset_notify) {
  2290. mcq->comp(mcq);
  2291. }
  2292. spin_unlock_irqrestore(&ibdev->reset_flow_resource_lock, flags);
  2293. pr_warn("mlx4_ib_handle_catas_error ended\n");
  2294. }
  2295. static void handle_bonded_port_state_event(struct work_struct *work)
  2296. {
  2297. struct ib_event_work *ew =
  2298. container_of(work, struct ib_event_work, work);
  2299. struct mlx4_ib_dev *ibdev = ew->ib_dev;
  2300. enum ib_port_state bonded_port_state = IB_PORT_NOP;
  2301. int i;
  2302. struct ib_event ibev;
  2303. kfree(ew);
  2304. spin_lock_bh(&ibdev->iboe.lock);
  2305. for (i = 0; i < MLX4_MAX_PORTS; ++i) {
  2306. struct net_device *curr_netdev = ibdev->iboe.netdevs[i];
  2307. enum ib_port_state curr_port_state;
  2308. if (!curr_netdev)
  2309. continue;
  2310. curr_port_state =
  2311. (netif_running(curr_netdev) &&
  2312. netif_carrier_ok(curr_netdev)) ?
  2313. IB_PORT_ACTIVE : IB_PORT_DOWN;
  2314. bonded_port_state = (bonded_port_state != IB_PORT_ACTIVE) ?
  2315. curr_port_state : IB_PORT_ACTIVE;
  2316. }
  2317. spin_unlock_bh(&ibdev->iboe.lock);
  2318. ibev.device = &ibdev->ib_dev;
  2319. ibev.element.port_num = 1;
  2320. ibev.event = (bonded_port_state == IB_PORT_ACTIVE) ?
  2321. IB_EVENT_PORT_ACTIVE : IB_EVENT_PORT_ERR;
  2322. ib_dispatch_event(&ibev);
  2323. }
  2324. static void mlx4_ib_event(struct mlx4_dev *dev, void *ibdev_ptr,
  2325. enum mlx4_dev_event event, unsigned long param)
  2326. {
  2327. struct ib_event ibev;
  2328. struct mlx4_ib_dev *ibdev = to_mdev((struct ib_device *) ibdev_ptr);
  2329. struct mlx4_eqe *eqe = NULL;
  2330. struct ib_event_work *ew;
  2331. int p = 0;
  2332. if (mlx4_is_bonded(dev) &&
  2333. ((event == MLX4_DEV_EVENT_PORT_UP) ||
  2334. (event == MLX4_DEV_EVENT_PORT_DOWN))) {
  2335. ew = kmalloc(sizeof(*ew), GFP_ATOMIC);
  2336. if (!ew)
  2337. return;
  2338. INIT_WORK(&ew->work, handle_bonded_port_state_event);
  2339. ew->ib_dev = ibdev;
  2340. queue_work(wq, &ew->work);
  2341. return;
  2342. }
  2343. if (event == MLX4_DEV_EVENT_PORT_MGMT_CHANGE)
  2344. eqe = (struct mlx4_eqe *)param;
  2345. else
  2346. p = (int) param;
  2347. switch (event) {
  2348. case MLX4_DEV_EVENT_PORT_UP:
  2349. if (p > ibdev->num_ports)
  2350. return;
  2351. if (mlx4_is_master(dev) &&
  2352. rdma_port_get_link_layer(&ibdev->ib_dev, p) ==
  2353. IB_LINK_LAYER_INFINIBAND) {
  2354. mlx4_ib_invalidate_all_guid_record(ibdev, p);
  2355. }
  2356. ibev.event = IB_EVENT_PORT_ACTIVE;
  2357. break;
  2358. case MLX4_DEV_EVENT_PORT_DOWN:
  2359. if (p > ibdev->num_ports)
  2360. return;
  2361. ibev.event = IB_EVENT_PORT_ERR;
  2362. break;
  2363. case MLX4_DEV_EVENT_CATASTROPHIC_ERROR:
  2364. ibdev->ib_active = false;
  2365. ibev.event = IB_EVENT_DEVICE_FATAL;
  2366. mlx4_ib_handle_catas_error(ibdev);
  2367. break;
  2368. case MLX4_DEV_EVENT_PORT_MGMT_CHANGE:
  2369. ew = kmalloc(sizeof *ew, GFP_ATOMIC);
  2370. if (!ew) {
  2371. pr_err("failed to allocate memory for events work\n");
  2372. break;
  2373. }
  2374. INIT_WORK(&ew->work, handle_port_mgmt_change_event);
  2375. memcpy(&ew->ib_eqe, eqe, sizeof *eqe);
  2376. ew->ib_dev = ibdev;
  2377. /* need to queue only for port owner, which uses GEN_EQE */
  2378. if (mlx4_is_master(dev))
  2379. queue_work(wq, &ew->work);
  2380. else
  2381. handle_port_mgmt_change_event(&ew->work);
  2382. return;
  2383. case MLX4_DEV_EVENT_SLAVE_INIT:
  2384. /* here, p is the slave id */
  2385. do_slave_init(ibdev, p, 1);
  2386. if (mlx4_is_master(dev)) {
  2387. int i;
  2388. for (i = 1; i <= ibdev->num_ports; i++) {
  2389. if (rdma_port_get_link_layer(&ibdev->ib_dev, i)
  2390. == IB_LINK_LAYER_INFINIBAND)
  2391. mlx4_ib_slave_alias_guid_event(ibdev,
  2392. p, i,
  2393. 1);
  2394. }
  2395. }
  2396. return;
  2397. case MLX4_DEV_EVENT_SLAVE_SHUTDOWN:
  2398. if (mlx4_is_master(dev)) {
  2399. int i;
  2400. for (i = 1; i <= ibdev->num_ports; i++) {
  2401. if (rdma_port_get_link_layer(&ibdev->ib_dev, i)
  2402. == IB_LINK_LAYER_INFINIBAND)
  2403. mlx4_ib_slave_alias_guid_event(ibdev,
  2404. p, i,
  2405. 0);
  2406. }
  2407. }
  2408. /* here, p is the slave id */
  2409. do_slave_init(ibdev, p, 0);
  2410. return;
  2411. default:
  2412. return;
  2413. }
  2414. ibev.device = ibdev_ptr;
  2415. ibev.element.port_num = mlx4_is_bonded(ibdev->dev) ? 1 : (u8)p;
  2416. ib_dispatch_event(&ibev);
  2417. }
  2418. static struct mlx4_interface mlx4_ib_interface = {
  2419. .add = mlx4_ib_add,
  2420. .remove = mlx4_ib_remove,
  2421. .event = mlx4_ib_event,
  2422. .protocol = MLX4_PROT_IB_IPV6,
  2423. .flags = MLX4_INTFF_BONDING
  2424. };
  2425. static int __init mlx4_ib_init(void)
  2426. {
  2427. int err;
  2428. wq = create_singlethread_workqueue("mlx4_ib");
  2429. if (!wq)
  2430. return -ENOMEM;
  2431. err = mlx4_ib_mcg_init();
  2432. if (err)
  2433. goto clean_wq;
  2434. err = mlx4_register_interface(&mlx4_ib_interface);
  2435. if (err)
  2436. goto clean_mcg;
  2437. return 0;
  2438. clean_mcg:
  2439. mlx4_ib_mcg_destroy();
  2440. clean_wq:
  2441. destroy_workqueue(wq);
  2442. return err;
  2443. }
  2444. static void __exit mlx4_ib_cleanup(void)
  2445. {
  2446. mlx4_unregister_interface(&mlx4_ib_interface);
  2447. mlx4_ib_mcg_destroy();
  2448. destroy_workqueue(wq);
  2449. }
  2450. module_init(mlx4_ib_init);
  2451. module_exit(mlx4_ib_cleanup);