intel-mid-touch.c 15 KB

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  1. /*
  2. * Intel MID Resistive Touch Screen Driver
  3. *
  4. * Copyright (C) 2008 Intel Corp
  5. *
  6. * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
  7. *
  8. * This program is free software; you can redistribute it and/or modify
  9. * it under the terms of the GNU General Public License as published by
  10. * the Free Software Foundation; version 2 of the License.
  11. *
  12. * This program is distributed in the hope that it will be useful, but
  13. * WITHOUT ANY WARRANTY; without even the implied warranty of
  14. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
  15. * General Public License for more details.
  16. *
  17. * You should have received a copy of the GNU General Public License along
  18. * with this program; if not, write to the Free Software Foundation, Inc.,
  19. * 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA.
  20. *
  21. * Questions/Comments/Bug fixes to Sreedhara (sreedhara.ds@intel.com)
  22. * Ramesh Agarwal (ramesh.agarwal@intel.com)
  23. * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
  24. *
  25. * TODO:
  26. * review conversion of r/m/w sequences
  27. */
  28. #include <linux/module.h>
  29. #include <linux/input.h>
  30. #include <linux/interrupt.h>
  31. #include <linux/err.h>
  32. #include <linux/param.h>
  33. #include <linux/slab.h>
  34. #include <linux/platform_device.h>
  35. #include <linux/irq.h>
  36. #include <linux/delay.h>
  37. #include <asm/intel_scu_ipc.h>
  38. #include <linux/device.h>
  39. /* PMIC Interrupt registers */
  40. #define PMIC_REG_ID1 0x00 /* PMIC ID1 register */
  41. /* PMIC Interrupt registers */
  42. #define PMIC_REG_INT 0x04 /* PMIC interrupt register */
  43. #define PMIC_REG_MINT 0x05 /* PMIC interrupt mask register */
  44. /* ADC Interrupt registers */
  45. #define PMIC_REG_ADCINT 0x5F /* ADC interrupt register */
  46. #define PMIC_REG_MADCINT 0x60 /* ADC interrupt mask register */
  47. /* ADC Control registers */
  48. #define PMIC_REG_ADCCNTL1 0x61 /* ADC control register */
  49. /* ADC Channel Selection registers */
  50. #define PMICADDR0 0xA4
  51. #define END_OF_CHANNEL 0x1F
  52. /* ADC Result register */
  53. #define PMIC_REG_ADCSNS0H 0x64
  54. /* ADC channels for touch screen */
  55. #define MRST_TS_CHAN10 0xA /* Touch screen X+ connection */
  56. #define MRST_TS_CHAN11 0xB /* Touch screen X- connection */
  57. #define MRST_TS_CHAN12 0xC /* Touch screen Y+ connection */
  58. #define MRST_TS_CHAN13 0xD /* Touch screen Y- connection */
  59. /* Touch screen channel BIAS constants */
  60. #define MRST_XBIAS 0x20
  61. #define MRST_YBIAS 0x40
  62. #define MRST_ZBIAS 0x80
  63. /* Touch screen coordinates */
  64. #define MRST_X_MIN 10
  65. #define MRST_X_MAX 1024
  66. #define MRST_X_FUZZ 5
  67. #define MRST_Y_MIN 10
  68. #define MRST_Y_MAX 1024
  69. #define MRST_Y_FUZZ 5
  70. #define MRST_PRESSURE_MIN 0
  71. #define MRST_PRESSURE_NOMINAL 50
  72. #define MRST_PRESSURE_MAX 100
  73. #define WAIT_ADC_COMPLETION 10 /* msec */
  74. /* PMIC ADC round robin delays */
  75. #define ADC_LOOP_DELAY0 0x0 /* Continuous loop */
  76. #define ADC_LOOP_DELAY1 0x1 /* 4.5 ms approximate */
  77. /* PMIC Vendor Identifiers */
  78. #define PMIC_VENDOR_FS 0 /* PMIC vendor FreeScale */
  79. #define PMIC_VENDOR_MAXIM 1 /* PMIC vendor MAXIM */
  80. #define PMIC_VENDOR_NEC 2 /* PMIC vendor NEC */
  81. #define MRSTOUCH_MAX_CHANNELS 32 /* Maximum ADC channels */
  82. /* Touch screen device structure */
  83. struct mrstouch_dev {
  84. struct device *dev; /* device associated with touch screen */
  85. struct input_dev *input;
  86. char phys[32];
  87. u16 asr; /* Address selection register */
  88. int irq;
  89. unsigned int vendor; /* PMIC vendor */
  90. unsigned int rev; /* PMIC revision */
  91. int (*read_prepare)(struct mrstouch_dev *tsdev);
  92. int (*read)(struct mrstouch_dev *tsdev, u16 *x, u16 *y, u16 *z);
  93. int (*read_finish)(struct mrstouch_dev *tsdev);
  94. };
  95. /*************************** NEC and Maxim Interface ************************/
  96. static int mrstouch_nec_adc_read_prepare(struct mrstouch_dev *tsdev)
  97. {
  98. return intel_scu_ipc_update_register(PMIC_REG_MADCINT, 0, 0x20);
  99. }
  100. /*
  101. * Enables PENDET interrupt.
  102. */
  103. static int mrstouch_nec_adc_read_finish(struct mrstouch_dev *tsdev)
  104. {
  105. int err;
  106. err = intel_scu_ipc_update_register(PMIC_REG_MADCINT, 0x20, 0x20);
  107. if (!err)
  108. err = intel_scu_ipc_update_register(PMIC_REG_ADCCNTL1, 0, 0x05);
  109. return err;
  110. }
  111. /*
  112. * Reads PMIC ADC touch screen result
  113. * Reads ADC storage registers for higher 7 and lower 3 bits and
  114. * converts the two readings into a single value and turns off gain bit
  115. */
  116. static int mrstouch_ts_chan_read(u16 offset, u16 chan, u16 *vp, u16 *vm)
  117. {
  118. int err;
  119. u16 result;
  120. u32 res;
  121. result = PMIC_REG_ADCSNS0H + offset;
  122. if (chan == MRST_TS_CHAN12)
  123. result += 4;
  124. err = intel_scu_ipc_ioread32(result, &res);
  125. if (err)
  126. return err;
  127. /* Mash the bits up */
  128. *vp = (res & 0xFF) << 3; /* Highest 7 bits */
  129. *vp |= (res >> 8) & 0x07; /* Lower 3 bits */
  130. *vp &= 0x3FF;
  131. res >>= 16;
  132. *vm = (res & 0xFF) << 3; /* Highest 7 bits */
  133. *vm |= (res >> 8) & 0x07; /* Lower 3 bits */
  134. *vm &= 0x3FF;
  135. return 0;
  136. }
  137. /*
  138. * Enables X, Y and Z bias values
  139. * Enables YPYM for X channels and XPXM for Y channels
  140. */
  141. static int mrstouch_ts_bias_set(uint offset, uint bias)
  142. {
  143. int count;
  144. u16 chan, start;
  145. u16 reg[4];
  146. u8 data[4];
  147. chan = PMICADDR0 + offset;
  148. start = MRST_TS_CHAN10;
  149. for (count = 0; count <= 3; count++) {
  150. reg[count] = chan++;
  151. data[count] = bias | (start + count);
  152. }
  153. return intel_scu_ipc_writev(reg, data, 4);
  154. }
  155. /* To read touch screen channel values */
  156. static int mrstouch_nec_adc_read(struct mrstouch_dev *tsdev,
  157. u16 *x, u16 *y, u16 *z)
  158. {
  159. int err;
  160. u16 xm, ym, zm;
  161. /* configure Y bias for X channels */
  162. err = mrstouch_ts_bias_set(tsdev->asr, MRST_YBIAS);
  163. if (err)
  164. goto ipc_error;
  165. msleep(WAIT_ADC_COMPLETION);
  166. /* read x+ and x- channels */
  167. err = mrstouch_ts_chan_read(tsdev->asr, MRST_TS_CHAN10, x, &xm);
  168. if (err)
  169. goto ipc_error;
  170. /* configure x bias for y channels */
  171. err = mrstouch_ts_bias_set(tsdev->asr, MRST_XBIAS);
  172. if (err)
  173. goto ipc_error;
  174. msleep(WAIT_ADC_COMPLETION);
  175. /* read y+ and y- channels */
  176. err = mrstouch_ts_chan_read(tsdev->asr, MRST_TS_CHAN12, y, &ym);
  177. if (err)
  178. goto ipc_error;
  179. /* configure z bias for x and y channels */
  180. err = mrstouch_ts_bias_set(tsdev->asr, MRST_ZBIAS);
  181. if (err)
  182. goto ipc_error;
  183. msleep(WAIT_ADC_COMPLETION);
  184. /* read z+ and z- channels */
  185. err = mrstouch_ts_chan_read(tsdev->asr, MRST_TS_CHAN10, z, &zm);
  186. if (err)
  187. goto ipc_error;
  188. return 0;
  189. ipc_error:
  190. dev_err(tsdev->dev, "ipc error during adc read\n");
  191. return err;
  192. }
  193. /*************************** Freescale Interface ************************/
  194. static int mrstouch_fs_adc_read_prepare(struct mrstouch_dev *tsdev)
  195. {
  196. int err, count;
  197. u16 chan;
  198. u16 reg[5];
  199. u8 data[5];
  200. /* Stop the ADC */
  201. err = intel_scu_ipc_update_register(PMIC_REG_MADCINT, 0x00, 0x02);
  202. if (err)
  203. goto ipc_error;
  204. chan = PMICADDR0 + tsdev->asr;
  205. /* Set X BIAS */
  206. for (count = 0; count <= 3; count++) {
  207. reg[count] = chan++;
  208. data[count] = 0x2A;
  209. }
  210. reg[count] = chan++; /* Dummy */
  211. data[count] = 0;
  212. err = intel_scu_ipc_writev(reg, data, 5);
  213. if (err)
  214. goto ipc_error;
  215. msleep(WAIT_ADC_COMPLETION);
  216. /* Set Y BIAS */
  217. for (count = 0; count <= 3; count++) {
  218. reg[count] = chan++;
  219. data[count] = 0x4A;
  220. }
  221. reg[count] = chan++; /* Dummy */
  222. data[count] = 0;
  223. err = intel_scu_ipc_writev(reg, data, 5);
  224. if (err)
  225. goto ipc_error;
  226. msleep(WAIT_ADC_COMPLETION);
  227. /* Set Z BIAS */
  228. err = intel_scu_ipc_iowrite32(chan + 2, 0x8A8A8A8A);
  229. if (err)
  230. goto ipc_error;
  231. msleep(WAIT_ADC_COMPLETION);
  232. return 0;
  233. ipc_error:
  234. dev_err(tsdev->dev, "ipc error during %s\n", __func__);
  235. return err;
  236. }
  237. static int mrstouch_fs_adc_read(struct mrstouch_dev *tsdev,
  238. u16 *x, u16 *y, u16 *z)
  239. {
  240. int err;
  241. u16 result;
  242. u16 reg[4];
  243. u8 data[4];
  244. result = PMIC_REG_ADCSNS0H + tsdev->asr;
  245. reg[0] = result + 4;
  246. reg[1] = result + 5;
  247. reg[2] = result + 16;
  248. reg[3] = result + 17;
  249. err = intel_scu_ipc_readv(reg, data, 4);
  250. if (err)
  251. goto ipc_error;
  252. *x = data[0] << 3; /* Higher 7 bits */
  253. *x |= data[1] & 0x7; /* Lower 3 bits */
  254. *x &= 0x3FF;
  255. *y = data[2] << 3; /* Higher 7 bits */
  256. *y |= data[3] & 0x7; /* Lower 3 bits */
  257. *y &= 0x3FF;
  258. /* Read Z value */
  259. reg[0] = result + 28;
  260. reg[1] = result + 29;
  261. err = intel_scu_ipc_readv(reg, data, 4);
  262. if (err)
  263. goto ipc_error;
  264. *z = data[0] << 3; /* Higher 7 bits */
  265. *z |= data[1] & 0x7; /* Lower 3 bits */
  266. *z &= 0x3FF;
  267. return 0;
  268. ipc_error:
  269. dev_err(tsdev->dev, "ipc error during %s\n", __func__);
  270. return err;
  271. }
  272. static int mrstouch_fs_adc_read_finish(struct mrstouch_dev *tsdev)
  273. {
  274. int err, count;
  275. u16 chan;
  276. u16 reg[5];
  277. u8 data[5];
  278. /* Clear all TS channels */
  279. chan = PMICADDR0 + tsdev->asr;
  280. for (count = 0; count <= 4; count++) {
  281. reg[count] = chan++;
  282. data[count] = 0;
  283. }
  284. err = intel_scu_ipc_writev(reg, data, 5);
  285. if (err)
  286. goto ipc_error;
  287. for (count = 0; count <= 4; count++) {
  288. reg[count] = chan++;
  289. data[count] = 0;
  290. }
  291. err = intel_scu_ipc_writev(reg, data, 5);
  292. if (err)
  293. goto ipc_error;
  294. err = intel_scu_ipc_iowrite32(chan + 2, 0x00000000);
  295. if (err)
  296. goto ipc_error;
  297. /* Start ADC */
  298. err = intel_scu_ipc_update_register(PMIC_REG_MADCINT, 0x02, 0x02);
  299. if (err)
  300. goto ipc_error;
  301. return 0;
  302. ipc_error:
  303. dev_err(tsdev->dev, "ipc error during %s\n", __func__);
  304. return err;
  305. }
  306. static void mrstouch_report_event(struct input_dev *input,
  307. unsigned int x, unsigned int y, unsigned int z)
  308. {
  309. if (z > MRST_PRESSURE_NOMINAL) {
  310. /* Pen touched, report button touch and coordinates */
  311. input_report_key(input, BTN_TOUCH, 1);
  312. input_report_abs(input, ABS_X, x);
  313. input_report_abs(input, ABS_Y, y);
  314. } else {
  315. input_report_key(input, BTN_TOUCH, 0);
  316. }
  317. input_report_abs(input, ABS_PRESSURE, z);
  318. input_sync(input);
  319. }
  320. /* PENDET interrupt handler */
  321. static irqreturn_t mrstouch_pendet_irq(int irq, void *dev_id)
  322. {
  323. struct mrstouch_dev *tsdev = dev_id;
  324. u16 x, y, z;
  325. /*
  326. * Should we lower thread priority? Probably not, since we are
  327. * not spinning but sleeping...
  328. */
  329. if (tsdev->read_prepare(tsdev))
  330. goto out;
  331. do {
  332. if (tsdev->read(tsdev, &x, &y, &z))
  333. break;
  334. mrstouch_report_event(tsdev->input, x, y, z);
  335. } while (z > MRST_PRESSURE_NOMINAL);
  336. tsdev->read_finish(tsdev);
  337. out:
  338. return IRQ_HANDLED;
  339. }
  340. /* Utility to read PMIC ID */
  341. static int mrstouch_read_pmic_id(uint *vendor, uint *rev)
  342. {
  343. int err;
  344. u8 r;
  345. err = intel_scu_ipc_ioread8(PMIC_REG_ID1, &r);
  346. if (err)
  347. return err;
  348. *vendor = r & 0x7;
  349. *rev = (r >> 3) & 0x7;
  350. return 0;
  351. }
  352. /*
  353. * Parse ADC channels to find end of the channel configured by other ADC user
  354. * NEC and MAXIM requires 4 channels and FreeScale needs 18 channels
  355. */
  356. static int mrstouch_chan_parse(struct mrstouch_dev *tsdev)
  357. {
  358. int found = 0;
  359. int err, i;
  360. u8 r8;
  361. for (i = 0; i < MRSTOUCH_MAX_CHANNELS; i++) {
  362. err = intel_scu_ipc_ioread8(PMICADDR0 + i, &r8);
  363. if (err)
  364. return err;
  365. if (r8 == END_OF_CHANNEL) {
  366. found = i;
  367. break;
  368. }
  369. }
  370. if (tsdev->vendor == PMIC_VENDOR_FS) {
  371. if (found > MRSTOUCH_MAX_CHANNELS - 18)
  372. return -ENOSPC;
  373. } else {
  374. if (found > MRSTOUCH_MAX_CHANNELS - 4)
  375. return -ENOSPC;
  376. }
  377. return found;
  378. }
  379. /*
  380. * Writes touch screen channels to ADC address selection registers
  381. */
  382. static int mrstouch_ts_chan_set(uint offset)
  383. {
  384. u16 chan;
  385. int ret, count;
  386. chan = PMICADDR0 + offset;
  387. for (count = 0; count <= 3; count++) {
  388. ret = intel_scu_ipc_iowrite8(chan++, MRST_TS_CHAN10 + count);
  389. if (ret)
  390. return ret;
  391. }
  392. return intel_scu_ipc_iowrite8(chan++, END_OF_CHANNEL);
  393. }
  394. /* Initialize ADC */
  395. static int mrstouch_adc_init(struct mrstouch_dev *tsdev)
  396. {
  397. int err, start;
  398. u8 ra, rm;
  399. err = mrstouch_read_pmic_id(&tsdev->vendor, &tsdev->rev);
  400. if (err) {
  401. dev_err(tsdev->dev, "Unable to read PMIC id\n");
  402. return err;
  403. }
  404. switch (tsdev->vendor) {
  405. case PMIC_VENDOR_NEC:
  406. case PMIC_VENDOR_MAXIM:
  407. tsdev->read_prepare = mrstouch_nec_adc_read_prepare;
  408. tsdev->read = mrstouch_nec_adc_read;
  409. tsdev->read_finish = mrstouch_nec_adc_read_finish;
  410. break;
  411. case PMIC_VENDOR_FS:
  412. tsdev->read_prepare = mrstouch_fs_adc_read_prepare;
  413. tsdev->read = mrstouch_fs_adc_read;
  414. tsdev->read_finish = mrstouch_fs_adc_read_finish;
  415. break;
  416. default:
  417. dev_err(tsdev->dev,
  418. "Unsupported touchscreen: %d\n", tsdev->vendor);
  419. return -ENXIO;
  420. }
  421. start = mrstouch_chan_parse(tsdev);
  422. if (start < 0) {
  423. dev_err(tsdev->dev, "Unable to parse channels\n");
  424. return start;
  425. }
  426. tsdev->asr = start;
  427. /*
  428. * ADC power on, start, enable PENDET and set loop delay
  429. * ADC loop delay is set to 4.5 ms approximately
  430. * Loop delay more than this results in jitter in adc readings
  431. * Setting loop delay to 0 (continuous loop) in MAXIM stops PENDET
  432. * interrupt generation sometimes.
  433. */
  434. if (tsdev->vendor == PMIC_VENDOR_FS) {
  435. ra = 0xE0 | ADC_LOOP_DELAY0;
  436. rm = 0x5;
  437. } else {
  438. /* NEC and MAXIm not consistent with loop delay 0 */
  439. ra = 0xE0 | ADC_LOOP_DELAY1;
  440. rm = 0x0;
  441. /* configure touch screen channels */
  442. err = mrstouch_ts_chan_set(tsdev->asr);
  443. if (err)
  444. return err;
  445. }
  446. err = intel_scu_ipc_update_register(PMIC_REG_ADCCNTL1, ra, 0xE7);
  447. if (err)
  448. return err;
  449. err = intel_scu_ipc_update_register(PMIC_REG_MADCINT, rm, 0x03);
  450. if (err)
  451. return err;
  452. return 0;
  453. }
  454. /* Probe function for touch screen driver */
  455. static int mrstouch_probe(struct platform_device *pdev)
  456. {
  457. struct mrstouch_dev *tsdev;
  458. struct input_dev *input;
  459. int err;
  460. int irq;
  461. irq = platform_get_irq(pdev, 0);
  462. if (irq < 0) {
  463. dev_err(&pdev->dev, "no interrupt assigned\n");
  464. return -EINVAL;
  465. }
  466. tsdev = devm_kzalloc(&pdev->dev, sizeof(struct mrstouch_dev),
  467. GFP_KERNEL);
  468. if (!tsdev) {
  469. dev_err(&pdev->dev, "unable to allocate memory\n");
  470. return -ENOMEM;
  471. }
  472. input = devm_input_allocate_device(&pdev->dev);
  473. if (!input) {
  474. dev_err(&pdev->dev, "unable to allocate input device\n");
  475. return -ENOMEM;
  476. }
  477. tsdev->dev = &pdev->dev;
  478. tsdev->input = input;
  479. tsdev->irq = irq;
  480. snprintf(tsdev->phys, sizeof(tsdev->phys),
  481. "%s/input0", dev_name(tsdev->dev));
  482. err = mrstouch_adc_init(tsdev);
  483. if (err) {
  484. dev_err(&pdev->dev, "ADC initialization failed\n");
  485. return err;
  486. }
  487. input->name = "mrst_touchscreen";
  488. input->phys = tsdev->phys;
  489. input->dev.parent = tsdev->dev;
  490. input->id.vendor = tsdev->vendor;
  491. input->id.version = tsdev->rev;
  492. input->evbit[0] = BIT_MASK(EV_KEY) | BIT_MASK(EV_ABS);
  493. input->keybit[BIT_WORD(BTN_TOUCH)] = BIT_MASK(BTN_TOUCH);
  494. input_set_abs_params(tsdev->input, ABS_X,
  495. MRST_X_MIN, MRST_X_MAX, MRST_X_FUZZ, 0);
  496. input_set_abs_params(tsdev->input, ABS_Y,
  497. MRST_Y_MIN, MRST_Y_MAX, MRST_Y_FUZZ, 0);
  498. input_set_abs_params(tsdev->input, ABS_PRESSURE,
  499. MRST_PRESSURE_MIN, MRST_PRESSURE_MAX, 0, 0);
  500. err = devm_request_threaded_irq(&pdev->dev, tsdev->irq, NULL,
  501. mrstouch_pendet_irq, IRQF_ONESHOT,
  502. "mrstouch", tsdev);
  503. if (err) {
  504. dev_err(tsdev->dev, "unable to allocate irq\n");
  505. return err;
  506. }
  507. err = input_register_device(tsdev->input);
  508. if (err) {
  509. dev_err(tsdev->dev, "unable to register input device\n");
  510. return err;
  511. }
  512. return 0;
  513. }
  514. static struct platform_driver mrstouch_driver = {
  515. .driver = {
  516. .name = "pmic_touch",
  517. },
  518. .probe = mrstouch_probe,
  519. };
  520. module_platform_driver(mrstouch_driver);
  521. MODULE_AUTHOR("Sreedhara Murthy. D.S, sreedhara.ds@intel.com");
  522. MODULE_DESCRIPTION("Intel Moorestown Resistive Touch Screen Driver");
  523. MODULE_LICENSE("GPL");