irq-mips-cpu.c 4.3 KB

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  1. /*
  2. * Copyright 2001 MontaVista Software Inc.
  3. * Author: Jun Sun, jsun@mvista.com or jsun@junsun.net
  4. *
  5. * Copyright (C) 2001 Ralf Baechle
  6. * Copyright (C) 2005 MIPS Technologies, Inc. All rights reserved.
  7. * Author: Maciej W. Rozycki <macro@mips.com>
  8. *
  9. * This file define the irq handler for MIPS CPU interrupts.
  10. *
  11. * This program is free software; you can redistribute it and/or modify it
  12. * under the terms of the GNU General Public License as published by the
  13. * Free Software Foundation; either version 2 of the License, or (at your
  14. * option) any later version.
  15. */
  16. /*
  17. * Almost all MIPS CPUs define 8 interrupt sources. They are typically
  18. * level triggered (i.e., cannot be cleared from CPU; must be cleared from
  19. * device). The first two are software interrupts which we don't really
  20. * use or support. The last one is usually the CPU timer interrupt if
  21. * counter register is present or, for CPUs with an external FPU, by
  22. * convention it's the FPU exception interrupt.
  23. *
  24. * Don't even think about using this on SMP. You have been warned.
  25. *
  26. * This file exports one global function:
  27. * void mips_cpu_irq_init(void);
  28. */
  29. #include <linux/init.h>
  30. #include <linux/interrupt.h>
  31. #include <linux/kernel.h>
  32. #include <linux/irq.h>
  33. #include <linux/irqchip.h>
  34. #include <linux/irqdomain.h>
  35. #include <asm/irq_cpu.h>
  36. #include <asm/mipsregs.h>
  37. #include <asm/mipsmtregs.h>
  38. #include <asm/setup.h>
  39. static inline void unmask_mips_irq(struct irq_data *d)
  40. {
  41. set_c0_status(0x100 << (d->irq - MIPS_CPU_IRQ_BASE));
  42. irq_enable_hazard();
  43. }
  44. static inline void mask_mips_irq(struct irq_data *d)
  45. {
  46. clear_c0_status(0x100 << (d->irq - MIPS_CPU_IRQ_BASE));
  47. irq_disable_hazard();
  48. }
  49. static struct irq_chip mips_cpu_irq_controller = {
  50. .name = "MIPS",
  51. .irq_ack = mask_mips_irq,
  52. .irq_mask = mask_mips_irq,
  53. .irq_mask_ack = mask_mips_irq,
  54. .irq_unmask = unmask_mips_irq,
  55. .irq_eoi = unmask_mips_irq,
  56. .irq_disable = mask_mips_irq,
  57. .irq_enable = unmask_mips_irq,
  58. };
  59. /*
  60. * Basically the same as above but taking care of all the MT stuff
  61. */
  62. static unsigned int mips_mt_cpu_irq_startup(struct irq_data *d)
  63. {
  64. unsigned int vpflags = dvpe();
  65. clear_c0_cause(0x100 << (d->irq - MIPS_CPU_IRQ_BASE));
  66. evpe(vpflags);
  67. unmask_mips_irq(d);
  68. return 0;
  69. }
  70. /*
  71. * While we ack the interrupt interrupts are disabled and thus we don't need
  72. * to deal with concurrency issues. Same for mips_cpu_irq_end.
  73. */
  74. static void mips_mt_cpu_irq_ack(struct irq_data *d)
  75. {
  76. unsigned int vpflags = dvpe();
  77. clear_c0_cause(0x100 << (d->irq - MIPS_CPU_IRQ_BASE));
  78. evpe(vpflags);
  79. mask_mips_irq(d);
  80. }
  81. static struct irq_chip mips_mt_cpu_irq_controller = {
  82. .name = "MIPS",
  83. .irq_startup = mips_mt_cpu_irq_startup,
  84. .irq_ack = mips_mt_cpu_irq_ack,
  85. .irq_mask = mask_mips_irq,
  86. .irq_mask_ack = mips_mt_cpu_irq_ack,
  87. .irq_unmask = unmask_mips_irq,
  88. .irq_eoi = unmask_mips_irq,
  89. .irq_disable = mask_mips_irq,
  90. .irq_enable = unmask_mips_irq,
  91. };
  92. asmlinkage void __weak plat_irq_dispatch(void)
  93. {
  94. unsigned long pending = read_c0_cause() & read_c0_status() & ST0_IM;
  95. int irq;
  96. if (!pending) {
  97. spurious_interrupt();
  98. return;
  99. }
  100. pending >>= CAUSEB_IP;
  101. while (pending) {
  102. irq = fls(pending) - 1;
  103. do_IRQ(MIPS_CPU_IRQ_BASE + irq);
  104. pending &= ~BIT(irq);
  105. }
  106. }
  107. static int mips_cpu_intc_map(struct irq_domain *d, unsigned int irq,
  108. irq_hw_number_t hw)
  109. {
  110. static struct irq_chip *chip;
  111. if (hw < 2 && cpu_has_mipsmt) {
  112. /* Software interrupts are used for MT/CMT IPI */
  113. chip = &mips_mt_cpu_irq_controller;
  114. } else {
  115. chip = &mips_cpu_irq_controller;
  116. }
  117. if (cpu_has_vint)
  118. set_vi_handler(hw, plat_irq_dispatch);
  119. irq_set_chip_and_handler(irq, chip, handle_percpu_irq);
  120. return 0;
  121. }
  122. static const struct irq_domain_ops mips_cpu_intc_irq_domain_ops = {
  123. .map = mips_cpu_intc_map,
  124. .xlate = irq_domain_xlate_onecell,
  125. };
  126. static void __init __mips_cpu_irq_init(struct device_node *of_node)
  127. {
  128. struct irq_domain *domain;
  129. /* Mask interrupts. */
  130. clear_c0_status(ST0_IM);
  131. clear_c0_cause(CAUSEF_IP);
  132. domain = irq_domain_add_legacy(of_node, 8, MIPS_CPU_IRQ_BASE, 0,
  133. &mips_cpu_intc_irq_domain_ops, NULL);
  134. if (!domain)
  135. panic("Failed to add irqdomain for MIPS CPU");
  136. }
  137. void __init mips_cpu_irq_init(void)
  138. {
  139. __mips_cpu_irq_init(NULL);
  140. }
  141. int __init mips_cpu_irq_of_init(struct device_node *of_node,
  142. struct device_node *parent)
  143. {
  144. __mips_cpu_irq_init(of_node);
  145. return 0;
  146. }
  147. IRQCHIP_DECLARE(cpu_intc, "mti,cpu-interrupt-controller", mips_cpu_irq_of_init);