irq-renesas-h8s.c 2.7 KB

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  1. /*
  2. * H8S interrupt contoller driver
  3. *
  4. * Copyright 2015 Yoshinori Sato <ysato@users.sourceforge.jp>
  5. */
  6. #include <linux/irq.h>
  7. #include <linux/irqchip.h>
  8. #include <linux/of_address.h>
  9. #include <linux/of_irq.h>
  10. #include <asm/io.h>
  11. static void *intc_baseaddr;
  12. #define IPRA ((unsigned long)intc_baseaddr)
  13. static const unsigned char ipr_table[] = {
  14. 0x03, 0x02, 0x01, 0x00, 0x13, 0x12, 0x11, 0x10, /* 16 - 23 */
  15. 0x23, 0x22, 0x21, 0x20, 0x33, 0x32, 0x31, 0x30, /* 24 - 31 */
  16. 0x43, 0x42, 0x41, 0x40, 0x53, 0x53, 0x52, 0x52, /* 32 - 39 */
  17. 0x51, 0x51, 0x51, 0x51, 0x51, 0x51, 0x51, 0x51, /* 40 - 47 */
  18. 0x50, 0x50, 0x50, 0x50, 0x63, 0x63, 0x63, 0x63, /* 48 - 55 */
  19. 0x62, 0x62, 0x62, 0x62, 0x62, 0x62, 0x62, 0x62, /* 56 - 63 */
  20. 0x61, 0x61, 0x61, 0x61, 0x60, 0x60, 0x60, 0x60, /* 64 - 71 */
  21. 0x73, 0x73, 0x73, 0x73, 0x72, 0x72, 0x72, 0x72, /* 72 - 79 */
  22. 0x71, 0x71, 0x71, 0x71, 0x70, 0x83, 0x82, 0x81, /* 80 - 87 */
  23. 0x80, 0x80, 0x80, 0x80, 0x93, 0x93, 0x93, 0x93, /* 88 - 95 */
  24. 0x92, 0x92, 0x92, 0x92, 0x91, 0x91, 0x91, 0x91, /* 96 - 103 */
  25. 0x90, 0x90, 0x90, 0x90, 0xa3, 0xa3, 0xa3, 0xa3, /* 104 - 111 */
  26. 0xa2, 0xa2, 0xa2, 0xa2, 0xa1, 0xa1, 0xa1, 0xa1, /* 112 - 119 */
  27. 0xa0, 0xa0, 0xa0, 0xa0, 0xa0, 0xa0, 0xa0, 0xa0, /* 120 - 127 */
  28. };
  29. static void h8s_disable_irq(struct irq_data *data)
  30. {
  31. int pos;
  32. unsigned int addr;
  33. unsigned short pri;
  34. int irq = data->irq;
  35. addr = IPRA + ((ipr_table[irq - 16] & 0xf0) >> 3);
  36. pos = (ipr_table[irq - 16] & 0x0f) * 4;
  37. pri = ~(0x000f << pos);
  38. pri &= ctrl_inw(addr);
  39. ctrl_outw(pri, addr);
  40. }
  41. static void h8s_enable_irq(struct irq_data *data)
  42. {
  43. int pos;
  44. unsigned int addr;
  45. unsigned short pri;
  46. int irq = data->irq;
  47. addr = IPRA + ((ipr_table[irq - 16] & 0xf0) >> 3);
  48. pos = (ipr_table[irq - 16] & 0x0f) * 4;
  49. pri = ~(0x000f << pos);
  50. pri &= ctrl_inw(addr);
  51. pri |= 1 << pos;
  52. ctrl_outw(pri, addr);
  53. }
  54. struct irq_chip h8s_irq_chip = {
  55. .name = "H8S-INTC",
  56. .irq_enable = h8s_enable_irq,
  57. .irq_disable = h8s_disable_irq,
  58. };
  59. static __init int irq_map(struct irq_domain *h, unsigned int virq,
  60. irq_hw_number_t hw_irq_num)
  61. {
  62. irq_set_chip_and_handler(virq, &h8s_irq_chip, handle_simple_irq);
  63. return 0;
  64. }
  65. static struct irq_domain_ops irq_ops = {
  66. .map = irq_map,
  67. .xlate = irq_domain_xlate_onecell,
  68. };
  69. static int __init h8s_intc_of_init(struct device_node *intc,
  70. struct device_node *parent)
  71. {
  72. struct irq_domain *domain;
  73. int n;
  74. intc_baseaddr = of_iomap(intc, 0);
  75. BUG_ON(!intc_baseaddr);
  76. /* All interrupt priority is 0 (disable) */
  77. /* IPRA to IPRK */
  78. for (n = 0; n <= 'k' - 'a'; n++)
  79. ctrl_outw(0x0000, IPRA + (n * 2));
  80. domain = irq_domain_add_linear(intc, NR_IRQS, &irq_ops, NULL);
  81. BUG_ON(!domain);
  82. irq_set_default_host(domain);
  83. return 0;
  84. }
  85. IRQCHIP_DECLARE(h8s_intc, "renesas,h8s-intc", h8s_intc_of_init);