pl320-ipc.c 5.1 KB

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  1. /*
  2. * Copyright 2012 Calxeda, Inc.
  3. *
  4. * This program is free software; you can redistribute it and/or modify it
  5. * under the terms and conditions of the GNU General Public License,
  6. * version 2, as published by the Free Software Foundation.
  7. *
  8. * This program is distributed in the hope it will be useful, but WITHOUT
  9. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  10. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  11. * more details.
  12. *
  13. * You should have received a copy of the GNU General Public License along with
  14. * this program. If not, see <http://www.gnu.org/licenses/>.
  15. */
  16. #include <linux/types.h>
  17. #include <linux/err.h>
  18. #include <linux/delay.h>
  19. #include <linux/export.h>
  20. #include <linux/io.h>
  21. #include <linux/interrupt.h>
  22. #include <linux/completion.h>
  23. #include <linux/mutex.h>
  24. #include <linux/notifier.h>
  25. #include <linux/spinlock.h>
  26. #include <linux/device.h>
  27. #include <linux/amba/bus.h>
  28. #include <linux/pl320-ipc.h>
  29. #define IPCMxSOURCE(m) ((m) * 0x40)
  30. #define IPCMxDSET(m) (((m) * 0x40) + 0x004)
  31. #define IPCMxDCLEAR(m) (((m) * 0x40) + 0x008)
  32. #define IPCMxDSTATUS(m) (((m) * 0x40) + 0x00C)
  33. #define IPCMxMODE(m) (((m) * 0x40) + 0x010)
  34. #define IPCMxMSET(m) (((m) * 0x40) + 0x014)
  35. #define IPCMxMCLEAR(m) (((m) * 0x40) + 0x018)
  36. #define IPCMxMSTATUS(m) (((m) * 0x40) + 0x01C)
  37. #define IPCMxSEND(m) (((m) * 0x40) + 0x020)
  38. #define IPCMxDR(m, dr) (((m) * 0x40) + ((dr) * 4) + 0x024)
  39. #define IPCMMIS(irq) (((irq) * 8) + 0x800)
  40. #define IPCMRIS(irq) (((irq) * 8) + 0x804)
  41. #define MBOX_MASK(n) (1 << (n))
  42. #define IPC_TX_MBOX 1
  43. #define IPC_RX_MBOX 2
  44. #define CHAN_MASK(n) (1 << (n))
  45. #define A9_SOURCE 1
  46. #define M3_SOURCE 0
  47. static void __iomem *ipc_base;
  48. static int ipc_irq;
  49. static DEFINE_MUTEX(ipc_m1_lock);
  50. static DECLARE_COMPLETION(ipc_completion);
  51. static ATOMIC_NOTIFIER_HEAD(ipc_notifier);
  52. static inline void set_destination(int source, int mbox)
  53. {
  54. __raw_writel(CHAN_MASK(source), ipc_base + IPCMxDSET(mbox));
  55. __raw_writel(CHAN_MASK(source), ipc_base + IPCMxMSET(mbox));
  56. }
  57. static inline void clear_destination(int source, int mbox)
  58. {
  59. __raw_writel(CHAN_MASK(source), ipc_base + IPCMxDCLEAR(mbox));
  60. __raw_writel(CHAN_MASK(source), ipc_base + IPCMxMCLEAR(mbox));
  61. }
  62. static void __ipc_send(int mbox, u32 *data)
  63. {
  64. int i;
  65. for (i = 0; i < 7; i++)
  66. __raw_writel(data[i], ipc_base + IPCMxDR(mbox, i));
  67. __raw_writel(0x1, ipc_base + IPCMxSEND(mbox));
  68. }
  69. static u32 __ipc_rcv(int mbox, u32 *data)
  70. {
  71. int i;
  72. for (i = 0; i < 7; i++)
  73. data[i] = __raw_readl(ipc_base + IPCMxDR(mbox, i));
  74. return data[1];
  75. }
  76. /* blocking implmentation from the A9 side, not usuable in interrupts! */
  77. int pl320_ipc_transmit(u32 *data)
  78. {
  79. int ret;
  80. mutex_lock(&ipc_m1_lock);
  81. init_completion(&ipc_completion);
  82. __ipc_send(IPC_TX_MBOX, data);
  83. ret = wait_for_completion_timeout(&ipc_completion,
  84. msecs_to_jiffies(1000));
  85. if (ret == 0) {
  86. ret = -ETIMEDOUT;
  87. goto out;
  88. }
  89. ret = __ipc_rcv(IPC_TX_MBOX, data);
  90. out:
  91. mutex_unlock(&ipc_m1_lock);
  92. return ret;
  93. }
  94. EXPORT_SYMBOL_GPL(pl320_ipc_transmit);
  95. static irqreturn_t ipc_handler(int irq, void *dev)
  96. {
  97. u32 irq_stat;
  98. u32 data[7];
  99. irq_stat = __raw_readl(ipc_base + IPCMMIS(1));
  100. if (irq_stat & MBOX_MASK(IPC_TX_MBOX)) {
  101. __raw_writel(0, ipc_base + IPCMxSEND(IPC_TX_MBOX));
  102. complete(&ipc_completion);
  103. }
  104. if (irq_stat & MBOX_MASK(IPC_RX_MBOX)) {
  105. __ipc_rcv(IPC_RX_MBOX, data);
  106. atomic_notifier_call_chain(&ipc_notifier, data[0], data + 1);
  107. __raw_writel(2, ipc_base + IPCMxSEND(IPC_RX_MBOX));
  108. }
  109. return IRQ_HANDLED;
  110. }
  111. int pl320_ipc_register_notifier(struct notifier_block *nb)
  112. {
  113. return atomic_notifier_chain_register(&ipc_notifier, nb);
  114. }
  115. EXPORT_SYMBOL_GPL(pl320_ipc_register_notifier);
  116. int pl320_ipc_unregister_notifier(struct notifier_block *nb)
  117. {
  118. return atomic_notifier_chain_unregister(&ipc_notifier, nb);
  119. }
  120. EXPORT_SYMBOL_GPL(pl320_ipc_unregister_notifier);
  121. static int pl320_probe(struct amba_device *adev, const struct amba_id *id)
  122. {
  123. int ret;
  124. ipc_base = ioremap(adev->res.start, resource_size(&adev->res));
  125. if (ipc_base == NULL)
  126. return -ENOMEM;
  127. __raw_writel(0, ipc_base + IPCMxSEND(IPC_TX_MBOX));
  128. ipc_irq = adev->irq[0];
  129. ret = request_irq(ipc_irq, ipc_handler, 0, dev_name(&adev->dev), NULL);
  130. if (ret < 0)
  131. goto err;
  132. /* Init slow mailbox */
  133. __raw_writel(CHAN_MASK(A9_SOURCE),
  134. ipc_base + IPCMxSOURCE(IPC_TX_MBOX));
  135. __raw_writel(CHAN_MASK(M3_SOURCE),
  136. ipc_base + IPCMxDSET(IPC_TX_MBOX));
  137. __raw_writel(CHAN_MASK(M3_SOURCE) | CHAN_MASK(A9_SOURCE),
  138. ipc_base + IPCMxMSET(IPC_TX_MBOX));
  139. /* Init receive mailbox */
  140. __raw_writel(CHAN_MASK(M3_SOURCE),
  141. ipc_base + IPCMxSOURCE(IPC_RX_MBOX));
  142. __raw_writel(CHAN_MASK(A9_SOURCE),
  143. ipc_base + IPCMxDSET(IPC_RX_MBOX));
  144. __raw_writel(CHAN_MASK(M3_SOURCE) | CHAN_MASK(A9_SOURCE),
  145. ipc_base + IPCMxMSET(IPC_RX_MBOX));
  146. return 0;
  147. err:
  148. iounmap(ipc_base);
  149. return ret;
  150. }
  151. static struct amba_id pl320_ids[] = {
  152. {
  153. .id = 0x00041320,
  154. .mask = 0x000fffff,
  155. },
  156. { 0, 0 },
  157. };
  158. static struct amba_driver pl320_driver = {
  159. .drv = {
  160. .name = "pl320",
  161. },
  162. .id_table = pl320_ids,
  163. .probe = pl320_probe,
  164. };
  165. static int __init ipc_init(void)
  166. {
  167. return amba_driver_register(&pl320_driver);
  168. }
  169. subsys_initcall(ipc_init);