adv7180.c 37 KB

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  1. /*
  2. * adv7180.c Analog Devices ADV7180 video decoder driver
  3. * Copyright (c) 2009 Intel Corporation
  4. * Copyright (C) 2013 Cogent Embedded, Inc.
  5. * Copyright (C) 2013 Renesas Solutions Corp.
  6. *
  7. * This program is free software; you can redistribute it and/or modify
  8. * it under the terms of the GNU General Public License version 2 as
  9. * published by the Free Software Foundation.
  10. *
  11. * This program is distributed in the hope that it will be useful,
  12. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  13. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  14. * GNU General Public License for more details.
  15. *
  16. * You should have received a copy of the GNU General Public License
  17. * along with this program; if not, write to the Free Software
  18. * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  19. */
  20. #include <linux/module.h>
  21. #include <linux/init.h>
  22. #include <linux/errno.h>
  23. #include <linux/kernel.h>
  24. #include <linux/interrupt.h>
  25. #include <linux/i2c.h>
  26. #include <linux/slab.h>
  27. #include <linux/of.h>
  28. #include <media/v4l2-ioctl.h>
  29. #include <linux/videodev2.h>
  30. #include <media/v4l2-device.h>
  31. #include <media/v4l2-ctrls.h>
  32. #include <linux/mutex.h>
  33. #include <linux/delay.h>
  34. #define ADV7180_STD_AD_PAL_BG_NTSC_J_SECAM 0x0
  35. #define ADV7180_STD_AD_PAL_BG_NTSC_J_SECAM_PED 0x1
  36. #define ADV7180_STD_AD_PAL_N_NTSC_J_SECAM 0x2
  37. #define ADV7180_STD_AD_PAL_N_NTSC_M_SECAM 0x3
  38. #define ADV7180_STD_NTSC_J 0x4
  39. #define ADV7180_STD_NTSC_M 0x5
  40. #define ADV7180_STD_PAL60 0x6
  41. #define ADV7180_STD_NTSC_443 0x7
  42. #define ADV7180_STD_PAL_BG 0x8
  43. #define ADV7180_STD_PAL_N 0x9
  44. #define ADV7180_STD_PAL_M 0xa
  45. #define ADV7180_STD_PAL_M_PED 0xb
  46. #define ADV7180_STD_PAL_COMB_N 0xc
  47. #define ADV7180_STD_PAL_COMB_N_PED 0xd
  48. #define ADV7180_STD_PAL_SECAM 0xe
  49. #define ADV7180_STD_PAL_SECAM_PED 0xf
  50. #define ADV7180_REG_INPUT_CONTROL 0x0000
  51. #define ADV7180_INPUT_CONTROL_INSEL_MASK 0x0f
  52. #define ADV7182_REG_INPUT_VIDSEL 0x0002
  53. #define ADV7180_REG_EXTENDED_OUTPUT_CONTROL 0x0004
  54. #define ADV7180_EXTENDED_OUTPUT_CONTROL_NTSCDIS 0xC5
  55. #define ADV7180_REG_AUTODETECT_ENABLE 0x07
  56. #define ADV7180_AUTODETECT_DEFAULT 0x7f
  57. /* Contrast */
  58. #define ADV7180_REG_CON 0x0008 /*Unsigned */
  59. #define ADV7180_CON_MIN 0
  60. #define ADV7180_CON_DEF 128
  61. #define ADV7180_CON_MAX 255
  62. /* Brightness*/
  63. #define ADV7180_REG_BRI 0x000a /*Signed */
  64. #define ADV7180_BRI_MIN -128
  65. #define ADV7180_BRI_DEF 0
  66. #define ADV7180_BRI_MAX 127
  67. /* Hue */
  68. #define ADV7180_REG_HUE 0x000b /*Signed, inverted */
  69. #define ADV7180_HUE_MIN -127
  70. #define ADV7180_HUE_DEF 0
  71. #define ADV7180_HUE_MAX 128
  72. #define ADV7180_REG_CTRL 0x000e
  73. #define ADV7180_CTRL_IRQ_SPACE 0x20
  74. #define ADV7180_REG_PWR_MAN 0x0f
  75. #define ADV7180_PWR_MAN_ON 0x04
  76. #define ADV7180_PWR_MAN_OFF 0x24
  77. #define ADV7180_PWR_MAN_RES 0x80
  78. #define ADV7180_REG_STATUS1 0x0010
  79. #define ADV7180_STATUS1_IN_LOCK 0x01
  80. #define ADV7180_STATUS1_AUTOD_MASK 0x70
  81. #define ADV7180_STATUS1_AUTOD_NTSM_M_J 0x00
  82. #define ADV7180_STATUS1_AUTOD_NTSC_4_43 0x10
  83. #define ADV7180_STATUS1_AUTOD_PAL_M 0x20
  84. #define ADV7180_STATUS1_AUTOD_PAL_60 0x30
  85. #define ADV7180_STATUS1_AUTOD_PAL_B_G 0x40
  86. #define ADV7180_STATUS1_AUTOD_SECAM 0x50
  87. #define ADV7180_STATUS1_AUTOD_PAL_COMB 0x60
  88. #define ADV7180_STATUS1_AUTOD_SECAM_525 0x70
  89. #define ADV7180_REG_IDENT 0x0011
  90. #define ADV7180_ID_7180 0x18
  91. #define ADV7180_REG_ICONF1 0x0040
  92. #define ADV7180_ICONF1_ACTIVE_LOW 0x01
  93. #define ADV7180_ICONF1_PSYNC_ONLY 0x10
  94. #define ADV7180_ICONF1_ACTIVE_TO_CLR 0xC0
  95. /* Saturation */
  96. #define ADV7180_REG_SD_SAT_CB 0x00e3 /*Unsigned */
  97. #define ADV7180_REG_SD_SAT_CR 0x00e4 /*Unsigned */
  98. #define ADV7180_SAT_MIN 0
  99. #define ADV7180_SAT_DEF 128
  100. #define ADV7180_SAT_MAX 255
  101. #define ADV7180_IRQ1_LOCK 0x01
  102. #define ADV7180_IRQ1_UNLOCK 0x02
  103. #define ADV7180_REG_ISR1 0x0042
  104. #define ADV7180_REG_ICR1 0x0043
  105. #define ADV7180_REG_IMR1 0x0044
  106. #define ADV7180_REG_IMR2 0x0048
  107. #define ADV7180_IRQ3_AD_CHANGE 0x08
  108. #define ADV7180_REG_ISR3 0x004A
  109. #define ADV7180_REG_ICR3 0x004B
  110. #define ADV7180_REG_IMR3 0x004C
  111. #define ADV7180_REG_IMR4 0x50
  112. #define ADV7180_REG_NTSC_V_BIT_END 0x00E6
  113. #define ADV7180_NTSC_V_BIT_END_MANUAL_NVEND 0x4F
  114. #define ADV7180_REG_VPP_SLAVE_ADDR 0xFD
  115. #define ADV7180_REG_CSI_SLAVE_ADDR 0xFE
  116. #define ADV7180_REG_FLCONTROL 0x40e0
  117. #define ADV7180_FLCONTROL_FL_ENABLE 0x1
  118. #define ADV7180_CSI_REG_PWRDN 0x00
  119. #define ADV7180_CSI_PWRDN 0x80
  120. #define ADV7180_INPUT_CVBS_AIN1 0x00
  121. #define ADV7180_INPUT_CVBS_AIN2 0x01
  122. #define ADV7180_INPUT_CVBS_AIN3 0x02
  123. #define ADV7180_INPUT_CVBS_AIN4 0x03
  124. #define ADV7180_INPUT_CVBS_AIN5 0x04
  125. #define ADV7180_INPUT_CVBS_AIN6 0x05
  126. #define ADV7180_INPUT_SVIDEO_AIN1_AIN2 0x06
  127. #define ADV7180_INPUT_SVIDEO_AIN3_AIN4 0x07
  128. #define ADV7180_INPUT_SVIDEO_AIN5_AIN6 0x08
  129. #define ADV7180_INPUT_YPRPB_AIN1_AIN2_AIN3 0x09
  130. #define ADV7180_INPUT_YPRPB_AIN4_AIN5_AIN6 0x0a
  131. #define ADV7182_INPUT_CVBS_AIN1 0x00
  132. #define ADV7182_INPUT_CVBS_AIN2 0x01
  133. #define ADV7182_INPUT_CVBS_AIN3 0x02
  134. #define ADV7182_INPUT_CVBS_AIN4 0x03
  135. #define ADV7182_INPUT_CVBS_AIN5 0x04
  136. #define ADV7182_INPUT_CVBS_AIN6 0x05
  137. #define ADV7182_INPUT_CVBS_AIN7 0x06
  138. #define ADV7182_INPUT_CVBS_AIN8 0x07
  139. #define ADV7182_INPUT_SVIDEO_AIN1_AIN2 0x08
  140. #define ADV7182_INPUT_SVIDEO_AIN3_AIN4 0x09
  141. #define ADV7182_INPUT_SVIDEO_AIN5_AIN6 0x0a
  142. #define ADV7182_INPUT_SVIDEO_AIN7_AIN8 0x0b
  143. #define ADV7182_INPUT_YPRPB_AIN1_AIN2_AIN3 0x0c
  144. #define ADV7182_INPUT_YPRPB_AIN4_AIN5_AIN6 0x0d
  145. #define ADV7182_INPUT_DIFF_CVBS_AIN1_AIN2 0x0e
  146. #define ADV7182_INPUT_DIFF_CVBS_AIN3_AIN4 0x0f
  147. #define ADV7182_INPUT_DIFF_CVBS_AIN5_AIN6 0x10
  148. #define ADV7182_INPUT_DIFF_CVBS_AIN7_AIN8 0x11
  149. #define ADV7180_DEFAULT_CSI_I2C_ADDR 0x44
  150. #define ADV7180_DEFAULT_VPP_I2C_ADDR 0x42
  151. #define V4L2_CID_ADV_FAST_SWITCH (V4L2_CID_USER_ADV7180_BASE + 0x00)
  152. struct adv7180_state;
  153. #define ADV7180_FLAG_RESET_POWERED BIT(0)
  154. #define ADV7180_FLAG_V2 BIT(1)
  155. #define ADV7180_FLAG_MIPI_CSI2 BIT(2)
  156. #define ADV7180_FLAG_I2P BIT(3)
  157. struct adv7180_chip_info {
  158. unsigned int flags;
  159. unsigned int valid_input_mask;
  160. int (*set_std)(struct adv7180_state *st, unsigned int std);
  161. int (*select_input)(struct adv7180_state *st, unsigned int input);
  162. int (*init)(struct adv7180_state *state);
  163. };
  164. struct adv7180_state {
  165. struct v4l2_ctrl_handler ctrl_hdl;
  166. struct v4l2_subdev sd;
  167. struct media_pad pad;
  168. struct mutex mutex; /* mutual excl. when accessing chip */
  169. int irq;
  170. v4l2_std_id curr_norm;
  171. bool autodetect;
  172. bool powered;
  173. u8 input;
  174. struct i2c_client *client;
  175. unsigned int register_page;
  176. struct i2c_client *csi_client;
  177. struct i2c_client *vpp_client;
  178. const struct adv7180_chip_info *chip_info;
  179. enum v4l2_field field;
  180. };
  181. #define to_adv7180_sd(_ctrl) (&container_of(_ctrl->handler, \
  182. struct adv7180_state, \
  183. ctrl_hdl)->sd)
  184. static int adv7180_select_page(struct adv7180_state *state, unsigned int page)
  185. {
  186. if (state->register_page != page) {
  187. i2c_smbus_write_byte_data(state->client, ADV7180_REG_CTRL,
  188. page);
  189. state->register_page = page;
  190. }
  191. return 0;
  192. }
  193. static int adv7180_write(struct adv7180_state *state, unsigned int reg,
  194. unsigned int value)
  195. {
  196. lockdep_assert_held(&state->mutex);
  197. adv7180_select_page(state, reg >> 8);
  198. return i2c_smbus_write_byte_data(state->client, reg & 0xff, value);
  199. }
  200. static int adv7180_read(struct adv7180_state *state, unsigned int reg)
  201. {
  202. lockdep_assert_held(&state->mutex);
  203. adv7180_select_page(state, reg >> 8);
  204. return i2c_smbus_read_byte_data(state->client, reg & 0xff);
  205. }
  206. static int adv7180_csi_write(struct adv7180_state *state, unsigned int reg,
  207. unsigned int value)
  208. {
  209. return i2c_smbus_write_byte_data(state->csi_client, reg, value);
  210. }
  211. static int adv7180_set_video_standard(struct adv7180_state *state,
  212. unsigned int std)
  213. {
  214. return state->chip_info->set_std(state, std);
  215. }
  216. static int adv7180_vpp_write(struct adv7180_state *state, unsigned int reg,
  217. unsigned int value)
  218. {
  219. return i2c_smbus_write_byte_data(state->vpp_client, reg, value);
  220. }
  221. static v4l2_std_id adv7180_std_to_v4l2(u8 status1)
  222. {
  223. /* in case V4L2_IN_ST_NO_SIGNAL */
  224. if (!(status1 & ADV7180_STATUS1_IN_LOCK))
  225. return V4L2_STD_UNKNOWN;
  226. switch (status1 & ADV7180_STATUS1_AUTOD_MASK) {
  227. case ADV7180_STATUS1_AUTOD_NTSM_M_J:
  228. return V4L2_STD_NTSC;
  229. case ADV7180_STATUS1_AUTOD_NTSC_4_43:
  230. return V4L2_STD_NTSC_443;
  231. case ADV7180_STATUS1_AUTOD_PAL_M:
  232. return V4L2_STD_PAL_M;
  233. case ADV7180_STATUS1_AUTOD_PAL_60:
  234. return V4L2_STD_PAL_60;
  235. case ADV7180_STATUS1_AUTOD_PAL_B_G:
  236. return V4L2_STD_PAL;
  237. case ADV7180_STATUS1_AUTOD_SECAM:
  238. return V4L2_STD_SECAM;
  239. case ADV7180_STATUS1_AUTOD_PAL_COMB:
  240. return V4L2_STD_PAL_Nc | V4L2_STD_PAL_N;
  241. case ADV7180_STATUS1_AUTOD_SECAM_525:
  242. return V4L2_STD_SECAM;
  243. default:
  244. return V4L2_STD_UNKNOWN;
  245. }
  246. }
  247. static int v4l2_std_to_adv7180(v4l2_std_id std)
  248. {
  249. if (std == V4L2_STD_PAL_60)
  250. return ADV7180_STD_PAL60;
  251. if (std == V4L2_STD_NTSC_443)
  252. return ADV7180_STD_NTSC_443;
  253. if (std == V4L2_STD_PAL_N)
  254. return ADV7180_STD_PAL_N;
  255. if (std == V4L2_STD_PAL_M)
  256. return ADV7180_STD_PAL_M;
  257. if (std == V4L2_STD_PAL_Nc)
  258. return ADV7180_STD_PAL_COMB_N;
  259. if (std & V4L2_STD_PAL)
  260. return ADV7180_STD_PAL_BG;
  261. if (std & V4L2_STD_NTSC)
  262. return ADV7180_STD_NTSC_M;
  263. if (std & V4L2_STD_SECAM)
  264. return ADV7180_STD_PAL_SECAM;
  265. return -EINVAL;
  266. }
  267. static u32 adv7180_status_to_v4l2(u8 status1)
  268. {
  269. if (!(status1 & ADV7180_STATUS1_IN_LOCK))
  270. return V4L2_IN_ST_NO_SIGNAL;
  271. return 0;
  272. }
  273. static int __adv7180_status(struct adv7180_state *state, u32 *status,
  274. v4l2_std_id *std)
  275. {
  276. int status1 = adv7180_read(state, ADV7180_REG_STATUS1);
  277. if (status1 < 0)
  278. return status1;
  279. if (status)
  280. *status = adv7180_status_to_v4l2(status1);
  281. if (std)
  282. *std = adv7180_std_to_v4l2(status1);
  283. return 0;
  284. }
  285. static inline struct adv7180_state *to_state(struct v4l2_subdev *sd)
  286. {
  287. return container_of(sd, struct adv7180_state, sd);
  288. }
  289. static int adv7180_querystd(struct v4l2_subdev *sd, v4l2_std_id *std)
  290. {
  291. struct adv7180_state *state = to_state(sd);
  292. int err = mutex_lock_interruptible(&state->mutex);
  293. if (err)
  294. return err;
  295. /* when we are interrupt driven we know the state */
  296. if (!state->autodetect || state->irq > 0)
  297. *std = state->curr_norm;
  298. else
  299. err = __adv7180_status(state, NULL, std);
  300. mutex_unlock(&state->mutex);
  301. return err;
  302. }
  303. static int adv7180_s_routing(struct v4l2_subdev *sd, u32 input,
  304. u32 output, u32 config)
  305. {
  306. struct adv7180_state *state = to_state(sd);
  307. int ret = mutex_lock_interruptible(&state->mutex);
  308. if (ret)
  309. return ret;
  310. if (input > 31 || !(BIT(input) & state->chip_info->valid_input_mask)) {
  311. ret = -EINVAL;
  312. goto out;
  313. }
  314. ret = state->chip_info->select_input(state, input);
  315. if (ret == 0)
  316. state->input = input;
  317. out:
  318. mutex_unlock(&state->mutex);
  319. return ret;
  320. }
  321. static int adv7180_g_input_status(struct v4l2_subdev *sd, u32 *status)
  322. {
  323. struct adv7180_state *state = to_state(sd);
  324. int ret = mutex_lock_interruptible(&state->mutex);
  325. if (ret)
  326. return ret;
  327. ret = __adv7180_status(state, status, NULL);
  328. mutex_unlock(&state->mutex);
  329. return ret;
  330. }
  331. static int adv7180_program_std(struct adv7180_state *state)
  332. {
  333. int ret;
  334. if (state->autodetect) {
  335. ret = adv7180_set_video_standard(state,
  336. ADV7180_STD_AD_PAL_BG_NTSC_J_SECAM);
  337. if (ret < 0)
  338. return ret;
  339. __adv7180_status(state, NULL, &state->curr_norm);
  340. } else {
  341. ret = v4l2_std_to_adv7180(state->curr_norm);
  342. if (ret < 0)
  343. return ret;
  344. ret = adv7180_set_video_standard(state, ret);
  345. if (ret < 0)
  346. return ret;
  347. }
  348. return 0;
  349. }
  350. static int adv7180_s_std(struct v4l2_subdev *sd, v4l2_std_id std)
  351. {
  352. struct adv7180_state *state = to_state(sd);
  353. int ret = mutex_lock_interruptible(&state->mutex);
  354. if (ret)
  355. return ret;
  356. /* all standards -> autodetect */
  357. if (std == V4L2_STD_ALL) {
  358. state->autodetect = true;
  359. } else {
  360. /* Make sure we can support this std */
  361. ret = v4l2_std_to_adv7180(std);
  362. if (ret < 0)
  363. goto out;
  364. state->curr_norm = std;
  365. state->autodetect = false;
  366. }
  367. ret = adv7180_program_std(state);
  368. out:
  369. mutex_unlock(&state->mutex);
  370. return ret;
  371. }
  372. static int adv7180_set_power(struct adv7180_state *state, bool on)
  373. {
  374. u8 val;
  375. int ret;
  376. if (on)
  377. val = ADV7180_PWR_MAN_ON;
  378. else
  379. val = ADV7180_PWR_MAN_OFF;
  380. ret = adv7180_write(state, ADV7180_REG_PWR_MAN, val);
  381. if (ret)
  382. return ret;
  383. if (state->chip_info->flags & ADV7180_FLAG_MIPI_CSI2) {
  384. if (on) {
  385. adv7180_csi_write(state, 0xDE, 0x02);
  386. adv7180_csi_write(state, 0xD2, 0xF7);
  387. adv7180_csi_write(state, 0xD8, 0x65);
  388. adv7180_csi_write(state, 0xE0, 0x09);
  389. adv7180_csi_write(state, 0x2C, 0x00);
  390. if (state->field == V4L2_FIELD_NONE)
  391. adv7180_csi_write(state, 0x1D, 0x80);
  392. adv7180_csi_write(state, 0x00, 0x00);
  393. } else {
  394. adv7180_csi_write(state, 0x00, 0x80);
  395. }
  396. }
  397. return 0;
  398. }
  399. static int adv7180_s_power(struct v4l2_subdev *sd, int on)
  400. {
  401. struct adv7180_state *state = to_state(sd);
  402. int ret;
  403. ret = mutex_lock_interruptible(&state->mutex);
  404. if (ret)
  405. return ret;
  406. ret = adv7180_set_power(state, on);
  407. if (ret == 0)
  408. state->powered = on;
  409. mutex_unlock(&state->mutex);
  410. return ret;
  411. }
  412. static int adv7180_s_ctrl(struct v4l2_ctrl *ctrl)
  413. {
  414. struct v4l2_subdev *sd = to_adv7180_sd(ctrl);
  415. struct adv7180_state *state = to_state(sd);
  416. int ret = mutex_lock_interruptible(&state->mutex);
  417. int val;
  418. if (ret)
  419. return ret;
  420. val = ctrl->val;
  421. switch (ctrl->id) {
  422. case V4L2_CID_BRIGHTNESS:
  423. ret = adv7180_write(state, ADV7180_REG_BRI, val);
  424. break;
  425. case V4L2_CID_HUE:
  426. /*Hue is inverted according to HSL chart */
  427. ret = adv7180_write(state, ADV7180_REG_HUE, -val);
  428. break;
  429. case V4L2_CID_CONTRAST:
  430. ret = adv7180_write(state, ADV7180_REG_CON, val);
  431. break;
  432. case V4L2_CID_SATURATION:
  433. /*
  434. *This could be V4L2_CID_BLUE_BALANCE/V4L2_CID_RED_BALANCE
  435. *Let's not confuse the user, everybody understands saturation
  436. */
  437. ret = adv7180_write(state, ADV7180_REG_SD_SAT_CB, val);
  438. if (ret < 0)
  439. break;
  440. ret = adv7180_write(state, ADV7180_REG_SD_SAT_CR, val);
  441. break;
  442. case V4L2_CID_ADV_FAST_SWITCH:
  443. if (ctrl->val) {
  444. /* ADI required write */
  445. adv7180_write(state, 0x80d9, 0x44);
  446. adv7180_write(state, ADV7180_REG_FLCONTROL,
  447. ADV7180_FLCONTROL_FL_ENABLE);
  448. } else {
  449. /* ADI required write */
  450. adv7180_write(state, 0x80d9, 0xc4);
  451. adv7180_write(state, ADV7180_REG_FLCONTROL, 0x00);
  452. }
  453. break;
  454. default:
  455. ret = -EINVAL;
  456. }
  457. mutex_unlock(&state->mutex);
  458. return ret;
  459. }
  460. static const struct v4l2_ctrl_ops adv7180_ctrl_ops = {
  461. .s_ctrl = adv7180_s_ctrl,
  462. };
  463. static const struct v4l2_ctrl_config adv7180_ctrl_fast_switch = {
  464. .ops = &adv7180_ctrl_ops,
  465. .id = V4L2_CID_ADV_FAST_SWITCH,
  466. .name = "Fast Switching",
  467. .type = V4L2_CTRL_TYPE_BOOLEAN,
  468. .min = 0,
  469. .max = 1,
  470. .step = 1,
  471. };
  472. static int adv7180_init_controls(struct adv7180_state *state)
  473. {
  474. v4l2_ctrl_handler_init(&state->ctrl_hdl, 4);
  475. v4l2_ctrl_new_std(&state->ctrl_hdl, &adv7180_ctrl_ops,
  476. V4L2_CID_BRIGHTNESS, ADV7180_BRI_MIN,
  477. ADV7180_BRI_MAX, 1, ADV7180_BRI_DEF);
  478. v4l2_ctrl_new_std(&state->ctrl_hdl, &adv7180_ctrl_ops,
  479. V4L2_CID_CONTRAST, ADV7180_CON_MIN,
  480. ADV7180_CON_MAX, 1, ADV7180_CON_DEF);
  481. v4l2_ctrl_new_std(&state->ctrl_hdl, &adv7180_ctrl_ops,
  482. V4L2_CID_SATURATION, ADV7180_SAT_MIN,
  483. ADV7180_SAT_MAX, 1, ADV7180_SAT_DEF);
  484. v4l2_ctrl_new_std(&state->ctrl_hdl, &adv7180_ctrl_ops,
  485. V4L2_CID_HUE, ADV7180_HUE_MIN,
  486. ADV7180_HUE_MAX, 1, ADV7180_HUE_DEF);
  487. v4l2_ctrl_new_custom(&state->ctrl_hdl, &adv7180_ctrl_fast_switch, NULL);
  488. state->sd.ctrl_handler = &state->ctrl_hdl;
  489. if (state->ctrl_hdl.error) {
  490. int err = state->ctrl_hdl.error;
  491. v4l2_ctrl_handler_free(&state->ctrl_hdl);
  492. return err;
  493. }
  494. v4l2_ctrl_handler_setup(&state->ctrl_hdl);
  495. return 0;
  496. }
  497. static void adv7180_exit_controls(struct adv7180_state *state)
  498. {
  499. v4l2_ctrl_handler_free(&state->ctrl_hdl);
  500. }
  501. static int adv7180_enum_mbus_code(struct v4l2_subdev *sd,
  502. struct v4l2_subdev_pad_config *cfg,
  503. struct v4l2_subdev_mbus_code_enum *code)
  504. {
  505. if (code->index != 0)
  506. return -EINVAL;
  507. code->code = MEDIA_BUS_FMT_YUYV8_2X8;
  508. return 0;
  509. }
  510. static int adv7180_mbus_fmt(struct v4l2_subdev *sd,
  511. struct v4l2_mbus_framefmt *fmt)
  512. {
  513. struct adv7180_state *state = to_state(sd);
  514. fmt->code = MEDIA_BUS_FMT_YUYV8_2X8;
  515. fmt->colorspace = V4L2_COLORSPACE_SMPTE170M;
  516. fmt->width = 720;
  517. fmt->height = state->curr_norm & V4L2_STD_525_60 ? 480 : 576;
  518. return 0;
  519. }
  520. static int adv7180_set_field_mode(struct adv7180_state *state)
  521. {
  522. if (!(state->chip_info->flags & ADV7180_FLAG_I2P))
  523. return 0;
  524. if (state->field == V4L2_FIELD_NONE) {
  525. if (state->chip_info->flags & ADV7180_FLAG_MIPI_CSI2) {
  526. adv7180_csi_write(state, 0x01, 0x20);
  527. adv7180_csi_write(state, 0x02, 0x28);
  528. adv7180_csi_write(state, 0x03, 0x38);
  529. adv7180_csi_write(state, 0x04, 0x30);
  530. adv7180_csi_write(state, 0x05, 0x30);
  531. adv7180_csi_write(state, 0x06, 0x80);
  532. adv7180_csi_write(state, 0x07, 0x70);
  533. adv7180_csi_write(state, 0x08, 0x50);
  534. }
  535. adv7180_vpp_write(state, 0xa3, 0x00);
  536. adv7180_vpp_write(state, 0x5b, 0x00);
  537. adv7180_vpp_write(state, 0x55, 0x80);
  538. } else {
  539. if (state->chip_info->flags & ADV7180_FLAG_MIPI_CSI2) {
  540. adv7180_csi_write(state, 0x01, 0x18);
  541. adv7180_csi_write(state, 0x02, 0x18);
  542. adv7180_csi_write(state, 0x03, 0x30);
  543. adv7180_csi_write(state, 0x04, 0x20);
  544. adv7180_csi_write(state, 0x05, 0x28);
  545. adv7180_csi_write(state, 0x06, 0x40);
  546. adv7180_csi_write(state, 0x07, 0x58);
  547. adv7180_csi_write(state, 0x08, 0x30);
  548. }
  549. adv7180_vpp_write(state, 0xa3, 0x70);
  550. adv7180_vpp_write(state, 0x5b, 0x80);
  551. adv7180_vpp_write(state, 0x55, 0x00);
  552. }
  553. return 0;
  554. }
  555. static int adv7180_get_pad_format(struct v4l2_subdev *sd,
  556. struct v4l2_subdev_pad_config *cfg,
  557. struct v4l2_subdev_format *format)
  558. {
  559. struct adv7180_state *state = to_state(sd);
  560. if (format->which == V4L2_SUBDEV_FORMAT_TRY) {
  561. format->format = *v4l2_subdev_get_try_format(sd, cfg, 0);
  562. } else {
  563. adv7180_mbus_fmt(sd, &format->format);
  564. format->format.field = state->field;
  565. }
  566. return 0;
  567. }
  568. static int adv7180_set_pad_format(struct v4l2_subdev *sd,
  569. struct v4l2_subdev_pad_config *cfg,
  570. struct v4l2_subdev_format *format)
  571. {
  572. struct adv7180_state *state = to_state(sd);
  573. struct v4l2_mbus_framefmt *framefmt;
  574. switch (format->format.field) {
  575. case V4L2_FIELD_NONE:
  576. if (!(state->chip_info->flags & ADV7180_FLAG_I2P))
  577. format->format.field = V4L2_FIELD_INTERLACED;
  578. break;
  579. default:
  580. format->format.field = V4L2_FIELD_INTERLACED;
  581. break;
  582. }
  583. if (format->which == V4L2_SUBDEV_FORMAT_ACTIVE) {
  584. framefmt = &format->format;
  585. if (state->field != format->format.field) {
  586. state->field = format->format.field;
  587. adv7180_set_power(state, false);
  588. adv7180_set_field_mode(state);
  589. adv7180_set_power(state, true);
  590. }
  591. } else {
  592. framefmt = v4l2_subdev_get_try_format(sd, cfg, 0);
  593. *framefmt = format->format;
  594. }
  595. return adv7180_mbus_fmt(sd, framefmt);
  596. }
  597. static int adv7180_g_mbus_config(struct v4l2_subdev *sd,
  598. struct v4l2_mbus_config *cfg)
  599. {
  600. struct adv7180_state *state = to_state(sd);
  601. if (state->chip_info->flags & ADV7180_FLAG_MIPI_CSI2) {
  602. cfg->type = V4L2_MBUS_CSI2;
  603. cfg->flags = V4L2_MBUS_CSI2_1_LANE |
  604. V4L2_MBUS_CSI2_CHANNEL_0 |
  605. V4L2_MBUS_CSI2_CONTINUOUS_CLOCK;
  606. } else {
  607. /*
  608. * The ADV7180 sensor supports BT.601/656 output modes.
  609. * The BT.656 is default and not yet configurable by s/w.
  610. */
  611. cfg->flags = V4L2_MBUS_MASTER | V4L2_MBUS_PCLK_SAMPLE_RISING |
  612. V4L2_MBUS_DATA_ACTIVE_HIGH;
  613. cfg->type = V4L2_MBUS_BT656;
  614. }
  615. return 0;
  616. }
  617. static const struct v4l2_subdev_video_ops adv7180_video_ops = {
  618. .s_std = adv7180_s_std,
  619. .querystd = adv7180_querystd,
  620. .g_input_status = adv7180_g_input_status,
  621. .s_routing = adv7180_s_routing,
  622. .g_mbus_config = adv7180_g_mbus_config,
  623. };
  624. static const struct v4l2_subdev_core_ops adv7180_core_ops = {
  625. .s_power = adv7180_s_power,
  626. };
  627. static const struct v4l2_subdev_pad_ops adv7180_pad_ops = {
  628. .enum_mbus_code = adv7180_enum_mbus_code,
  629. .set_fmt = adv7180_set_pad_format,
  630. .get_fmt = adv7180_get_pad_format,
  631. };
  632. static const struct v4l2_subdev_ops adv7180_ops = {
  633. .core = &adv7180_core_ops,
  634. .video = &adv7180_video_ops,
  635. .pad = &adv7180_pad_ops,
  636. };
  637. static irqreturn_t adv7180_irq(int irq, void *devid)
  638. {
  639. struct adv7180_state *state = devid;
  640. u8 isr3;
  641. mutex_lock(&state->mutex);
  642. isr3 = adv7180_read(state, ADV7180_REG_ISR3);
  643. /* clear */
  644. adv7180_write(state, ADV7180_REG_ICR3, isr3);
  645. if (isr3 & ADV7180_IRQ3_AD_CHANGE && state->autodetect)
  646. __adv7180_status(state, NULL, &state->curr_norm);
  647. mutex_unlock(&state->mutex);
  648. return IRQ_HANDLED;
  649. }
  650. static int adv7180_init(struct adv7180_state *state)
  651. {
  652. int ret;
  653. /* ITU-R BT.656-4 compatible */
  654. ret = adv7180_write(state, ADV7180_REG_EXTENDED_OUTPUT_CONTROL,
  655. ADV7180_EXTENDED_OUTPUT_CONTROL_NTSCDIS);
  656. if (ret < 0)
  657. return ret;
  658. /* Manually set V bit end position in NTSC mode */
  659. return adv7180_write(state, ADV7180_REG_NTSC_V_BIT_END,
  660. ADV7180_NTSC_V_BIT_END_MANUAL_NVEND);
  661. }
  662. static int adv7180_set_std(struct adv7180_state *state, unsigned int std)
  663. {
  664. return adv7180_write(state, ADV7180_REG_INPUT_CONTROL,
  665. (std << 4) | state->input);
  666. }
  667. static int adv7180_select_input(struct adv7180_state *state, unsigned int input)
  668. {
  669. int ret;
  670. ret = adv7180_read(state, ADV7180_REG_INPUT_CONTROL);
  671. if (ret < 0)
  672. return ret;
  673. ret &= ~ADV7180_INPUT_CONTROL_INSEL_MASK;
  674. ret |= input;
  675. return adv7180_write(state, ADV7180_REG_INPUT_CONTROL, ret);
  676. }
  677. static int adv7182_init(struct adv7180_state *state)
  678. {
  679. if (state->chip_info->flags & ADV7180_FLAG_MIPI_CSI2)
  680. adv7180_write(state, ADV7180_REG_CSI_SLAVE_ADDR,
  681. ADV7180_DEFAULT_CSI_I2C_ADDR << 1);
  682. if (state->chip_info->flags & ADV7180_FLAG_I2P)
  683. adv7180_write(state, ADV7180_REG_VPP_SLAVE_ADDR,
  684. ADV7180_DEFAULT_VPP_I2C_ADDR << 1);
  685. if (state->chip_info->flags & ADV7180_FLAG_V2) {
  686. /* ADI recommended writes for improved video quality */
  687. adv7180_write(state, 0x0080, 0x51);
  688. adv7180_write(state, 0x0081, 0x51);
  689. adv7180_write(state, 0x0082, 0x68);
  690. }
  691. /* ADI required writes */
  692. if (state->chip_info->flags & ADV7180_FLAG_MIPI_CSI2) {
  693. adv7180_write(state, 0x0003, 0x4e);
  694. adv7180_write(state, 0x0004, 0x57);
  695. adv7180_write(state, 0x001d, 0xc0);
  696. } else {
  697. if (state->chip_info->flags & ADV7180_FLAG_V2)
  698. adv7180_write(state, 0x0004, 0x17);
  699. else
  700. adv7180_write(state, 0x0004, 0x07);
  701. adv7180_write(state, 0x0003, 0x0c);
  702. adv7180_write(state, 0x001d, 0x40);
  703. }
  704. adv7180_write(state, 0x0013, 0x00);
  705. return 0;
  706. }
  707. static int adv7182_set_std(struct adv7180_state *state, unsigned int std)
  708. {
  709. return adv7180_write(state, ADV7182_REG_INPUT_VIDSEL, std << 4);
  710. }
  711. enum adv7182_input_type {
  712. ADV7182_INPUT_TYPE_CVBS,
  713. ADV7182_INPUT_TYPE_DIFF_CVBS,
  714. ADV7182_INPUT_TYPE_SVIDEO,
  715. ADV7182_INPUT_TYPE_YPBPR,
  716. };
  717. static enum adv7182_input_type adv7182_get_input_type(unsigned int input)
  718. {
  719. switch (input) {
  720. case ADV7182_INPUT_CVBS_AIN1:
  721. case ADV7182_INPUT_CVBS_AIN2:
  722. case ADV7182_INPUT_CVBS_AIN3:
  723. case ADV7182_INPUT_CVBS_AIN4:
  724. case ADV7182_INPUT_CVBS_AIN5:
  725. case ADV7182_INPUT_CVBS_AIN6:
  726. case ADV7182_INPUT_CVBS_AIN7:
  727. case ADV7182_INPUT_CVBS_AIN8:
  728. return ADV7182_INPUT_TYPE_CVBS;
  729. case ADV7182_INPUT_SVIDEO_AIN1_AIN2:
  730. case ADV7182_INPUT_SVIDEO_AIN3_AIN4:
  731. case ADV7182_INPUT_SVIDEO_AIN5_AIN6:
  732. case ADV7182_INPUT_SVIDEO_AIN7_AIN8:
  733. return ADV7182_INPUT_TYPE_SVIDEO;
  734. case ADV7182_INPUT_YPRPB_AIN1_AIN2_AIN3:
  735. case ADV7182_INPUT_YPRPB_AIN4_AIN5_AIN6:
  736. return ADV7182_INPUT_TYPE_YPBPR;
  737. case ADV7182_INPUT_DIFF_CVBS_AIN1_AIN2:
  738. case ADV7182_INPUT_DIFF_CVBS_AIN3_AIN4:
  739. case ADV7182_INPUT_DIFF_CVBS_AIN5_AIN6:
  740. case ADV7182_INPUT_DIFF_CVBS_AIN7_AIN8:
  741. return ADV7182_INPUT_TYPE_DIFF_CVBS;
  742. default: /* Will never happen */
  743. return 0;
  744. }
  745. }
  746. /* ADI recommended writes to registers 0x52, 0x53, 0x54 */
  747. static unsigned int adv7182_lbias_settings[][3] = {
  748. [ADV7182_INPUT_TYPE_CVBS] = { 0xCB, 0x4E, 0x80 },
  749. [ADV7182_INPUT_TYPE_DIFF_CVBS] = { 0xC0, 0x4E, 0x80 },
  750. [ADV7182_INPUT_TYPE_SVIDEO] = { 0x0B, 0xCE, 0x80 },
  751. [ADV7182_INPUT_TYPE_YPBPR] = { 0x0B, 0x4E, 0xC0 },
  752. };
  753. static unsigned int adv7280_lbias_settings[][3] = {
  754. [ADV7182_INPUT_TYPE_CVBS] = { 0xCD, 0x4E, 0x80 },
  755. [ADV7182_INPUT_TYPE_DIFF_CVBS] = { 0xC0, 0x4E, 0x80 },
  756. [ADV7182_INPUT_TYPE_SVIDEO] = { 0x0B, 0xCE, 0x80 },
  757. [ADV7182_INPUT_TYPE_YPBPR] = { 0x0B, 0x4E, 0xC0 },
  758. };
  759. static int adv7182_select_input(struct adv7180_state *state, unsigned int input)
  760. {
  761. enum adv7182_input_type input_type;
  762. unsigned int *lbias;
  763. unsigned int i;
  764. int ret;
  765. ret = adv7180_write(state, ADV7180_REG_INPUT_CONTROL, input);
  766. if (ret)
  767. return ret;
  768. /* Reset clamp circuitry - ADI recommended writes */
  769. adv7180_write(state, 0x809c, 0x00);
  770. adv7180_write(state, 0x809c, 0xff);
  771. input_type = adv7182_get_input_type(input);
  772. switch (input_type) {
  773. case ADV7182_INPUT_TYPE_CVBS:
  774. case ADV7182_INPUT_TYPE_DIFF_CVBS:
  775. /* ADI recommends to use the SH1 filter */
  776. adv7180_write(state, 0x0017, 0x41);
  777. break;
  778. default:
  779. adv7180_write(state, 0x0017, 0x01);
  780. break;
  781. }
  782. if (state->chip_info->flags & ADV7180_FLAG_V2)
  783. lbias = adv7280_lbias_settings[input_type];
  784. else
  785. lbias = adv7182_lbias_settings[input_type];
  786. for (i = 0; i < ARRAY_SIZE(adv7182_lbias_settings[0]); i++)
  787. adv7180_write(state, 0x0052 + i, lbias[i]);
  788. if (input_type == ADV7182_INPUT_TYPE_DIFF_CVBS) {
  789. /* ADI required writes to make differential CVBS work */
  790. adv7180_write(state, 0x005f, 0xa8);
  791. adv7180_write(state, 0x005a, 0x90);
  792. adv7180_write(state, 0x0060, 0xb0);
  793. adv7180_write(state, 0x80b6, 0x08);
  794. adv7180_write(state, 0x80c0, 0xa0);
  795. } else {
  796. adv7180_write(state, 0x005f, 0xf0);
  797. adv7180_write(state, 0x005a, 0xd0);
  798. adv7180_write(state, 0x0060, 0x10);
  799. adv7180_write(state, 0x80b6, 0x9c);
  800. adv7180_write(state, 0x80c0, 0x00);
  801. }
  802. return 0;
  803. }
  804. static const struct adv7180_chip_info adv7180_info = {
  805. .flags = ADV7180_FLAG_RESET_POWERED,
  806. /* We cannot discriminate between LQFP and 40-pin LFCSP, so accept
  807. * all inputs and let the card driver take care of validation
  808. */
  809. .valid_input_mask = BIT(ADV7180_INPUT_CVBS_AIN1) |
  810. BIT(ADV7180_INPUT_CVBS_AIN2) |
  811. BIT(ADV7180_INPUT_CVBS_AIN3) |
  812. BIT(ADV7180_INPUT_CVBS_AIN4) |
  813. BIT(ADV7180_INPUT_CVBS_AIN5) |
  814. BIT(ADV7180_INPUT_CVBS_AIN6) |
  815. BIT(ADV7180_INPUT_SVIDEO_AIN1_AIN2) |
  816. BIT(ADV7180_INPUT_SVIDEO_AIN3_AIN4) |
  817. BIT(ADV7180_INPUT_SVIDEO_AIN5_AIN6) |
  818. BIT(ADV7180_INPUT_YPRPB_AIN1_AIN2_AIN3) |
  819. BIT(ADV7180_INPUT_YPRPB_AIN4_AIN5_AIN6),
  820. .init = adv7180_init,
  821. .set_std = adv7180_set_std,
  822. .select_input = adv7180_select_input,
  823. };
  824. static const struct adv7180_chip_info adv7182_info = {
  825. .valid_input_mask = BIT(ADV7182_INPUT_CVBS_AIN1) |
  826. BIT(ADV7182_INPUT_CVBS_AIN2) |
  827. BIT(ADV7182_INPUT_CVBS_AIN3) |
  828. BIT(ADV7182_INPUT_CVBS_AIN4) |
  829. BIT(ADV7182_INPUT_SVIDEO_AIN1_AIN2) |
  830. BIT(ADV7182_INPUT_SVIDEO_AIN3_AIN4) |
  831. BIT(ADV7182_INPUT_YPRPB_AIN1_AIN2_AIN3) |
  832. BIT(ADV7182_INPUT_DIFF_CVBS_AIN1_AIN2) |
  833. BIT(ADV7182_INPUT_DIFF_CVBS_AIN3_AIN4),
  834. .init = adv7182_init,
  835. .set_std = adv7182_set_std,
  836. .select_input = adv7182_select_input,
  837. };
  838. static const struct adv7180_chip_info adv7280_info = {
  839. .flags = ADV7180_FLAG_V2 | ADV7180_FLAG_I2P,
  840. .valid_input_mask = BIT(ADV7182_INPUT_CVBS_AIN1) |
  841. BIT(ADV7182_INPUT_CVBS_AIN2) |
  842. BIT(ADV7182_INPUT_CVBS_AIN3) |
  843. BIT(ADV7182_INPUT_CVBS_AIN4) |
  844. BIT(ADV7182_INPUT_SVIDEO_AIN1_AIN2) |
  845. BIT(ADV7182_INPUT_SVIDEO_AIN3_AIN4) |
  846. BIT(ADV7182_INPUT_YPRPB_AIN1_AIN2_AIN3),
  847. .init = adv7182_init,
  848. .set_std = adv7182_set_std,
  849. .select_input = adv7182_select_input,
  850. };
  851. static const struct adv7180_chip_info adv7280_m_info = {
  852. .flags = ADV7180_FLAG_V2 | ADV7180_FLAG_MIPI_CSI2 | ADV7180_FLAG_I2P,
  853. .valid_input_mask = BIT(ADV7182_INPUT_CVBS_AIN1) |
  854. BIT(ADV7182_INPUT_CVBS_AIN2) |
  855. BIT(ADV7182_INPUT_CVBS_AIN3) |
  856. BIT(ADV7182_INPUT_CVBS_AIN4) |
  857. BIT(ADV7182_INPUT_CVBS_AIN5) |
  858. BIT(ADV7182_INPUT_CVBS_AIN6) |
  859. BIT(ADV7182_INPUT_CVBS_AIN7) |
  860. BIT(ADV7182_INPUT_CVBS_AIN8) |
  861. BIT(ADV7182_INPUT_SVIDEO_AIN1_AIN2) |
  862. BIT(ADV7182_INPUT_SVIDEO_AIN3_AIN4) |
  863. BIT(ADV7182_INPUT_SVIDEO_AIN5_AIN6) |
  864. BIT(ADV7182_INPUT_SVIDEO_AIN7_AIN8) |
  865. BIT(ADV7182_INPUT_YPRPB_AIN1_AIN2_AIN3) |
  866. BIT(ADV7182_INPUT_YPRPB_AIN4_AIN5_AIN6),
  867. .init = adv7182_init,
  868. .set_std = adv7182_set_std,
  869. .select_input = adv7182_select_input,
  870. };
  871. static const struct adv7180_chip_info adv7281_info = {
  872. .flags = ADV7180_FLAG_V2 | ADV7180_FLAG_MIPI_CSI2,
  873. .valid_input_mask = BIT(ADV7182_INPUT_CVBS_AIN1) |
  874. BIT(ADV7182_INPUT_CVBS_AIN2) |
  875. BIT(ADV7182_INPUT_CVBS_AIN7) |
  876. BIT(ADV7182_INPUT_CVBS_AIN8) |
  877. BIT(ADV7182_INPUT_SVIDEO_AIN1_AIN2) |
  878. BIT(ADV7182_INPUT_SVIDEO_AIN7_AIN8) |
  879. BIT(ADV7182_INPUT_DIFF_CVBS_AIN1_AIN2) |
  880. BIT(ADV7182_INPUT_DIFF_CVBS_AIN7_AIN8),
  881. .init = adv7182_init,
  882. .set_std = adv7182_set_std,
  883. .select_input = adv7182_select_input,
  884. };
  885. static const struct adv7180_chip_info adv7281_m_info = {
  886. .flags = ADV7180_FLAG_V2 | ADV7180_FLAG_MIPI_CSI2,
  887. .valid_input_mask = BIT(ADV7182_INPUT_CVBS_AIN1) |
  888. BIT(ADV7182_INPUT_CVBS_AIN2) |
  889. BIT(ADV7182_INPUT_CVBS_AIN3) |
  890. BIT(ADV7182_INPUT_CVBS_AIN4) |
  891. BIT(ADV7182_INPUT_CVBS_AIN7) |
  892. BIT(ADV7182_INPUT_CVBS_AIN8) |
  893. BIT(ADV7182_INPUT_SVIDEO_AIN1_AIN2) |
  894. BIT(ADV7182_INPUT_SVIDEO_AIN3_AIN4) |
  895. BIT(ADV7182_INPUT_SVIDEO_AIN7_AIN8) |
  896. BIT(ADV7182_INPUT_YPRPB_AIN1_AIN2_AIN3) |
  897. BIT(ADV7182_INPUT_DIFF_CVBS_AIN1_AIN2) |
  898. BIT(ADV7182_INPUT_DIFF_CVBS_AIN3_AIN4) |
  899. BIT(ADV7182_INPUT_DIFF_CVBS_AIN7_AIN8),
  900. .init = adv7182_init,
  901. .set_std = adv7182_set_std,
  902. .select_input = adv7182_select_input,
  903. };
  904. static const struct adv7180_chip_info adv7281_ma_info = {
  905. .flags = ADV7180_FLAG_V2 | ADV7180_FLAG_MIPI_CSI2,
  906. .valid_input_mask = BIT(ADV7182_INPUT_CVBS_AIN1) |
  907. BIT(ADV7182_INPUT_CVBS_AIN2) |
  908. BIT(ADV7182_INPUT_CVBS_AIN3) |
  909. BIT(ADV7182_INPUT_CVBS_AIN4) |
  910. BIT(ADV7182_INPUT_CVBS_AIN5) |
  911. BIT(ADV7182_INPUT_CVBS_AIN6) |
  912. BIT(ADV7182_INPUT_CVBS_AIN7) |
  913. BIT(ADV7182_INPUT_CVBS_AIN8) |
  914. BIT(ADV7182_INPUT_SVIDEO_AIN1_AIN2) |
  915. BIT(ADV7182_INPUT_SVIDEO_AIN3_AIN4) |
  916. BIT(ADV7182_INPUT_SVIDEO_AIN5_AIN6) |
  917. BIT(ADV7182_INPUT_SVIDEO_AIN7_AIN8) |
  918. BIT(ADV7182_INPUT_YPRPB_AIN1_AIN2_AIN3) |
  919. BIT(ADV7182_INPUT_YPRPB_AIN4_AIN5_AIN6) |
  920. BIT(ADV7182_INPUT_DIFF_CVBS_AIN1_AIN2) |
  921. BIT(ADV7182_INPUT_DIFF_CVBS_AIN3_AIN4) |
  922. BIT(ADV7182_INPUT_DIFF_CVBS_AIN5_AIN6) |
  923. BIT(ADV7182_INPUT_DIFF_CVBS_AIN7_AIN8),
  924. .init = adv7182_init,
  925. .set_std = adv7182_set_std,
  926. .select_input = adv7182_select_input,
  927. };
  928. static const struct adv7180_chip_info adv7282_info = {
  929. .flags = ADV7180_FLAG_V2 | ADV7180_FLAG_I2P,
  930. .valid_input_mask = BIT(ADV7182_INPUT_CVBS_AIN1) |
  931. BIT(ADV7182_INPUT_CVBS_AIN2) |
  932. BIT(ADV7182_INPUT_CVBS_AIN7) |
  933. BIT(ADV7182_INPUT_CVBS_AIN8) |
  934. BIT(ADV7182_INPUT_SVIDEO_AIN1_AIN2) |
  935. BIT(ADV7182_INPUT_SVIDEO_AIN7_AIN8) |
  936. BIT(ADV7182_INPUT_DIFF_CVBS_AIN1_AIN2) |
  937. BIT(ADV7182_INPUT_DIFF_CVBS_AIN7_AIN8),
  938. .init = adv7182_init,
  939. .set_std = adv7182_set_std,
  940. .select_input = adv7182_select_input,
  941. };
  942. static const struct adv7180_chip_info adv7282_m_info = {
  943. .flags = ADV7180_FLAG_V2 | ADV7180_FLAG_MIPI_CSI2 | ADV7180_FLAG_I2P,
  944. .valid_input_mask = BIT(ADV7182_INPUT_CVBS_AIN1) |
  945. BIT(ADV7182_INPUT_CVBS_AIN2) |
  946. BIT(ADV7182_INPUT_CVBS_AIN3) |
  947. BIT(ADV7182_INPUT_CVBS_AIN4) |
  948. BIT(ADV7182_INPUT_CVBS_AIN7) |
  949. BIT(ADV7182_INPUT_CVBS_AIN8) |
  950. BIT(ADV7182_INPUT_SVIDEO_AIN1_AIN2) |
  951. BIT(ADV7182_INPUT_SVIDEO_AIN3_AIN4) |
  952. BIT(ADV7182_INPUT_SVIDEO_AIN7_AIN8) |
  953. BIT(ADV7182_INPUT_DIFF_CVBS_AIN1_AIN2) |
  954. BIT(ADV7182_INPUT_DIFF_CVBS_AIN3_AIN4) |
  955. BIT(ADV7182_INPUT_DIFF_CVBS_AIN7_AIN8),
  956. .init = adv7182_init,
  957. .set_std = adv7182_set_std,
  958. .select_input = adv7182_select_input,
  959. };
  960. static int init_device(struct adv7180_state *state)
  961. {
  962. int ret;
  963. mutex_lock(&state->mutex);
  964. adv7180_write(state, ADV7180_REG_PWR_MAN, ADV7180_PWR_MAN_RES);
  965. usleep_range(2000, 10000);
  966. ret = state->chip_info->init(state);
  967. if (ret)
  968. goto out_unlock;
  969. ret = adv7180_program_std(state);
  970. if (ret)
  971. goto out_unlock;
  972. adv7180_set_field_mode(state);
  973. /* register for interrupts */
  974. if (state->irq > 0) {
  975. /* config the Interrupt pin to be active low */
  976. ret = adv7180_write(state, ADV7180_REG_ICONF1,
  977. ADV7180_ICONF1_ACTIVE_LOW |
  978. ADV7180_ICONF1_PSYNC_ONLY);
  979. if (ret < 0)
  980. goto out_unlock;
  981. ret = adv7180_write(state, ADV7180_REG_IMR1, 0);
  982. if (ret < 0)
  983. goto out_unlock;
  984. ret = adv7180_write(state, ADV7180_REG_IMR2, 0);
  985. if (ret < 0)
  986. goto out_unlock;
  987. /* enable AD change interrupts interrupts */
  988. ret = adv7180_write(state, ADV7180_REG_IMR3,
  989. ADV7180_IRQ3_AD_CHANGE);
  990. if (ret < 0)
  991. goto out_unlock;
  992. ret = adv7180_write(state, ADV7180_REG_IMR4, 0);
  993. if (ret < 0)
  994. goto out_unlock;
  995. }
  996. out_unlock:
  997. mutex_unlock(&state->mutex);
  998. return ret;
  999. }
  1000. static int adv7180_probe(struct i2c_client *client,
  1001. const struct i2c_device_id *id)
  1002. {
  1003. struct adv7180_state *state;
  1004. struct v4l2_subdev *sd;
  1005. int ret;
  1006. /* Check if the adapter supports the needed features */
  1007. if (!i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_BYTE_DATA))
  1008. return -EIO;
  1009. v4l_info(client, "chip found @ 0x%02x (%s)\n",
  1010. client->addr, client->adapter->name);
  1011. state = devm_kzalloc(&client->dev, sizeof(*state), GFP_KERNEL);
  1012. if (state == NULL)
  1013. return -ENOMEM;
  1014. state->client = client;
  1015. state->field = V4L2_FIELD_INTERLACED;
  1016. state->chip_info = (struct adv7180_chip_info *)id->driver_data;
  1017. if (state->chip_info->flags & ADV7180_FLAG_MIPI_CSI2) {
  1018. state->csi_client = i2c_new_dummy(client->adapter,
  1019. ADV7180_DEFAULT_CSI_I2C_ADDR);
  1020. if (!state->csi_client)
  1021. return -ENOMEM;
  1022. }
  1023. if (state->chip_info->flags & ADV7180_FLAG_I2P) {
  1024. state->vpp_client = i2c_new_dummy(client->adapter,
  1025. ADV7180_DEFAULT_VPP_I2C_ADDR);
  1026. if (!state->vpp_client) {
  1027. ret = -ENOMEM;
  1028. goto err_unregister_csi_client;
  1029. }
  1030. }
  1031. state->irq = client->irq;
  1032. mutex_init(&state->mutex);
  1033. state->autodetect = true;
  1034. if (state->chip_info->flags & ADV7180_FLAG_RESET_POWERED)
  1035. state->powered = true;
  1036. else
  1037. state->powered = false;
  1038. state->input = 0;
  1039. sd = &state->sd;
  1040. v4l2_i2c_subdev_init(sd, client, &adv7180_ops);
  1041. sd->flags = V4L2_SUBDEV_FL_HAS_DEVNODE;
  1042. ret = adv7180_init_controls(state);
  1043. if (ret)
  1044. goto err_unregister_vpp_client;
  1045. state->pad.flags = MEDIA_PAD_FL_SOURCE;
  1046. sd->entity.flags |= MEDIA_ENT_T_V4L2_SUBDEV_DECODER;
  1047. ret = media_entity_init(&sd->entity, 1, &state->pad, 0);
  1048. if (ret)
  1049. goto err_free_ctrl;
  1050. ret = init_device(state);
  1051. if (ret)
  1052. goto err_media_entity_cleanup;
  1053. if (state->irq) {
  1054. ret = request_threaded_irq(client->irq, NULL, adv7180_irq,
  1055. IRQF_ONESHOT | IRQF_TRIGGER_FALLING,
  1056. KBUILD_MODNAME, state);
  1057. if (ret)
  1058. goto err_media_entity_cleanup;
  1059. }
  1060. ret = v4l2_async_register_subdev(sd);
  1061. if (ret)
  1062. goto err_free_irq;
  1063. return 0;
  1064. err_free_irq:
  1065. if (state->irq > 0)
  1066. free_irq(client->irq, state);
  1067. err_media_entity_cleanup:
  1068. media_entity_cleanup(&sd->entity);
  1069. err_free_ctrl:
  1070. adv7180_exit_controls(state);
  1071. err_unregister_vpp_client:
  1072. if (state->chip_info->flags & ADV7180_FLAG_I2P)
  1073. i2c_unregister_device(state->vpp_client);
  1074. err_unregister_csi_client:
  1075. if (state->chip_info->flags & ADV7180_FLAG_MIPI_CSI2)
  1076. i2c_unregister_device(state->csi_client);
  1077. mutex_destroy(&state->mutex);
  1078. return ret;
  1079. }
  1080. static int adv7180_remove(struct i2c_client *client)
  1081. {
  1082. struct v4l2_subdev *sd = i2c_get_clientdata(client);
  1083. struct adv7180_state *state = to_state(sd);
  1084. v4l2_async_unregister_subdev(sd);
  1085. if (state->irq > 0)
  1086. free_irq(client->irq, state);
  1087. media_entity_cleanup(&sd->entity);
  1088. adv7180_exit_controls(state);
  1089. if (state->chip_info->flags & ADV7180_FLAG_I2P)
  1090. i2c_unregister_device(state->vpp_client);
  1091. if (state->chip_info->flags & ADV7180_FLAG_MIPI_CSI2)
  1092. i2c_unregister_device(state->csi_client);
  1093. mutex_destroy(&state->mutex);
  1094. return 0;
  1095. }
  1096. static const struct i2c_device_id adv7180_id[] = {
  1097. { "adv7180", (kernel_ulong_t)&adv7180_info },
  1098. { "adv7182", (kernel_ulong_t)&adv7182_info },
  1099. { "adv7280", (kernel_ulong_t)&adv7280_info },
  1100. { "adv7280-m", (kernel_ulong_t)&adv7280_m_info },
  1101. { "adv7281", (kernel_ulong_t)&adv7281_info },
  1102. { "adv7281-m", (kernel_ulong_t)&adv7281_m_info },
  1103. { "adv7281-ma", (kernel_ulong_t)&adv7281_ma_info },
  1104. { "adv7282", (kernel_ulong_t)&adv7282_info },
  1105. { "adv7282-m", (kernel_ulong_t)&adv7282_m_info },
  1106. {},
  1107. };
  1108. MODULE_DEVICE_TABLE(i2c, adv7180_id);
  1109. #ifdef CONFIG_PM_SLEEP
  1110. static int adv7180_suspend(struct device *dev)
  1111. {
  1112. struct i2c_client *client = to_i2c_client(dev);
  1113. struct v4l2_subdev *sd = i2c_get_clientdata(client);
  1114. struct adv7180_state *state = to_state(sd);
  1115. return adv7180_set_power(state, false);
  1116. }
  1117. static int adv7180_resume(struct device *dev)
  1118. {
  1119. struct i2c_client *client = to_i2c_client(dev);
  1120. struct v4l2_subdev *sd = i2c_get_clientdata(client);
  1121. struct adv7180_state *state = to_state(sd);
  1122. int ret;
  1123. ret = init_device(state);
  1124. if (ret < 0)
  1125. return ret;
  1126. ret = adv7180_set_power(state, state->powered);
  1127. if (ret)
  1128. return ret;
  1129. return 0;
  1130. }
  1131. static SIMPLE_DEV_PM_OPS(adv7180_pm_ops, adv7180_suspend, adv7180_resume);
  1132. #define ADV7180_PM_OPS (&adv7180_pm_ops)
  1133. #else
  1134. #define ADV7180_PM_OPS NULL
  1135. #endif
  1136. #ifdef CONFIG_OF
  1137. static const struct of_device_id adv7180_of_id[] = {
  1138. { .compatible = "adi,adv7180", },
  1139. { },
  1140. };
  1141. MODULE_DEVICE_TABLE(of, adv7180_of_id);
  1142. #endif
  1143. static struct i2c_driver adv7180_driver = {
  1144. .driver = {
  1145. .name = KBUILD_MODNAME,
  1146. .pm = ADV7180_PM_OPS,
  1147. .of_match_table = of_match_ptr(adv7180_of_id),
  1148. },
  1149. .probe = adv7180_probe,
  1150. .remove = adv7180_remove,
  1151. .id_table = adv7180_id,
  1152. };
  1153. module_i2c_driver(adv7180_driver);
  1154. MODULE_DESCRIPTION("Analog Devices ADV7180 video decoder driver");
  1155. MODULE_AUTHOR("Mocean Laboratories");
  1156. MODULE_LICENSE("GPL v2");