adv7343.c 13 KB

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  1. /*
  2. * adv7343 - ADV7343 Video Encoder Driver
  3. *
  4. * The encoder hardware does not support SECAM.
  5. *
  6. * Copyright (C) 2009 Texas Instruments Incorporated - http://www.ti.com/
  7. *
  8. * This program is free software; you can redistribute it and/or
  9. * modify it under the terms of the GNU General Public License as
  10. * published by the Free Software Foundation version 2.
  11. *
  12. * This program is distributed .as is. WITHOUT ANY WARRANTY of any
  13. * kind, whether express or implied; without even the implied warranty
  14. * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  15. * GNU General Public License for more details.
  16. */
  17. #include <linux/kernel.h>
  18. #include <linux/init.h>
  19. #include <linux/ctype.h>
  20. #include <linux/slab.h>
  21. #include <linux/i2c.h>
  22. #include <linux/device.h>
  23. #include <linux/delay.h>
  24. #include <linux/module.h>
  25. #include <linux/videodev2.h>
  26. #include <linux/uaccess.h>
  27. #include <linux/of.h>
  28. #include <linux/of_graph.h>
  29. #include <media/adv7343.h>
  30. #include <media/v4l2-async.h>
  31. #include <media/v4l2-device.h>
  32. #include <media/v4l2-ctrls.h>
  33. #include "adv7343_regs.h"
  34. MODULE_DESCRIPTION("ADV7343 video encoder driver");
  35. MODULE_LICENSE("GPL");
  36. static int debug;
  37. module_param(debug, int, 0644);
  38. MODULE_PARM_DESC(debug, "Debug level 0-1");
  39. struct adv7343_state {
  40. struct v4l2_subdev sd;
  41. struct v4l2_ctrl_handler hdl;
  42. const struct adv7343_platform_data *pdata;
  43. u8 reg00;
  44. u8 reg01;
  45. u8 reg02;
  46. u8 reg35;
  47. u8 reg80;
  48. u8 reg82;
  49. u32 output;
  50. v4l2_std_id std;
  51. };
  52. static inline struct adv7343_state *to_state(struct v4l2_subdev *sd)
  53. {
  54. return container_of(sd, struct adv7343_state, sd);
  55. }
  56. static inline struct v4l2_subdev *to_sd(struct v4l2_ctrl *ctrl)
  57. {
  58. return &container_of(ctrl->handler, struct adv7343_state, hdl)->sd;
  59. }
  60. static inline int adv7343_write(struct v4l2_subdev *sd, u8 reg, u8 value)
  61. {
  62. struct i2c_client *client = v4l2_get_subdevdata(sd);
  63. return i2c_smbus_write_byte_data(client, reg, value);
  64. }
  65. static const u8 adv7343_init_reg_val[] = {
  66. ADV7343_SOFT_RESET, ADV7343_SOFT_RESET_DEFAULT,
  67. ADV7343_POWER_MODE_REG, ADV7343_POWER_MODE_REG_DEFAULT,
  68. ADV7343_HD_MODE_REG1, ADV7343_HD_MODE_REG1_DEFAULT,
  69. ADV7343_HD_MODE_REG2, ADV7343_HD_MODE_REG2_DEFAULT,
  70. ADV7343_HD_MODE_REG3, ADV7343_HD_MODE_REG3_DEFAULT,
  71. ADV7343_HD_MODE_REG4, ADV7343_HD_MODE_REG4_DEFAULT,
  72. ADV7343_HD_MODE_REG5, ADV7343_HD_MODE_REG5_DEFAULT,
  73. ADV7343_HD_MODE_REG6, ADV7343_HD_MODE_REG6_DEFAULT,
  74. ADV7343_HD_MODE_REG7, ADV7343_HD_MODE_REG7_DEFAULT,
  75. ADV7343_SD_MODE_REG1, ADV7343_SD_MODE_REG1_DEFAULT,
  76. ADV7343_SD_MODE_REG2, ADV7343_SD_MODE_REG2_DEFAULT,
  77. ADV7343_SD_MODE_REG3, ADV7343_SD_MODE_REG3_DEFAULT,
  78. ADV7343_SD_MODE_REG4, ADV7343_SD_MODE_REG4_DEFAULT,
  79. ADV7343_SD_MODE_REG5, ADV7343_SD_MODE_REG5_DEFAULT,
  80. ADV7343_SD_MODE_REG6, ADV7343_SD_MODE_REG6_DEFAULT,
  81. ADV7343_SD_MODE_REG7, ADV7343_SD_MODE_REG7_DEFAULT,
  82. ADV7343_SD_MODE_REG8, ADV7343_SD_MODE_REG8_DEFAULT,
  83. ADV7343_SD_HUE_REG, ADV7343_SD_HUE_REG_DEFAULT,
  84. ADV7343_SD_CGMS_WSS0, ADV7343_SD_CGMS_WSS0_DEFAULT,
  85. ADV7343_SD_BRIGHTNESS_WSS, ADV7343_SD_BRIGHTNESS_WSS_DEFAULT,
  86. };
  87. /*
  88. * 2^32
  89. * FSC(reg) = FSC (HZ) * --------
  90. * 27000000
  91. */
  92. static const struct adv7343_std_info stdinfo[] = {
  93. {
  94. /* FSC(Hz) = 3,579,545.45 Hz */
  95. SD_STD_NTSC, 569408542, V4L2_STD_NTSC,
  96. }, {
  97. /* FSC(Hz) = 3,575,611.00 Hz */
  98. SD_STD_PAL_M, 568782678, V4L2_STD_PAL_M,
  99. }, {
  100. /* FSC(Hz) = 3,582,056.00 */
  101. SD_STD_PAL_N, 569807903, V4L2_STD_PAL_Nc,
  102. }, {
  103. /* FSC(Hz) = 4,433,618.75 Hz */
  104. SD_STD_PAL_N, 705268427, V4L2_STD_PAL_N,
  105. }, {
  106. /* FSC(Hz) = 4,433,618.75 Hz */
  107. SD_STD_PAL_BDGHI, 705268427, V4L2_STD_PAL,
  108. }, {
  109. /* FSC(Hz) = 4,433,618.75 Hz */
  110. SD_STD_NTSC, 705268427, V4L2_STD_NTSC_443,
  111. }, {
  112. /* FSC(Hz) = 4,433,618.75 Hz */
  113. SD_STD_PAL_M, 705268427, V4L2_STD_PAL_60,
  114. },
  115. };
  116. static int adv7343_setstd(struct v4l2_subdev *sd, v4l2_std_id std)
  117. {
  118. struct adv7343_state *state = to_state(sd);
  119. struct adv7343_std_info *std_info;
  120. int num_std;
  121. char *fsc_ptr;
  122. u8 reg, val;
  123. int err = 0;
  124. int i = 0;
  125. std_info = (struct adv7343_std_info *)stdinfo;
  126. num_std = ARRAY_SIZE(stdinfo);
  127. for (i = 0; i < num_std; i++) {
  128. if (std_info[i].stdid & std)
  129. break;
  130. }
  131. if (i == num_std) {
  132. v4l2_dbg(1, debug, sd,
  133. "Invalid std or std is not supported: %llx\n",
  134. (unsigned long long)std);
  135. return -EINVAL;
  136. }
  137. /* Set the standard */
  138. val = state->reg80 & (~(SD_STD_MASK));
  139. val |= std_info[i].standard_val3;
  140. err = adv7343_write(sd, ADV7343_SD_MODE_REG1, val);
  141. if (err < 0)
  142. goto setstd_exit;
  143. state->reg80 = val;
  144. /* Configure the input mode register */
  145. val = state->reg01 & (~((u8) INPUT_MODE_MASK));
  146. val |= SD_INPUT_MODE;
  147. err = adv7343_write(sd, ADV7343_MODE_SELECT_REG, val);
  148. if (err < 0)
  149. goto setstd_exit;
  150. state->reg01 = val;
  151. /* Program the sub carrier frequency registers */
  152. fsc_ptr = (unsigned char *)&std_info[i].fsc_val;
  153. reg = ADV7343_FSC_REG0;
  154. for (i = 0; i < 4; i++, reg++, fsc_ptr++) {
  155. err = adv7343_write(sd, reg, *fsc_ptr);
  156. if (err < 0)
  157. goto setstd_exit;
  158. }
  159. val = state->reg80;
  160. /* Filter settings */
  161. if (std & (V4L2_STD_NTSC | V4L2_STD_NTSC_443))
  162. val &= 0x03;
  163. else if (std & ~V4L2_STD_SECAM)
  164. val |= 0x04;
  165. err = adv7343_write(sd, ADV7343_SD_MODE_REG1, val);
  166. if (err < 0)
  167. goto setstd_exit;
  168. state->reg80 = val;
  169. setstd_exit:
  170. if (err != 0)
  171. v4l2_err(sd, "Error setting std, write failed\n");
  172. return err;
  173. }
  174. static int adv7343_setoutput(struct v4l2_subdev *sd, u32 output_type)
  175. {
  176. struct adv7343_state *state = to_state(sd);
  177. unsigned char val;
  178. int err = 0;
  179. if (output_type > ADV7343_SVIDEO_ID) {
  180. v4l2_dbg(1, debug, sd,
  181. "Invalid output type or output type not supported:%d\n",
  182. output_type);
  183. return -EINVAL;
  184. }
  185. /* Enable Appropriate DAC */
  186. val = state->reg00 & 0x03;
  187. /* configure default configuration */
  188. if (!state->pdata)
  189. if (output_type == ADV7343_COMPOSITE_ID)
  190. val |= ADV7343_COMPOSITE_POWER_VALUE;
  191. else if (output_type == ADV7343_COMPONENT_ID)
  192. val |= ADV7343_COMPONENT_POWER_VALUE;
  193. else
  194. val |= ADV7343_SVIDEO_POWER_VALUE;
  195. else
  196. val = state->pdata->mode_config.sleep_mode << 0 |
  197. state->pdata->mode_config.pll_control << 1 |
  198. state->pdata->mode_config.dac[2] << 2 |
  199. state->pdata->mode_config.dac[1] << 3 |
  200. state->pdata->mode_config.dac[0] << 4 |
  201. state->pdata->mode_config.dac[5] << 5 |
  202. state->pdata->mode_config.dac[4] << 6 |
  203. state->pdata->mode_config.dac[3] << 7;
  204. err = adv7343_write(sd, ADV7343_POWER_MODE_REG, val);
  205. if (err < 0)
  206. goto setoutput_exit;
  207. state->reg00 = val;
  208. /* Enable YUV output */
  209. val = state->reg02 | YUV_OUTPUT_SELECT;
  210. err = adv7343_write(sd, ADV7343_MODE_REG0, val);
  211. if (err < 0)
  212. goto setoutput_exit;
  213. state->reg02 = val;
  214. /* configure SD DAC Output 2 and SD DAC Output 1 bit to zero */
  215. val = state->reg82 & (SD_DAC_1_DI & SD_DAC_2_DI);
  216. if (state->pdata && state->pdata->sd_config.sd_dac_out[0])
  217. val = val | (state->pdata->sd_config.sd_dac_out[0] << 1);
  218. else if (state->pdata && !state->pdata->sd_config.sd_dac_out[0])
  219. val = val & ~(state->pdata->sd_config.sd_dac_out[0] << 1);
  220. if (state->pdata && state->pdata->sd_config.sd_dac_out[1])
  221. val = val | (state->pdata->sd_config.sd_dac_out[1] << 2);
  222. else if (state->pdata && !state->pdata->sd_config.sd_dac_out[1])
  223. val = val & ~(state->pdata->sd_config.sd_dac_out[1] << 2);
  224. err = adv7343_write(sd, ADV7343_SD_MODE_REG2, val);
  225. if (err < 0)
  226. goto setoutput_exit;
  227. state->reg82 = val;
  228. /* configure ED/HD Color DAC Swap and ED/HD RGB Input Enable bit to
  229. * zero */
  230. val = state->reg35 & (HD_RGB_INPUT_DI & HD_DAC_SWAP_DI);
  231. err = adv7343_write(sd, ADV7343_HD_MODE_REG6, val);
  232. if (err < 0)
  233. goto setoutput_exit;
  234. state->reg35 = val;
  235. setoutput_exit:
  236. if (err != 0)
  237. v4l2_err(sd, "Error setting output, write failed\n");
  238. return err;
  239. }
  240. static int adv7343_log_status(struct v4l2_subdev *sd)
  241. {
  242. struct adv7343_state *state = to_state(sd);
  243. v4l2_info(sd, "Standard: %llx\n", (unsigned long long)state->std);
  244. v4l2_info(sd, "Output: %s\n", (state->output == 0) ? "Composite" :
  245. ((state->output == 1) ? "Component" : "S-Video"));
  246. return 0;
  247. }
  248. static int adv7343_s_ctrl(struct v4l2_ctrl *ctrl)
  249. {
  250. struct v4l2_subdev *sd = to_sd(ctrl);
  251. switch (ctrl->id) {
  252. case V4L2_CID_BRIGHTNESS:
  253. return adv7343_write(sd, ADV7343_SD_BRIGHTNESS_WSS,
  254. ctrl->val);
  255. case V4L2_CID_HUE:
  256. return adv7343_write(sd, ADV7343_SD_HUE_REG, ctrl->val);
  257. case V4L2_CID_GAIN:
  258. return adv7343_write(sd, ADV7343_DAC2_OUTPUT_LEVEL, ctrl->val);
  259. }
  260. return -EINVAL;
  261. }
  262. static const struct v4l2_ctrl_ops adv7343_ctrl_ops = {
  263. .s_ctrl = adv7343_s_ctrl,
  264. };
  265. static const struct v4l2_subdev_core_ops adv7343_core_ops = {
  266. .log_status = adv7343_log_status,
  267. };
  268. static int adv7343_s_std_output(struct v4l2_subdev *sd, v4l2_std_id std)
  269. {
  270. struct adv7343_state *state = to_state(sd);
  271. int err = 0;
  272. if (state->std == std)
  273. return 0;
  274. err = adv7343_setstd(sd, std);
  275. if (!err)
  276. state->std = std;
  277. return err;
  278. }
  279. static int adv7343_s_routing(struct v4l2_subdev *sd,
  280. u32 input, u32 output, u32 config)
  281. {
  282. struct adv7343_state *state = to_state(sd);
  283. int err = 0;
  284. if (state->output == output)
  285. return 0;
  286. err = adv7343_setoutput(sd, output);
  287. if (!err)
  288. state->output = output;
  289. return err;
  290. }
  291. static const struct v4l2_subdev_video_ops adv7343_video_ops = {
  292. .s_std_output = adv7343_s_std_output,
  293. .s_routing = adv7343_s_routing,
  294. };
  295. static const struct v4l2_subdev_ops adv7343_ops = {
  296. .core = &adv7343_core_ops,
  297. .video = &adv7343_video_ops,
  298. };
  299. static int adv7343_initialize(struct v4l2_subdev *sd)
  300. {
  301. struct adv7343_state *state = to_state(sd);
  302. int err = 0;
  303. int i;
  304. for (i = 0; i < ARRAY_SIZE(adv7343_init_reg_val); i += 2) {
  305. err = adv7343_write(sd, adv7343_init_reg_val[i],
  306. adv7343_init_reg_val[i+1]);
  307. if (err) {
  308. v4l2_err(sd, "Error initializing\n");
  309. return err;
  310. }
  311. }
  312. /* Configure for default video standard */
  313. err = adv7343_setoutput(sd, state->output);
  314. if (err < 0) {
  315. v4l2_err(sd, "Error setting output during init\n");
  316. return -EINVAL;
  317. }
  318. err = adv7343_setstd(sd, state->std);
  319. if (err < 0) {
  320. v4l2_err(sd, "Error setting std during init\n");
  321. return -EINVAL;
  322. }
  323. return err;
  324. }
  325. static struct adv7343_platform_data *
  326. adv7343_get_pdata(struct i2c_client *client)
  327. {
  328. struct adv7343_platform_data *pdata;
  329. struct device_node *np;
  330. if (!IS_ENABLED(CONFIG_OF) || !client->dev.of_node)
  331. return client->dev.platform_data;
  332. np = of_graph_get_next_endpoint(client->dev.of_node, NULL);
  333. if (!np)
  334. return NULL;
  335. pdata = devm_kzalloc(&client->dev, sizeof(*pdata), GFP_KERNEL);
  336. if (!pdata)
  337. goto done;
  338. pdata->mode_config.sleep_mode =
  339. of_property_read_bool(np, "adi,power-mode-sleep-mode");
  340. pdata->mode_config.pll_control =
  341. of_property_read_bool(np, "adi,power-mode-pll-ctrl");
  342. of_property_read_u32_array(np, "adi,dac-enable",
  343. pdata->mode_config.dac, 6);
  344. of_property_read_u32_array(np, "adi,sd-dac-enable",
  345. pdata->sd_config.sd_dac_out, 2);
  346. done:
  347. of_node_put(np);
  348. return pdata;
  349. }
  350. static int adv7343_probe(struct i2c_client *client,
  351. const struct i2c_device_id *id)
  352. {
  353. struct adv7343_state *state;
  354. int err;
  355. if (!i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_BYTE_DATA))
  356. return -ENODEV;
  357. v4l_info(client, "chip found @ 0x%x (%s)\n",
  358. client->addr << 1, client->adapter->name);
  359. state = devm_kzalloc(&client->dev, sizeof(struct adv7343_state),
  360. GFP_KERNEL);
  361. if (state == NULL)
  362. return -ENOMEM;
  363. /* Copy board specific information here */
  364. state->pdata = adv7343_get_pdata(client);
  365. state->reg00 = 0x80;
  366. state->reg01 = 0x00;
  367. state->reg02 = 0x20;
  368. state->reg35 = 0x00;
  369. state->reg80 = ADV7343_SD_MODE_REG1_DEFAULT;
  370. state->reg82 = ADV7343_SD_MODE_REG2_DEFAULT;
  371. state->output = ADV7343_COMPOSITE_ID;
  372. state->std = V4L2_STD_NTSC;
  373. v4l2_i2c_subdev_init(&state->sd, client, &adv7343_ops);
  374. v4l2_ctrl_handler_init(&state->hdl, 2);
  375. v4l2_ctrl_new_std(&state->hdl, &adv7343_ctrl_ops,
  376. V4L2_CID_BRIGHTNESS, ADV7343_BRIGHTNESS_MIN,
  377. ADV7343_BRIGHTNESS_MAX, 1,
  378. ADV7343_BRIGHTNESS_DEF);
  379. v4l2_ctrl_new_std(&state->hdl, &adv7343_ctrl_ops,
  380. V4L2_CID_HUE, ADV7343_HUE_MIN,
  381. ADV7343_HUE_MAX, 1,
  382. ADV7343_HUE_DEF);
  383. v4l2_ctrl_new_std(&state->hdl, &adv7343_ctrl_ops,
  384. V4L2_CID_GAIN, ADV7343_GAIN_MIN,
  385. ADV7343_GAIN_MAX, 1,
  386. ADV7343_GAIN_DEF);
  387. state->sd.ctrl_handler = &state->hdl;
  388. if (state->hdl.error) {
  389. err = state->hdl.error;
  390. goto done;
  391. }
  392. v4l2_ctrl_handler_setup(&state->hdl);
  393. err = adv7343_initialize(&state->sd);
  394. if (err)
  395. goto done;
  396. err = v4l2_async_register_subdev(&state->sd);
  397. done:
  398. if (err < 0)
  399. v4l2_ctrl_handler_free(&state->hdl);
  400. return err;
  401. }
  402. static int adv7343_remove(struct i2c_client *client)
  403. {
  404. struct v4l2_subdev *sd = i2c_get_clientdata(client);
  405. struct adv7343_state *state = to_state(sd);
  406. v4l2_async_unregister_subdev(&state->sd);
  407. v4l2_ctrl_handler_free(&state->hdl);
  408. return 0;
  409. }
  410. static const struct i2c_device_id adv7343_id[] = {
  411. {"adv7343", 0},
  412. {},
  413. };
  414. MODULE_DEVICE_TABLE(i2c, adv7343_id);
  415. #if IS_ENABLED(CONFIG_OF)
  416. static const struct of_device_id adv7343_of_match[] = {
  417. {.compatible = "adi,adv7343", },
  418. { /* sentinel */ },
  419. };
  420. MODULE_DEVICE_TABLE(of, adv7343_of_match);
  421. #endif
  422. static struct i2c_driver adv7343_driver = {
  423. .driver = {
  424. .of_match_table = of_match_ptr(adv7343_of_match),
  425. .name = "adv7343",
  426. },
  427. .probe = adv7343_probe,
  428. .remove = adv7343_remove,
  429. .id_table = adv7343_id,
  430. };
  431. module_i2c_driver(adv7343_driver);