Inicio Explorar Axuda
Rexistro Iniciar sesión
dingyu
/
CooCenter-System-kernel
1
0
Fork 0
Ficheiros Incidencias 0 Pull Requests 0 Wiki
Árbore: e68e7644fa
Ramas Etiquetas
CooCenter-Sy...
/
drivers
/
media
/
i2c
/
tvp5150_reg.h

tvp5150_reg.h 6.4 KB
Histórico Raw

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139 
  1. /*
    2. 

  2.  * tvp5150 - Texas Instruments TVP5150A/AM1 video decoder registers
    3. 

  3.  *
    4. 

  4.  * Copyright (c) 2005,2006 Mauro Carvalho Chehab (mchehab@infradead.org)
    5. 

  5.  * This code is placed under the terms of the GNU General Public License v2
    6. 

  6.  */
    7. 

  7. 

  8. #define TVP5150_VD_IN_SRC_SEL_1      0x00 /* Video input source selection #1 */
    9. 

  9. #define TVP5150_ANAL_CHL_CTL         0x01 /* Analog channel controls */
    10. 

  10. #define TVP5150_OP_MODE_CTL          0x02 /* Operation mode controls */
    11. 

  11. #define TVP5150_MISC_CTL             0x03 /* Miscellaneous controls */
    12. 

  12. #define TVP5150_AUTOSW_MSK           0x04 /* Autoswitch mask: TVP5150A / TVP5150AM */
    13. 

  13. 

  14. /* Reserved 05h */
    15. 

  15. 

  16. #define TVP5150_COLOR_KIL_THSH_CTL   0x06 /* Color killer threshold control */
    17. 

  17. #define TVP5150_LUMA_PROC_CTL_1      0x07 /* Luminance processing control #1 */
    18. 

  18. #define TVP5150_LUMA_PROC_CTL_2      0x08 /* Luminance processing control #2 */
    19. 

  19. #define TVP5150_BRIGHT_CTL           0x09 /* Brightness control */
    20. 

  20. #define TVP5150_SATURATION_CTL       0x0a /* Color saturation control */
    21. 

  21. #define TVP5150_HUE_CTL              0x0b /* Hue control */
    22. 

  22. #define TVP5150_CONTRAST_CTL         0x0c /* Contrast control */
    23. 

  23. #define TVP5150_DATA_RATE_SEL        0x0d /* Outputs and data rates select */
    24. 

  24. #define TVP5150_LUMA_PROC_CTL_3      0x0e /* Luminance processing control #3 */
    25. 

  25. #define TVP5150_CONF_SHARED_PIN      0x0f /* Configuration shared pins */
    26. 

  26. 

  27. /* Reserved 10h */
    28. 

  28. 

  29. #define TVP5150_ACT_VD_CROP_ST_MSB   0x11 /* Active video cropping start MSB */
    30. 

  30. #define TVP5150_ACT_VD_CROP_ST_LSB   0x12 /* Active video cropping start LSB */
    31. 

  31. #define TVP5150_ACT_VD_CROP_STP_MSB  0x13 /* Active video cropping stop MSB */
    32. 

  32. #define TVP5150_ACT_VD_CROP_STP_LSB  0x14 /* Active video cropping stop LSB */
    33. 

  33. #define TVP5150_GENLOCK              0x15 /* Genlock/RTC */
    34. 

  34. #define TVP5150_HORIZ_SYNC_START     0x16 /* Horizontal sync start */
    35. 

  35. 

  36. /* Reserved 17h */
    37. 

  37. 

  38. #define TVP5150_VERT_BLANKING_START 0x18 /* Vertical blanking start */
    39. 

  39. #define TVP5150_VERT_BLANKING_STOP  0x19 /* Vertical blanking stop */
    40. 

  40. #define TVP5150_CHROMA_PROC_CTL_1   0x1a /* Chrominance processing control #1 */
    41. 

  41. #define TVP5150_CHROMA_PROC_CTL_2   0x1b /* Chrominance processing control #2 */
    42. 

  42. #define TVP5150_INT_RESET_REG_B     0x1c /* Interrupt reset register B */
    43. 

  43. #define TVP5150_INT_ENABLE_REG_B    0x1d /* Interrupt enable register B */
    44. 

  44. #define TVP5150_INTT_CONFIG_REG_B   0x1e /* Interrupt configuration register B */
    45. 

  45. 

  46. /* Reserved 1Fh-27h */
    47. 

  47. 

  48. #define VIDEO_STD_MASK			 (0x07 >> 1)
    49. 

  49. #define TVP5150_VIDEO_STD                0x28 /* Video standard */
    50. 

  50. #define VIDEO_STD_AUTO_SWITCH_BIT	 0x00
    51. 

  51. #define VIDEO_STD_NTSC_MJ_BIT		 0x02
    52. 

  52. #define VIDEO_STD_PAL_BDGHIN_BIT	 0x04
    53. 

  53. #define VIDEO_STD_PAL_M_BIT		 0x06
    54. 

  54. #define VIDEO_STD_PAL_COMBINATION_N_BIT	 0x08
    55. 

  55. #define VIDEO_STD_NTSC_4_43_BIT		 0x0a
    56. 

  56. #define VIDEO_STD_SECAM_BIT		 0x0c
    57. 

  57. 

  58. #define VIDEO_STD_NTSC_MJ_BIT_AS                 0x01
    59. 

  59. #define VIDEO_STD_PAL_BDGHIN_BIT_AS              0x03
    60. 

  60. #define VIDEO_STD_PAL_M_BIT_AS		         0x05
    61. 

  61. #define VIDEO_STD_PAL_COMBINATION_N_BIT_AS	 0x07
    62. 

  62. #define VIDEO_STD_NTSC_4_43_BIT_AS		 0x09
    63. 

  63. #define VIDEO_STD_SECAM_BIT_AS		         0x0b
    64. 

  64. 

  65. /* Reserved 29h-2bh */
    66. 

  66. 

  67. #define TVP5150_CB_GAIN_FACT        0x2c /* Cb gain factor */
    68. 

  68. #define TVP5150_CR_GAIN_FACTOR      0x2d /* Cr gain factor */
    69. 

  69. #define TVP5150_MACROVISION_ON_CTR  0x2e /* Macrovision on counter */
    70. 

  70. #define TVP5150_MACROVISION_OFF_CTR 0x2f /* Macrovision off counter */
    71. 

  71. #define TVP5150_REV_SELECT          0x30 /* revision select (TVP5150AM1 only) */
    72. 

  72. 

  73. /* Reserved	31h-7Fh */
    74. 

  74. 

  75. #define TVP5150_MSB_DEV_ID          0x80 /* MSB of device ID */
    76. 

  76. #define TVP5150_LSB_DEV_ID          0x81 /* LSB of device ID */
    77. 

  77. #define TVP5150_ROM_MAJOR_VER       0x82 /* ROM major version */
    78. 

  78. #define TVP5150_ROM_MINOR_VER       0x83 /* ROM minor version */
    79. 

  79. #define TVP5150_VERT_LN_COUNT_MSB   0x84 /* Vertical line count MSB */
    80. 

  80. #define TVP5150_VERT_LN_COUNT_LSB   0x85 /* Vertical line count LSB */
    81. 

  81. #define TVP5150_INT_STATUS_REG_B    0x86 /* Interrupt status register B */
    82. 

  82. #define TVP5150_INT_ACTIVE_REG_B    0x87 /* Interrupt active register B */
    83. 

  83. #define TVP5150_STATUS_REG_1        0x88 /* Status register #1 */
    84. 

  84. #define TVP5150_STATUS_REG_2        0x89 /* Status register #2 */
    85. 

  85. #define TVP5150_STATUS_REG_3        0x8a /* Status register #3 */
    86. 

  86. #define TVP5150_STATUS_REG_4        0x8b /* Status register #4 */
    87. 

  87. #define TVP5150_STATUS_REG_5        0x8c /* Status register #5 */
    88. 

  88. /* Reserved	8Dh-8Fh */
    89. 

  89.  /* Closed caption data registers */
    90. 

  90. #define TVP5150_CC_DATA_INI         0x90
    91. 

  91. #define TVP5150_CC_DATA_END         0x93
    92. 

  92. 

  93.  /* WSS data registers */
    94. 

  94. #define TVP5150_WSS_DATA_INI        0x94
    95. 

  95. #define TVP5150_WSS_DATA_END        0x99
    96. 

  96. 

  97. /* VPS data registers */
    98. 

  98. #define TVP5150_VPS_DATA_INI        0x9a
    99. 

  99. #define TVP5150_VPS_DATA_END        0xa6
    100. 

  100. 

  101. /* VITC data registers */
    102. 

  102. #define TVP5150_VITC_DATA_INI       0xa7
    103. 

  103. #define TVP5150_VITC_DATA_END       0xaf
    104. 

  104. 

  105. #define TVP5150_VBI_FIFO_READ_DATA  0xb0 /* VBI FIFO read data */
    106. 

  106. 

  107. /* Teletext filter 1 */
    108. 

  108. #define TVP5150_TELETEXT_FIL1_INI  0xb1
    109. 

  109. #define TVP5150_TELETEXT_FIL1_END  0xb5
    110. 

  110. 

  111. /* Teletext filter 2 */
    112. 

  112. #define TVP5150_TELETEXT_FIL2_INI  0xb6
    113. 

  113. #define TVP5150_TELETEXT_FIL2_END  0xba
    114. 

  114. 

  115. #define TVP5150_TELETEXT_FIL_ENA    0xbb /* Teletext filter enable */
    116. 

  116. /* Reserved	BCh-BFh */
    117. 

  117. #define TVP5150_INT_STATUS_REG_A    0xc0 /* Interrupt status register A */
    118. 

  118. #define TVP5150_INT_ENABLE_REG_A    0xc1 /* Interrupt enable register A */
    119. 

  119. #define TVP5150_INT_CONF            0xc2 /* Interrupt configuration */
    120. 

  120. #define TVP5150_VDP_CONF_RAM_DATA   0xc3 /* VDP configuration RAM data */
    121. 

  121. #define TVP5150_CONF_RAM_ADDR_LOW   0xc4 /* Configuration RAM address low byte */
    122. 

  122. #define TVP5150_CONF_RAM_ADDR_HIGH  0xc5 /* Configuration RAM address high byte */
    123. 

  123. #define TVP5150_VDP_STATUS_REG      0xc6 /* VDP status register */
    124. 

  124. #define TVP5150_FIFO_WORD_COUNT     0xc7 /* FIFO word count */
    125. 

  125. #define TVP5150_FIFO_INT_THRESHOLD  0xc8 /* FIFO interrupt threshold */
    126. 

  126. #define TVP5150_FIFO_RESET          0xc9 /* FIFO reset */
    127. 

  127. #define TVP5150_LINE_NUMBER_INT     0xca /* Line number interrupt */
    128. 

  128. #define TVP5150_PIX_ALIGN_REG_LOW   0xcb /* Pixel alignment register low byte */
    129. 

  129. #define TVP5150_PIX_ALIGN_REG_HIGH  0xcc /* Pixel alignment register high byte */
    130. 

  130. #define TVP5150_FIFO_OUT_CTRL       0xcd /* FIFO output control */
    131. 

  131. /* Reserved	CEh */
    132. 

  132. #define TVP5150_FULL_FIELD_ENA      0xcf /* Full field enable 1 */
    133. 

  133. 

  134. /* Line mode registers */
    135. 

  135. #define TVP5150_LINE_MODE_INI       0xd0
    136. 

  136. #define TVP5150_LINE_MODE_END       0xfb
    137. 

  137. 

  138. #define TVP5150_FULL_FIELD_MODE_REG 0xfc /* Full field mode register */
    139. 

  139. /* Reserved	FDh-FFh */
    140.