coda-bit.c 59 KB

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  1. /*
  2. * Coda multi-standard codec IP - BIT processor functions
  3. *
  4. * Copyright (C) 2012 Vista Silicon S.L.
  5. * Javier Martin, <javier.martin@vista-silicon.com>
  6. * Xavier Duret
  7. * Copyright (C) 2012-2014 Philipp Zabel, Pengutronix
  8. *
  9. * This program is free software; you can redistribute it and/or modify
  10. * it under the terms of the GNU General Public License as published by
  11. * the Free Software Foundation; either version 2 of the License, or
  12. * (at your option) any later version.
  13. */
  14. #include <linux/clk.h>
  15. #include <linux/irqreturn.h>
  16. #include <linux/kernel.h>
  17. #include <linux/log2.h>
  18. #include <linux/platform_device.h>
  19. #include <linux/reset.h>
  20. #include <linux/slab.h>
  21. #include <linux/videodev2.h>
  22. #include <media/v4l2-common.h>
  23. #include <media/v4l2-ctrls.h>
  24. #include <media/v4l2-fh.h>
  25. #include <media/v4l2-mem2mem.h>
  26. #include <media/videobuf2-v4l2.h>
  27. #include <media/videobuf2-dma-contig.h>
  28. #include <media/videobuf2-vmalloc.h>
  29. #include "coda.h"
  30. #define CREATE_TRACE_POINTS
  31. #include "trace.h"
  32. #define CODA_PARA_BUF_SIZE (10 * 1024)
  33. #define CODA7_PS_BUF_SIZE 0x28000
  34. #define CODA9_PS_SAVE_SIZE (512 * 1024)
  35. #define CODA_DEFAULT_GAMMA 4096
  36. #define CODA9_DEFAULT_GAMMA 24576 /* 0.75 * 32768 */
  37. static void coda_free_bitstream_buffer(struct coda_ctx *ctx);
  38. static inline int coda_is_initialized(struct coda_dev *dev)
  39. {
  40. return coda_read(dev, CODA_REG_BIT_CUR_PC) != 0;
  41. }
  42. static inline unsigned long coda_isbusy(struct coda_dev *dev)
  43. {
  44. return coda_read(dev, CODA_REG_BIT_BUSY);
  45. }
  46. static int coda_wait_timeout(struct coda_dev *dev)
  47. {
  48. unsigned long timeout = jiffies + msecs_to_jiffies(1000);
  49. while (coda_isbusy(dev)) {
  50. if (time_after(jiffies, timeout))
  51. return -ETIMEDOUT;
  52. }
  53. return 0;
  54. }
  55. static void coda_command_async(struct coda_ctx *ctx, int cmd)
  56. {
  57. struct coda_dev *dev = ctx->dev;
  58. if (dev->devtype->product == CODA_960 ||
  59. dev->devtype->product == CODA_7541) {
  60. /* Restore context related registers to CODA */
  61. coda_write(dev, ctx->bit_stream_param,
  62. CODA_REG_BIT_BIT_STREAM_PARAM);
  63. coda_write(dev, ctx->frm_dis_flg,
  64. CODA_REG_BIT_FRM_DIS_FLG(ctx->reg_idx));
  65. coda_write(dev, ctx->frame_mem_ctrl,
  66. CODA_REG_BIT_FRAME_MEM_CTRL);
  67. coda_write(dev, ctx->workbuf.paddr, CODA_REG_BIT_WORK_BUF_ADDR);
  68. }
  69. if (dev->devtype->product == CODA_960) {
  70. coda_write(dev, 1, CODA9_GDI_WPROT_ERR_CLR);
  71. coda_write(dev, 0, CODA9_GDI_WPROT_RGN_EN);
  72. }
  73. coda_write(dev, CODA_REG_BIT_BUSY_FLAG, CODA_REG_BIT_BUSY);
  74. coda_write(dev, ctx->idx, CODA_REG_BIT_RUN_INDEX);
  75. coda_write(dev, ctx->params.codec_mode, CODA_REG_BIT_RUN_COD_STD);
  76. coda_write(dev, ctx->params.codec_mode_aux, CODA7_REG_BIT_RUN_AUX_STD);
  77. trace_coda_bit_run(ctx, cmd);
  78. coda_write(dev, cmd, CODA_REG_BIT_RUN_COMMAND);
  79. }
  80. static int coda_command_sync(struct coda_ctx *ctx, int cmd)
  81. {
  82. struct coda_dev *dev = ctx->dev;
  83. int ret;
  84. coda_command_async(ctx, cmd);
  85. ret = coda_wait_timeout(dev);
  86. trace_coda_bit_done(ctx);
  87. return ret;
  88. }
  89. int coda_hw_reset(struct coda_ctx *ctx)
  90. {
  91. struct coda_dev *dev = ctx->dev;
  92. unsigned long timeout;
  93. unsigned int idx;
  94. int ret;
  95. if (!dev->rstc)
  96. return -ENOENT;
  97. idx = coda_read(dev, CODA_REG_BIT_RUN_INDEX);
  98. if (dev->devtype->product == CODA_960) {
  99. timeout = jiffies + msecs_to_jiffies(100);
  100. coda_write(dev, 0x11, CODA9_GDI_BUS_CTRL);
  101. while (coda_read(dev, CODA9_GDI_BUS_STATUS) != 0x77) {
  102. if (time_after(jiffies, timeout))
  103. return -ETIME;
  104. cpu_relax();
  105. }
  106. }
  107. ret = reset_control_reset(dev->rstc);
  108. if (ret < 0)
  109. return ret;
  110. if (dev->devtype->product == CODA_960)
  111. coda_write(dev, 0x00, CODA9_GDI_BUS_CTRL);
  112. coda_write(dev, CODA_REG_BIT_BUSY_FLAG, CODA_REG_BIT_BUSY);
  113. coda_write(dev, CODA_REG_RUN_ENABLE, CODA_REG_BIT_CODE_RUN);
  114. ret = coda_wait_timeout(dev);
  115. coda_write(dev, idx, CODA_REG_BIT_RUN_INDEX);
  116. return ret;
  117. }
  118. static void coda_kfifo_sync_from_device(struct coda_ctx *ctx)
  119. {
  120. struct __kfifo *kfifo = &ctx->bitstream_fifo.kfifo;
  121. struct coda_dev *dev = ctx->dev;
  122. u32 rd_ptr;
  123. rd_ptr = coda_read(dev, CODA_REG_BIT_RD_PTR(ctx->reg_idx));
  124. kfifo->out = (kfifo->in & ~kfifo->mask) |
  125. (rd_ptr - ctx->bitstream.paddr);
  126. if (kfifo->out > kfifo->in)
  127. kfifo->out -= kfifo->mask + 1;
  128. }
  129. static void coda_kfifo_sync_to_device_full(struct coda_ctx *ctx)
  130. {
  131. struct __kfifo *kfifo = &ctx->bitstream_fifo.kfifo;
  132. struct coda_dev *dev = ctx->dev;
  133. u32 rd_ptr, wr_ptr;
  134. rd_ptr = ctx->bitstream.paddr + (kfifo->out & kfifo->mask);
  135. coda_write(dev, rd_ptr, CODA_REG_BIT_RD_PTR(ctx->reg_idx));
  136. wr_ptr = ctx->bitstream.paddr + (kfifo->in & kfifo->mask);
  137. coda_write(dev, wr_ptr, CODA_REG_BIT_WR_PTR(ctx->reg_idx));
  138. }
  139. static void coda_kfifo_sync_to_device_write(struct coda_ctx *ctx)
  140. {
  141. struct __kfifo *kfifo = &ctx->bitstream_fifo.kfifo;
  142. struct coda_dev *dev = ctx->dev;
  143. u32 wr_ptr;
  144. wr_ptr = ctx->bitstream.paddr + (kfifo->in & kfifo->mask);
  145. coda_write(dev, wr_ptr, CODA_REG_BIT_WR_PTR(ctx->reg_idx));
  146. }
  147. static int coda_bitstream_queue(struct coda_ctx *ctx,
  148. struct vb2_v4l2_buffer *src_buf)
  149. {
  150. u32 src_size = vb2_get_plane_payload(&src_buf->vb2_buf, 0);
  151. u32 n;
  152. n = kfifo_in(&ctx->bitstream_fifo,
  153. vb2_plane_vaddr(&src_buf->vb2_buf, 0), src_size);
  154. if (n < src_size)
  155. return -ENOSPC;
  156. src_buf->sequence = ctx->qsequence++;
  157. return 0;
  158. }
  159. static bool coda_bitstream_try_queue(struct coda_ctx *ctx,
  160. struct vb2_v4l2_buffer *src_buf)
  161. {
  162. int ret;
  163. if (coda_get_bitstream_payload(ctx) +
  164. vb2_get_plane_payload(&src_buf->vb2_buf, 0) + 512 >=
  165. ctx->bitstream.size)
  166. return false;
  167. if (vb2_plane_vaddr(&src_buf->vb2_buf, 0) == NULL) {
  168. v4l2_err(&ctx->dev->v4l2_dev, "trying to queue empty buffer\n");
  169. return true;
  170. }
  171. ret = coda_bitstream_queue(ctx, src_buf);
  172. if (ret < 0) {
  173. v4l2_err(&ctx->dev->v4l2_dev, "bitstream buffer overflow\n");
  174. return false;
  175. }
  176. /* Sync read pointer to device */
  177. if (ctx == v4l2_m2m_get_curr_priv(ctx->dev->m2m_dev))
  178. coda_kfifo_sync_to_device_write(ctx);
  179. ctx->hold = false;
  180. return true;
  181. }
  182. void coda_fill_bitstream(struct coda_ctx *ctx, bool streaming)
  183. {
  184. struct vb2_v4l2_buffer *src_buf;
  185. struct coda_buffer_meta *meta;
  186. unsigned long flags;
  187. u32 start;
  188. if (ctx->bit_stream_param & CODA_BIT_STREAM_END_FLAG)
  189. return;
  190. while (v4l2_m2m_num_src_bufs_ready(ctx->fh.m2m_ctx) > 0) {
  191. /*
  192. * Only queue a single JPEG into the bitstream buffer, except
  193. * to increase payload over 512 bytes or if in hold state.
  194. */
  195. if (ctx->codec->src_fourcc == V4L2_PIX_FMT_JPEG &&
  196. (coda_get_bitstream_payload(ctx) >= 512) && !ctx->hold)
  197. break;
  198. src_buf = v4l2_m2m_next_src_buf(ctx->fh.m2m_ctx);
  199. /* Drop frames that do not start/end with a SOI/EOI markers */
  200. if (ctx->codec->src_fourcc == V4L2_PIX_FMT_JPEG &&
  201. !coda_jpeg_check_buffer(ctx, src_buf)) {
  202. v4l2_err(&ctx->dev->v4l2_dev,
  203. "dropping invalid JPEG frame %d\n",
  204. ctx->qsequence);
  205. src_buf = v4l2_m2m_src_buf_remove(ctx->fh.m2m_ctx);
  206. v4l2_m2m_buf_done(src_buf, streaming ?
  207. VB2_BUF_STATE_ERROR :
  208. VB2_BUF_STATE_QUEUED);
  209. continue;
  210. }
  211. /* Dump empty buffers */
  212. if (!vb2_get_plane_payload(&src_buf->vb2_buf, 0)) {
  213. src_buf = v4l2_m2m_src_buf_remove(ctx->fh.m2m_ctx);
  214. v4l2_m2m_buf_done(src_buf, VB2_BUF_STATE_DONE);
  215. continue;
  216. }
  217. /* Buffer start position */
  218. start = ctx->bitstream_fifo.kfifo.in &
  219. ctx->bitstream_fifo.kfifo.mask;
  220. if (coda_bitstream_try_queue(ctx, src_buf)) {
  221. /*
  222. * Source buffer is queued in the bitstream ringbuffer;
  223. * queue the timestamp and mark source buffer as done
  224. */
  225. src_buf = v4l2_m2m_src_buf_remove(ctx->fh.m2m_ctx);
  226. meta = kmalloc(sizeof(*meta), GFP_KERNEL);
  227. if (meta) {
  228. meta->sequence = src_buf->sequence;
  229. meta->timecode = src_buf->timecode;
  230. meta->timestamp = src_buf->timestamp;
  231. meta->start = start;
  232. meta->end = ctx->bitstream_fifo.kfifo.in &
  233. ctx->bitstream_fifo.kfifo.mask;
  234. spin_lock_irqsave(&ctx->buffer_meta_lock,
  235. flags);
  236. list_add_tail(&meta->list,
  237. &ctx->buffer_meta_list);
  238. ctx->num_metas++;
  239. spin_unlock_irqrestore(&ctx->buffer_meta_lock,
  240. flags);
  241. trace_coda_bit_queue(ctx, src_buf, meta);
  242. }
  243. v4l2_m2m_buf_done(src_buf, VB2_BUF_STATE_DONE);
  244. } else {
  245. break;
  246. }
  247. }
  248. }
  249. void coda_bit_stream_end_flag(struct coda_ctx *ctx)
  250. {
  251. struct coda_dev *dev = ctx->dev;
  252. ctx->bit_stream_param |= CODA_BIT_STREAM_END_FLAG;
  253. /* If this context is currently running, update the hardware flag */
  254. if ((dev->devtype->product == CODA_960) &&
  255. coda_isbusy(dev) &&
  256. (ctx->idx == coda_read(dev, CODA_REG_BIT_RUN_INDEX))) {
  257. coda_write(dev, ctx->bit_stream_param,
  258. CODA_REG_BIT_BIT_STREAM_PARAM);
  259. }
  260. }
  261. static void coda_parabuf_write(struct coda_ctx *ctx, int index, u32 value)
  262. {
  263. struct coda_dev *dev = ctx->dev;
  264. u32 *p = ctx->parabuf.vaddr;
  265. if (dev->devtype->product == CODA_DX6)
  266. p[index] = value;
  267. else
  268. p[index ^ 1] = value;
  269. }
  270. static inline int coda_alloc_context_buf(struct coda_ctx *ctx,
  271. struct coda_aux_buf *buf, size_t size,
  272. const char *name)
  273. {
  274. return coda_alloc_aux_buf(ctx->dev, buf, size, name, ctx->debugfs_entry);
  275. }
  276. static void coda_free_framebuffers(struct coda_ctx *ctx)
  277. {
  278. int i;
  279. for (i = 0; i < CODA_MAX_FRAMEBUFFERS; i++)
  280. coda_free_aux_buf(ctx->dev, &ctx->internal_frames[i]);
  281. }
  282. static int coda_alloc_framebuffers(struct coda_ctx *ctx,
  283. struct coda_q_data *q_data, u32 fourcc)
  284. {
  285. struct coda_dev *dev = ctx->dev;
  286. int width, height;
  287. int ysize;
  288. int ret;
  289. int i;
  290. if (ctx->codec && (ctx->codec->src_fourcc == V4L2_PIX_FMT_H264 ||
  291. ctx->codec->dst_fourcc == V4L2_PIX_FMT_H264)) {
  292. width = round_up(q_data->width, 16);
  293. height = round_up(q_data->height, 16);
  294. } else {
  295. width = round_up(q_data->width, 8);
  296. height = q_data->height;
  297. }
  298. ysize = width * height;
  299. /* Allocate frame buffers */
  300. for (i = 0; i < ctx->num_internal_frames; i++) {
  301. size_t size;
  302. char *name;
  303. if (ctx->tiled_map_type == GDI_TILED_FRAME_MB_RASTER_MAP)
  304. size = round_up(ysize, 4096) + ysize / 2;
  305. else
  306. size = ysize + ysize / 2;
  307. if (ctx->codec->src_fourcc == V4L2_PIX_FMT_H264 &&
  308. dev->devtype->product != CODA_DX6)
  309. size += ysize / 4;
  310. name = kasprintf(GFP_KERNEL, "fb%d", i);
  311. ret = coda_alloc_context_buf(ctx, &ctx->internal_frames[i],
  312. size, name);
  313. kfree(name);
  314. if (ret < 0) {
  315. coda_free_framebuffers(ctx);
  316. return ret;
  317. }
  318. }
  319. /* Register frame buffers in the parameter buffer */
  320. for (i = 0; i < ctx->num_internal_frames; i++) {
  321. u32 y, cb, cr;
  322. /* Start addresses of Y, Cb, Cr planes */
  323. y = ctx->internal_frames[i].paddr;
  324. cb = y + ysize;
  325. cr = y + ysize + ysize/4;
  326. if (ctx->tiled_map_type == GDI_TILED_FRAME_MB_RASTER_MAP) {
  327. cb = round_up(cb, 4096);
  328. cr = 0;
  329. /* Packed 20-bit MSB of base addresses */
  330. /* YYYYYCCC, CCyyyyyc, cccc.... */
  331. y = (y & 0xfffff000) | cb >> 20;
  332. cb = (cb & 0x000ff000) << 12;
  333. }
  334. coda_parabuf_write(ctx, i * 3 + 0, y);
  335. coda_parabuf_write(ctx, i * 3 + 1, cb);
  336. coda_parabuf_write(ctx, i * 3 + 2, cr);
  337. /* mvcol buffer for h.264 */
  338. if (ctx->codec->src_fourcc == V4L2_PIX_FMT_H264 &&
  339. dev->devtype->product != CODA_DX6)
  340. coda_parabuf_write(ctx, 96 + i,
  341. ctx->internal_frames[i].paddr +
  342. ysize + ysize/4 + ysize/4);
  343. }
  344. /* mvcol buffer for mpeg4 */
  345. if ((dev->devtype->product != CODA_DX6) &&
  346. (ctx->codec->src_fourcc == V4L2_PIX_FMT_MPEG4))
  347. coda_parabuf_write(ctx, 97, ctx->internal_frames[0].paddr +
  348. ysize + ysize/4 + ysize/4);
  349. return 0;
  350. }
  351. static void coda_free_context_buffers(struct coda_ctx *ctx)
  352. {
  353. struct coda_dev *dev = ctx->dev;
  354. coda_free_aux_buf(dev, &ctx->slicebuf);
  355. coda_free_aux_buf(dev, &ctx->psbuf);
  356. if (dev->devtype->product != CODA_DX6)
  357. coda_free_aux_buf(dev, &ctx->workbuf);
  358. coda_free_aux_buf(dev, &ctx->parabuf);
  359. }
  360. static int coda_alloc_context_buffers(struct coda_ctx *ctx,
  361. struct coda_q_data *q_data)
  362. {
  363. struct coda_dev *dev = ctx->dev;
  364. size_t size;
  365. int ret;
  366. if (!ctx->parabuf.vaddr) {
  367. ret = coda_alloc_context_buf(ctx, &ctx->parabuf,
  368. CODA_PARA_BUF_SIZE, "parabuf");
  369. if (ret < 0)
  370. return ret;
  371. }
  372. if (dev->devtype->product == CODA_DX6)
  373. return 0;
  374. if (!ctx->slicebuf.vaddr && q_data->fourcc == V4L2_PIX_FMT_H264) {
  375. /* worst case slice size */
  376. size = (DIV_ROUND_UP(q_data->width, 16) *
  377. DIV_ROUND_UP(q_data->height, 16)) * 3200 / 8 + 512;
  378. ret = coda_alloc_context_buf(ctx, &ctx->slicebuf, size,
  379. "slicebuf");
  380. if (ret < 0)
  381. goto err;
  382. }
  383. if (!ctx->psbuf.vaddr && dev->devtype->product == CODA_7541) {
  384. ret = coda_alloc_context_buf(ctx, &ctx->psbuf,
  385. CODA7_PS_BUF_SIZE, "psbuf");
  386. if (ret < 0)
  387. goto err;
  388. }
  389. if (!ctx->workbuf.vaddr) {
  390. size = dev->devtype->workbuf_size;
  391. if (dev->devtype->product == CODA_960 &&
  392. q_data->fourcc == V4L2_PIX_FMT_H264)
  393. size += CODA9_PS_SAVE_SIZE;
  394. ret = coda_alloc_context_buf(ctx, &ctx->workbuf, size,
  395. "workbuf");
  396. if (ret < 0)
  397. goto err;
  398. }
  399. return 0;
  400. err:
  401. coda_free_context_buffers(ctx);
  402. return ret;
  403. }
  404. static int coda_encode_header(struct coda_ctx *ctx, struct vb2_v4l2_buffer *buf,
  405. int header_code, u8 *header, int *size)
  406. {
  407. struct vb2_buffer *vb = &buf->vb2_buf;
  408. struct coda_dev *dev = ctx->dev;
  409. size_t bufsize;
  410. int ret;
  411. int i;
  412. if (dev->devtype->product == CODA_960)
  413. memset(vb2_plane_vaddr(vb, 0), 0, 64);
  414. coda_write(dev, vb2_dma_contig_plane_dma_addr(vb, 0),
  415. CODA_CMD_ENC_HEADER_BB_START);
  416. bufsize = vb2_plane_size(vb, 0);
  417. if (dev->devtype->product == CODA_960)
  418. bufsize /= 1024;
  419. coda_write(dev, bufsize, CODA_CMD_ENC_HEADER_BB_SIZE);
  420. coda_write(dev, header_code, CODA_CMD_ENC_HEADER_CODE);
  421. ret = coda_command_sync(ctx, CODA_COMMAND_ENCODE_HEADER);
  422. if (ret < 0) {
  423. v4l2_err(&dev->v4l2_dev, "CODA_COMMAND_ENCODE_HEADER timeout\n");
  424. return ret;
  425. }
  426. if (dev->devtype->product == CODA_960) {
  427. for (i = 63; i > 0; i--)
  428. if (((char *)vb2_plane_vaddr(vb, 0))[i] != 0)
  429. break;
  430. *size = i + 1;
  431. } else {
  432. *size = coda_read(dev, CODA_REG_BIT_WR_PTR(ctx->reg_idx)) -
  433. coda_read(dev, CODA_CMD_ENC_HEADER_BB_START);
  434. }
  435. memcpy(header, vb2_plane_vaddr(vb, 0), *size);
  436. return 0;
  437. }
  438. static phys_addr_t coda_iram_alloc(struct coda_iram_info *iram, size_t size)
  439. {
  440. phys_addr_t ret;
  441. size = round_up(size, 1024);
  442. if (size > iram->remaining)
  443. return 0;
  444. iram->remaining -= size;
  445. ret = iram->next_paddr;
  446. iram->next_paddr += size;
  447. return ret;
  448. }
  449. static void coda_setup_iram(struct coda_ctx *ctx)
  450. {
  451. struct coda_iram_info *iram_info = &ctx->iram_info;
  452. struct coda_dev *dev = ctx->dev;
  453. int w64, w128;
  454. int mb_width;
  455. int dbk_bits;
  456. int bit_bits;
  457. int ip_bits;
  458. memset(iram_info, 0, sizeof(*iram_info));
  459. iram_info->next_paddr = dev->iram.paddr;
  460. iram_info->remaining = dev->iram.size;
  461. if (!dev->iram.vaddr)
  462. return;
  463. switch (dev->devtype->product) {
  464. case CODA_7541:
  465. dbk_bits = CODA7_USE_HOST_DBK_ENABLE | CODA7_USE_DBK_ENABLE;
  466. bit_bits = CODA7_USE_HOST_BIT_ENABLE | CODA7_USE_BIT_ENABLE;
  467. ip_bits = CODA7_USE_HOST_IP_ENABLE | CODA7_USE_IP_ENABLE;
  468. break;
  469. case CODA_960:
  470. dbk_bits = CODA9_USE_HOST_DBK_ENABLE | CODA9_USE_DBK_ENABLE;
  471. bit_bits = CODA9_USE_HOST_BIT_ENABLE | CODA7_USE_BIT_ENABLE;
  472. ip_bits = CODA9_USE_HOST_IP_ENABLE | CODA7_USE_IP_ENABLE;
  473. break;
  474. default: /* CODA_DX6 */
  475. return;
  476. }
  477. if (ctx->inst_type == CODA_INST_ENCODER) {
  478. struct coda_q_data *q_data_src;
  479. q_data_src = get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_OUTPUT);
  480. mb_width = DIV_ROUND_UP(q_data_src->width, 16);
  481. w128 = mb_width * 128;
  482. w64 = mb_width * 64;
  483. /* Prioritize in case IRAM is too small for everything */
  484. if (dev->devtype->product == CODA_7541) {
  485. iram_info->search_ram_size = round_up(mb_width * 16 *
  486. 36 + 2048, 1024);
  487. iram_info->search_ram_paddr = coda_iram_alloc(iram_info,
  488. iram_info->search_ram_size);
  489. if (!iram_info->search_ram_paddr) {
  490. pr_err("IRAM is smaller than the search ram size\n");
  491. goto out;
  492. }
  493. iram_info->axi_sram_use |= CODA7_USE_HOST_ME_ENABLE |
  494. CODA7_USE_ME_ENABLE;
  495. }
  496. /* Only H.264BP and H.263P3 are considered */
  497. iram_info->buf_dbk_y_use = coda_iram_alloc(iram_info, w64);
  498. iram_info->buf_dbk_c_use = coda_iram_alloc(iram_info, w64);
  499. if (!iram_info->buf_dbk_c_use)
  500. goto out;
  501. iram_info->axi_sram_use |= dbk_bits;
  502. iram_info->buf_bit_use = coda_iram_alloc(iram_info, w128);
  503. if (!iram_info->buf_bit_use)
  504. goto out;
  505. iram_info->axi_sram_use |= bit_bits;
  506. iram_info->buf_ip_ac_dc_use = coda_iram_alloc(iram_info, w128);
  507. if (!iram_info->buf_ip_ac_dc_use)
  508. goto out;
  509. iram_info->axi_sram_use |= ip_bits;
  510. /* OVL and BTP disabled for encoder */
  511. } else if (ctx->inst_type == CODA_INST_DECODER) {
  512. struct coda_q_data *q_data_dst;
  513. q_data_dst = get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_CAPTURE);
  514. mb_width = DIV_ROUND_UP(q_data_dst->width, 16);
  515. w128 = mb_width * 128;
  516. iram_info->buf_dbk_y_use = coda_iram_alloc(iram_info, w128);
  517. iram_info->buf_dbk_c_use = coda_iram_alloc(iram_info, w128);
  518. if (!iram_info->buf_dbk_c_use)
  519. goto out;
  520. iram_info->axi_sram_use |= dbk_bits;
  521. iram_info->buf_bit_use = coda_iram_alloc(iram_info, w128);
  522. if (!iram_info->buf_bit_use)
  523. goto out;
  524. iram_info->axi_sram_use |= bit_bits;
  525. iram_info->buf_ip_ac_dc_use = coda_iram_alloc(iram_info, w128);
  526. if (!iram_info->buf_ip_ac_dc_use)
  527. goto out;
  528. iram_info->axi_sram_use |= ip_bits;
  529. /* OVL and BTP unused as there is no VC1 support yet */
  530. }
  531. out:
  532. if (!(iram_info->axi_sram_use & CODA7_USE_HOST_IP_ENABLE))
  533. v4l2_dbg(1, coda_debug, &ctx->dev->v4l2_dev,
  534. "IRAM smaller than needed\n");
  535. if (dev->devtype->product == CODA_7541) {
  536. /* TODO - Enabling these causes picture errors on CODA7541 */
  537. if (ctx->inst_type == CODA_INST_DECODER) {
  538. /* fw 1.4.50 */
  539. iram_info->axi_sram_use &= ~(CODA7_USE_HOST_IP_ENABLE |
  540. CODA7_USE_IP_ENABLE);
  541. } else {
  542. /* fw 13.4.29 */
  543. iram_info->axi_sram_use &= ~(CODA7_USE_HOST_IP_ENABLE |
  544. CODA7_USE_HOST_DBK_ENABLE |
  545. CODA7_USE_IP_ENABLE |
  546. CODA7_USE_DBK_ENABLE);
  547. }
  548. }
  549. }
  550. static u32 coda_supported_firmwares[] = {
  551. CODA_FIRMWARE_VERNUM(CODA_DX6, 2, 2, 5),
  552. CODA_FIRMWARE_VERNUM(CODA_7541, 1, 4, 50),
  553. CODA_FIRMWARE_VERNUM(CODA_960, 2, 1, 5),
  554. };
  555. static bool coda_firmware_supported(u32 vernum)
  556. {
  557. int i;
  558. for (i = 0; i < ARRAY_SIZE(coda_supported_firmwares); i++)
  559. if (vernum == coda_supported_firmwares[i])
  560. return true;
  561. return false;
  562. }
  563. int coda_check_firmware(struct coda_dev *dev)
  564. {
  565. u16 product, major, minor, release;
  566. u32 data;
  567. int ret;
  568. ret = clk_prepare_enable(dev->clk_per);
  569. if (ret)
  570. goto err_clk_per;
  571. ret = clk_prepare_enable(dev->clk_ahb);
  572. if (ret)
  573. goto err_clk_ahb;
  574. coda_write(dev, 0, CODA_CMD_FIRMWARE_VERNUM);
  575. coda_write(dev, CODA_REG_BIT_BUSY_FLAG, CODA_REG_BIT_BUSY);
  576. coda_write(dev, 0, CODA_REG_BIT_RUN_INDEX);
  577. coda_write(dev, 0, CODA_REG_BIT_RUN_COD_STD);
  578. coda_write(dev, CODA_COMMAND_FIRMWARE_GET, CODA_REG_BIT_RUN_COMMAND);
  579. if (coda_wait_timeout(dev)) {
  580. v4l2_err(&dev->v4l2_dev, "firmware get command error\n");
  581. ret = -EIO;
  582. goto err_run_cmd;
  583. }
  584. if (dev->devtype->product == CODA_960) {
  585. data = coda_read(dev, CODA9_CMD_FIRMWARE_CODE_REV);
  586. v4l2_info(&dev->v4l2_dev, "Firmware code revision: %d\n",
  587. data);
  588. }
  589. /* Check we are compatible with the loaded firmware */
  590. data = coda_read(dev, CODA_CMD_FIRMWARE_VERNUM);
  591. product = CODA_FIRMWARE_PRODUCT(data);
  592. major = CODA_FIRMWARE_MAJOR(data);
  593. minor = CODA_FIRMWARE_MINOR(data);
  594. release = CODA_FIRMWARE_RELEASE(data);
  595. clk_disable_unprepare(dev->clk_per);
  596. clk_disable_unprepare(dev->clk_ahb);
  597. if (product != dev->devtype->product) {
  598. v4l2_err(&dev->v4l2_dev,
  599. "Wrong firmware. Hw: %s, Fw: %s, Version: %u.%u.%u\n",
  600. coda_product_name(dev->devtype->product),
  601. coda_product_name(product), major, minor, release);
  602. return -EINVAL;
  603. }
  604. v4l2_info(&dev->v4l2_dev, "Initialized %s.\n",
  605. coda_product_name(product));
  606. if (coda_firmware_supported(data)) {
  607. v4l2_info(&dev->v4l2_dev, "Firmware version: %u.%u.%u\n",
  608. major, minor, release);
  609. } else {
  610. v4l2_warn(&dev->v4l2_dev,
  611. "Unsupported firmware version: %u.%u.%u\n",
  612. major, minor, release);
  613. }
  614. return 0;
  615. err_run_cmd:
  616. clk_disable_unprepare(dev->clk_ahb);
  617. err_clk_ahb:
  618. clk_disable_unprepare(dev->clk_per);
  619. err_clk_per:
  620. return ret;
  621. }
  622. static void coda9_set_frame_cache(struct coda_ctx *ctx, u32 fourcc)
  623. {
  624. u32 cache_size, cache_config;
  625. if (ctx->tiled_map_type == GDI_LINEAR_FRAME_MAP) {
  626. /* Luma 2x0 page, 2x6 cache, chroma 2x0 page, 2x4 cache size */
  627. cache_size = 0x20262024;
  628. cache_config = 2 << CODA9_CACHE_PAGEMERGE_OFFSET;
  629. } else {
  630. /* Luma 0x2 page, 4x4 cache, chroma 0x2 page, 4x3 cache size */
  631. cache_size = 0x02440243;
  632. cache_config = 1 << CODA9_CACHE_PAGEMERGE_OFFSET;
  633. }
  634. coda_write(ctx->dev, cache_size, CODA9_CMD_SET_FRAME_CACHE_SIZE);
  635. if (fourcc == V4L2_PIX_FMT_NV12) {
  636. cache_config |= 32 << CODA9_CACHE_LUMA_BUFFER_SIZE_OFFSET |
  637. 16 << CODA9_CACHE_CR_BUFFER_SIZE_OFFSET |
  638. 0 << CODA9_CACHE_CB_BUFFER_SIZE_OFFSET;
  639. } else {
  640. cache_config |= 32 << CODA9_CACHE_LUMA_BUFFER_SIZE_OFFSET |
  641. 8 << CODA9_CACHE_CR_BUFFER_SIZE_OFFSET |
  642. 8 << CODA9_CACHE_CB_BUFFER_SIZE_OFFSET;
  643. }
  644. coda_write(ctx->dev, cache_config, CODA9_CMD_SET_FRAME_CACHE_CONFIG);
  645. }
  646. /*
  647. * Encoder context operations
  648. */
  649. static int coda_encoder_reqbufs(struct coda_ctx *ctx,
  650. struct v4l2_requestbuffers *rb)
  651. {
  652. struct coda_q_data *q_data_src;
  653. int ret;
  654. if (rb->type != V4L2_BUF_TYPE_VIDEO_OUTPUT)
  655. return 0;
  656. if (rb->count) {
  657. q_data_src = get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_OUTPUT);
  658. ret = coda_alloc_context_buffers(ctx, q_data_src);
  659. if (ret < 0)
  660. return ret;
  661. } else {
  662. coda_free_context_buffers(ctx);
  663. }
  664. return 0;
  665. }
  666. static int coda_start_encoding(struct coda_ctx *ctx)
  667. {
  668. struct coda_dev *dev = ctx->dev;
  669. struct v4l2_device *v4l2_dev = &dev->v4l2_dev;
  670. struct coda_q_data *q_data_src, *q_data_dst;
  671. u32 bitstream_buf, bitstream_size;
  672. struct vb2_v4l2_buffer *buf;
  673. int gamma, ret, value;
  674. u32 dst_fourcc;
  675. int num_fb;
  676. u32 stride;
  677. q_data_src = get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_OUTPUT);
  678. q_data_dst = get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_CAPTURE);
  679. dst_fourcc = q_data_dst->fourcc;
  680. buf = v4l2_m2m_next_dst_buf(ctx->fh.m2m_ctx);
  681. bitstream_buf = vb2_dma_contig_plane_dma_addr(&buf->vb2_buf, 0);
  682. bitstream_size = q_data_dst->sizeimage;
  683. if (!coda_is_initialized(dev)) {
  684. v4l2_err(v4l2_dev, "coda is not initialized.\n");
  685. return -EFAULT;
  686. }
  687. if (dst_fourcc == V4L2_PIX_FMT_JPEG) {
  688. if (!ctx->params.jpeg_qmat_tab[0])
  689. ctx->params.jpeg_qmat_tab[0] = kmalloc(64, GFP_KERNEL);
  690. if (!ctx->params.jpeg_qmat_tab[1])
  691. ctx->params.jpeg_qmat_tab[1] = kmalloc(64, GFP_KERNEL);
  692. coda_set_jpeg_compression_quality(ctx, ctx->params.jpeg_quality);
  693. }
  694. mutex_lock(&dev->coda_mutex);
  695. coda_write(dev, ctx->parabuf.paddr, CODA_REG_BIT_PARA_BUF_ADDR);
  696. coda_write(dev, bitstream_buf, CODA_REG_BIT_RD_PTR(ctx->reg_idx));
  697. coda_write(dev, bitstream_buf, CODA_REG_BIT_WR_PTR(ctx->reg_idx));
  698. switch (dev->devtype->product) {
  699. case CODA_DX6:
  700. coda_write(dev, CODADX6_STREAM_BUF_DYNALLOC_EN |
  701. CODADX6_STREAM_BUF_PIC_RESET, CODA_REG_BIT_STREAM_CTRL);
  702. break;
  703. case CODA_960:
  704. coda_write(dev, 0, CODA9_GDI_WPROT_RGN_EN);
  705. /* fallthrough */
  706. case CODA_7541:
  707. coda_write(dev, CODA7_STREAM_BUF_DYNALLOC_EN |
  708. CODA7_STREAM_BUF_PIC_RESET, CODA_REG_BIT_STREAM_CTRL);
  709. break;
  710. }
  711. ctx->frame_mem_ctrl &= ~(CODA_FRAME_CHROMA_INTERLEAVE | (0x3 << 9) |
  712. CODA9_FRAME_TILED2LINEAR);
  713. if (q_data_src->fourcc == V4L2_PIX_FMT_NV12)
  714. ctx->frame_mem_ctrl |= CODA_FRAME_CHROMA_INTERLEAVE;
  715. if (ctx->tiled_map_type == GDI_TILED_FRAME_MB_RASTER_MAP)
  716. ctx->frame_mem_ctrl |= (0x3 << 9) | CODA9_FRAME_TILED2LINEAR;
  717. coda_write(dev, ctx->frame_mem_ctrl, CODA_REG_BIT_FRAME_MEM_CTRL);
  718. if (dev->devtype->product == CODA_DX6) {
  719. /* Configure the coda */
  720. coda_write(dev, dev->iram.paddr,
  721. CODADX6_REG_BIT_SEARCH_RAM_BASE_ADDR);
  722. }
  723. /* Could set rotation here if needed */
  724. value = 0;
  725. switch (dev->devtype->product) {
  726. case CODA_DX6:
  727. value = (q_data_src->width & CODADX6_PICWIDTH_MASK)
  728. << CODADX6_PICWIDTH_OFFSET;
  729. value |= (q_data_src->height & CODADX6_PICHEIGHT_MASK)
  730. << CODA_PICHEIGHT_OFFSET;
  731. break;
  732. case CODA_7541:
  733. if (dst_fourcc == V4L2_PIX_FMT_H264) {
  734. value = (round_up(q_data_src->width, 16) &
  735. CODA7_PICWIDTH_MASK) << CODA7_PICWIDTH_OFFSET;
  736. value |= (round_up(q_data_src->height, 16) &
  737. CODA7_PICHEIGHT_MASK) << CODA_PICHEIGHT_OFFSET;
  738. break;
  739. }
  740. /* fallthrough */
  741. case CODA_960:
  742. value = (q_data_src->width & CODA7_PICWIDTH_MASK)
  743. << CODA7_PICWIDTH_OFFSET;
  744. value |= (q_data_src->height & CODA7_PICHEIGHT_MASK)
  745. << CODA_PICHEIGHT_OFFSET;
  746. }
  747. coda_write(dev, value, CODA_CMD_ENC_SEQ_SRC_SIZE);
  748. if (dst_fourcc == V4L2_PIX_FMT_JPEG)
  749. ctx->params.framerate = 0;
  750. coda_write(dev, ctx->params.framerate,
  751. CODA_CMD_ENC_SEQ_SRC_F_RATE);
  752. ctx->params.codec_mode = ctx->codec->mode;
  753. switch (dst_fourcc) {
  754. case V4L2_PIX_FMT_MPEG4:
  755. if (dev->devtype->product == CODA_960)
  756. coda_write(dev, CODA9_STD_MPEG4,
  757. CODA_CMD_ENC_SEQ_COD_STD);
  758. else
  759. coda_write(dev, CODA_STD_MPEG4,
  760. CODA_CMD_ENC_SEQ_COD_STD);
  761. coda_write(dev, 0, CODA_CMD_ENC_SEQ_MP4_PARA);
  762. break;
  763. case V4L2_PIX_FMT_H264:
  764. if (dev->devtype->product == CODA_960)
  765. coda_write(dev, CODA9_STD_H264,
  766. CODA_CMD_ENC_SEQ_COD_STD);
  767. else
  768. coda_write(dev, CODA_STD_H264,
  769. CODA_CMD_ENC_SEQ_COD_STD);
  770. if (ctx->params.h264_deblk_enabled) {
  771. value = ((ctx->params.h264_deblk_alpha &
  772. CODA_264PARAM_DEBLKFILTEROFFSETALPHA_MASK) <<
  773. CODA_264PARAM_DEBLKFILTEROFFSETALPHA_OFFSET) |
  774. ((ctx->params.h264_deblk_beta &
  775. CODA_264PARAM_DEBLKFILTEROFFSETBETA_MASK) <<
  776. CODA_264PARAM_DEBLKFILTEROFFSETBETA_OFFSET);
  777. } else {
  778. value = 1 << CODA_264PARAM_DISABLEDEBLK_OFFSET;
  779. }
  780. coda_write(dev, value, CODA_CMD_ENC_SEQ_264_PARA);
  781. break;
  782. case V4L2_PIX_FMT_JPEG:
  783. coda_write(dev, 0, CODA_CMD_ENC_SEQ_JPG_PARA);
  784. coda_write(dev, ctx->params.jpeg_restart_interval,
  785. CODA_CMD_ENC_SEQ_JPG_RST_INTERVAL);
  786. coda_write(dev, 0, CODA_CMD_ENC_SEQ_JPG_THUMB_EN);
  787. coda_write(dev, 0, CODA_CMD_ENC_SEQ_JPG_THUMB_SIZE);
  788. coda_write(dev, 0, CODA_CMD_ENC_SEQ_JPG_THUMB_OFFSET);
  789. coda_jpeg_write_tables(ctx);
  790. break;
  791. default:
  792. v4l2_err(v4l2_dev,
  793. "dst format (0x%08x) invalid.\n", dst_fourcc);
  794. ret = -EINVAL;
  795. goto out;
  796. }
  797. /*
  798. * slice mode and GOP size registers are used for thumb size/offset
  799. * in JPEG mode
  800. */
  801. if (dst_fourcc != V4L2_PIX_FMT_JPEG) {
  802. switch (ctx->params.slice_mode) {
  803. case V4L2_MPEG_VIDEO_MULTI_SLICE_MODE_SINGLE:
  804. value = 0;
  805. break;
  806. case V4L2_MPEG_VIDEO_MULTI_SICE_MODE_MAX_MB:
  807. value = (ctx->params.slice_max_mb &
  808. CODA_SLICING_SIZE_MASK)
  809. << CODA_SLICING_SIZE_OFFSET;
  810. value |= (1 & CODA_SLICING_UNIT_MASK)
  811. << CODA_SLICING_UNIT_OFFSET;
  812. value |= 1 & CODA_SLICING_MODE_MASK;
  813. break;
  814. case V4L2_MPEG_VIDEO_MULTI_SICE_MODE_MAX_BYTES:
  815. value = (ctx->params.slice_max_bits &
  816. CODA_SLICING_SIZE_MASK)
  817. << CODA_SLICING_SIZE_OFFSET;
  818. value |= (0 & CODA_SLICING_UNIT_MASK)
  819. << CODA_SLICING_UNIT_OFFSET;
  820. value |= 1 & CODA_SLICING_MODE_MASK;
  821. break;
  822. }
  823. coda_write(dev, value, CODA_CMD_ENC_SEQ_SLICE_MODE);
  824. value = ctx->params.gop_size & CODA_GOP_SIZE_MASK;
  825. coda_write(dev, value, CODA_CMD_ENC_SEQ_GOP_SIZE);
  826. }
  827. if (ctx->params.bitrate) {
  828. /* Rate control enabled */
  829. value = (ctx->params.bitrate & CODA_RATECONTROL_BITRATE_MASK)
  830. << CODA_RATECONTROL_BITRATE_OFFSET;
  831. value |= 1 & CODA_RATECONTROL_ENABLE_MASK;
  832. value |= (ctx->params.vbv_delay &
  833. CODA_RATECONTROL_INITIALDELAY_MASK)
  834. << CODA_RATECONTROL_INITIALDELAY_OFFSET;
  835. if (dev->devtype->product == CODA_960)
  836. value |= BIT(31); /* disable autoskip */
  837. } else {
  838. value = 0;
  839. }
  840. coda_write(dev, value, CODA_CMD_ENC_SEQ_RC_PARA);
  841. coda_write(dev, ctx->params.vbv_size, CODA_CMD_ENC_SEQ_RC_BUF_SIZE);
  842. coda_write(dev, ctx->params.intra_refresh,
  843. CODA_CMD_ENC_SEQ_INTRA_REFRESH);
  844. coda_write(dev, bitstream_buf, CODA_CMD_ENC_SEQ_BB_START);
  845. coda_write(dev, bitstream_size / 1024, CODA_CMD_ENC_SEQ_BB_SIZE);
  846. value = 0;
  847. if (dev->devtype->product == CODA_960)
  848. gamma = CODA9_DEFAULT_GAMMA;
  849. else
  850. gamma = CODA_DEFAULT_GAMMA;
  851. if (gamma > 0) {
  852. coda_write(dev, (gamma & CODA_GAMMA_MASK) << CODA_GAMMA_OFFSET,
  853. CODA_CMD_ENC_SEQ_RC_GAMMA);
  854. }
  855. if (ctx->params.h264_min_qp || ctx->params.h264_max_qp) {
  856. coda_write(dev,
  857. ctx->params.h264_min_qp << CODA_QPMIN_OFFSET |
  858. ctx->params.h264_max_qp << CODA_QPMAX_OFFSET,
  859. CODA_CMD_ENC_SEQ_RC_QP_MIN_MAX);
  860. }
  861. if (dev->devtype->product == CODA_960) {
  862. if (ctx->params.h264_max_qp)
  863. value |= 1 << CODA9_OPTION_RCQPMAX_OFFSET;
  864. if (CODA_DEFAULT_GAMMA > 0)
  865. value |= 1 << CODA9_OPTION_GAMMA_OFFSET;
  866. } else {
  867. if (CODA_DEFAULT_GAMMA > 0) {
  868. if (dev->devtype->product == CODA_DX6)
  869. value |= 1 << CODADX6_OPTION_GAMMA_OFFSET;
  870. else
  871. value |= 1 << CODA7_OPTION_GAMMA_OFFSET;
  872. }
  873. if (ctx->params.h264_min_qp)
  874. value |= 1 << CODA7_OPTION_RCQPMIN_OFFSET;
  875. if (ctx->params.h264_max_qp)
  876. value |= 1 << CODA7_OPTION_RCQPMAX_OFFSET;
  877. }
  878. coda_write(dev, value, CODA_CMD_ENC_SEQ_OPTION);
  879. coda_write(dev, 0, CODA_CMD_ENC_SEQ_RC_INTERVAL_MODE);
  880. coda_setup_iram(ctx);
  881. if (dst_fourcc == V4L2_PIX_FMT_H264) {
  882. switch (dev->devtype->product) {
  883. case CODA_DX6:
  884. value = FMO_SLICE_SAVE_BUF_SIZE << 7;
  885. coda_write(dev, value, CODADX6_CMD_ENC_SEQ_FMO);
  886. break;
  887. case CODA_7541:
  888. coda_write(dev, ctx->iram_info.search_ram_paddr,
  889. CODA7_CMD_ENC_SEQ_SEARCH_BASE);
  890. coda_write(dev, ctx->iram_info.search_ram_size,
  891. CODA7_CMD_ENC_SEQ_SEARCH_SIZE);
  892. break;
  893. case CODA_960:
  894. coda_write(dev, 0, CODA9_CMD_ENC_SEQ_ME_OPTION);
  895. coda_write(dev, 0, CODA9_CMD_ENC_SEQ_INTRA_WEIGHT);
  896. }
  897. }
  898. ret = coda_command_sync(ctx, CODA_COMMAND_SEQ_INIT);
  899. if (ret < 0) {
  900. v4l2_err(v4l2_dev, "CODA_COMMAND_SEQ_INIT timeout\n");
  901. goto out;
  902. }
  903. if (coda_read(dev, CODA_RET_ENC_SEQ_SUCCESS) == 0) {
  904. v4l2_err(v4l2_dev, "CODA_COMMAND_SEQ_INIT failed\n");
  905. ret = -EFAULT;
  906. goto out;
  907. }
  908. ctx->initialized = 1;
  909. if (dst_fourcc != V4L2_PIX_FMT_JPEG) {
  910. if (dev->devtype->product == CODA_960)
  911. ctx->num_internal_frames = 4;
  912. else
  913. ctx->num_internal_frames = 2;
  914. ret = coda_alloc_framebuffers(ctx, q_data_src, dst_fourcc);
  915. if (ret < 0) {
  916. v4l2_err(v4l2_dev, "failed to allocate framebuffers\n");
  917. goto out;
  918. }
  919. num_fb = 2;
  920. stride = q_data_src->bytesperline;
  921. } else {
  922. ctx->num_internal_frames = 0;
  923. num_fb = 0;
  924. stride = 0;
  925. }
  926. coda_write(dev, num_fb, CODA_CMD_SET_FRAME_BUF_NUM);
  927. coda_write(dev, stride, CODA_CMD_SET_FRAME_BUF_STRIDE);
  928. if (dev->devtype->product == CODA_7541) {
  929. coda_write(dev, q_data_src->bytesperline,
  930. CODA7_CMD_SET_FRAME_SOURCE_BUF_STRIDE);
  931. }
  932. if (dev->devtype->product != CODA_DX6) {
  933. coda_write(dev, ctx->iram_info.buf_bit_use,
  934. CODA7_CMD_SET_FRAME_AXI_BIT_ADDR);
  935. coda_write(dev, ctx->iram_info.buf_ip_ac_dc_use,
  936. CODA7_CMD_SET_FRAME_AXI_IPACDC_ADDR);
  937. coda_write(dev, ctx->iram_info.buf_dbk_y_use,
  938. CODA7_CMD_SET_FRAME_AXI_DBKY_ADDR);
  939. coda_write(dev, ctx->iram_info.buf_dbk_c_use,
  940. CODA7_CMD_SET_FRAME_AXI_DBKC_ADDR);
  941. coda_write(dev, ctx->iram_info.buf_ovl_use,
  942. CODA7_CMD_SET_FRAME_AXI_OVL_ADDR);
  943. if (dev->devtype->product == CODA_960) {
  944. coda_write(dev, ctx->iram_info.buf_btp_use,
  945. CODA9_CMD_SET_FRAME_AXI_BTP_ADDR);
  946. coda9_set_frame_cache(ctx, q_data_src->fourcc);
  947. /* FIXME */
  948. coda_write(dev, ctx->internal_frames[2].paddr,
  949. CODA9_CMD_SET_FRAME_SUBSAMP_A);
  950. coda_write(dev, ctx->internal_frames[3].paddr,
  951. CODA9_CMD_SET_FRAME_SUBSAMP_B);
  952. }
  953. }
  954. ret = coda_command_sync(ctx, CODA_COMMAND_SET_FRAME_BUF);
  955. if (ret < 0) {
  956. v4l2_err(v4l2_dev, "CODA_COMMAND_SET_FRAME_BUF timeout\n");
  957. goto out;
  958. }
  959. /* Save stream headers */
  960. buf = v4l2_m2m_next_dst_buf(ctx->fh.m2m_ctx);
  961. switch (dst_fourcc) {
  962. case V4L2_PIX_FMT_H264:
  963. /*
  964. * Get SPS in the first frame and copy it to an
  965. * intermediate buffer.
  966. */
  967. ret = coda_encode_header(ctx, buf, CODA_HEADER_H264_SPS,
  968. &ctx->vpu_header[0][0],
  969. &ctx->vpu_header_size[0]);
  970. if (ret < 0)
  971. goto out;
  972. /*
  973. * Get PPS in the first frame and copy it to an
  974. * intermediate buffer.
  975. */
  976. ret = coda_encode_header(ctx, buf, CODA_HEADER_H264_PPS,
  977. &ctx->vpu_header[1][0],
  978. &ctx->vpu_header_size[1]);
  979. if (ret < 0)
  980. goto out;
  981. /*
  982. * Length of H.264 headers is variable and thus it might not be
  983. * aligned for the coda to append the encoded frame. In that is
  984. * the case a filler NAL must be added to header 2.
  985. */
  986. ctx->vpu_header_size[2] = coda_h264_padding(
  987. (ctx->vpu_header_size[0] +
  988. ctx->vpu_header_size[1]),
  989. ctx->vpu_header[2]);
  990. break;
  991. case V4L2_PIX_FMT_MPEG4:
  992. /*
  993. * Get VOS in the first frame and copy it to an
  994. * intermediate buffer
  995. */
  996. ret = coda_encode_header(ctx, buf, CODA_HEADER_MP4V_VOS,
  997. &ctx->vpu_header[0][0],
  998. &ctx->vpu_header_size[0]);
  999. if (ret < 0)
  1000. goto out;
  1001. ret = coda_encode_header(ctx, buf, CODA_HEADER_MP4V_VIS,
  1002. &ctx->vpu_header[1][0],
  1003. &ctx->vpu_header_size[1]);
  1004. if (ret < 0)
  1005. goto out;
  1006. ret = coda_encode_header(ctx, buf, CODA_HEADER_MP4V_VOL,
  1007. &ctx->vpu_header[2][0],
  1008. &ctx->vpu_header_size[2]);
  1009. if (ret < 0)
  1010. goto out;
  1011. break;
  1012. default:
  1013. /* No more formats need to save headers at the moment */
  1014. break;
  1015. }
  1016. out:
  1017. mutex_unlock(&dev->coda_mutex);
  1018. return ret;
  1019. }
  1020. static int coda_prepare_encode(struct coda_ctx *ctx)
  1021. {
  1022. struct coda_q_data *q_data_src, *q_data_dst;
  1023. struct vb2_v4l2_buffer *src_buf, *dst_buf;
  1024. struct coda_dev *dev = ctx->dev;
  1025. int force_ipicture;
  1026. int quant_param = 0;
  1027. u32 pic_stream_buffer_addr, pic_stream_buffer_size;
  1028. u32 rot_mode = 0;
  1029. u32 dst_fourcc;
  1030. u32 reg;
  1031. src_buf = v4l2_m2m_next_src_buf(ctx->fh.m2m_ctx);
  1032. dst_buf = v4l2_m2m_next_dst_buf(ctx->fh.m2m_ctx);
  1033. q_data_src = get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_OUTPUT);
  1034. q_data_dst = get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_CAPTURE);
  1035. dst_fourcc = q_data_dst->fourcc;
  1036. src_buf->sequence = ctx->osequence;
  1037. dst_buf->sequence = ctx->osequence;
  1038. ctx->osequence++;
  1039. /*
  1040. * Workaround coda firmware BUG that only marks the first
  1041. * frame as IDR. This is a problem for some decoders that can't
  1042. * recover when a frame is lost.
  1043. */
  1044. if (src_buf->sequence % ctx->params.gop_size) {
  1045. src_buf->flags |= V4L2_BUF_FLAG_PFRAME;
  1046. src_buf->flags &= ~V4L2_BUF_FLAG_KEYFRAME;
  1047. } else {
  1048. src_buf->flags |= V4L2_BUF_FLAG_KEYFRAME;
  1049. src_buf->flags &= ~V4L2_BUF_FLAG_PFRAME;
  1050. }
  1051. if (dev->devtype->product == CODA_960)
  1052. coda_set_gdi_regs(ctx);
  1053. /*
  1054. * Copy headers at the beginning of the first frame for H.264 only.
  1055. * In MPEG4 they are already copied by the coda.
  1056. */
  1057. if (src_buf->sequence == 0) {
  1058. pic_stream_buffer_addr =
  1059. vb2_dma_contig_plane_dma_addr(&dst_buf->vb2_buf, 0) +
  1060. ctx->vpu_header_size[0] +
  1061. ctx->vpu_header_size[1] +
  1062. ctx->vpu_header_size[2];
  1063. pic_stream_buffer_size = q_data_dst->sizeimage -
  1064. ctx->vpu_header_size[0] -
  1065. ctx->vpu_header_size[1] -
  1066. ctx->vpu_header_size[2];
  1067. memcpy(vb2_plane_vaddr(&dst_buf->vb2_buf, 0),
  1068. &ctx->vpu_header[0][0], ctx->vpu_header_size[0]);
  1069. memcpy(vb2_plane_vaddr(&dst_buf->vb2_buf, 0)
  1070. + ctx->vpu_header_size[0], &ctx->vpu_header[1][0],
  1071. ctx->vpu_header_size[1]);
  1072. memcpy(vb2_plane_vaddr(&dst_buf->vb2_buf, 0)
  1073. + ctx->vpu_header_size[0] + ctx->vpu_header_size[1],
  1074. &ctx->vpu_header[2][0], ctx->vpu_header_size[2]);
  1075. } else {
  1076. pic_stream_buffer_addr =
  1077. vb2_dma_contig_plane_dma_addr(&dst_buf->vb2_buf, 0);
  1078. pic_stream_buffer_size = q_data_dst->sizeimage;
  1079. }
  1080. if (src_buf->flags & V4L2_BUF_FLAG_KEYFRAME) {
  1081. force_ipicture = 1;
  1082. switch (dst_fourcc) {
  1083. case V4L2_PIX_FMT_H264:
  1084. quant_param = ctx->params.h264_intra_qp;
  1085. break;
  1086. case V4L2_PIX_FMT_MPEG4:
  1087. quant_param = ctx->params.mpeg4_intra_qp;
  1088. break;
  1089. case V4L2_PIX_FMT_JPEG:
  1090. quant_param = 30;
  1091. break;
  1092. default:
  1093. v4l2_warn(&ctx->dev->v4l2_dev,
  1094. "cannot set intra qp, fmt not supported\n");
  1095. break;
  1096. }
  1097. } else {
  1098. force_ipicture = 0;
  1099. switch (dst_fourcc) {
  1100. case V4L2_PIX_FMT_H264:
  1101. quant_param = ctx->params.h264_inter_qp;
  1102. break;
  1103. case V4L2_PIX_FMT_MPEG4:
  1104. quant_param = ctx->params.mpeg4_inter_qp;
  1105. break;
  1106. default:
  1107. v4l2_warn(&ctx->dev->v4l2_dev,
  1108. "cannot set inter qp, fmt not supported\n");
  1109. break;
  1110. }
  1111. }
  1112. /* submit */
  1113. if (ctx->params.rot_mode)
  1114. rot_mode = CODA_ROT_MIR_ENABLE | ctx->params.rot_mode;
  1115. coda_write(dev, rot_mode, CODA_CMD_ENC_PIC_ROT_MODE);
  1116. coda_write(dev, quant_param, CODA_CMD_ENC_PIC_QS);
  1117. if (dev->devtype->product == CODA_960) {
  1118. coda_write(dev, 4/*FIXME: 0*/, CODA9_CMD_ENC_PIC_SRC_INDEX);
  1119. coda_write(dev, q_data_src->width, CODA9_CMD_ENC_PIC_SRC_STRIDE);
  1120. coda_write(dev, 0, CODA9_CMD_ENC_PIC_SUB_FRAME_SYNC);
  1121. reg = CODA9_CMD_ENC_PIC_SRC_ADDR_Y;
  1122. } else {
  1123. reg = CODA_CMD_ENC_PIC_SRC_ADDR_Y;
  1124. }
  1125. coda_write_base(ctx, q_data_src, src_buf, reg);
  1126. coda_write(dev, force_ipicture << 1 & 0x2,
  1127. CODA_CMD_ENC_PIC_OPTION);
  1128. coda_write(dev, pic_stream_buffer_addr, CODA_CMD_ENC_PIC_BB_START);
  1129. coda_write(dev, pic_stream_buffer_size / 1024,
  1130. CODA_CMD_ENC_PIC_BB_SIZE);
  1131. if (!ctx->streamon_out) {
  1132. /* After streamoff on the output side, set stream end flag */
  1133. ctx->bit_stream_param |= CODA_BIT_STREAM_END_FLAG;
  1134. coda_write(dev, ctx->bit_stream_param,
  1135. CODA_REG_BIT_BIT_STREAM_PARAM);
  1136. }
  1137. if (dev->devtype->product != CODA_DX6)
  1138. coda_write(dev, ctx->iram_info.axi_sram_use,
  1139. CODA7_REG_BIT_AXI_SRAM_USE);
  1140. trace_coda_enc_pic_run(ctx, src_buf);
  1141. coda_command_async(ctx, CODA_COMMAND_PIC_RUN);
  1142. return 0;
  1143. }
  1144. static void coda_finish_encode(struct coda_ctx *ctx)
  1145. {
  1146. struct vb2_v4l2_buffer *src_buf, *dst_buf;
  1147. struct coda_dev *dev = ctx->dev;
  1148. u32 wr_ptr, start_ptr;
  1149. src_buf = v4l2_m2m_src_buf_remove(ctx->fh.m2m_ctx);
  1150. dst_buf = v4l2_m2m_next_dst_buf(ctx->fh.m2m_ctx);
  1151. trace_coda_enc_pic_done(ctx, dst_buf);
  1152. /* Get results from the coda */
  1153. start_ptr = coda_read(dev, CODA_CMD_ENC_PIC_BB_START);
  1154. wr_ptr = coda_read(dev, CODA_REG_BIT_WR_PTR(ctx->reg_idx));
  1155. /* Calculate bytesused field */
  1156. if (dst_buf->sequence == 0) {
  1157. vb2_set_plane_payload(&dst_buf->vb2_buf, 0, wr_ptr - start_ptr +
  1158. ctx->vpu_header_size[0] +
  1159. ctx->vpu_header_size[1] +
  1160. ctx->vpu_header_size[2]);
  1161. } else {
  1162. vb2_set_plane_payload(&dst_buf->vb2_buf, 0, wr_ptr - start_ptr);
  1163. }
  1164. v4l2_dbg(1, coda_debug, &ctx->dev->v4l2_dev, "frame size = %u\n",
  1165. wr_ptr - start_ptr);
  1166. coda_read(dev, CODA_RET_ENC_PIC_SLICE_NUM);
  1167. coda_read(dev, CODA_RET_ENC_PIC_FLAG);
  1168. if (coda_read(dev, CODA_RET_ENC_PIC_TYPE) == 0) {
  1169. dst_buf->flags |= V4L2_BUF_FLAG_KEYFRAME;
  1170. dst_buf->flags &= ~V4L2_BUF_FLAG_PFRAME;
  1171. } else {
  1172. dst_buf->flags |= V4L2_BUF_FLAG_PFRAME;
  1173. dst_buf->flags &= ~V4L2_BUF_FLAG_KEYFRAME;
  1174. }
  1175. dst_buf->timestamp = src_buf->timestamp;
  1176. dst_buf->flags &= ~V4L2_BUF_FLAG_TSTAMP_SRC_MASK;
  1177. dst_buf->flags |=
  1178. src_buf->flags & V4L2_BUF_FLAG_TSTAMP_SRC_MASK;
  1179. dst_buf->timecode = src_buf->timecode;
  1180. v4l2_m2m_buf_done(src_buf, VB2_BUF_STATE_DONE);
  1181. dst_buf = v4l2_m2m_dst_buf_remove(ctx->fh.m2m_ctx);
  1182. coda_m2m_buf_done(ctx, dst_buf, VB2_BUF_STATE_DONE);
  1183. ctx->gopcounter--;
  1184. if (ctx->gopcounter < 0)
  1185. ctx->gopcounter = ctx->params.gop_size - 1;
  1186. v4l2_dbg(1, coda_debug, &dev->v4l2_dev,
  1187. "job finished: encoding frame (%d) (%s)\n",
  1188. dst_buf->sequence,
  1189. (dst_buf->flags & V4L2_BUF_FLAG_KEYFRAME) ?
  1190. "KEYFRAME" : "PFRAME");
  1191. }
  1192. static void coda_seq_end_work(struct work_struct *work)
  1193. {
  1194. struct coda_ctx *ctx = container_of(work, struct coda_ctx, seq_end_work);
  1195. struct coda_dev *dev = ctx->dev;
  1196. mutex_lock(&ctx->buffer_mutex);
  1197. mutex_lock(&dev->coda_mutex);
  1198. if (ctx->initialized == 0)
  1199. goto out;
  1200. v4l2_dbg(1, coda_debug, &dev->v4l2_dev,
  1201. "%d: %s: sent command 'SEQ_END' to coda\n", ctx->idx,
  1202. __func__);
  1203. if (coda_command_sync(ctx, CODA_COMMAND_SEQ_END)) {
  1204. v4l2_err(&dev->v4l2_dev,
  1205. "CODA_COMMAND_SEQ_END failed\n");
  1206. }
  1207. /*
  1208. * FIXME: Sometimes h.264 encoding fails with 8-byte sequences missing
  1209. * from the output stream after the h.264 decoder has run. Resetting the
  1210. * hardware after the decoder has finished seems to help.
  1211. */
  1212. if (dev->devtype->product == CODA_960)
  1213. coda_hw_reset(ctx);
  1214. kfifo_init(&ctx->bitstream_fifo,
  1215. ctx->bitstream.vaddr, ctx->bitstream.size);
  1216. coda_free_framebuffers(ctx);
  1217. ctx->initialized = 0;
  1218. out:
  1219. mutex_unlock(&dev->coda_mutex);
  1220. mutex_unlock(&ctx->buffer_mutex);
  1221. }
  1222. static void coda_bit_release(struct coda_ctx *ctx)
  1223. {
  1224. mutex_lock(&ctx->buffer_mutex);
  1225. coda_free_framebuffers(ctx);
  1226. coda_free_context_buffers(ctx);
  1227. coda_free_bitstream_buffer(ctx);
  1228. mutex_unlock(&ctx->buffer_mutex);
  1229. }
  1230. const struct coda_context_ops coda_bit_encode_ops = {
  1231. .queue_init = coda_encoder_queue_init,
  1232. .reqbufs = coda_encoder_reqbufs,
  1233. .start_streaming = coda_start_encoding,
  1234. .prepare_run = coda_prepare_encode,
  1235. .finish_run = coda_finish_encode,
  1236. .seq_end_work = coda_seq_end_work,
  1237. .release = coda_bit_release,
  1238. };
  1239. /*
  1240. * Decoder context operations
  1241. */
  1242. static int coda_alloc_bitstream_buffer(struct coda_ctx *ctx,
  1243. struct coda_q_data *q_data)
  1244. {
  1245. if (ctx->bitstream.vaddr)
  1246. return 0;
  1247. ctx->bitstream.size = roundup_pow_of_two(q_data->sizeimage * 2);
  1248. ctx->bitstream.vaddr = dma_alloc_writecombine(
  1249. &ctx->dev->plat_dev->dev, ctx->bitstream.size,
  1250. &ctx->bitstream.paddr, GFP_KERNEL);
  1251. if (!ctx->bitstream.vaddr) {
  1252. v4l2_err(&ctx->dev->v4l2_dev,
  1253. "failed to allocate bitstream ringbuffer");
  1254. return -ENOMEM;
  1255. }
  1256. kfifo_init(&ctx->bitstream_fifo,
  1257. ctx->bitstream.vaddr, ctx->bitstream.size);
  1258. return 0;
  1259. }
  1260. static void coda_free_bitstream_buffer(struct coda_ctx *ctx)
  1261. {
  1262. if (ctx->bitstream.vaddr == NULL)
  1263. return;
  1264. dma_free_writecombine(&ctx->dev->plat_dev->dev, ctx->bitstream.size,
  1265. ctx->bitstream.vaddr, ctx->bitstream.paddr);
  1266. ctx->bitstream.vaddr = NULL;
  1267. kfifo_init(&ctx->bitstream_fifo, NULL, 0);
  1268. }
  1269. static int coda_decoder_reqbufs(struct coda_ctx *ctx,
  1270. struct v4l2_requestbuffers *rb)
  1271. {
  1272. struct coda_q_data *q_data_src;
  1273. int ret;
  1274. if (rb->type != V4L2_BUF_TYPE_VIDEO_OUTPUT)
  1275. return 0;
  1276. if (rb->count) {
  1277. q_data_src = get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_OUTPUT);
  1278. ret = coda_alloc_context_buffers(ctx, q_data_src);
  1279. if (ret < 0)
  1280. return ret;
  1281. ret = coda_alloc_bitstream_buffer(ctx, q_data_src);
  1282. if (ret < 0) {
  1283. coda_free_context_buffers(ctx);
  1284. return ret;
  1285. }
  1286. } else {
  1287. coda_free_bitstream_buffer(ctx);
  1288. coda_free_context_buffers(ctx);
  1289. }
  1290. return 0;
  1291. }
  1292. static int __coda_start_decoding(struct coda_ctx *ctx)
  1293. {
  1294. struct coda_q_data *q_data_src, *q_data_dst;
  1295. u32 bitstream_buf, bitstream_size;
  1296. struct coda_dev *dev = ctx->dev;
  1297. int width, height;
  1298. u32 src_fourcc, dst_fourcc;
  1299. u32 val;
  1300. int ret;
  1301. /* Start decoding */
  1302. q_data_src = get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_OUTPUT);
  1303. q_data_dst = get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_CAPTURE);
  1304. bitstream_buf = ctx->bitstream.paddr;
  1305. bitstream_size = ctx->bitstream.size;
  1306. src_fourcc = q_data_src->fourcc;
  1307. dst_fourcc = q_data_dst->fourcc;
  1308. coda_write(dev, ctx->parabuf.paddr, CODA_REG_BIT_PARA_BUF_ADDR);
  1309. /* Update coda bitstream read and write pointers from kfifo */
  1310. coda_kfifo_sync_to_device_full(ctx);
  1311. ctx->frame_mem_ctrl &= ~(CODA_FRAME_CHROMA_INTERLEAVE | (0x3 << 9) |
  1312. CODA9_FRAME_TILED2LINEAR);
  1313. if (dst_fourcc == V4L2_PIX_FMT_NV12)
  1314. ctx->frame_mem_ctrl |= CODA_FRAME_CHROMA_INTERLEAVE;
  1315. if (ctx->tiled_map_type == GDI_TILED_FRAME_MB_RASTER_MAP)
  1316. ctx->frame_mem_ctrl |= (0x3 << 9) | CODA9_FRAME_TILED2LINEAR;
  1317. coda_write(dev, ctx->frame_mem_ctrl, CODA_REG_BIT_FRAME_MEM_CTRL);
  1318. ctx->display_idx = -1;
  1319. ctx->frm_dis_flg = 0;
  1320. coda_write(dev, 0, CODA_REG_BIT_FRM_DIS_FLG(ctx->reg_idx));
  1321. coda_write(dev, CODA_BIT_DEC_SEQ_INIT_ESCAPE,
  1322. CODA_REG_BIT_BIT_STREAM_PARAM);
  1323. coda_write(dev, bitstream_buf, CODA_CMD_DEC_SEQ_BB_START);
  1324. coda_write(dev, bitstream_size / 1024, CODA_CMD_DEC_SEQ_BB_SIZE);
  1325. val = 0;
  1326. if ((dev->devtype->product == CODA_7541) ||
  1327. (dev->devtype->product == CODA_960))
  1328. val |= CODA_REORDER_ENABLE;
  1329. if (ctx->codec->src_fourcc == V4L2_PIX_FMT_JPEG)
  1330. val |= CODA_NO_INT_ENABLE;
  1331. coda_write(dev, val, CODA_CMD_DEC_SEQ_OPTION);
  1332. ctx->params.codec_mode = ctx->codec->mode;
  1333. if (dev->devtype->product == CODA_960 &&
  1334. src_fourcc == V4L2_PIX_FMT_MPEG4)
  1335. ctx->params.codec_mode_aux = CODA_MP4_AUX_MPEG4;
  1336. else
  1337. ctx->params.codec_mode_aux = 0;
  1338. if (src_fourcc == V4L2_PIX_FMT_H264) {
  1339. if (dev->devtype->product == CODA_7541) {
  1340. coda_write(dev, ctx->psbuf.paddr,
  1341. CODA_CMD_DEC_SEQ_PS_BB_START);
  1342. coda_write(dev, (CODA7_PS_BUF_SIZE / 1024),
  1343. CODA_CMD_DEC_SEQ_PS_BB_SIZE);
  1344. }
  1345. if (dev->devtype->product == CODA_960) {
  1346. coda_write(dev, 0, CODA_CMD_DEC_SEQ_X264_MV_EN);
  1347. coda_write(dev, 512, CODA_CMD_DEC_SEQ_SPP_CHUNK_SIZE);
  1348. }
  1349. }
  1350. if (dev->devtype->product != CODA_960)
  1351. coda_write(dev, 0, CODA_CMD_DEC_SEQ_SRC_SIZE);
  1352. if (coda_command_sync(ctx, CODA_COMMAND_SEQ_INIT)) {
  1353. v4l2_err(&dev->v4l2_dev, "CODA_COMMAND_SEQ_INIT timeout\n");
  1354. coda_write(dev, 0, CODA_REG_BIT_BIT_STREAM_PARAM);
  1355. return -ETIMEDOUT;
  1356. }
  1357. ctx->initialized = 1;
  1358. /* Update kfifo out pointer from coda bitstream read pointer */
  1359. coda_kfifo_sync_from_device(ctx);
  1360. coda_write(dev, 0, CODA_REG_BIT_BIT_STREAM_PARAM);
  1361. if (coda_read(dev, CODA_RET_DEC_SEQ_SUCCESS) == 0) {
  1362. v4l2_err(&dev->v4l2_dev,
  1363. "CODA_COMMAND_SEQ_INIT failed, error code = %d\n",
  1364. coda_read(dev, CODA_RET_DEC_SEQ_ERR_REASON));
  1365. return -EAGAIN;
  1366. }
  1367. val = coda_read(dev, CODA_RET_DEC_SEQ_SRC_SIZE);
  1368. if (dev->devtype->product == CODA_DX6) {
  1369. width = (val >> CODADX6_PICWIDTH_OFFSET) & CODADX6_PICWIDTH_MASK;
  1370. height = val & CODADX6_PICHEIGHT_MASK;
  1371. } else {
  1372. width = (val >> CODA7_PICWIDTH_OFFSET) & CODA7_PICWIDTH_MASK;
  1373. height = val & CODA7_PICHEIGHT_MASK;
  1374. }
  1375. if (width > q_data_dst->bytesperline || height > q_data_dst->height) {
  1376. v4l2_err(&dev->v4l2_dev, "stream is %dx%d, not %dx%d\n",
  1377. width, height, q_data_dst->bytesperline,
  1378. q_data_dst->height);
  1379. return -EINVAL;
  1380. }
  1381. width = round_up(width, 16);
  1382. height = round_up(height, 16);
  1383. v4l2_dbg(1, coda_debug, &dev->v4l2_dev, "%s instance %d now: %dx%d\n",
  1384. __func__, ctx->idx, width, height);
  1385. ctx->num_internal_frames = coda_read(dev, CODA_RET_DEC_SEQ_FRAME_NEED);
  1386. if (ctx->num_internal_frames > CODA_MAX_FRAMEBUFFERS) {
  1387. v4l2_err(&dev->v4l2_dev,
  1388. "not enough framebuffers to decode (%d < %d)\n",
  1389. CODA_MAX_FRAMEBUFFERS, ctx->num_internal_frames);
  1390. return -EINVAL;
  1391. }
  1392. if (src_fourcc == V4L2_PIX_FMT_H264) {
  1393. u32 left_right;
  1394. u32 top_bottom;
  1395. left_right = coda_read(dev, CODA_RET_DEC_SEQ_CROP_LEFT_RIGHT);
  1396. top_bottom = coda_read(dev, CODA_RET_DEC_SEQ_CROP_TOP_BOTTOM);
  1397. q_data_dst->rect.left = (left_right >> 10) & 0x3ff;
  1398. q_data_dst->rect.top = (top_bottom >> 10) & 0x3ff;
  1399. q_data_dst->rect.width = width - q_data_dst->rect.left -
  1400. (left_right & 0x3ff);
  1401. q_data_dst->rect.height = height - q_data_dst->rect.top -
  1402. (top_bottom & 0x3ff);
  1403. }
  1404. ret = coda_alloc_framebuffers(ctx, q_data_dst, src_fourcc);
  1405. if (ret < 0) {
  1406. v4l2_err(&dev->v4l2_dev, "failed to allocate framebuffers\n");
  1407. return ret;
  1408. }
  1409. /* Tell the decoder how many frame buffers we allocated. */
  1410. coda_write(dev, ctx->num_internal_frames, CODA_CMD_SET_FRAME_BUF_NUM);
  1411. coda_write(dev, width, CODA_CMD_SET_FRAME_BUF_STRIDE);
  1412. if (dev->devtype->product != CODA_DX6) {
  1413. /* Set secondary AXI IRAM */
  1414. coda_setup_iram(ctx);
  1415. coda_write(dev, ctx->iram_info.buf_bit_use,
  1416. CODA7_CMD_SET_FRAME_AXI_BIT_ADDR);
  1417. coda_write(dev, ctx->iram_info.buf_ip_ac_dc_use,
  1418. CODA7_CMD_SET_FRAME_AXI_IPACDC_ADDR);
  1419. coda_write(dev, ctx->iram_info.buf_dbk_y_use,
  1420. CODA7_CMD_SET_FRAME_AXI_DBKY_ADDR);
  1421. coda_write(dev, ctx->iram_info.buf_dbk_c_use,
  1422. CODA7_CMD_SET_FRAME_AXI_DBKC_ADDR);
  1423. coda_write(dev, ctx->iram_info.buf_ovl_use,
  1424. CODA7_CMD_SET_FRAME_AXI_OVL_ADDR);
  1425. if (dev->devtype->product == CODA_960) {
  1426. coda_write(dev, ctx->iram_info.buf_btp_use,
  1427. CODA9_CMD_SET_FRAME_AXI_BTP_ADDR);
  1428. coda_write(dev, -1, CODA9_CMD_SET_FRAME_DELAY);
  1429. coda9_set_frame_cache(ctx, dst_fourcc);
  1430. }
  1431. }
  1432. if (src_fourcc == V4L2_PIX_FMT_H264) {
  1433. coda_write(dev, ctx->slicebuf.paddr,
  1434. CODA_CMD_SET_FRAME_SLICE_BB_START);
  1435. coda_write(dev, ctx->slicebuf.size / 1024,
  1436. CODA_CMD_SET_FRAME_SLICE_BB_SIZE);
  1437. }
  1438. if (dev->devtype->product == CODA_7541) {
  1439. int max_mb_x = 1920 / 16;
  1440. int max_mb_y = 1088 / 16;
  1441. int max_mb_num = max_mb_x * max_mb_y;
  1442. coda_write(dev, max_mb_num << 16 | max_mb_x << 8 | max_mb_y,
  1443. CODA7_CMD_SET_FRAME_MAX_DEC_SIZE);
  1444. } else if (dev->devtype->product == CODA_960) {
  1445. int max_mb_x = 1920 / 16;
  1446. int max_mb_y = 1088 / 16;
  1447. int max_mb_num = max_mb_x * max_mb_y;
  1448. coda_write(dev, max_mb_num << 16 | max_mb_x << 8 | max_mb_y,
  1449. CODA9_CMD_SET_FRAME_MAX_DEC_SIZE);
  1450. }
  1451. if (coda_command_sync(ctx, CODA_COMMAND_SET_FRAME_BUF)) {
  1452. v4l2_err(&ctx->dev->v4l2_dev,
  1453. "CODA_COMMAND_SET_FRAME_BUF timeout\n");
  1454. return -ETIMEDOUT;
  1455. }
  1456. return 0;
  1457. }
  1458. static int coda_start_decoding(struct coda_ctx *ctx)
  1459. {
  1460. struct coda_dev *dev = ctx->dev;
  1461. int ret;
  1462. mutex_lock(&dev->coda_mutex);
  1463. ret = __coda_start_decoding(ctx);
  1464. mutex_unlock(&dev->coda_mutex);
  1465. return ret;
  1466. }
  1467. static int coda_prepare_decode(struct coda_ctx *ctx)
  1468. {
  1469. struct vb2_v4l2_buffer *dst_buf;
  1470. struct coda_dev *dev = ctx->dev;
  1471. struct coda_q_data *q_data_dst;
  1472. struct coda_buffer_meta *meta;
  1473. unsigned long flags;
  1474. u32 reg_addr, reg_stride;
  1475. dst_buf = v4l2_m2m_next_dst_buf(ctx->fh.m2m_ctx);
  1476. q_data_dst = get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_CAPTURE);
  1477. /* Try to copy source buffer contents into the bitstream ringbuffer */
  1478. mutex_lock(&ctx->bitstream_mutex);
  1479. coda_fill_bitstream(ctx, true);
  1480. mutex_unlock(&ctx->bitstream_mutex);
  1481. if (coda_get_bitstream_payload(ctx) < 512 &&
  1482. (!(ctx->bit_stream_param & CODA_BIT_STREAM_END_FLAG))) {
  1483. v4l2_dbg(1, coda_debug, &dev->v4l2_dev,
  1484. "bitstream payload: %d, skipping\n",
  1485. coda_get_bitstream_payload(ctx));
  1486. v4l2_m2m_job_finish(ctx->dev->m2m_dev, ctx->fh.m2m_ctx);
  1487. return -EAGAIN;
  1488. }
  1489. /* Run coda_start_decoding (again) if not yet initialized */
  1490. if (!ctx->initialized) {
  1491. int ret = __coda_start_decoding(ctx);
  1492. if (ret < 0) {
  1493. v4l2_err(&dev->v4l2_dev, "failed to start decoding\n");
  1494. v4l2_m2m_job_finish(ctx->dev->m2m_dev, ctx->fh.m2m_ctx);
  1495. return -EAGAIN;
  1496. } else {
  1497. ctx->initialized = 1;
  1498. }
  1499. }
  1500. if (dev->devtype->product == CODA_960)
  1501. coda_set_gdi_regs(ctx);
  1502. if (dev->devtype->product == CODA_960) {
  1503. /*
  1504. * The CODA960 seems to have an internal list of buffers with
  1505. * 64 entries that includes the registered frame buffers as
  1506. * well as the rotator buffer output.
  1507. * ROT_INDEX needs to be < 0x40, but > ctx->num_internal_frames.
  1508. */
  1509. coda_write(dev, CODA_MAX_FRAMEBUFFERS + dst_buf->vb2_buf.index,
  1510. CODA9_CMD_DEC_PIC_ROT_INDEX);
  1511. reg_addr = CODA9_CMD_DEC_PIC_ROT_ADDR_Y;
  1512. reg_stride = CODA9_CMD_DEC_PIC_ROT_STRIDE;
  1513. } else {
  1514. reg_addr = CODA_CMD_DEC_PIC_ROT_ADDR_Y;
  1515. reg_stride = CODA_CMD_DEC_PIC_ROT_STRIDE;
  1516. }
  1517. coda_write_base(ctx, q_data_dst, dst_buf, reg_addr);
  1518. coda_write(dev, q_data_dst->bytesperline, reg_stride);
  1519. coda_write(dev, CODA_ROT_MIR_ENABLE | ctx->params.rot_mode,
  1520. CODA_CMD_DEC_PIC_ROT_MODE);
  1521. switch (dev->devtype->product) {
  1522. case CODA_DX6:
  1523. /* TBD */
  1524. case CODA_7541:
  1525. coda_write(dev, CODA_PRE_SCAN_EN, CODA_CMD_DEC_PIC_OPTION);
  1526. break;
  1527. case CODA_960:
  1528. /* 'hardcode to use interrupt disable mode'? */
  1529. coda_write(dev, (1 << 10), CODA_CMD_DEC_PIC_OPTION);
  1530. break;
  1531. }
  1532. coda_write(dev, 0, CODA_CMD_DEC_PIC_SKIP_NUM);
  1533. coda_write(dev, 0, CODA_CMD_DEC_PIC_BB_START);
  1534. coda_write(dev, 0, CODA_CMD_DEC_PIC_START_BYTE);
  1535. if (dev->devtype->product != CODA_DX6)
  1536. coda_write(dev, ctx->iram_info.axi_sram_use,
  1537. CODA7_REG_BIT_AXI_SRAM_USE);
  1538. spin_lock_irqsave(&ctx->buffer_meta_lock, flags);
  1539. meta = list_first_entry_or_null(&ctx->buffer_meta_list,
  1540. struct coda_buffer_meta, list);
  1541. if (meta && ctx->codec->src_fourcc == V4L2_PIX_FMT_JPEG) {
  1542. /* If this is the last buffer in the bitstream, add padding */
  1543. if (meta->end == (ctx->bitstream_fifo.kfifo.in &
  1544. ctx->bitstream_fifo.kfifo.mask)) {
  1545. static unsigned char buf[512];
  1546. unsigned int pad;
  1547. /* Pad to multiple of 256 and then add 256 more */
  1548. pad = ((0 - meta->end) & 0xff) + 256;
  1549. memset(buf, 0xff, sizeof(buf));
  1550. kfifo_in(&ctx->bitstream_fifo, buf, pad);
  1551. }
  1552. }
  1553. spin_unlock_irqrestore(&ctx->buffer_meta_lock, flags);
  1554. coda_kfifo_sync_to_device_full(ctx);
  1555. /* Clear decode success flag */
  1556. coda_write(dev, 0, CODA_RET_DEC_PIC_SUCCESS);
  1557. trace_coda_dec_pic_run(ctx, meta);
  1558. coda_command_async(ctx, CODA_COMMAND_PIC_RUN);
  1559. return 0;
  1560. }
  1561. static void coda_finish_decode(struct coda_ctx *ctx)
  1562. {
  1563. struct coda_dev *dev = ctx->dev;
  1564. struct coda_q_data *q_data_src;
  1565. struct coda_q_data *q_data_dst;
  1566. struct vb2_v4l2_buffer *dst_buf;
  1567. struct coda_buffer_meta *meta;
  1568. unsigned long payload;
  1569. unsigned long flags;
  1570. int width, height;
  1571. int decoded_idx;
  1572. int display_idx;
  1573. u32 src_fourcc;
  1574. int success;
  1575. u32 err_mb;
  1576. u32 val;
  1577. /* Update kfifo out pointer from coda bitstream read pointer */
  1578. coda_kfifo_sync_from_device(ctx);
  1579. /*
  1580. * in stream-end mode, the read pointer can overshoot the write pointer
  1581. * by up to 512 bytes
  1582. */
  1583. if (ctx->bit_stream_param & CODA_BIT_STREAM_END_FLAG) {
  1584. if (coda_get_bitstream_payload(ctx) >= ctx->bitstream.size - 512)
  1585. kfifo_init(&ctx->bitstream_fifo,
  1586. ctx->bitstream.vaddr, ctx->bitstream.size);
  1587. }
  1588. q_data_src = get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_OUTPUT);
  1589. src_fourcc = q_data_src->fourcc;
  1590. val = coda_read(dev, CODA_RET_DEC_PIC_SUCCESS);
  1591. if (val != 1)
  1592. pr_err("DEC_PIC_SUCCESS = %d\n", val);
  1593. success = val & 0x1;
  1594. if (!success)
  1595. v4l2_err(&dev->v4l2_dev, "decode failed\n");
  1596. if (src_fourcc == V4L2_PIX_FMT_H264) {
  1597. if (val & (1 << 3))
  1598. v4l2_err(&dev->v4l2_dev,
  1599. "insufficient PS buffer space (%d bytes)\n",
  1600. ctx->psbuf.size);
  1601. if (val & (1 << 2))
  1602. v4l2_err(&dev->v4l2_dev,
  1603. "insufficient slice buffer space (%d bytes)\n",
  1604. ctx->slicebuf.size);
  1605. }
  1606. val = coda_read(dev, CODA_RET_DEC_PIC_SIZE);
  1607. width = (val >> 16) & 0xffff;
  1608. height = val & 0xffff;
  1609. q_data_dst = get_q_data(ctx, V4L2_BUF_TYPE_VIDEO_CAPTURE);
  1610. /* frame crop information */
  1611. if (src_fourcc == V4L2_PIX_FMT_H264) {
  1612. u32 left_right;
  1613. u32 top_bottom;
  1614. left_right = coda_read(dev, CODA_RET_DEC_PIC_CROP_LEFT_RIGHT);
  1615. top_bottom = coda_read(dev, CODA_RET_DEC_PIC_CROP_TOP_BOTTOM);
  1616. if (left_right == 0xffffffff && top_bottom == 0xffffffff) {
  1617. /* Keep current crop information */
  1618. } else {
  1619. struct v4l2_rect *rect = &q_data_dst->rect;
  1620. rect->left = left_right >> 16 & 0xffff;
  1621. rect->top = top_bottom >> 16 & 0xffff;
  1622. rect->width = width - rect->left -
  1623. (left_right & 0xffff);
  1624. rect->height = height - rect->top -
  1625. (top_bottom & 0xffff);
  1626. }
  1627. } else {
  1628. /* no cropping */
  1629. }
  1630. err_mb = coda_read(dev, CODA_RET_DEC_PIC_ERR_MB);
  1631. if (err_mb > 0)
  1632. v4l2_err(&dev->v4l2_dev,
  1633. "errors in %d macroblocks\n", err_mb);
  1634. if (dev->devtype->product == CODA_7541) {
  1635. val = coda_read(dev, CODA_RET_DEC_PIC_OPTION);
  1636. if (val == 0) {
  1637. /* not enough bitstream data */
  1638. v4l2_dbg(1, coda_debug, &dev->v4l2_dev,
  1639. "prescan failed: %d\n", val);
  1640. ctx->hold = true;
  1641. return;
  1642. }
  1643. }
  1644. ctx->frm_dis_flg = coda_read(dev,
  1645. CODA_REG_BIT_FRM_DIS_FLG(ctx->reg_idx));
  1646. /*
  1647. * The previous display frame was copied out by the rotator,
  1648. * now it can be overwritten again
  1649. */
  1650. if (ctx->display_idx >= 0 &&
  1651. ctx->display_idx < ctx->num_internal_frames) {
  1652. ctx->frm_dis_flg &= ~(1 << ctx->display_idx);
  1653. coda_write(dev, ctx->frm_dis_flg,
  1654. CODA_REG_BIT_FRM_DIS_FLG(ctx->reg_idx));
  1655. }
  1656. /*
  1657. * The index of the last decoded frame, not necessarily in
  1658. * display order, and the index of the next display frame.
  1659. * The latter could have been decoded in a previous run.
  1660. */
  1661. decoded_idx = coda_read(dev, CODA_RET_DEC_PIC_CUR_IDX);
  1662. display_idx = coda_read(dev, CODA_RET_DEC_PIC_FRAME_IDX);
  1663. if (decoded_idx == -1) {
  1664. /* no frame was decoded, but we might have a display frame */
  1665. if (display_idx >= 0 && display_idx < ctx->num_internal_frames)
  1666. ctx->sequence_offset++;
  1667. else if (ctx->display_idx < 0)
  1668. ctx->hold = true;
  1669. } else if (decoded_idx == -2) {
  1670. /* no frame was decoded, we still return remaining buffers */
  1671. } else if (decoded_idx < 0 || decoded_idx >= ctx->num_internal_frames) {
  1672. v4l2_err(&dev->v4l2_dev,
  1673. "decoded frame index out of range: %d\n", decoded_idx);
  1674. } else {
  1675. val = coda_read(dev, CODA_RET_DEC_PIC_FRAME_NUM) - 1;
  1676. val -= ctx->sequence_offset;
  1677. spin_lock_irqsave(&ctx->buffer_meta_lock, flags);
  1678. if (!list_empty(&ctx->buffer_meta_list)) {
  1679. meta = list_first_entry(&ctx->buffer_meta_list,
  1680. struct coda_buffer_meta, list);
  1681. list_del(&meta->list);
  1682. ctx->num_metas--;
  1683. spin_unlock_irqrestore(&ctx->buffer_meta_lock, flags);
  1684. /*
  1685. * Clamp counters to 16 bits for comparison, as the HW
  1686. * counter rolls over at this point for h.264. This
  1687. * may be different for other formats, but using 16 bits
  1688. * should be enough to detect most errors and saves us
  1689. * from doing different things based on the format.
  1690. */
  1691. if ((val & 0xffff) != (meta->sequence & 0xffff)) {
  1692. v4l2_err(&dev->v4l2_dev,
  1693. "sequence number mismatch (%d(%d) != %d)\n",
  1694. val, ctx->sequence_offset,
  1695. meta->sequence);
  1696. }
  1697. ctx->frame_metas[decoded_idx] = *meta;
  1698. kfree(meta);
  1699. } else {
  1700. spin_unlock_irqrestore(&ctx->buffer_meta_lock, flags);
  1701. v4l2_err(&dev->v4l2_dev, "empty timestamp list!\n");
  1702. memset(&ctx->frame_metas[decoded_idx], 0,
  1703. sizeof(struct coda_buffer_meta));
  1704. ctx->frame_metas[decoded_idx].sequence = val;
  1705. ctx->sequence_offset++;
  1706. }
  1707. trace_coda_dec_pic_done(ctx, &ctx->frame_metas[decoded_idx]);
  1708. val = coda_read(dev, CODA_RET_DEC_PIC_TYPE) & 0x7;
  1709. if (val == 0)
  1710. ctx->frame_types[decoded_idx] = V4L2_BUF_FLAG_KEYFRAME;
  1711. else if (val == 1)
  1712. ctx->frame_types[decoded_idx] = V4L2_BUF_FLAG_PFRAME;
  1713. else
  1714. ctx->frame_types[decoded_idx] = V4L2_BUF_FLAG_BFRAME;
  1715. ctx->frame_errors[decoded_idx] = err_mb;
  1716. }
  1717. if (display_idx == -1) {
  1718. /*
  1719. * no more frames to be decoded, but there could still
  1720. * be rotator output to dequeue
  1721. */
  1722. ctx->hold = true;
  1723. } else if (display_idx == -3) {
  1724. /* possibly prescan failure */
  1725. } else if (display_idx < 0 || display_idx >= ctx->num_internal_frames) {
  1726. v4l2_err(&dev->v4l2_dev,
  1727. "presentation frame index out of range: %d\n",
  1728. display_idx);
  1729. }
  1730. /* If a frame was copied out, return it */
  1731. if (ctx->display_idx >= 0 &&
  1732. ctx->display_idx < ctx->num_internal_frames) {
  1733. dst_buf = v4l2_m2m_dst_buf_remove(ctx->fh.m2m_ctx);
  1734. dst_buf->sequence = ctx->osequence++;
  1735. dst_buf->flags &= ~(V4L2_BUF_FLAG_KEYFRAME |
  1736. V4L2_BUF_FLAG_PFRAME |
  1737. V4L2_BUF_FLAG_BFRAME);
  1738. dst_buf->flags |= ctx->frame_types[ctx->display_idx];
  1739. meta = &ctx->frame_metas[ctx->display_idx];
  1740. dst_buf->timecode = meta->timecode;
  1741. dst_buf->timestamp = meta->timestamp;
  1742. trace_coda_dec_rot_done(ctx, dst_buf, meta);
  1743. switch (q_data_dst->fourcc) {
  1744. case V4L2_PIX_FMT_YUV420:
  1745. case V4L2_PIX_FMT_YVU420:
  1746. case V4L2_PIX_FMT_NV12:
  1747. default:
  1748. payload = width * height * 3 / 2;
  1749. break;
  1750. case V4L2_PIX_FMT_YUV422P:
  1751. payload = width * height * 2;
  1752. break;
  1753. }
  1754. vb2_set_plane_payload(&dst_buf->vb2_buf, 0, payload);
  1755. coda_m2m_buf_done(ctx, dst_buf, ctx->frame_errors[display_idx] ?
  1756. VB2_BUF_STATE_ERROR : VB2_BUF_STATE_DONE);
  1757. v4l2_dbg(1, coda_debug, &dev->v4l2_dev,
  1758. "job finished: decoding frame (%d) (%s)\n",
  1759. dst_buf->sequence,
  1760. (dst_buf->flags & V4L2_BUF_FLAG_KEYFRAME) ?
  1761. "KEYFRAME" : "PFRAME");
  1762. } else {
  1763. v4l2_dbg(1, coda_debug, &dev->v4l2_dev,
  1764. "job finished: no frame decoded\n");
  1765. }
  1766. /* The rotator will copy the current display frame next time */
  1767. ctx->display_idx = display_idx;
  1768. }
  1769. const struct coda_context_ops coda_bit_decode_ops = {
  1770. .queue_init = coda_decoder_queue_init,
  1771. .reqbufs = coda_decoder_reqbufs,
  1772. .start_streaming = coda_start_decoding,
  1773. .prepare_run = coda_prepare_decode,
  1774. .finish_run = coda_finish_decode,
  1775. .seq_end_work = coda_seq_end_work,
  1776. .release = coda_bit_release,
  1777. };
  1778. irqreturn_t coda_irq_handler(int irq, void *data)
  1779. {
  1780. struct coda_dev *dev = data;
  1781. struct coda_ctx *ctx;
  1782. /* read status register to attend the IRQ */
  1783. coda_read(dev, CODA_REG_BIT_INT_STATUS);
  1784. coda_write(dev, CODA_REG_BIT_INT_CLEAR_SET,
  1785. CODA_REG_BIT_INT_CLEAR);
  1786. ctx = v4l2_m2m_get_curr_priv(dev->m2m_dev);
  1787. if (ctx == NULL) {
  1788. v4l2_err(&dev->v4l2_dev,
  1789. "Instance released before the end of transaction\n");
  1790. mutex_unlock(&dev->coda_mutex);
  1791. return IRQ_HANDLED;
  1792. }
  1793. trace_coda_bit_done(ctx);
  1794. if (ctx->aborting) {
  1795. v4l2_dbg(1, coda_debug, &ctx->dev->v4l2_dev,
  1796. "task has been aborted\n");
  1797. }
  1798. if (coda_isbusy(ctx->dev)) {
  1799. v4l2_dbg(1, coda_debug, &ctx->dev->v4l2_dev,
  1800. "coda is still busy!!!!\n");
  1801. return IRQ_NONE;
  1802. }
  1803. complete(&ctx->completion);
  1804. return IRQ_HANDLED;
  1805. }