fimc-lite.c 45 KB

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  1. /*
  2. * Samsung EXYNOS FIMC-LITE (camera host interface) driver
  3. *
  4. * Copyright (C) 2012 - 2013 Samsung Electronics Co., Ltd.
  5. * Author: Sylwester Nawrocki <s.nawrocki@samsung.com>
  6. *
  7. * This program is free software; you can redistribute it and/or modify
  8. * it under the terms of the GNU General Public License version 2 as
  9. * published by the Free Software Foundation.
  10. */
  11. #define pr_fmt(fmt) "%s:%d " fmt, __func__, __LINE__
  12. #include <linux/bug.h>
  13. #include <linux/clk.h>
  14. #include <linux/device.h>
  15. #include <linux/errno.h>
  16. #include <linux/interrupt.h>
  17. #include <linux/kernel.h>
  18. #include <linux/list.h>
  19. #include <linux/module.h>
  20. #include <linux/of.h>
  21. #include <linux/types.h>
  22. #include <linux/platform_device.h>
  23. #include <linux/pm_runtime.h>
  24. #include <linux/slab.h>
  25. #include <linux/videodev2.h>
  26. #include <media/v4l2-device.h>
  27. #include <media/v4l2-ioctl.h>
  28. #include <media/v4l2-mem2mem.h>
  29. #include <media/videobuf2-v4l2.h>
  30. #include <media/videobuf2-dma-contig.h>
  31. #include <media/exynos-fimc.h>
  32. #include "common.h"
  33. #include "fimc-core.h"
  34. #include "fimc-lite.h"
  35. #include "fimc-lite-reg.h"
  36. static int debug;
  37. module_param(debug, int, 0644);
  38. static const struct fimc_fmt fimc_lite_formats[] = {
  39. {
  40. .name = "YUV 4:2:2 packed, YCbYCr",
  41. .fourcc = V4L2_PIX_FMT_YUYV,
  42. .colorspace = V4L2_COLORSPACE_JPEG,
  43. .depth = { 16 },
  44. .color = FIMC_FMT_YCBYCR422,
  45. .memplanes = 1,
  46. .mbus_code = MEDIA_BUS_FMT_YUYV8_2X8,
  47. .flags = FMT_FLAGS_YUV,
  48. }, {
  49. .name = "YUV 4:2:2 packed, CbYCrY",
  50. .fourcc = V4L2_PIX_FMT_UYVY,
  51. .colorspace = V4L2_COLORSPACE_JPEG,
  52. .depth = { 16 },
  53. .color = FIMC_FMT_CBYCRY422,
  54. .memplanes = 1,
  55. .mbus_code = MEDIA_BUS_FMT_UYVY8_2X8,
  56. .flags = FMT_FLAGS_YUV,
  57. }, {
  58. .name = "YUV 4:2:2 packed, CrYCbY",
  59. .fourcc = V4L2_PIX_FMT_VYUY,
  60. .colorspace = V4L2_COLORSPACE_JPEG,
  61. .depth = { 16 },
  62. .color = FIMC_FMT_CRYCBY422,
  63. .memplanes = 1,
  64. .mbus_code = MEDIA_BUS_FMT_VYUY8_2X8,
  65. .flags = FMT_FLAGS_YUV,
  66. }, {
  67. .name = "YUV 4:2:2 packed, YCrYCb",
  68. .fourcc = V4L2_PIX_FMT_YVYU,
  69. .colorspace = V4L2_COLORSPACE_JPEG,
  70. .depth = { 16 },
  71. .color = FIMC_FMT_YCRYCB422,
  72. .memplanes = 1,
  73. .mbus_code = MEDIA_BUS_FMT_YVYU8_2X8,
  74. .flags = FMT_FLAGS_YUV,
  75. }, {
  76. .name = "RAW8 (GRBG)",
  77. .fourcc = V4L2_PIX_FMT_SGRBG8,
  78. .colorspace = V4L2_COLORSPACE_SRGB,
  79. .depth = { 8 },
  80. .color = FIMC_FMT_RAW8,
  81. .memplanes = 1,
  82. .mbus_code = MEDIA_BUS_FMT_SGRBG8_1X8,
  83. .flags = FMT_FLAGS_RAW_BAYER,
  84. }, {
  85. .name = "RAW10 (GRBG)",
  86. .fourcc = V4L2_PIX_FMT_SGRBG10,
  87. .colorspace = V4L2_COLORSPACE_SRGB,
  88. .depth = { 16 },
  89. .color = FIMC_FMT_RAW10,
  90. .memplanes = 1,
  91. .mbus_code = MEDIA_BUS_FMT_SGRBG10_1X10,
  92. .flags = FMT_FLAGS_RAW_BAYER,
  93. }, {
  94. .name = "RAW12 (GRBG)",
  95. .fourcc = V4L2_PIX_FMT_SGRBG12,
  96. .colorspace = V4L2_COLORSPACE_SRGB,
  97. .depth = { 16 },
  98. .color = FIMC_FMT_RAW12,
  99. .memplanes = 1,
  100. .mbus_code = MEDIA_BUS_FMT_SGRBG12_1X12,
  101. .flags = FMT_FLAGS_RAW_BAYER,
  102. },
  103. };
  104. /**
  105. * fimc_lite_find_format - lookup fimc color format by fourcc or media bus code
  106. * @pixelformat: fourcc to match, ignored if null
  107. * @mbus_code: media bus code to match, ignored if null
  108. * @mask: the color format flags to match
  109. * @index: index to the fimc_lite_formats array, ignored if negative
  110. */
  111. static const struct fimc_fmt *fimc_lite_find_format(const u32 *pixelformat,
  112. const u32 *mbus_code, unsigned int mask, int index)
  113. {
  114. const struct fimc_fmt *fmt, *def_fmt = NULL;
  115. unsigned int i;
  116. int id = 0;
  117. if (index >= (int)ARRAY_SIZE(fimc_lite_formats))
  118. return NULL;
  119. for (i = 0; i < ARRAY_SIZE(fimc_lite_formats); ++i) {
  120. fmt = &fimc_lite_formats[i];
  121. if (mask && !(fmt->flags & mask))
  122. continue;
  123. if (pixelformat && fmt->fourcc == *pixelformat)
  124. return fmt;
  125. if (mbus_code && fmt->mbus_code == *mbus_code)
  126. return fmt;
  127. if (index == id)
  128. def_fmt = fmt;
  129. id++;
  130. }
  131. return def_fmt;
  132. }
  133. static int fimc_lite_hw_init(struct fimc_lite *fimc, bool isp_output)
  134. {
  135. struct fimc_source_info *si;
  136. unsigned long flags;
  137. if (fimc->sensor == NULL)
  138. return -ENXIO;
  139. if (fimc->inp_frame.fmt == NULL || fimc->out_frame.fmt == NULL)
  140. return -EINVAL;
  141. /* Get sensor configuration data from the sensor subdev */
  142. si = v4l2_get_subdev_hostdata(fimc->sensor);
  143. if (!si)
  144. return -EINVAL;
  145. spin_lock_irqsave(&fimc->slock, flags);
  146. flite_hw_set_camera_bus(fimc, si);
  147. flite_hw_set_source_format(fimc, &fimc->inp_frame);
  148. flite_hw_set_window_offset(fimc, &fimc->inp_frame);
  149. flite_hw_set_dma_buf_mask(fimc, 0);
  150. flite_hw_set_output_dma(fimc, &fimc->out_frame, !isp_output);
  151. flite_hw_set_interrupt_mask(fimc);
  152. flite_hw_set_test_pattern(fimc, fimc->test_pattern->val);
  153. if (debug > 0)
  154. flite_hw_dump_regs(fimc, __func__);
  155. spin_unlock_irqrestore(&fimc->slock, flags);
  156. return 0;
  157. }
  158. /*
  159. * Reinitialize the driver so it is ready to start the streaming again.
  160. * Set fimc->state to indicate stream off and the hardware shut down state.
  161. * If not suspending (@suspend is false), return any buffers to videobuf2.
  162. * Otherwise put any owned buffers onto the pending buffers queue, so they
  163. * can be re-spun when the device is being resumed. Also perform FIMC
  164. * software reset and disable streaming on the whole pipeline if required.
  165. */
  166. static int fimc_lite_reinit(struct fimc_lite *fimc, bool suspend)
  167. {
  168. struct flite_buffer *buf;
  169. unsigned long flags;
  170. bool streaming;
  171. spin_lock_irqsave(&fimc->slock, flags);
  172. streaming = fimc->state & (1 << ST_SENSOR_STREAM);
  173. fimc->state &= ~(1 << ST_FLITE_RUN | 1 << ST_FLITE_OFF |
  174. 1 << ST_FLITE_STREAM | 1 << ST_SENSOR_STREAM);
  175. if (suspend)
  176. fimc->state |= (1 << ST_FLITE_SUSPENDED);
  177. else
  178. fimc->state &= ~(1 << ST_FLITE_PENDING |
  179. 1 << ST_FLITE_SUSPENDED);
  180. /* Release unused buffers */
  181. while (!suspend && !list_empty(&fimc->pending_buf_q)) {
  182. buf = fimc_lite_pending_queue_pop(fimc);
  183. vb2_buffer_done(&buf->vb.vb2_buf, VB2_BUF_STATE_ERROR);
  184. }
  185. /* If suspending put unused buffers onto pending queue */
  186. while (!list_empty(&fimc->active_buf_q)) {
  187. buf = fimc_lite_active_queue_pop(fimc);
  188. if (suspend)
  189. fimc_lite_pending_queue_add(fimc, buf);
  190. else
  191. vb2_buffer_done(&buf->vb.vb2_buf, VB2_BUF_STATE_ERROR);
  192. }
  193. spin_unlock_irqrestore(&fimc->slock, flags);
  194. flite_hw_reset(fimc);
  195. if (!streaming)
  196. return 0;
  197. return fimc_pipeline_call(&fimc->ve, set_stream, 0);
  198. }
  199. static int fimc_lite_stop_capture(struct fimc_lite *fimc, bool suspend)
  200. {
  201. unsigned long flags;
  202. if (!fimc_lite_active(fimc))
  203. return 0;
  204. spin_lock_irqsave(&fimc->slock, flags);
  205. set_bit(ST_FLITE_OFF, &fimc->state);
  206. flite_hw_capture_stop(fimc);
  207. spin_unlock_irqrestore(&fimc->slock, flags);
  208. wait_event_timeout(fimc->irq_queue,
  209. !test_bit(ST_FLITE_OFF, &fimc->state),
  210. (2*HZ/10)); /* 200 ms */
  211. return fimc_lite_reinit(fimc, suspend);
  212. }
  213. /* Must be called with fimc.slock spinlock held. */
  214. static void fimc_lite_config_update(struct fimc_lite *fimc)
  215. {
  216. flite_hw_set_window_offset(fimc, &fimc->inp_frame);
  217. flite_hw_set_dma_window(fimc, &fimc->out_frame);
  218. flite_hw_set_test_pattern(fimc, fimc->test_pattern->val);
  219. clear_bit(ST_FLITE_CONFIG, &fimc->state);
  220. }
  221. static irqreturn_t flite_irq_handler(int irq, void *priv)
  222. {
  223. struct fimc_lite *fimc = priv;
  224. struct flite_buffer *vbuf;
  225. unsigned long flags;
  226. u32 intsrc;
  227. spin_lock_irqsave(&fimc->slock, flags);
  228. intsrc = flite_hw_get_interrupt_source(fimc);
  229. flite_hw_clear_pending_irq(fimc);
  230. if (test_and_clear_bit(ST_FLITE_OFF, &fimc->state)) {
  231. wake_up(&fimc->irq_queue);
  232. goto done;
  233. }
  234. if (intsrc & FLITE_REG_CISTATUS_IRQ_SRC_OVERFLOW) {
  235. clear_bit(ST_FLITE_RUN, &fimc->state);
  236. fimc->events.data_overflow++;
  237. }
  238. if (intsrc & FLITE_REG_CISTATUS_IRQ_SRC_LASTCAPEND) {
  239. flite_hw_clear_last_capture_end(fimc);
  240. clear_bit(ST_FLITE_STREAM, &fimc->state);
  241. wake_up(&fimc->irq_queue);
  242. }
  243. if (atomic_read(&fimc->out_path) != FIMC_IO_DMA)
  244. goto done;
  245. if ((intsrc & FLITE_REG_CISTATUS_IRQ_SRC_FRMSTART) &&
  246. test_bit(ST_FLITE_RUN, &fimc->state) &&
  247. !list_empty(&fimc->pending_buf_q)) {
  248. vbuf = fimc_lite_pending_queue_pop(fimc);
  249. flite_hw_set_dma_buffer(fimc, vbuf);
  250. fimc_lite_active_queue_add(fimc, vbuf);
  251. }
  252. if ((intsrc & FLITE_REG_CISTATUS_IRQ_SRC_FRMEND) &&
  253. test_bit(ST_FLITE_RUN, &fimc->state) &&
  254. !list_empty(&fimc->active_buf_q)) {
  255. vbuf = fimc_lite_active_queue_pop(fimc);
  256. v4l2_get_timestamp(&vbuf->vb.timestamp);
  257. vbuf->vb.sequence = fimc->frame_count++;
  258. flite_hw_mask_dma_buffer(fimc, vbuf->index);
  259. vb2_buffer_done(&vbuf->vb.vb2_buf, VB2_BUF_STATE_DONE);
  260. }
  261. if (test_bit(ST_FLITE_CONFIG, &fimc->state))
  262. fimc_lite_config_update(fimc);
  263. if (list_empty(&fimc->pending_buf_q)) {
  264. flite_hw_capture_stop(fimc);
  265. clear_bit(ST_FLITE_STREAM, &fimc->state);
  266. }
  267. done:
  268. set_bit(ST_FLITE_RUN, &fimc->state);
  269. spin_unlock_irqrestore(&fimc->slock, flags);
  270. return IRQ_HANDLED;
  271. }
  272. static int start_streaming(struct vb2_queue *q, unsigned int count)
  273. {
  274. struct fimc_lite *fimc = q->drv_priv;
  275. unsigned long flags;
  276. int ret;
  277. spin_lock_irqsave(&fimc->slock, flags);
  278. fimc->buf_index = 0;
  279. fimc->frame_count = 0;
  280. spin_unlock_irqrestore(&fimc->slock, flags);
  281. ret = fimc_lite_hw_init(fimc, false);
  282. if (ret) {
  283. fimc_lite_reinit(fimc, false);
  284. return ret;
  285. }
  286. set_bit(ST_FLITE_PENDING, &fimc->state);
  287. if (!list_empty(&fimc->active_buf_q) &&
  288. !test_and_set_bit(ST_FLITE_STREAM, &fimc->state)) {
  289. flite_hw_capture_start(fimc);
  290. if (!test_and_set_bit(ST_SENSOR_STREAM, &fimc->state))
  291. fimc_pipeline_call(&fimc->ve, set_stream, 1);
  292. }
  293. if (debug > 0)
  294. flite_hw_dump_regs(fimc, __func__);
  295. return 0;
  296. }
  297. static void stop_streaming(struct vb2_queue *q)
  298. {
  299. struct fimc_lite *fimc = q->drv_priv;
  300. if (!fimc_lite_active(fimc))
  301. return;
  302. fimc_lite_stop_capture(fimc, false);
  303. }
  304. static int queue_setup(struct vb2_queue *vq, const void *parg,
  305. unsigned int *num_buffers, unsigned int *num_planes,
  306. unsigned int sizes[], void *allocators[])
  307. {
  308. const struct v4l2_format *pfmt = parg;
  309. const struct v4l2_pix_format_mplane *pixm = NULL;
  310. struct fimc_lite *fimc = vq->drv_priv;
  311. struct flite_frame *frame = &fimc->out_frame;
  312. const struct fimc_fmt *fmt = frame->fmt;
  313. unsigned long wh;
  314. int i;
  315. if (pfmt) {
  316. pixm = &pfmt->fmt.pix_mp;
  317. fmt = fimc_lite_find_format(&pixm->pixelformat, NULL, 0, -1);
  318. wh = pixm->width * pixm->height;
  319. } else {
  320. wh = frame->f_width * frame->f_height;
  321. }
  322. if (fmt == NULL)
  323. return -EINVAL;
  324. *num_planes = fmt->memplanes;
  325. for (i = 0; i < fmt->memplanes; i++) {
  326. unsigned int size = (wh * fmt->depth[i]) / 8;
  327. if (pixm)
  328. sizes[i] = max(size, pixm->plane_fmt[i].sizeimage);
  329. else
  330. sizes[i] = size;
  331. allocators[i] = fimc->alloc_ctx;
  332. }
  333. return 0;
  334. }
  335. static int buffer_prepare(struct vb2_buffer *vb)
  336. {
  337. struct vb2_queue *vq = vb->vb2_queue;
  338. struct fimc_lite *fimc = vq->drv_priv;
  339. int i;
  340. if (fimc->out_frame.fmt == NULL)
  341. return -EINVAL;
  342. for (i = 0; i < fimc->out_frame.fmt->memplanes; i++) {
  343. unsigned long size = fimc->payload[i];
  344. if (vb2_plane_size(vb, i) < size) {
  345. v4l2_err(&fimc->ve.vdev,
  346. "User buffer too small (%ld < %ld)\n",
  347. vb2_plane_size(vb, i), size);
  348. return -EINVAL;
  349. }
  350. vb2_set_plane_payload(vb, i, size);
  351. }
  352. return 0;
  353. }
  354. static void buffer_queue(struct vb2_buffer *vb)
  355. {
  356. struct vb2_v4l2_buffer *vbuf = to_vb2_v4l2_buffer(vb);
  357. struct flite_buffer *buf
  358. = container_of(vbuf, struct flite_buffer, vb);
  359. struct fimc_lite *fimc = vb2_get_drv_priv(vb->vb2_queue);
  360. unsigned long flags;
  361. spin_lock_irqsave(&fimc->slock, flags);
  362. buf->paddr = vb2_dma_contig_plane_dma_addr(vb, 0);
  363. buf->index = fimc->buf_index++;
  364. if (fimc->buf_index >= fimc->reqbufs_count)
  365. fimc->buf_index = 0;
  366. if (!test_bit(ST_FLITE_SUSPENDED, &fimc->state) &&
  367. !test_bit(ST_FLITE_STREAM, &fimc->state) &&
  368. list_empty(&fimc->active_buf_q)) {
  369. flite_hw_set_dma_buffer(fimc, buf);
  370. fimc_lite_active_queue_add(fimc, buf);
  371. } else {
  372. fimc_lite_pending_queue_add(fimc, buf);
  373. }
  374. if (vb2_is_streaming(&fimc->vb_queue) &&
  375. !list_empty(&fimc->pending_buf_q) &&
  376. !test_and_set_bit(ST_FLITE_STREAM, &fimc->state)) {
  377. flite_hw_capture_start(fimc);
  378. spin_unlock_irqrestore(&fimc->slock, flags);
  379. if (!test_and_set_bit(ST_SENSOR_STREAM, &fimc->state))
  380. fimc_pipeline_call(&fimc->ve, set_stream, 1);
  381. return;
  382. }
  383. spin_unlock_irqrestore(&fimc->slock, flags);
  384. }
  385. static const struct vb2_ops fimc_lite_qops = {
  386. .queue_setup = queue_setup,
  387. .buf_prepare = buffer_prepare,
  388. .buf_queue = buffer_queue,
  389. .wait_prepare = vb2_ops_wait_prepare,
  390. .wait_finish = vb2_ops_wait_finish,
  391. .start_streaming = start_streaming,
  392. .stop_streaming = stop_streaming,
  393. };
  394. static void fimc_lite_clear_event_counters(struct fimc_lite *fimc)
  395. {
  396. unsigned long flags;
  397. spin_lock_irqsave(&fimc->slock, flags);
  398. memset(&fimc->events, 0, sizeof(fimc->events));
  399. spin_unlock_irqrestore(&fimc->slock, flags);
  400. }
  401. static int fimc_lite_open(struct file *file)
  402. {
  403. struct fimc_lite *fimc = video_drvdata(file);
  404. struct media_entity *me = &fimc->ve.vdev.entity;
  405. int ret;
  406. mutex_lock(&fimc->lock);
  407. if (atomic_read(&fimc->out_path) != FIMC_IO_DMA) {
  408. ret = -EBUSY;
  409. goto unlock;
  410. }
  411. set_bit(ST_FLITE_IN_USE, &fimc->state);
  412. ret = pm_runtime_get_sync(&fimc->pdev->dev);
  413. if (ret < 0)
  414. goto unlock;
  415. ret = v4l2_fh_open(file);
  416. if (ret < 0)
  417. goto err_pm;
  418. if (!v4l2_fh_is_singular_file(file) ||
  419. atomic_read(&fimc->out_path) != FIMC_IO_DMA)
  420. goto unlock;
  421. mutex_lock(&me->parent->graph_mutex);
  422. ret = fimc_pipeline_call(&fimc->ve, open, me, true);
  423. /* Mark video pipeline ending at this video node as in use. */
  424. if (ret == 0)
  425. me->use_count++;
  426. mutex_unlock(&me->parent->graph_mutex);
  427. if (!ret) {
  428. fimc_lite_clear_event_counters(fimc);
  429. goto unlock;
  430. }
  431. v4l2_fh_release(file);
  432. err_pm:
  433. pm_runtime_put_sync(&fimc->pdev->dev);
  434. clear_bit(ST_FLITE_IN_USE, &fimc->state);
  435. unlock:
  436. mutex_unlock(&fimc->lock);
  437. return ret;
  438. }
  439. static int fimc_lite_release(struct file *file)
  440. {
  441. struct fimc_lite *fimc = video_drvdata(file);
  442. struct media_entity *entity = &fimc->ve.vdev.entity;
  443. mutex_lock(&fimc->lock);
  444. if (v4l2_fh_is_singular_file(file) &&
  445. atomic_read(&fimc->out_path) == FIMC_IO_DMA) {
  446. if (fimc->streaming) {
  447. media_entity_pipeline_stop(entity);
  448. fimc->streaming = false;
  449. }
  450. fimc_lite_stop_capture(fimc, false);
  451. fimc_pipeline_call(&fimc->ve, close);
  452. clear_bit(ST_FLITE_IN_USE, &fimc->state);
  453. mutex_lock(&entity->parent->graph_mutex);
  454. entity->use_count--;
  455. mutex_unlock(&entity->parent->graph_mutex);
  456. }
  457. _vb2_fop_release(file, NULL);
  458. pm_runtime_put(&fimc->pdev->dev);
  459. clear_bit(ST_FLITE_SUSPENDED, &fimc->state);
  460. mutex_unlock(&fimc->lock);
  461. return 0;
  462. }
  463. static const struct v4l2_file_operations fimc_lite_fops = {
  464. .owner = THIS_MODULE,
  465. .open = fimc_lite_open,
  466. .release = fimc_lite_release,
  467. .poll = vb2_fop_poll,
  468. .unlocked_ioctl = video_ioctl2,
  469. .mmap = vb2_fop_mmap,
  470. };
  471. /*
  472. * Format and crop negotiation helpers
  473. */
  474. static const struct fimc_fmt *fimc_lite_subdev_try_fmt(struct fimc_lite *fimc,
  475. struct v4l2_subdev_pad_config *cfg,
  476. struct v4l2_subdev_format *format)
  477. {
  478. struct flite_drvdata *dd = fimc->dd;
  479. struct v4l2_mbus_framefmt *mf = &format->format;
  480. const struct fimc_fmt *fmt = NULL;
  481. if (format->pad == FLITE_SD_PAD_SINK) {
  482. v4l_bound_align_image(&mf->width, 8, dd->max_width,
  483. ffs(dd->out_width_align) - 1,
  484. &mf->height, 0, dd->max_height, 0, 0);
  485. fmt = fimc_lite_find_format(NULL, &mf->code, 0, 0);
  486. if (WARN_ON(!fmt))
  487. return NULL;
  488. mf->colorspace = fmt->colorspace;
  489. mf->code = fmt->mbus_code;
  490. } else {
  491. struct flite_frame *sink = &fimc->inp_frame;
  492. struct v4l2_mbus_framefmt *sink_fmt;
  493. struct v4l2_rect *rect;
  494. if (format->which == V4L2_SUBDEV_FORMAT_TRY) {
  495. sink_fmt = v4l2_subdev_get_try_format(&fimc->subdev, cfg,
  496. FLITE_SD_PAD_SINK);
  497. mf->code = sink_fmt->code;
  498. mf->colorspace = sink_fmt->colorspace;
  499. rect = v4l2_subdev_get_try_crop(&fimc->subdev, cfg,
  500. FLITE_SD_PAD_SINK);
  501. } else {
  502. mf->code = sink->fmt->mbus_code;
  503. mf->colorspace = sink->fmt->colorspace;
  504. rect = &sink->rect;
  505. }
  506. /* Allow changing format only on sink pad */
  507. mf->width = rect->width;
  508. mf->height = rect->height;
  509. }
  510. mf->field = V4L2_FIELD_NONE;
  511. v4l2_dbg(1, debug, &fimc->subdev, "code: %#x (%d), %dx%d\n",
  512. mf->code, mf->colorspace, mf->width, mf->height);
  513. return fmt;
  514. }
  515. static void fimc_lite_try_crop(struct fimc_lite *fimc, struct v4l2_rect *r)
  516. {
  517. struct flite_frame *frame = &fimc->inp_frame;
  518. v4l_bound_align_image(&r->width, 0, frame->f_width, 0,
  519. &r->height, 0, frame->f_height, 0, 0);
  520. /* Adjust left/top if cropping rectangle got out of bounds */
  521. r->left = clamp_t(u32, r->left, 0, frame->f_width - r->width);
  522. r->left = round_down(r->left, fimc->dd->win_hor_offs_align);
  523. r->top = clamp_t(u32, r->top, 0, frame->f_height - r->height);
  524. v4l2_dbg(1, debug, &fimc->subdev, "(%d,%d)/%dx%d, sink fmt: %dx%d\n",
  525. r->left, r->top, r->width, r->height,
  526. frame->f_width, frame->f_height);
  527. }
  528. static void fimc_lite_try_compose(struct fimc_lite *fimc, struct v4l2_rect *r)
  529. {
  530. struct flite_frame *frame = &fimc->out_frame;
  531. struct v4l2_rect *crop_rect = &fimc->inp_frame.rect;
  532. /* Scaling is not supported so we enforce compose rectangle size
  533. same as size of the sink crop rectangle. */
  534. r->width = crop_rect->width;
  535. r->height = crop_rect->height;
  536. /* Adjust left/top if the composing rectangle got out of bounds */
  537. r->left = clamp_t(u32, r->left, 0, frame->f_width - r->width);
  538. r->left = round_down(r->left, fimc->dd->out_hor_offs_align);
  539. r->top = clamp_t(u32, r->top, 0, fimc->out_frame.f_height - r->height);
  540. v4l2_dbg(1, debug, &fimc->subdev, "(%d,%d)/%dx%d, source fmt: %dx%d\n",
  541. r->left, r->top, r->width, r->height,
  542. frame->f_width, frame->f_height);
  543. }
  544. /*
  545. * Video node ioctl operations
  546. */
  547. static int fimc_lite_querycap(struct file *file, void *priv,
  548. struct v4l2_capability *cap)
  549. {
  550. struct fimc_lite *fimc = video_drvdata(file);
  551. strlcpy(cap->driver, FIMC_LITE_DRV_NAME, sizeof(cap->driver));
  552. strlcpy(cap->card, FIMC_LITE_DRV_NAME, sizeof(cap->card));
  553. snprintf(cap->bus_info, sizeof(cap->bus_info), "platform:%s",
  554. dev_name(&fimc->pdev->dev));
  555. cap->device_caps = V4L2_CAP_STREAMING;
  556. cap->capabilities = cap->device_caps | V4L2_CAP_DEVICE_CAPS;
  557. return 0;
  558. }
  559. static int fimc_lite_enum_fmt_mplane(struct file *file, void *priv,
  560. struct v4l2_fmtdesc *f)
  561. {
  562. const struct fimc_fmt *fmt;
  563. if (f->index >= ARRAY_SIZE(fimc_lite_formats))
  564. return -EINVAL;
  565. fmt = &fimc_lite_formats[f->index];
  566. strlcpy(f->description, fmt->name, sizeof(f->description));
  567. f->pixelformat = fmt->fourcc;
  568. return 0;
  569. }
  570. static int fimc_lite_g_fmt_mplane(struct file *file, void *fh,
  571. struct v4l2_format *f)
  572. {
  573. struct fimc_lite *fimc = video_drvdata(file);
  574. struct v4l2_pix_format_mplane *pixm = &f->fmt.pix_mp;
  575. struct v4l2_plane_pix_format *plane_fmt = &pixm->plane_fmt[0];
  576. struct flite_frame *frame = &fimc->out_frame;
  577. const struct fimc_fmt *fmt = frame->fmt;
  578. plane_fmt->bytesperline = (frame->f_width * fmt->depth[0]) / 8;
  579. plane_fmt->sizeimage = plane_fmt->bytesperline * frame->f_height;
  580. pixm->num_planes = fmt->memplanes;
  581. pixm->pixelformat = fmt->fourcc;
  582. pixm->width = frame->f_width;
  583. pixm->height = frame->f_height;
  584. pixm->field = V4L2_FIELD_NONE;
  585. pixm->colorspace = fmt->colorspace;
  586. return 0;
  587. }
  588. static int fimc_lite_try_fmt(struct fimc_lite *fimc,
  589. struct v4l2_pix_format_mplane *pixm,
  590. const struct fimc_fmt **ffmt)
  591. {
  592. u32 bpl = pixm->plane_fmt[0].bytesperline;
  593. struct flite_drvdata *dd = fimc->dd;
  594. const struct fimc_fmt *inp_fmt = fimc->inp_frame.fmt;
  595. const struct fimc_fmt *fmt;
  596. if (WARN_ON(inp_fmt == NULL))
  597. return -EINVAL;
  598. /*
  599. * We allow some flexibility only for YUV formats. In case of raw
  600. * raw Bayer the FIMC-LITE's output format must match its camera
  601. * interface input format.
  602. */
  603. if (inp_fmt->flags & FMT_FLAGS_YUV)
  604. fmt = fimc_lite_find_format(&pixm->pixelformat, NULL,
  605. inp_fmt->flags, 0);
  606. else
  607. fmt = inp_fmt;
  608. if (WARN_ON(fmt == NULL))
  609. return -EINVAL;
  610. if (ffmt)
  611. *ffmt = fmt;
  612. v4l_bound_align_image(&pixm->width, 8, dd->max_width,
  613. ffs(dd->out_width_align) - 1,
  614. &pixm->height, 0, dd->max_height, 0, 0);
  615. if ((bpl == 0 || ((bpl * 8) / fmt->depth[0]) < pixm->width))
  616. pixm->plane_fmt[0].bytesperline = (pixm->width *
  617. fmt->depth[0]) / 8;
  618. if (pixm->plane_fmt[0].sizeimage == 0)
  619. pixm->plane_fmt[0].sizeimage = (pixm->width * pixm->height *
  620. fmt->depth[0]) / 8;
  621. pixm->num_planes = fmt->memplanes;
  622. pixm->pixelformat = fmt->fourcc;
  623. pixm->colorspace = fmt->colorspace;
  624. pixm->field = V4L2_FIELD_NONE;
  625. return 0;
  626. }
  627. static int fimc_lite_try_fmt_mplane(struct file *file, void *fh,
  628. struct v4l2_format *f)
  629. {
  630. struct fimc_lite *fimc = video_drvdata(file);
  631. return fimc_lite_try_fmt(fimc, &f->fmt.pix_mp, NULL);
  632. }
  633. static int fimc_lite_s_fmt_mplane(struct file *file, void *priv,
  634. struct v4l2_format *f)
  635. {
  636. struct v4l2_pix_format_mplane *pixm = &f->fmt.pix_mp;
  637. struct fimc_lite *fimc = video_drvdata(file);
  638. struct flite_frame *frame = &fimc->out_frame;
  639. const struct fimc_fmt *fmt = NULL;
  640. int ret;
  641. if (vb2_is_busy(&fimc->vb_queue))
  642. return -EBUSY;
  643. ret = fimc_lite_try_fmt(fimc, &f->fmt.pix_mp, &fmt);
  644. if (ret < 0)
  645. return ret;
  646. frame->fmt = fmt;
  647. fimc->payload[0] = max((pixm->width * pixm->height * fmt->depth[0]) / 8,
  648. pixm->plane_fmt[0].sizeimage);
  649. frame->f_width = pixm->width;
  650. frame->f_height = pixm->height;
  651. return 0;
  652. }
  653. static int fimc_pipeline_validate(struct fimc_lite *fimc)
  654. {
  655. struct v4l2_subdev *sd = &fimc->subdev;
  656. struct v4l2_subdev_format sink_fmt, src_fmt;
  657. struct media_pad *pad;
  658. int ret;
  659. while (1) {
  660. /* Retrieve format at the sink pad */
  661. pad = &sd->entity.pads[0];
  662. if (!(pad->flags & MEDIA_PAD_FL_SINK))
  663. break;
  664. /* Don't call FIMC subdev operation to avoid nested locking */
  665. if (sd == &fimc->subdev) {
  666. struct flite_frame *ff = &fimc->out_frame;
  667. sink_fmt.format.width = ff->f_width;
  668. sink_fmt.format.height = ff->f_height;
  669. sink_fmt.format.code = fimc->inp_frame.fmt->mbus_code;
  670. } else {
  671. sink_fmt.pad = pad->index;
  672. sink_fmt.which = V4L2_SUBDEV_FORMAT_ACTIVE;
  673. ret = v4l2_subdev_call(sd, pad, get_fmt, NULL,
  674. &sink_fmt);
  675. if (ret < 0 && ret != -ENOIOCTLCMD)
  676. return -EPIPE;
  677. }
  678. /* Retrieve format at the source pad */
  679. pad = media_entity_remote_pad(pad);
  680. if (pad == NULL ||
  681. media_entity_type(pad->entity) != MEDIA_ENT_T_V4L2_SUBDEV)
  682. break;
  683. sd = media_entity_to_v4l2_subdev(pad->entity);
  684. src_fmt.pad = pad->index;
  685. src_fmt.which = V4L2_SUBDEV_FORMAT_ACTIVE;
  686. ret = v4l2_subdev_call(sd, pad, get_fmt, NULL, &src_fmt);
  687. if (ret < 0 && ret != -ENOIOCTLCMD)
  688. return -EPIPE;
  689. if (src_fmt.format.width != sink_fmt.format.width ||
  690. src_fmt.format.height != sink_fmt.format.height ||
  691. src_fmt.format.code != sink_fmt.format.code)
  692. return -EPIPE;
  693. }
  694. return 0;
  695. }
  696. static int fimc_lite_streamon(struct file *file, void *priv,
  697. enum v4l2_buf_type type)
  698. {
  699. struct fimc_lite *fimc = video_drvdata(file);
  700. struct media_entity *entity = &fimc->ve.vdev.entity;
  701. int ret;
  702. if (fimc_lite_active(fimc))
  703. return -EBUSY;
  704. ret = media_entity_pipeline_start(entity, &fimc->ve.pipe->mp);
  705. if (ret < 0)
  706. return ret;
  707. ret = fimc_pipeline_validate(fimc);
  708. if (ret < 0)
  709. goto err_p_stop;
  710. fimc->sensor = fimc_find_remote_sensor(&fimc->subdev.entity);
  711. ret = vb2_ioctl_streamon(file, priv, type);
  712. if (!ret) {
  713. fimc->streaming = true;
  714. return ret;
  715. }
  716. err_p_stop:
  717. media_entity_pipeline_stop(entity);
  718. return 0;
  719. }
  720. static int fimc_lite_streamoff(struct file *file, void *priv,
  721. enum v4l2_buf_type type)
  722. {
  723. struct fimc_lite *fimc = video_drvdata(file);
  724. int ret;
  725. ret = vb2_ioctl_streamoff(file, priv, type);
  726. if (ret < 0)
  727. return ret;
  728. media_entity_pipeline_stop(&fimc->ve.vdev.entity);
  729. fimc->streaming = false;
  730. return 0;
  731. }
  732. static int fimc_lite_reqbufs(struct file *file, void *priv,
  733. struct v4l2_requestbuffers *reqbufs)
  734. {
  735. struct fimc_lite *fimc = video_drvdata(file);
  736. int ret;
  737. reqbufs->count = max_t(u32, FLITE_REQ_BUFS_MIN, reqbufs->count);
  738. ret = vb2_ioctl_reqbufs(file, priv, reqbufs);
  739. if (!ret)
  740. fimc->reqbufs_count = reqbufs->count;
  741. return ret;
  742. }
  743. /* Return 1 if rectangle a is enclosed in rectangle b, or 0 otherwise. */
  744. static int enclosed_rectangle(struct v4l2_rect *a, struct v4l2_rect *b)
  745. {
  746. if (a->left < b->left || a->top < b->top)
  747. return 0;
  748. if (a->left + a->width > b->left + b->width)
  749. return 0;
  750. if (a->top + a->height > b->top + b->height)
  751. return 0;
  752. return 1;
  753. }
  754. static int fimc_lite_g_selection(struct file *file, void *fh,
  755. struct v4l2_selection *sel)
  756. {
  757. struct fimc_lite *fimc = video_drvdata(file);
  758. struct flite_frame *f = &fimc->out_frame;
  759. if (sel->type != V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE)
  760. return -EINVAL;
  761. switch (sel->target) {
  762. case V4L2_SEL_TGT_COMPOSE_BOUNDS:
  763. case V4L2_SEL_TGT_COMPOSE_DEFAULT:
  764. sel->r.left = 0;
  765. sel->r.top = 0;
  766. sel->r.width = f->f_width;
  767. sel->r.height = f->f_height;
  768. return 0;
  769. case V4L2_SEL_TGT_COMPOSE:
  770. sel->r = f->rect;
  771. return 0;
  772. }
  773. return -EINVAL;
  774. }
  775. static int fimc_lite_s_selection(struct file *file, void *fh,
  776. struct v4l2_selection *sel)
  777. {
  778. struct fimc_lite *fimc = video_drvdata(file);
  779. struct flite_frame *f = &fimc->out_frame;
  780. struct v4l2_rect rect = sel->r;
  781. unsigned long flags;
  782. if (sel->type != V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE ||
  783. sel->target != V4L2_SEL_TGT_COMPOSE)
  784. return -EINVAL;
  785. fimc_lite_try_compose(fimc, &rect);
  786. if ((sel->flags & V4L2_SEL_FLAG_LE) &&
  787. !enclosed_rectangle(&rect, &sel->r))
  788. return -ERANGE;
  789. if ((sel->flags & V4L2_SEL_FLAG_GE) &&
  790. !enclosed_rectangle(&sel->r, &rect))
  791. return -ERANGE;
  792. sel->r = rect;
  793. spin_lock_irqsave(&fimc->slock, flags);
  794. f->rect = rect;
  795. set_bit(ST_FLITE_CONFIG, &fimc->state);
  796. spin_unlock_irqrestore(&fimc->slock, flags);
  797. return 0;
  798. }
  799. static const struct v4l2_ioctl_ops fimc_lite_ioctl_ops = {
  800. .vidioc_querycap = fimc_lite_querycap,
  801. .vidioc_enum_fmt_vid_cap_mplane = fimc_lite_enum_fmt_mplane,
  802. .vidioc_try_fmt_vid_cap_mplane = fimc_lite_try_fmt_mplane,
  803. .vidioc_s_fmt_vid_cap_mplane = fimc_lite_s_fmt_mplane,
  804. .vidioc_g_fmt_vid_cap_mplane = fimc_lite_g_fmt_mplane,
  805. .vidioc_g_selection = fimc_lite_g_selection,
  806. .vidioc_s_selection = fimc_lite_s_selection,
  807. .vidioc_reqbufs = fimc_lite_reqbufs,
  808. .vidioc_querybuf = vb2_ioctl_querybuf,
  809. .vidioc_prepare_buf = vb2_ioctl_prepare_buf,
  810. .vidioc_create_bufs = vb2_ioctl_create_bufs,
  811. .vidioc_qbuf = vb2_ioctl_qbuf,
  812. .vidioc_dqbuf = vb2_ioctl_dqbuf,
  813. .vidioc_streamon = fimc_lite_streamon,
  814. .vidioc_streamoff = fimc_lite_streamoff,
  815. };
  816. /* Capture subdev media entity operations */
  817. static int fimc_lite_link_setup(struct media_entity *entity,
  818. const struct media_pad *local,
  819. const struct media_pad *remote, u32 flags)
  820. {
  821. struct v4l2_subdev *sd = media_entity_to_v4l2_subdev(entity);
  822. struct fimc_lite *fimc = v4l2_get_subdevdata(sd);
  823. unsigned int remote_ent_type = media_entity_type(remote->entity);
  824. int ret = 0;
  825. if (WARN_ON(fimc == NULL))
  826. return 0;
  827. v4l2_dbg(1, debug, sd, "%s: %s --> %s, flags: 0x%x. source_id: 0x%x\n",
  828. __func__, remote->entity->name, local->entity->name,
  829. flags, fimc->source_subdev_grp_id);
  830. switch (local->index) {
  831. case FLITE_SD_PAD_SINK:
  832. if (remote_ent_type != MEDIA_ENT_T_V4L2_SUBDEV) {
  833. ret = -EINVAL;
  834. break;
  835. }
  836. if (flags & MEDIA_LNK_FL_ENABLED) {
  837. if (fimc->source_subdev_grp_id == 0)
  838. fimc->source_subdev_grp_id = sd->grp_id;
  839. else
  840. ret = -EBUSY;
  841. } else {
  842. fimc->source_subdev_grp_id = 0;
  843. fimc->sensor = NULL;
  844. }
  845. break;
  846. case FLITE_SD_PAD_SOURCE_DMA:
  847. if (!(flags & MEDIA_LNK_FL_ENABLED))
  848. atomic_set(&fimc->out_path, FIMC_IO_NONE);
  849. else if (remote_ent_type == MEDIA_ENT_T_DEVNODE)
  850. atomic_set(&fimc->out_path, FIMC_IO_DMA);
  851. else
  852. ret = -EINVAL;
  853. break;
  854. case FLITE_SD_PAD_SOURCE_ISP:
  855. if (!(flags & MEDIA_LNK_FL_ENABLED))
  856. atomic_set(&fimc->out_path, FIMC_IO_NONE);
  857. else if (remote_ent_type == MEDIA_ENT_T_V4L2_SUBDEV)
  858. atomic_set(&fimc->out_path, FIMC_IO_ISP);
  859. else
  860. ret = -EINVAL;
  861. break;
  862. default:
  863. v4l2_err(sd, "Invalid pad index\n");
  864. ret = -EINVAL;
  865. }
  866. mb();
  867. return ret;
  868. }
  869. static const struct media_entity_operations fimc_lite_subdev_media_ops = {
  870. .link_setup = fimc_lite_link_setup,
  871. };
  872. static int fimc_lite_subdev_enum_mbus_code(struct v4l2_subdev *sd,
  873. struct v4l2_subdev_pad_config *cfg,
  874. struct v4l2_subdev_mbus_code_enum *code)
  875. {
  876. const struct fimc_fmt *fmt;
  877. fmt = fimc_lite_find_format(NULL, NULL, 0, code->index);
  878. if (!fmt)
  879. return -EINVAL;
  880. code->code = fmt->mbus_code;
  881. return 0;
  882. }
  883. static struct v4l2_mbus_framefmt *__fimc_lite_subdev_get_try_fmt(
  884. struct v4l2_subdev *sd,
  885. struct v4l2_subdev_pad_config *cfg, unsigned int pad)
  886. {
  887. if (pad != FLITE_SD_PAD_SINK)
  888. pad = FLITE_SD_PAD_SOURCE_DMA;
  889. return v4l2_subdev_get_try_format(sd, cfg, pad);
  890. }
  891. static int fimc_lite_subdev_get_fmt(struct v4l2_subdev *sd,
  892. struct v4l2_subdev_pad_config *cfg,
  893. struct v4l2_subdev_format *fmt)
  894. {
  895. struct fimc_lite *fimc = v4l2_get_subdevdata(sd);
  896. struct v4l2_mbus_framefmt *mf = &fmt->format;
  897. struct flite_frame *f = &fimc->inp_frame;
  898. if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
  899. mf = __fimc_lite_subdev_get_try_fmt(sd, cfg, fmt->pad);
  900. fmt->format = *mf;
  901. return 0;
  902. }
  903. mutex_lock(&fimc->lock);
  904. mf->colorspace = f->fmt->colorspace;
  905. mf->code = f->fmt->mbus_code;
  906. if (fmt->pad == FLITE_SD_PAD_SINK) {
  907. /* full camera input frame size */
  908. mf->width = f->f_width;
  909. mf->height = f->f_height;
  910. } else {
  911. /* crop size */
  912. mf->width = f->rect.width;
  913. mf->height = f->rect.height;
  914. }
  915. mutex_unlock(&fimc->lock);
  916. return 0;
  917. }
  918. static int fimc_lite_subdev_set_fmt(struct v4l2_subdev *sd,
  919. struct v4l2_subdev_pad_config *cfg,
  920. struct v4l2_subdev_format *fmt)
  921. {
  922. struct fimc_lite *fimc = v4l2_get_subdevdata(sd);
  923. struct v4l2_mbus_framefmt *mf = &fmt->format;
  924. struct flite_frame *sink = &fimc->inp_frame;
  925. struct flite_frame *source = &fimc->out_frame;
  926. const struct fimc_fmt *ffmt;
  927. v4l2_dbg(1, debug, sd, "pad%d: code: 0x%x, %dx%d\n",
  928. fmt->pad, mf->code, mf->width, mf->height);
  929. mutex_lock(&fimc->lock);
  930. if ((atomic_read(&fimc->out_path) == FIMC_IO_ISP &&
  931. sd->entity.stream_count > 0) ||
  932. (atomic_read(&fimc->out_path) == FIMC_IO_DMA &&
  933. vb2_is_busy(&fimc->vb_queue))) {
  934. mutex_unlock(&fimc->lock);
  935. return -EBUSY;
  936. }
  937. ffmt = fimc_lite_subdev_try_fmt(fimc, cfg, fmt);
  938. if (fmt->which == V4L2_SUBDEV_FORMAT_TRY) {
  939. struct v4l2_mbus_framefmt *src_fmt;
  940. mf = __fimc_lite_subdev_get_try_fmt(sd, cfg, fmt->pad);
  941. *mf = fmt->format;
  942. if (fmt->pad == FLITE_SD_PAD_SINK) {
  943. unsigned int pad = FLITE_SD_PAD_SOURCE_DMA;
  944. src_fmt = __fimc_lite_subdev_get_try_fmt(sd, cfg, pad);
  945. *src_fmt = *mf;
  946. }
  947. mutex_unlock(&fimc->lock);
  948. return 0;
  949. }
  950. if (fmt->pad == FLITE_SD_PAD_SINK) {
  951. sink->f_width = mf->width;
  952. sink->f_height = mf->height;
  953. sink->fmt = ffmt;
  954. /* Set sink crop rectangle */
  955. sink->rect.width = mf->width;
  956. sink->rect.height = mf->height;
  957. sink->rect.left = 0;
  958. sink->rect.top = 0;
  959. /* Reset source format and crop rectangle */
  960. source->rect = sink->rect;
  961. source->f_width = mf->width;
  962. source->f_height = mf->height;
  963. }
  964. mutex_unlock(&fimc->lock);
  965. return 0;
  966. }
  967. static int fimc_lite_subdev_get_selection(struct v4l2_subdev *sd,
  968. struct v4l2_subdev_pad_config *cfg,
  969. struct v4l2_subdev_selection *sel)
  970. {
  971. struct fimc_lite *fimc = v4l2_get_subdevdata(sd);
  972. struct flite_frame *f = &fimc->inp_frame;
  973. if ((sel->target != V4L2_SEL_TGT_CROP &&
  974. sel->target != V4L2_SEL_TGT_CROP_BOUNDS) ||
  975. sel->pad != FLITE_SD_PAD_SINK)
  976. return -EINVAL;
  977. if (sel->which == V4L2_SUBDEV_FORMAT_TRY) {
  978. sel->r = *v4l2_subdev_get_try_crop(sd, cfg, sel->pad);
  979. return 0;
  980. }
  981. mutex_lock(&fimc->lock);
  982. if (sel->target == V4L2_SEL_TGT_CROP) {
  983. sel->r = f->rect;
  984. } else {
  985. sel->r.left = 0;
  986. sel->r.top = 0;
  987. sel->r.width = f->f_width;
  988. sel->r.height = f->f_height;
  989. }
  990. mutex_unlock(&fimc->lock);
  991. v4l2_dbg(1, debug, sd, "%s: (%d,%d) %dx%d, f_w: %d, f_h: %d\n",
  992. __func__, f->rect.left, f->rect.top, f->rect.width,
  993. f->rect.height, f->f_width, f->f_height);
  994. return 0;
  995. }
  996. static int fimc_lite_subdev_set_selection(struct v4l2_subdev *sd,
  997. struct v4l2_subdev_pad_config *cfg,
  998. struct v4l2_subdev_selection *sel)
  999. {
  1000. struct fimc_lite *fimc = v4l2_get_subdevdata(sd);
  1001. struct flite_frame *f = &fimc->inp_frame;
  1002. int ret = 0;
  1003. if (sel->target != V4L2_SEL_TGT_CROP || sel->pad != FLITE_SD_PAD_SINK)
  1004. return -EINVAL;
  1005. mutex_lock(&fimc->lock);
  1006. fimc_lite_try_crop(fimc, &sel->r);
  1007. if (sel->which == V4L2_SUBDEV_FORMAT_TRY) {
  1008. *v4l2_subdev_get_try_crop(sd, cfg, sel->pad) = sel->r;
  1009. } else {
  1010. unsigned long flags;
  1011. spin_lock_irqsave(&fimc->slock, flags);
  1012. f->rect = sel->r;
  1013. /* Same crop rectangle on the source pad */
  1014. fimc->out_frame.rect = sel->r;
  1015. set_bit(ST_FLITE_CONFIG, &fimc->state);
  1016. spin_unlock_irqrestore(&fimc->slock, flags);
  1017. }
  1018. mutex_unlock(&fimc->lock);
  1019. v4l2_dbg(1, debug, sd, "%s: (%d,%d) %dx%d, f_w: %d, f_h: %d\n",
  1020. __func__, f->rect.left, f->rect.top, f->rect.width,
  1021. f->rect.height, f->f_width, f->f_height);
  1022. return ret;
  1023. }
  1024. static int fimc_lite_subdev_s_stream(struct v4l2_subdev *sd, int on)
  1025. {
  1026. struct fimc_lite *fimc = v4l2_get_subdevdata(sd);
  1027. unsigned long flags;
  1028. int ret;
  1029. /*
  1030. * Find sensor subdev linked to FIMC-LITE directly or through
  1031. * MIPI-CSIS. This is required for configuration where FIMC-LITE
  1032. * is used as a subdev only and feeds data internally to FIMC-IS.
  1033. * The pipeline links are protected through entity.stream_count
  1034. * so there is no need to take the media graph mutex here.
  1035. */
  1036. fimc->sensor = fimc_find_remote_sensor(&sd->entity);
  1037. if (atomic_read(&fimc->out_path) != FIMC_IO_ISP)
  1038. return -ENOIOCTLCMD;
  1039. mutex_lock(&fimc->lock);
  1040. if (on) {
  1041. flite_hw_reset(fimc);
  1042. ret = fimc_lite_hw_init(fimc, true);
  1043. if (!ret) {
  1044. spin_lock_irqsave(&fimc->slock, flags);
  1045. flite_hw_capture_start(fimc);
  1046. spin_unlock_irqrestore(&fimc->slock, flags);
  1047. }
  1048. } else {
  1049. set_bit(ST_FLITE_OFF, &fimc->state);
  1050. spin_lock_irqsave(&fimc->slock, flags);
  1051. flite_hw_capture_stop(fimc);
  1052. spin_unlock_irqrestore(&fimc->slock, flags);
  1053. ret = wait_event_timeout(fimc->irq_queue,
  1054. !test_bit(ST_FLITE_OFF, &fimc->state),
  1055. msecs_to_jiffies(200));
  1056. if (ret == 0)
  1057. v4l2_err(sd, "s_stream(0) timeout\n");
  1058. clear_bit(ST_FLITE_RUN, &fimc->state);
  1059. }
  1060. mutex_unlock(&fimc->lock);
  1061. return ret;
  1062. }
  1063. static int fimc_lite_log_status(struct v4l2_subdev *sd)
  1064. {
  1065. struct fimc_lite *fimc = v4l2_get_subdevdata(sd);
  1066. flite_hw_dump_regs(fimc, __func__);
  1067. return 0;
  1068. }
  1069. static int fimc_lite_subdev_registered(struct v4l2_subdev *sd)
  1070. {
  1071. struct fimc_lite *fimc = v4l2_get_subdevdata(sd);
  1072. struct vb2_queue *q = &fimc->vb_queue;
  1073. struct video_device *vfd = &fimc->ve.vdev;
  1074. int ret;
  1075. memset(vfd, 0, sizeof(*vfd));
  1076. atomic_set(&fimc->out_path, FIMC_IO_DMA);
  1077. snprintf(vfd->name, sizeof(vfd->name), "fimc-lite.%d.capture",
  1078. fimc->index);
  1079. vfd->fops = &fimc_lite_fops;
  1080. vfd->ioctl_ops = &fimc_lite_ioctl_ops;
  1081. vfd->v4l2_dev = sd->v4l2_dev;
  1082. vfd->minor = -1;
  1083. vfd->release = video_device_release_empty;
  1084. vfd->queue = q;
  1085. fimc->reqbufs_count = 0;
  1086. INIT_LIST_HEAD(&fimc->pending_buf_q);
  1087. INIT_LIST_HEAD(&fimc->active_buf_q);
  1088. memset(q, 0, sizeof(*q));
  1089. q->type = V4L2_BUF_TYPE_VIDEO_CAPTURE_MPLANE;
  1090. q->io_modes = VB2_MMAP | VB2_USERPTR;
  1091. q->ops = &fimc_lite_qops;
  1092. q->mem_ops = &vb2_dma_contig_memops;
  1093. q->buf_struct_size = sizeof(struct flite_buffer);
  1094. q->drv_priv = fimc;
  1095. q->timestamp_flags = V4L2_BUF_FLAG_TIMESTAMP_MONOTONIC;
  1096. q->lock = &fimc->lock;
  1097. ret = vb2_queue_init(q);
  1098. if (ret < 0)
  1099. return ret;
  1100. fimc->vd_pad.flags = MEDIA_PAD_FL_SINK;
  1101. ret = media_entity_init(&vfd->entity, 1, &fimc->vd_pad, 0);
  1102. if (ret < 0)
  1103. return ret;
  1104. video_set_drvdata(vfd, fimc);
  1105. fimc->ve.pipe = v4l2_get_subdev_hostdata(sd);
  1106. ret = video_register_device(vfd, VFL_TYPE_GRABBER, -1);
  1107. if (ret < 0) {
  1108. media_entity_cleanup(&vfd->entity);
  1109. fimc->ve.pipe = NULL;
  1110. return ret;
  1111. }
  1112. v4l2_info(sd->v4l2_dev, "Registered %s as /dev/%s\n",
  1113. vfd->name, video_device_node_name(vfd));
  1114. return 0;
  1115. }
  1116. static void fimc_lite_subdev_unregistered(struct v4l2_subdev *sd)
  1117. {
  1118. struct fimc_lite *fimc = v4l2_get_subdevdata(sd);
  1119. if (fimc == NULL)
  1120. return;
  1121. mutex_lock(&fimc->lock);
  1122. if (video_is_registered(&fimc->ve.vdev)) {
  1123. video_unregister_device(&fimc->ve.vdev);
  1124. media_entity_cleanup(&fimc->ve.vdev.entity);
  1125. fimc->ve.pipe = NULL;
  1126. }
  1127. mutex_unlock(&fimc->lock);
  1128. }
  1129. static const struct v4l2_subdev_internal_ops fimc_lite_subdev_internal_ops = {
  1130. .registered = fimc_lite_subdev_registered,
  1131. .unregistered = fimc_lite_subdev_unregistered,
  1132. };
  1133. static const struct v4l2_subdev_pad_ops fimc_lite_subdev_pad_ops = {
  1134. .enum_mbus_code = fimc_lite_subdev_enum_mbus_code,
  1135. .get_selection = fimc_lite_subdev_get_selection,
  1136. .set_selection = fimc_lite_subdev_set_selection,
  1137. .get_fmt = fimc_lite_subdev_get_fmt,
  1138. .set_fmt = fimc_lite_subdev_set_fmt,
  1139. };
  1140. static const struct v4l2_subdev_video_ops fimc_lite_subdev_video_ops = {
  1141. .s_stream = fimc_lite_subdev_s_stream,
  1142. };
  1143. static const struct v4l2_subdev_core_ops fimc_lite_core_ops = {
  1144. .log_status = fimc_lite_log_status,
  1145. };
  1146. static struct v4l2_subdev_ops fimc_lite_subdev_ops = {
  1147. .core = &fimc_lite_core_ops,
  1148. .video = &fimc_lite_subdev_video_ops,
  1149. .pad = &fimc_lite_subdev_pad_ops,
  1150. };
  1151. static int fimc_lite_s_ctrl(struct v4l2_ctrl *ctrl)
  1152. {
  1153. struct fimc_lite *fimc = container_of(ctrl->handler, struct fimc_lite,
  1154. ctrl_handler);
  1155. set_bit(ST_FLITE_CONFIG, &fimc->state);
  1156. return 0;
  1157. }
  1158. static const struct v4l2_ctrl_ops fimc_lite_ctrl_ops = {
  1159. .s_ctrl = fimc_lite_s_ctrl,
  1160. };
  1161. static const struct v4l2_ctrl_config fimc_lite_ctrl = {
  1162. .ops = &fimc_lite_ctrl_ops,
  1163. .id = V4L2_CTRL_CLASS_USER | 0x1001,
  1164. .type = V4L2_CTRL_TYPE_BOOLEAN,
  1165. .name = "Test Pattern 640x480",
  1166. .step = 1,
  1167. };
  1168. static void fimc_lite_set_default_config(struct fimc_lite *fimc)
  1169. {
  1170. struct flite_frame *sink = &fimc->inp_frame;
  1171. struct flite_frame *source = &fimc->out_frame;
  1172. sink->fmt = &fimc_lite_formats[0];
  1173. sink->f_width = FLITE_DEFAULT_WIDTH;
  1174. sink->f_height = FLITE_DEFAULT_HEIGHT;
  1175. sink->rect.width = FLITE_DEFAULT_WIDTH;
  1176. sink->rect.height = FLITE_DEFAULT_HEIGHT;
  1177. sink->rect.left = 0;
  1178. sink->rect.top = 0;
  1179. *source = *sink;
  1180. }
  1181. static int fimc_lite_create_capture_subdev(struct fimc_lite *fimc)
  1182. {
  1183. struct v4l2_ctrl_handler *handler = &fimc->ctrl_handler;
  1184. struct v4l2_subdev *sd = &fimc->subdev;
  1185. int ret;
  1186. v4l2_subdev_init(sd, &fimc_lite_subdev_ops);
  1187. sd->flags |= V4L2_SUBDEV_FL_HAS_DEVNODE;
  1188. snprintf(sd->name, sizeof(sd->name), "FIMC-LITE.%d", fimc->index);
  1189. fimc->subdev_pads[FLITE_SD_PAD_SINK].flags = MEDIA_PAD_FL_SINK;
  1190. fimc->subdev_pads[FLITE_SD_PAD_SOURCE_DMA].flags = MEDIA_PAD_FL_SOURCE;
  1191. fimc->subdev_pads[FLITE_SD_PAD_SOURCE_ISP].flags = MEDIA_PAD_FL_SOURCE;
  1192. ret = media_entity_init(&sd->entity, FLITE_SD_PADS_NUM,
  1193. fimc->subdev_pads, 0);
  1194. if (ret)
  1195. return ret;
  1196. v4l2_ctrl_handler_init(handler, 1);
  1197. fimc->test_pattern = v4l2_ctrl_new_custom(handler, &fimc_lite_ctrl,
  1198. NULL);
  1199. if (handler->error) {
  1200. media_entity_cleanup(&sd->entity);
  1201. return handler->error;
  1202. }
  1203. sd->ctrl_handler = handler;
  1204. sd->internal_ops = &fimc_lite_subdev_internal_ops;
  1205. sd->entity.ops = &fimc_lite_subdev_media_ops;
  1206. sd->owner = THIS_MODULE;
  1207. v4l2_set_subdevdata(sd, fimc);
  1208. return 0;
  1209. }
  1210. static void fimc_lite_unregister_capture_subdev(struct fimc_lite *fimc)
  1211. {
  1212. struct v4l2_subdev *sd = &fimc->subdev;
  1213. v4l2_device_unregister_subdev(sd);
  1214. media_entity_cleanup(&sd->entity);
  1215. v4l2_ctrl_handler_free(&fimc->ctrl_handler);
  1216. v4l2_set_subdevdata(sd, NULL);
  1217. }
  1218. static void fimc_lite_clk_put(struct fimc_lite *fimc)
  1219. {
  1220. if (IS_ERR(fimc->clock))
  1221. return;
  1222. clk_unprepare(fimc->clock);
  1223. clk_put(fimc->clock);
  1224. fimc->clock = ERR_PTR(-EINVAL);
  1225. }
  1226. static int fimc_lite_clk_get(struct fimc_lite *fimc)
  1227. {
  1228. int ret;
  1229. fimc->clock = clk_get(&fimc->pdev->dev, FLITE_CLK_NAME);
  1230. if (IS_ERR(fimc->clock))
  1231. return PTR_ERR(fimc->clock);
  1232. ret = clk_prepare(fimc->clock);
  1233. if (ret < 0) {
  1234. clk_put(fimc->clock);
  1235. fimc->clock = ERR_PTR(-EINVAL);
  1236. }
  1237. return ret;
  1238. }
  1239. static const struct of_device_id flite_of_match[];
  1240. static int fimc_lite_probe(struct platform_device *pdev)
  1241. {
  1242. struct flite_drvdata *drv_data = NULL;
  1243. struct device *dev = &pdev->dev;
  1244. const struct of_device_id *of_id;
  1245. struct fimc_lite *fimc;
  1246. struct resource *res;
  1247. int ret;
  1248. if (!dev->of_node)
  1249. return -ENODEV;
  1250. fimc = devm_kzalloc(dev, sizeof(*fimc), GFP_KERNEL);
  1251. if (!fimc)
  1252. return -ENOMEM;
  1253. of_id = of_match_node(flite_of_match, dev->of_node);
  1254. if (of_id)
  1255. drv_data = (struct flite_drvdata *)of_id->data;
  1256. fimc->index = of_alias_get_id(dev->of_node, "fimc-lite");
  1257. if (!drv_data || fimc->index >= drv_data->num_instances ||
  1258. fimc->index < 0) {
  1259. dev_err(dev, "Wrong %s node alias\n",
  1260. dev->of_node->full_name);
  1261. return -EINVAL;
  1262. }
  1263. fimc->dd = drv_data;
  1264. fimc->pdev = pdev;
  1265. init_waitqueue_head(&fimc->irq_queue);
  1266. spin_lock_init(&fimc->slock);
  1267. mutex_init(&fimc->lock);
  1268. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  1269. fimc->regs = devm_ioremap_resource(dev, res);
  1270. if (IS_ERR(fimc->regs))
  1271. return PTR_ERR(fimc->regs);
  1272. res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
  1273. if (res == NULL) {
  1274. dev_err(dev, "Failed to get IRQ resource\n");
  1275. return -ENXIO;
  1276. }
  1277. ret = fimc_lite_clk_get(fimc);
  1278. if (ret)
  1279. return ret;
  1280. ret = devm_request_irq(dev, res->start, flite_irq_handler,
  1281. 0, dev_name(dev), fimc);
  1282. if (ret) {
  1283. dev_err(dev, "Failed to install irq (%d)\n", ret);
  1284. goto err_clk_put;
  1285. }
  1286. /* The video node will be created within the subdev's registered() op */
  1287. ret = fimc_lite_create_capture_subdev(fimc);
  1288. if (ret)
  1289. goto err_clk_put;
  1290. platform_set_drvdata(pdev, fimc);
  1291. pm_runtime_enable(dev);
  1292. if (!pm_runtime_enabled(dev)) {
  1293. ret = clk_enable(fimc->clock);
  1294. if (ret < 0)
  1295. goto err_sd;
  1296. }
  1297. fimc->alloc_ctx = vb2_dma_contig_init_ctx(dev);
  1298. if (IS_ERR(fimc->alloc_ctx)) {
  1299. ret = PTR_ERR(fimc->alloc_ctx);
  1300. goto err_clk_dis;
  1301. }
  1302. fimc_lite_set_default_config(fimc);
  1303. dev_dbg(dev, "FIMC-LITE.%d registered successfully\n",
  1304. fimc->index);
  1305. return 0;
  1306. err_clk_dis:
  1307. if (!pm_runtime_enabled(dev))
  1308. clk_disable(fimc->clock);
  1309. err_sd:
  1310. fimc_lite_unregister_capture_subdev(fimc);
  1311. err_clk_put:
  1312. fimc_lite_clk_put(fimc);
  1313. return ret;
  1314. }
  1315. #ifdef CONFIG_PM
  1316. static int fimc_lite_runtime_resume(struct device *dev)
  1317. {
  1318. struct fimc_lite *fimc = dev_get_drvdata(dev);
  1319. clk_enable(fimc->clock);
  1320. return 0;
  1321. }
  1322. static int fimc_lite_runtime_suspend(struct device *dev)
  1323. {
  1324. struct fimc_lite *fimc = dev_get_drvdata(dev);
  1325. clk_disable(fimc->clock);
  1326. return 0;
  1327. }
  1328. #endif
  1329. #ifdef CONFIG_PM_SLEEP
  1330. static int fimc_lite_resume(struct device *dev)
  1331. {
  1332. struct fimc_lite *fimc = dev_get_drvdata(dev);
  1333. struct flite_buffer *buf;
  1334. unsigned long flags;
  1335. int i;
  1336. spin_lock_irqsave(&fimc->slock, flags);
  1337. if (!test_and_clear_bit(ST_LPM, &fimc->state) ||
  1338. !test_bit(ST_FLITE_IN_USE, &fimc->state)) {
  1339. spin_unlock_irqrestore(&fimc->slock, flags);
  1340. return 0;
  1341. }
  1342. flite_hw_reset(fimc);
  1343. spin_unlock_irqrestore(&fimc->slock, flags);
  1344. if (!test_and_clear_bit(ST_FLITE_SUSPENDED, &fimc->state))
  1345. return 0;
  1346. INIT_LIST_HEAD(&fimc->active_buf_q);
  1347. fimc_pipeline_call(&fimc->ve, open,
  1348. &fimc->ve.vdev.entity, false);
  1349. fimc_lite_hw_init(fimc, atomic_read(&fimc->out_path) == FIMC_IO_ISP);
  1350. clear_bit(ST_FLITE_SUSPENDED, &fimc->state);
  1351. for (i = 0; i < fimc->reqbufs_count; i++) {
  1352. if (list_empty(&fimc->pending_buf_q))
  1353. break;
  1354. buf = fimc_lite_pending_queue_pop(fimc);
  1355. buffer_queue(&buf->vb.vb2_buf);
  1356. }
  1357. return 0;
  1358. }
  1359. static int fimc_lite_suspend(struct device *dev)
  1360. {
  1361. struct fimc_lite *fimc = dev_get_drvdata(dev);
  1362. bool suspend = test_bit(ST_FLITE_IN_USE, &fimc->state);
  1363. int ret;
  1364. if (test_and_set_bit(ST_LPM, &fimc->state))
  1365. return 0;
  1366. ret = fimc_lite_stop_capture(fimc, suspend);
  1367. if (ret < 0 || !fimc_lite_active(fimc))
  1368. return ret;
  1369. return fimc_pipeline_call(&fimc->ve, close);
  1370. }
  1371. #endif /* CONFIG_PM_SLEEP */
  1372. static int fimc_lite_remove(struct platform_device *pdev)
  1373. {
  1374. struct fimc_lite *fimc = platform_get_drvdata(pdev);
  1375. struct device *dev = &pdev->dev;
  1376. pm_runtime_disable(dev);
  1377. pm_runtime_set_suspended(dev);
  1378. fimc_lite_unregister_capture_subdev(fimc);
  1379. vb2_dma_contig_cleanup_ctx(fimc->alloc_ctx);
  1380. fimc_lite_clk_put(fimc);
  1381. dev_info(dev, "Driver unloaded\n");
  1382. return 0;
  1383. }
  1384. static const struct dev_pm_ops fimc_lite_pm_ops = {
  1385. SET_SYSTEM_SLEEP_PM_OPS(fimc_lite_suspend, fimc_lite_resume)
  1386. SET_RUNTIME_PM_OPS(fimc_lite_runtime_suspend, fimc_lite_runtime_resume,
  1387. NULL)
  1388. };
  1389. /* EXYNOS4212, EXYNOS4412 */
  1390. static struct flite_drvdata fimc_lite_drvdata_exynos4 = {
  1391. .max_width = 8192,
  1392. .max_height = 8192,
  1393. .out_width_align = 8,
  1394. .win_hor_offs_align = 2,
  1395. .out_hor_offs_align = 8,
  1396. .max_dma_bufs = 1,
  1397. .num_instances = 2,
  1398. };
  1399. /* EXYNOS5250 */
  1400. static struct flite_drvdata fimc_lite_drvdata_exynos5 = {
  1401. .max_width = 8192,
  1402. .max_height = 8192,
  1403. .out_width_align = 8,
  1404. .win_hor_offs_align = 2,
  1405. .out_hor_offs_align = 8,
  1406. .max_dma_bufs = 32,
  1407. .num_instances = 3,
  1408. };
  1409. static const struct of_device_id flite_of_match[] = {
  1410. {
  1411. .compatible = "samsung,exynos4212-fimc-lite",
  1412. .data = &fimc_lite_drvdata_exynos4,
  1413. },
  1414. {
  1415. .compatible = "samsung,exynos5250-fimc-lite",
  1416. .data = &fimc_lite_drvdata_exynos5,
  1417. },
  1418. { /* sentinel */ },
  1419. };
  1420. MODULE_DEVICE_TABLE(of, flite_of_match);
  1421. static struct platform_driver fimc_lite_driver = {
  1422. .probe = fimc_lite_probe,
  1423. .remove = fimc_lite_remove,
  1424. .driver = {
  1425. .of_match_table = flite_of_match,
  1426. .name = FIMC_LITE_DRV_NAME,
  1427. .pm = &fimc_lite_pm_ops,
  1428. }
  1429. };
  1430. module_platform_driver(fimc_lite_driver);
  1431. MODULE_LICENSE("GPL");
  1432. MODULE_ALIAS("platform:" FIMC_LITE_DRV_NAME);