s5p_mfc_cmd_v5.c 4.7 KB

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  1. /*
  2. * linux/drivers/media/platform/s5p-mfc/s5p_mfc_cmd_v5.c
  3. *
  4. * Copyright (C) 2011 Samsung Electronics Co., Ltd.
  5. * http://www.samsung.com/
  6. *
  7. * This program is free software; you can redistribute it and/or modify
  8. * it under the terms of the GNU General Public License as published by
  9. * the Free Software Foundation; either version 2 of the License, or
  10. * (at your option) any later version.
  11. */
  12. #include "regs-mfc.h"
  13. #include "s5p_mfc_cmd.h"
  14. #include "s5p_mfc_common.h"
  15. #include "s5p_mfc_debug.h"
  16. #include "s5p_mfc_cmd_v5.h"
  17. /* This function is used to send a command to the MFC */
  18. static int s5p_mfc_cmd_host2risc_v5(struct s5p_mfc_dev *dev, int cmd,
  19. struct s5p_mfc_cmd_args *args)
  20. {
  21. int cur_cmd;
  22. unsigned long timeout;
  23. timeout = jiffies + msecs_to_jiffies(MFC_BW_TIMEOUT);
  24. /* wait until host to risc command register becomes 'H2R_CMD_EMPTY' */
  25. do {
  26. if (time_after(jiffies, timeout)) {
  27. mfc_err("Timeout while waiting for hardware\n");
  28. return -EIO;
  29. }
  30. cur_cmd = mfc_read(dev, S5P_FIMV_HOST2RISC_CMD);
  31. } while (cur_cmd != S5P_FIMV_H2R_CMD_EMPTY);
  32. mfc_write(dev, args->arg[0], S5P_FIMV_HOST2RISC_ARG1);
  33. mfc_write(dev, args->arg[1], S5P_FIMV_HOST2RISC_ARG2);
  34. mfc_write(dev, args->arg[2], S5P_FIMV_HOST2RISC_ARG3);
  35. mfc_write(dev, args->arg[3], S5P_FIMV_HOST2RISC_ARG4);
  36. /* Issue the command */
  37. mfc_write(dev, cmd, S5P_FIMV_HOST2RISC_CMD);
  38. return 0;
  39. }
  40. /* Initialize the MFC */
  41. static int s5p_mfc_sys_init_cmd_v5(struct s5p_mfc_dev *dev)
  42. {
  43. struct s5p_mfc_cmd_args h2r_args;
  44. memset(&h2r_args, 0, sizeof(struct s5p_mfc_cmd_args));
  45. h2r_args.arg[0] = dev->fw_size;
  46. return s5p_mfc_cmd_host2risc_v5(dev, S5P_FIMV_H2R_CMD_SYS_INIT,
  47. &h2r_args);
  48. }
  49. /* Suspend the MFC hardware */
  50. static int s5p_mfc_sleep_cmd_v5(struct s5p_mfc_dev *dev)
  51. {
  52. struct s5p_mfc_cmd_args h2r_args;
  53. memset(&h2r_args, 0, sizeof(struct s5p_mfc_cmd_args));
  54. return s5p_mfc_cmd_host2risc_v5(dev, S5P_FIMV_H2R_CMD_SLEEP, &h2r_args);
  55. }
  56. /* Wake up the MFC hardware */
  57. static int s5p_mfc_wakeup_cmd_v5(struct s5p_mfc_dev *dev)
  58. {
  59. struct s5p_mfc_cmd_args h2r_args;
  60. memset(&h2r_args, 0, sizeof(struct s5p_mfc_cmd_args));
  61. return s5p_mfc_cmd_host2risc_v5(dev, S5P_FIMV_H2R_CMD_WAKEUP,
  62. &h2r_args);
  63. }
  64. static int s5p_mfc_open_inst_cmd_v5(struct s5p_mfc_ctx *ctx)
  65. {
  66. struct s5p_mfc_dev *dev = ctx->dev;
  67. struct s5p_mfc_cmd_args h2r_args;
  68. int ret;
  69. /* Preparing decoding - getting instance number */
  70. mfc_debug(2, "Getting instance number (codec: %d)\n", ctx->codec_mode);
  71. dev->curr_ctx = ctx->num;
  72. memset(&h2r_args, 0, sizeof(struct s5p_mfc_cmd_args));
  73. switch (ctx->codec_mode) {
  74. case S5P_MFC_CODEC_H264_DEC:
  75. h2r_args.arg[0] = S5P_FIMV_CODEC_H264_DEC;
  76. break;
  77. case S5P_MFC_CODEC_VC1_DEC:
  78. h2r_args.arg[0] = S5P_FIMV_CODEC_VC1_DEC;
  79. break;
  80. case S5P_MFC_CODEC_MPEG4_DEC:
  81. h2r_args.arg[0] = S5P_FIMV_CODEC_MPEG4_DEC;
  82. break;
  83. case S5P_MFC_CODEC_MPEG2_DEC:
  84. h2r_args.arg[0] = S5P_FIMV_CODEC_MPEG2_DEC;
  85. break;
  86. case S5P_MFC_CODEC_H263_DEC:
  87. h2r_args.arg[0] = S5P_FIMV_CODEC_H263_DEC;
  88. break;
  89. case S5P_MFC_CODEC_VC1RCV_DEC:
  90. h2r_args.arg[0] = S5P_FIMV_CODEC_VC1RCV_DEC;
  91. break;
  92. case S5P_MFC_CODEC_H264_ENC:
  93. h2r_args.arg[0] = S5P_FIMV_CODEC_H264_ENC;
  94. break;
  95. case S5P_MFC_CODEC_MPEG4_ENC:
  96. h2r_args.arg[0] = S5P_FIMV_CODEC_MPEG4_ENC;
  97. break;
  98. case S5P_MFC_CODEC_H263_ENC:
  99. h2r_args.arg[0] = S5P_FIMV_CODEC_H263_ENC;
  100. break;
  101. default:
  102. h2r_args.arg[0] = S5P_FIMV_CODEC_NONE;
  103. }
  104. h2r_args.arg[1] = 0; /* no crc & no pixelcache */
  105. h2r_args.arg[2] = ctx->ctx.ofs;
  106. h2r_args.arg[3] = ctx->ctx.size;
  107. ret = s5p_mfc_cmd_host2risc_v5(dev, S5P_FIMV_H2R_CMD_OPEN_INSTANCE,
  108. &h2r_args);
  109. if (ret) {
  110. mfc_err("Failed to create a new instance\n");
  111. ctx->state = MFCINST_ERROR;
  112. }
  113. return ret;
  114. }
  115. static int s5p_mfc_close_inst_cmd_v5(struct s5p_mfc_ctx *ctx)
  116. {
  117. struct s5p_mfc_dev *dev = ctx->dev;
  118. struct s5p_mfc_cmd_args h2r_args;
  119. int ret;
  120. if (ctx->state == MFCINST_FREE) {
  121. mfc_err("Instance already returned\n");
  122. ctx->state = MFCINST_ERROR;
  123. return -EINVAL;
  124. }
  125. /* Closing decoding instance */
  126. mfc_debug(2, "Returning instance number %d\n", ctx->inst_no);
  127. dev->curr_ctx = ctx->num;
  128. memset(&h2r_args, 0, sizeof(struct s5p_mfc_cmd_args));
  129. h2r_args.arg[0] = ctx->inst_no;
  130. ret = s5p_mfc_cmd_host2risc_v5(dev, S5P_FIMV_H2R_CMD_CLOSE_INSTANCE,
  131. &h2r_args);
  132. if (ret) {
  133. mfc_err("Failed to return an instance\n");
  134. ctx->state = MFCINST_ERROR;
  135. return -EINVAL;
  136. }
  137. return 0;
  138. }
  139. /* Initialize cmd function pointers for MFC v5 */
  140. static struct s5p_mfc_hw_cmds s5p_mfc_cmds_v5 = {
  141. .cmd_host2risc = s5p_mfc_cmd_host2risc_v5,
  142. .sys_init_cmd = s5p_mfc_sys_init_cmd_v5,
  143. .sleep_cmd = s5p_mfc_sleep_cmd_v5,
  144. .wakeup_cmd = s5p_mfc_wakeup_cmd_v5,
  145. .open_inst_cmd = s5p_mfc_open_inst_cmd_v5,
  146. .close_inst_cmd = s5p_mfc_close_inst_cmd_v5,
  147. };
  148. struct s5p_mfc_hw_cmds *s5p_mfc_init_hw_cmds_v5(void)
  149. {
  150. return &s5p_mfc_cmds_v5;
  151. }