fc0011.c 13 KB

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  1. /*
  2. * Fitipower FC0011 tuner driver
  3. *
  4. * Copyright (C) 2012 Michael Buesch <m@bues.ch>
  5. *
  6. * Derived from FC0012 tuner driver:
  7. * Copyright (C) 2012 Hans-Frieder Vogt <hfvogt@gmx.net>
  8. *
  9. * This program is free software; you can redistribute it and/or modify
  10. * it under the terms of the GNU General Public License as published by
  11. * the Free Software Foundation; either version 2 of the License, or
  12. * (at your option) any later version.
  13. *
  14. * This program is distributed in the hope that it will be useful,
  15. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  17. * GNU General Public License for more details.
  18. *
  19. * You should have received a copy of the GNU General Public License
  20. * along with this program; if not, write to the Free Software
  21. * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
  22. */
  23. #include "fc0011.h"
  24. /* Tuner registers */
  25. enum {
  26. FC11_REG_0,
  27. FC11_REG_FA, /* FA */
  28. FC11_REG_FP, /* FP */
  29. FC11_REG_XINHI, /* XIN high 8 bit */
  30. FC11_REG_XINLO, /* XIN low 8 bit */
  31. FC11_REG_VCO, /* VCO */
  32. FC11_REG_VCOSEL, /* VCO select */
  33. FC11_REG_7, /* Unknown tuner reg 7 */
  34. FC11_REG_8, /* Unknown tuner reg 8 */
  35. FC11_REG_9,
  36. FC11_REG_10, /* Unknown tuner reg 10 */
  37. FC11_REG_11, /* Unknown tuner reg 11 */
  38. FC11_REG_12,
  39. FC11_REG_RCCAL, /* RC calibrate */
  40. FC11_REG_VCOCAL, /* VCO calibrate */
  41. FC11_REG_15,
  42. FC11_REG_16, /* Unknown tuner reg 16 */
  43. FC11_REG_17,
  44. FC11_NR_REGS, /* Number of registers */
  45. };
  46. enum FC11_REG_VCOSEL_bits {
  47. FC11_VCOSEL_2 = 0x08, /* VCO select 2 */
  48. FC11_VCOSEL_1 = 0x10, /* VCO select 1 */
  49. FC11_VCOSEL_CLKOUT = 0x20, /* Fix clock out */
  50. FC11_VCOSEL_BW7M = 0x40, /* 7MHz bw */
  51. FC11_VCOSEL_BW6M = 0x80, /* 6MHz bw */
  52. };
  53. enum FC11_REG_RCCAL_bits {
  54. FC11_RCCAL_FORCE = 0x10, /* force */
  55. };
  56. enum FC11_REG_VCOCAL_bits {
  57. FC11_VCOCAL_RUN = 0, /* VCO calibration run */
  58. FC11_VCOCAL_VALUEMASK = 0x3F, /* VCO calibration value mask */
  59. FC11_VCOCAL_OK = 0x40, /* VCO calibration Ok */
  60. FC11_VCOCAL_RESET = 0x80, /* VCO calibration reset */
  61. };
  62. struct fc0011_priv {
  63. struct i2c_adapter *i2c;
  64. u8 addr;
  65. u32 frequency;
  66. u32 bandwidth;
  67. };
  68. static int fc0011_writereg(struct fc0011_priv *priv, u8 reg, u8 val)
  69. {
  70. u8 buf[2] = { reg, val };
  71. struct i2c_msg msg = { .addr = priv->addr,
  72. .flags = 0, .buf = buf, .len = 2 };
  73. if (i2c_transfer(priv->i2c, &msg, 1) != 1) {
  74. dev_err(&priv->i2c->dev,
  75. "I2C write reg failed, reg: %02x, val: %02x\n",
  76. reg, val);
  77. return -EIO;
  78. }
  79. return 0;
  80. }
  81. static int fc0011_readreg(struct fc0011_priv *priv, u8 reg, u8 *val)
  82. {
  83. u8 dummy;
  84. struct i2c_msg msg[2] = {
  85. { .addr = priv->addr,
  86. .flags = 0, .buf = &reg, .len = 1 },
  87. { .addr = priv->addr,
  88. .flags = I2C_M_RD, .buf = val ? : &dummy, .len = 1 },
  89. };
  90. if (i2c_transfer(priv->i2c, msg, 2) != 2) {
  91. dev_err(&priv->i2c->dev,
  92. "I2C read failed, reg: %02x\n", reg);
  93. return -EIO;
  94. }
  95. return 0;
  96. }
  97. static int fc0011_release(struct dvb_frontend *fe)
  98. {
  99. kfree(fe->tuner_priv);
  100. fe->tuner_priv = NULL;
  101. return 0;
  102. }
  103. static int fc0011_init(struct dvb_frontend *fe)
  104. {
  105. struct fc0011_priv *priv = fe->tuner_priv;
  106. int err;
  107. if (WARN_ON(!fe->callback))
  108. return -EINVAL;
  109. err = fe->callback(priv->i2c, DVB_FRONTEND_COMPONENT_TUNER,
  110. FC0011_FE_CALLBACK_POWER, priv->addr);
  111. if (err) {
  112. dev_err(&priv->i2c->dev, "Power-on callback failed\n");
  113. return err;
  114. }
  115. err = fe->callback(priv->i2c, DVB_FRONTEND_COMPONENT_TUNER,
  116. FC0011_FE_CALLBACK_RESET, priv->addr);
  117. if (err) {
  118. dev_err(&priv->i2c->dev, "Reset callback failed\n");
  119. return err;
  120. }
  121. return 0;
  122. }
  123. /* Initiate VCO calibration */
  124. static int fc0011_vcocal_trigger(struct fc0011_priv *priv)
  125. {
  126. int err;
  127. err = fc0011_writereg(priv, FC11_REG_VCOCAL, FC11_VCOCAL_RESET);
  128. if (err)
  129. return err;
  130. err = fc0011_writereg(priv, FC11_REG_VCOCAL, FC11_VCOCAL_RUN);
  131. if (err)
  132. return err;
  133. return 0;
  134. }
  135. /* Read VCO calibration value */
  136. static int fc0011_vcocal_read(struct fc0011_priv *priv, u8 *value)
  137. {
  138. int err;
  139. err = fc0011_writereg(priv, FC11_REG_VCOCAL, FC11_VCOCAL_RUN);
  140. if (err)
  141. return err;
  142. usleep_range(10000, 20000);
  143. err = fc0011_readreg(priv, FC11_REG_VCOCAL, value);
  144. if (err)
  145. return err;
  146. return 0;
  147. }
  148. static int fc0011_set_params(struct dvb_frontend *fe)
  149. {
  150. struct dtv_frontend_properties *p = &fe->dtv_property_cache;
  151. struct fc0011_priv *priv = fe->tuner_priv;
  152. int err;
  153. unsigned int i, vco_retries;
  154. u32 freq = p->frequency / 1000;
  155. u32 bandwidth = p->bandwidth_hz / 1000;
  156. u32 fvco, xin, frac, xdiv, xdivr;
  157. u8 fa, fp, vco_sel, vco_cal;
  158. u8 regs[FC11_NR_REGS] = { };
  159. regs[FC11_REG_7] = 0x0F;
  160. regs[FC11_REG_8] = 0x3E;
  161. regs[FC11_REG_10] = 0xB8;
  162. regs[FC11_REG_11] = 0x80;
  163. regs[FC11_REG_RCCAL] = 0x04;
  164. err = fc0011_writereg(priv, FC11_REG_7, regs[FC11_REG_7]);
  165. err |= fc0011_writereg(priv, FC11_REG_8, regs[FC11_REG_8]);
  166. err |= fc0011_writereg(priv, FC11_REG_10, regs[FC11_REG_10]);
  167. err |= fc0011_writereg(priv, FC11_REG_11, regs[FC11_REG_11]);
  168. err |= fc0011_writereg(priv, FC11_REG_RCCAL, regs[FC11_REG_RCCAL]);
  169. if (err)
  170. return -EIO;
  171. /* Set VCO freq and VCO div */
  172. if (freq < 54000) {
  173. fvco = freq * 64;
  174. regs[FC11_REG_VCO] = 0x82;
  175. } else if (freq < 108000) {
  176. fvco = freq * 32;
  177. regs[FC11_REG_VCO] = 0x42;
  178. } else if (freq < 216000) {
  179. fvco = freq * 16;
  180. regs[FC11_REG_VCO] = 0x22;
  181. } else if (freq < 432000) {
  182. fvco = freq * 8;
  183. regs[FC11_REG_VCO] = 0x12;
  184. } else {
  185. fvco = freq * 4;
  186. regs[FC11_REG_VCO] = 0x0A;
  187. }
  188. /* Calc XIN. The PLL reference frequency is 18 MHz. */
  189. xdiv = fvco / 18000;
  190. WARN_ON(xdiv > 0xFF);
  191. frac = fvco - xdiv * 18000;
  192. frac = (frac << 15) / 18000;
  193. if (frac >= 16384)
  194. frac += 32786;
  195. if (!frac)
  196. xin = 0;
  197. else
  198. xin = clamp_t(u32, frac, 512, 65024);
  199. regs[FC11_REG_XINHI] = xin >> 8;
  200. regs[FC11_REG_XINLO] = xin;
  201. /* Calc FP and FA */
  202. xdivr = xdiv;
  203. if (fvco - xdiv * 18000 >= 9000)
  204. xdivr += 1; /* round */
  205. fp = xdivr / 8;
  206. fa = xdivr - fp * 8;
  207. if (fa < 2) {
  208. fp -= 1;
  209. fa += 8;
  210. }
  211. if (fp > 0x1F) {
  212. fp = 0x1F;
  213. fa = 0xF;
  214. }
  215. if (fa >= fp) {
  216. dev_warn(&priv->i2c->dev,
  217. "fa %02X >= fp %02X, but trying to continue\n",
  218. (unsigned int)(u8)fa, (unsigned int)(u8)fp);
  219. }
  220. regs[FC11_REG_FA] = fa;
  221. regs[FC11_REG_FP] = fp;
  222. /* Select bandwidth */
  223. switch (bandwidth) {
  224. case 8000:
  225. break;
  226. case 7000:
  227. regs[FC11_REG_VCOSEL] |= FC11_VCOSEL_BW7M;
  228. break;
  229. default:
  230. dev_warn(&priv->i2c->dev, "Unsupported bandwidth %u kHz. "
  231. "Using 6000 kHz.\n",
  232. bandwidth);
  233. bandwidth = 6000;
  234. /* fallthrough */
  235. case 6000:
  236. regs[FC11_REG_VCOSEL] |= FC11_VCOSEL_BW6M;
  237. break;
  238. }
  239. /* Pre VCO select */
  240. if (fvco < 2320000) {
  241. vco_sel = 0;
  242. regs[FC11_REG_VCOSEL] &= ~(FC11_VCOSEL_1 | FC11_VCOSEL_2);
  243. } else if (fvco < 3080000) {
  244. vco_sel = 1;
  245. regs[FC11_REG_VCOSEL] &= ~(FC11_VCOSEL_1 | FC11_VCOSEL_2);
  246. regs[FC11_REG_VCOSEL] |= FC11_VCOSEL_1;
  247. } else {
  248. vco_sel = 2;
  249. regs[FC11_REG_VCOSEL] &= ~(FC11_VCOSEL_1 | FC11_VCOSEL_2);
  250. regs[FC11_REG_VCOSEL] |= FC11_VCOSEL_2;
  251. }
  252. /* Fix for low freqs */
  253. if (freq < 45000) {
  254. regs[FC11_REG_FA] = 0x6;
  255. regs[FC11_REG_FP] = 0x11;
  256. }
  257. /* Clock out fix */
  258. regs[FC11_REG_VCOSEL] |= FC11_VCOSEL_CLKOUT;
  259. /* Write the cached registers */
  260. for (i = FC11_REG_FA; i <= FC11_REG_VCOSEL; i++) {
  261. err = fc0011_writereg(priv, i, regs[i]);
  262. if (err)
  263. return err;
  264. }
  265. /* VCO calibration */
  266. err = fc0011_vcocal_trigger(priv);
  267. if (err)
  268. return err;
  269. err = fc0011_vcocal_read(priv, &vco_cal);
  270. if (err)
  271. return err;
  272. vco_retries = 0;
  273. while (!(vco_cal & FC11_VCOCAL_OK) && vco_retries < 3) {
  274. /* Reset the tuner and try again */
  275. err = fe->callback(priv->i2c, DVB_FRONTEND_COMPONENT_TUNER,
  276. FC0011_FE_CALLBACK_RESET, priv->addr);
  277. if (err) {
  278. dev_err(&priv->i2c->dev, "Failed to reset tuner\n");
  279. return err;
  280. }
  281. /* Reinit tuner config */
  282. err = 0;
  283. for (i = FC11_REG_FA; i <= FC11_REG_VCOSEL; i++)
  284. err |= fc0011_writereg(priv, i, regs[i]);
  285. err |= fc0011_writereg(priv, FC11_REG_7, regs[FC11_REG_7]);
  286. err |= fc0011_writereg(priv, FC11_REG_8, regs[FC11_REG_8]);
  287. err |= fc0011_writereg(priv, FC11_REG_10, regs[FC11_REG_10]);
  288. err |= fc0011_writereg(priv, FC11_REG_11, regs[FC11_REG_11]);
  289. err |= fc0011_writereg(priv, FC11_REG_RCCAL, regs[FC11_REG_RCCAL]);
  290. if (err)
  291. return -EIO;
  292. /* VCO calibration */
  293. err = fc0011_vcocal_trigger(priv);
  294. if (err)
  295. return err;
  296. err = fc0011_vcocal_read(priv, &vco_cal);
  297. if (err)
  298. return err;
  299. vco_retries++;
  300. }
  301. if (!(vco_cal & FC11_VCOCAL_OK)) {
  302. dev_err(&priv->i2c->dev,
  303. "Failed to read VCO calibration value (got %02X)\n",
  304. (unsigned int)vco_cal);
  305. return -EIO;
  306. }
  307. vco_cal &= FC11_VCOCAL_VALUEMASK;
  308. switch (vco_sel) {
  309. default:
  310. WARN_ON(1);
  311. case 0:
  312. if (vco_cal < 8) {
  313. regs[FC11_REG_VCOSEL] &= ~(FC11_VCOSEL_1 | FC11_VCOSEL_2);
  314. regs[FC11_REG_VCOSEL] |= FC11_VCOSEL_1;
  315. err = fc0011_writereg(priv, FC11_REG_VCOSEL,
  316. regs[FC11_REG_VCOSEL]);
  317. if (err)
  318. return err;
  319. err = fc0011_vcocal_trigger(priv);
  320. if (err)
  321. return err;
  322. } else {
  323. regs[FC11_REG_VCOSEL] &= ~(FC11_VCOSEL_1 | FC11_VCOSEL_2);
  324. err = fc0011_writereg(priv, FC11_REG_VCOSEL,
  325. regs[FC11_REG_VCOSEL]);
  326. if (err)
  327. return err;
  328. }
  329. break;
  330. case 1:
  331. if (vco_cal < 5) {
  332. regs[FC11_REG_VCOSEL] &= ~(FC11_VCOSEL_1 | FC11_VCOSEL_2);
  333. regs[FC11_REG_VCOSEL] |= FC11_VCOSEL_2;
  334. err = fc0011_writereg(priv, FC11_REG_VCOSEL,
  335. regs[FC11_REG_VCOSEL]);
  336. if (err)
  337. return err;
  338. err = fc0011_vcocal_trigger(priv);
  339. if (err)
  340. return err;
  341. } else if (vco_cal <= 48) {
  342. regs[FC11_REG_VCOSEL] &= ~(FC11_VCOSEL_1 | FC11_VCOSEL_2);
  343. regs[FC11_REG_VCOSEL] |= FC11_VCOSEL_1;
  344. err = fc0011_writereg(priv, FC11_REG_VCOSEL,
  345. regs[FC11_REG_VCOSEL]);
  346. if (err)
  347. return err;
  348. } else {
  349. regs[FC11_REG_VCOSEL] &= ~(FC11_VCOSEL_1 | FC11_VCOSEL_2);
  350. err = fc0011_writereg(priv, FC11_REG_VCOSEL,
  351. regs[FC11_REG_VCOSEL]);
  352. if (err)
  353. return err;
  354. err = fc0011_vcocal_trigger(priv);
  355. if (err)
  356. return err;
  357. }
  358. break;
  359. case 2:
  360. if (vco_cal > 53) {
  361. regs[FC11_REG_VCOSEL] &= ~(FC11_VCOSEL_1 | FC11_VCOSEL_2);
  362. regs[FC11_REG_VCOSEL] |= FC11_VCOSEL_1;
  363. err = fc0011_writereg(priv, FC11_REG_VCOSEL,
  364. regs[FC11_REG_VCOSEL]);
  365. if (err)
  366. return err;
  367. err = fc0011_vcocal_trigger(priv);
  368. if (err)
  369. return err;
  370. } else {
  371. regs[FC11_REG_VCOSEL] &= ~(FC11_VCOSEL_1 | FC11_VCOSEL_2);
  372. regs[FC11_REG_VCOSEL] |= FC11_VCOSEL_2;
  373. err = fc0011_writereg(priv, FC11_REG_VCOSEL,
  374. regs[FC11_REG_VCOSEL]);
  375. if (err)
  376. return err;
  377. }
  378. break;
  379. }
  380. err = fc0011_vcocal_read(priv, NULL);
  381. if (err)
  382. return err;
  383. usleep_range(10000, 50000);
  384. err = fc0011_readreg(priv, FC11_REG_RCCAL, &regs[FC11_REG_RCCAL]);
  385. if (err)
  386. return err;
  387. regs[FC11_REG_RCCAL] |= FC11_RCCAL_FORCE;
  388. err = fc0011_writereg(priv, FC11_REG_RCCAL, regs[FC11_REG_RCCAL]);
  389. if (err)
  390. return err;
  391. regs[FC11_REG_16] = 0xB;
  392. err = fc0011_writereg(priv, FC11_REG_16, regs[FC11_REG_16]);
  393. if (err)
  394. return err;
  395. dev_dbg(&priv->i2c->dev, "Tuned to "
  396. "fa=%02X fp=%02X xin=%02X%02X vco=%02X vcosel=%02X "
  397. "vcocal=%02X(%u) bw=%u\n",
  398. (unsigned int)regs[FC11_REG_FA],
  399. (unsigned int)regs[FC11_REG_FP],
  400. (unsigned int)regs[FC11_REG_XINHI],
  401. (unsigned int)regs[FC11_REG_XINLO],
  402. (unsigned int)regs[FC11_REG_VCO],
  403. (unsigned int)regs[FC11_REG_VCOSEL],
  404. (unsigned int)vco_cal, vco_retries,
  405. (unsigned int)bandwidth);
  406. priv->frequency = p->frequency;
  407. priv->bandwidth = p->bandwidth_hz;
  408. return 0;
  409. }
  410. static int fc0011_get_frequency(struct dvb_frontend *fe, u32 *frequency)
  411. {
  412. struct fc0011_priv *priv = fe->tuner_priv;
  413. *frequency = priv->frequency;
  414. return 0;
  415. }
  416. static int fc0011_get_if_frequency(struct dvb_frontend *fe, u32 *frequency)
  417. {
  418. *frequency = 0;
  419. return 0;
  420. }
  421. static int fc0011_get_bandwidth(struct dvb_frontend *fe, u32 *bandwidth)
  422. {
  423. struct fc0011_priv *priv = fe->tuner_priv;
  424. *bandwidth = priv->bandwidth;
  425. return 0;
  426. }
  427. static const struct dvb_tuner_ops fc0011_tuner_ops = {
  428. .info = {
  429. .name = "Fitipower FC0011",
  430. .frequency_min = 45000000,
  431. .frequency_max = 1000000000,
  432. },
  433. .release = fc0011_release,
  434. .init = fc0011_init,
  435. .set_params = fc0011_set_params,
  436. .get_frequency = fc0011_get_frequency,
  437. .get_if_frequency = fc0011_get_if_frequency,
  438. .get_bandwidth = fc0011_get_bandwidth,
  439. };
  440. struct dvb_frontend *fc0011_attach(struct dvb_frontend *fe,
  441. struct i2c_adapter *i2c,
  442. const struct fc0011_config *config)
  443. {
  444. struct fc0011_priv *priv;
  445. priv = kzalloc(sizeof(struct fc0011_priv), GFP_KERNEL);
  446. if (!priv)
  447. return NULL;
  448. priv->i2c = i2c;
  449. priv->addr = config->i2c_address;
  450. fe->tuner_priv = priv;
  451. fe->ops.tuner_ops = fc0011_tuner_ops;
  452. dev_info(&priv->i2c->dev, "Fitipower FC0011 tuner attached\n");
  453. return fe;
  454. }
  455. EXPORT_SYMBOL(fc0011_attach);
  456. MODULE_DESCRIPTION("Fitipower FC0011 silicon tuner driver");
  457. MODULE_AUTHOR("Michael Buesch <m@bues.ch>");
  458. MODULE_LICENSE("GPL");