vsc8211.c 11 KB

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  1. /*
  2. * Copyright (c) 2005-2008 Chelsio, Inc. All rights reserved.
  3. *
  4. * This software is available to you under a choice of one of two
  5. * licenses. You may choose to be licensed under the terms of the GNU
  6. * General Public License (GPL) Version 2, available from the file
  7. * COPYING in the main directory of this source tree, or the
  8. * OpenIB.org BSD license below:
  9. *
  10. * Redistribution and use in source and binary forms, with or
  11. * without modification, are permitted provided that the following
  12. * conditions are met:
  13. *
  14. * - Redistributions of source code must retain the above
  15. * copyright notice, this list of conditions and the following
  16. * disclaimer.
  17. *
  18. * - Redistributions in binary form must reproduce the above
  19. * copyright notice, this list of conditions and the following
  20. * disclaimer in the documentation and/or other materials
  21. * provided with the distribution.
  22. *
  23. * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
  24. * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
  25. * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
  26. * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
  27. * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
  28. * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
  29. * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  30. * SOFTWARE.
  31. */
  32. #include "common.h"
  33. /* VSC8211 PHY specific registers. */
  34. enum {
  35. VSC8211_SIGDET_CTRL = 19,
  36. VSC8211_EXT_CTRL = 23,
  37. VSC8211_INTR_ENABLE = 25,
  38. VSC8211_INTR_STATUS = 26,
  39. VSC8211_LED_CTRL = 27,
  40. VSC8211_AUX_CTRL_STAT = 28,
  41. VSC8211_EXT_PAGE_AXS = 31,
  42. };
  43. enum {
  44. VSC_INTR_RX_ERR = 1 << 0,
  45. VSC_INTR_MS_ERR = 1 << 1, /* master/slave resolution error */
  46. VSC_INTR_CABLE = 1 << 2, /* cable impairment */
  47. VSC_INTR_FALSE_CARR = 1 << 3, /* false carrier */
  48. VSC_INTR_MEDIA_CHG = 1 << 4, /* AMS media change */
  49. VSC_INTR_RX_FIFO = 1 << 5, /* Rx FIFO over/underflow */
  50. VSC_INTR_TX_FIFO = 1 << 6, /* Tx FIFO over/underflow */
  51. VSC_INTR_DESCRAMBL = 1 << 7, /* descrambler lock-lost */
  52. VSC_INTR_SYMBOL_ERR = 1 << 8, /* symbol error */
  53. VSC_INTR_NEG_DONE = 1 << 10, /* autoneg done */
  54. VSC_INTR_NEG_ERR = 1 << 11, /* autoneg error */
  55. VSC_INTR_DPLX_CHG = 1 << 12, /* duplex change */
  56. VSC_INTR_LINK_CHG = 1 << 13, /* link change */
  57. VSC_INTR_SPD_CHG = 1 << 14, /* speed change */
  58. VSC_INTR_ENABLE = 1 << 15, /* interrupt enable */
  59. };
  60. enum {
  61. VSC_CTRL_CLAUSE37_VIEW = 1 << 4, /* Switch to Clause 37 view */
  62. VSC_CTRL_MEDIA_MODE_HI = 0xf000 /* High part of media mode select */
  63. };
  64. #define CFG_CHG_INTR_MASK (VSC_INTR_LINK_CHG | VSC_INTR_NEG_ERR | \
  65. VSC_INTR_DPLX_CHG | VSC_INTR_SPD_CHG | \
  66. VSC_INTR_NEG_DONE)
  67. #define INTR_MASK (CFG_CHG_INTR_MASK | VSC_INTR_TX_FIFO | VSC_INTR_RX_FIFO | \
  68. VSC_INTR_ENABLE)
  69. /* PHY specific auxiliary control & status register fields */
  70. #define S_ACSR_ACTIPHY_TMR 0
  71. #define M_ACSR_ACTIPHY_TMR 0x3
  72. #define V_ACSR_ACTIPHY_TMR(x) ((x) << S_ACSR_ACTIPHY_TMR)
  73. #define S_ACSR_SPEED 3
  74. #define M_ACSR_SPEED 0x3
  75. #define G_ACSR_SPEED(x) (((x) >> S_ACSR_SPEED) & M_ACSR_SPEED)
  76. #define S_ACSR_DUPLEX 5
  77. #define F_ACSR_DUPLEX (1 << S_ACSR_DUPLEX)
  78. #define S_ACSR_ACTIPHY 6
  79. #define F_ACSR_ACTIPHY (1 << S_ACSR_ACTIPHY)
  80. /*
  81. * Reset the PHY. This PHY completes reset immediately so we never wait.
  82. */
  83. static int vsc8211_reset(struct cphy *cphy, int wait)
  84. {
  85. return t3_phy_reset(cphy, MDIO_DEVAD_NONE, 0);
  86. }
  87. static int vsc8211_intr_enable(struct cphy *cphy)
  88. {
  89. return t3_mdio_write(cphy, MDIO_DEVAD_NONE, VSC8211_INTR_ENABLE,
  90. INTR_MASK);
  91. }
  92. static int vsc8211_intr_disable(struct cphy *cphy)
  93. {
  94. return t3_mdio_write(cphy, MDIO_DEVAD_NONE, VSC8211_INTR_ENABLE, 0);
  95. }
  96. static int vsc8211_intr_clear(struct cphy *cphy)
  97. {
  98. u32 val;
  99. /* Clear PHY interrupts by reading the register. */
  100. return t3_mdio_read(cphy, MDIO_DEVAD_NONE, VSC8211_INTR_STATUS, &val);
  101. }
  102. static int vsc8211_autoneg_enable(struct cphy *cphy)
  103. {
  104. return t3_mdio_change_bits(cphy, MDIO_DEVAD_NONE, MII_BMCR,
  105. BMCR_PDOWN | BMCR_ISOLATE,
  106. BMCR_ANENABLE | BMCR_ANRESTART);
  107. }
  108. static int vsc8211_autoneg_restart(struct cphy *cphy)
  109. {
  110. return t3_mdio_change_bits(cphy, MDIO_DEVAD_NONE, MII_BMCR,
  111. BMCR_PDOWN | BMCR_ISOLATE,
  112. BMCR_ANRESTART);
  113. }
  114. static int vsc8211_get_link_status(struct cphy *cphy, int *link_ok,
  115. int *speed, int *duplex, int *fc)
  116. {
  117. unsigned int bmcr, status, lpa, adv;
  118. int err, sp = -1, dplx = -1, pause = 0;
  119. err = t3_mdio_read(cphy, MDIO_DEVAD_NONE, MII_BMCR, &bmcr);
  120. if (!err)
  121. err = t3_mdio_read(cphy, MDIO_DEVAD_NONE, MII_BMSR, &status);
  122. if (err)
  123. return err;
  124. if (link_ok) {
  125. /*
  126. * BMSR_LSTATUS is latch-low, so if it is 0 we need to read it
  127. * once more to get the current link state.
  128. */
  129. if (!(status & BMSR_LSTATUS))
  130. err = t3_mdio_read(cphy, MDIO_DEVAD_NONE, MII_BMSR,
  131. &status);
  132. if (err)
  133. return err;
  134. *link_ok = (status & BMSR_LSTATUS) != 0;
  135. }
  136. if (!(bmcr & BMCR_ANENABLE)) {
  137. dplx = (bmcr & BMCR_FULLDPLX) ? DUPLEX_FULL : DUPLEX_HALF;
  138. if (bmcr & BMCR_SPEED1000)
  139. sp = SPEED_1000;
  140. else if (bmcr & BMCR_SPEED100)
  141. sp = SPEED_100;
  142. else
  143. sp = SPEED_10;
  144. } else if (status & BMSR_ANEGCOMPLETE) {
  145. err = t3_mdio_read(cphy, MDIO_DEVAD_NONE, VSC8211_AUX_CTRL_STAT,
  146. &status);
  147. if (err)
  148. return err;
  149. dplx = (status & F_ACSR_DUPLEX) ? DUPLEX_FULL : DUPLEX_HALF;
  150. sp = G_ACSR_SPEED(status);
  151. if (sp == 0)
  152. sp = SPEED_10;
  153. else if (sp == 1)
  154. sp = SPEED_100;
  155. else
  156. sp = SPEED_1000;
  157. if (fc && dplx == DUPLEX_FULL) {
  158. err = t3_mdio_read(cphy, MDIO_DEVAD_NONE, MII_LPA,
  159. &lpa);
  160. if (!err)
  161. err = t3_mdio_read(cphy, MDIO_DEVAD_NONE,
  162. MII_ADVERTISE, &adv);
  163. if (err)
  164. return err;
  165. if (lpa & adv & ADVERTISE_PAUSE_CAP)
  166. pause = PAUSE_RX | PAUSE_TX;
  167. else if ((lpa & ADVERTISE_PAUSE_CAP) &&
  168. (lpa & ADVERTISE_PAUSE_ASYM) &&
  169. (adv & ADVERTISE_PAUSE_ASYM))
  170. pause = PAUSE_TX;
  171. else if ((lpa & ADVERTISE_PAUSE_ASYM) &&
  172. (adv & ADVERTISE_PAUSE_CAP))
  173. pause = PAUSE_RX;
  174. }
  175. }
  176. if (speed)
  177. *speed = sp;
  178. if (duplex)
  179. *duplex = dplx;
  180. if (fc)
  181. *fc = pause;
  182. return 0;
  183. }
  184. static int vsc8211_get_link_status_fiber(struct cphy *cphy, int *link_ok,
  185. int *speed, int *duplex, int *fc)
  186. {
  187. unsigned int bmcr, status, lpa, adv;
  188. int err, sp = -1, dplx = -1, pause = 0;
  189. err = t3_mdio_read(cphy, MDIO_DEVAD_NONE, MII_BMCR, &bmcr);
  190. if (!err)
  191. err = t3_mdio_read(cphy, MDIO_DEVAD_NONE, MII_BMSR, &status);
  192. if (err)
  193. return err;
  194. if (link_ok) {
  195. /*
  196. * BMSR_LSTATUS is latch-low, so if it is 0 we need to read it
  197. * once more to get the current link state.
  198. */
  199. if (!(status & BMSR_LSTATUS))
  200. err = t3_mdio_read(cphy, MDIO_DEVAD_NONE, MII_BMSR,
  201. &status);
  202. if (err)
  203. return err;
  204. *link_ok = (status & BMSR_LSTATUS) != 0;
  205. }
  206. if (!(bmcr & BMCR_ANENABLE)) {
  207. dplx = (bmcr & BMCR_FULLDPLX) ? DUPLEX_FULL : DUPLEX_HALF;
  208. if (bmcr & BMCR_SPEED1000)
  209. sp = SPEED_1000;
  210. else if (bmcr & BMCR_SPEED100)
  211. sp = SPEED_100;
  212. else
  213. sp = SPEED_10;
  214. } else if (status & BMSR_ANEGCOMPLETE) {
  215. err = t3_mdio_read(cphy, MDIO_DEVAD_NONE, MII_LPA, &lpa);
  216. if (!err)
  217. err = t3_mdio_read(cphy, MDIO_DEVAD_NONE, MII_ADVERTISE,
  218. &adv);
  219. if (err)
  220. return err;
  221. if (adv & lpa & ADVERTISE_1000XFULL) {
  222. dplx = DUPLEX_FULL;
  223. sp = SPEED_1000;
  224. } else if (adv & lpa & ADVERTISE_1000XHALF) {
  225. dplx = DUPLEX_HALF;
  226. sp = SPEED_1000;
  227. }
  228. if (fc && dplx == DUPLEX_FULL) {
  229. if (lpa & adv & ADVERTISE_1000XPAUSE)
  230. pause = PAUSE_RX | PAUSE_TX;
  231. else if ((lpa & ADVERTISE_1000XPAUSE) &&
  232. (adv & lpa & ADVERTISE_1000XPSE_ASYM))
  233. pause = PAUSE_TX;
  234. else if ((lpa & ADVERTISE_1000XPSE_ASYM) &&
  235. (adv & ADVERTISE_1000XPAUSE))
  236. pause = PAUSE_RX;
  237. }
  238. }
  239. if (speed)
  240. *speed = sp;
  241. if (duplex)
  242. *duplex = dplx;
  243. if (fc)
  244. *fc = pause;
  245. return 0;
  246. }
  247. #ifdef UNUSED
  248. /*
  249. * Enable/disable auto MDI/MDI-X in forced link speed mode.
  250. */
  251. static int vsc8211_set_automdi(struct cphy *phy, int enable)
  252. {
  253. int err;
  254. err = t3_mdio_write(phy, MDIO_DEVAD_NONE, VSC8211_EXT_PAGE_AXS, 0x52b5);
  255. if (err)
  256. return err;
  257. err = t3_mdio_write(phy, MDIO_DEVAD_NONE, 18, 0x12);
  258. if (err)
  259. return err;
  260. err = t3_mdio_write(phy, MDIO_DEVAD_NONE, 17, enable ? 0x2803 : 0x3003);
  261. if (err)
  262. return err;
  263. err = t3_mdio_write(phy, MDIO_DEVAD_NONE, 16, 0x87fa);
  264. if (err)
  265. return err;
  266. err = t3_mdio_write(phy, MDIO_DEVAD_NONE, VSC8211_EXT_PAGE_AXS, 0);
  267. if (err)
  268. return err;
  269. return 0;
  270. }
  271. int vsc8211_set_speed_duplex(struct cphy *phy, int speed, int duplex)
  272. {
  273. int err;
  274. err = t3_set_phy_speed_duplex(phy, speed, duplex);
  275. if (!err)
  276. err = vsc8211_set_automdi(phy, 1);
  277. return err;
  278. }
  279. #endif /* UNUSED */
  280. static int vsc8211_power_down(struct cphy *cphy, int enable)
  281. {
  282. return t3_mdio_change_bits(cphy, 0, MII_BMCR, BMCR_PDOWN,
  283. enable ? BMCR_PDOWN : 0);
  284. }
  285. static int vsc8211_intr_handler(struct cphy *cphy)
  286. {
  287. unsigned int cause;
  288. int err, cphy_cause = 0;
  289. err = t3_mdio_read(cphy, MDIO_DEVAD_NONE, VSC8211_INTR_STATUS, &cause);
  290. if (err)
  291. return err;
  292. cause &= INTR_MASK;
  293. if (cause & CFG_CHG_INTR_MASK)
  294. cphy_cause |= cphy_cause_link_change;
  295. if (cause & (VSC_INTR_RX_FIFO | VSC_INTR_TX_FIFO))
  296. cphy_cause |= cphy_cause_fifo_error;
  297. return cphy_cause;
  298. }
  299. static struct cphy_ops vsc8211_ops = {
  300. .reset = vsc8211_reset,
  301. .intr_enable = vsc8211_intr_enable,
  302. .intr_disable = vsc8211_intr_disable,
  303. .intr_clear = vsc8211_intr_clear,
  304. .intr_handler = vsc8211_intr_handler,
  305. .autoneg_enable = vsc8211_autoneg_enable,
  306. .autoneg_restart = vsc8211_autoneg_restart,
  307. .advertise = t3_phy_advertise,
  308. .set_speed_duplex = t3_set_phy_speed_duplex,
  309. .get_link_status = vsc8211_get_link_status,
  310. .power_down = vsc8211_power_down,
  311. };
  312. static struct cphy_ops vsc8211_fiber_ops = {
  313. .reset = vsc8211_reset,
  314. .intr_enable = vsc8211_intr_enable,
  315. .intr_disable = vsc8211_intr_disable,
  316. .intr_clear = vsc8211_intr_clear,
  317. .intr_handler = vsc8211_intr_handler,
  318. .autoneg_enable = vsc8211_autoneg_enable,
  319. .autoneg_restart = vsc8211_autoneg_restart,
  320. .advertise = t3_phy_advertise_fiber,
  321. .set_speed_duplex = t3_set_phy_speed_duplex,
  322. .get_link_status = vsc8211_get_link_status_fiber,
  323. .power_down = vsc8211_power_down,
  324. };
  325. int t3_vsc8211_phy_prep(struct cphy *phy, struct adapter *adapter,
  326. int phy_addr, const struct mdio_ops *mdio_ops)
  327. {
  328. int err;
  329. unsigned int val;
  330. cphy_init(phy, adapter, phy_addr, &vsc8211_ops, mdio_ops,
  331. SUPPORTED_10baseT_Full | SUPPORTED_100baseT_Full |
  332. SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg | SUPPORTED_MII |
  333. SUPPORTED_TP | SUPPORTED_IRQ, "10/100/1000BASE-T");
  334. msleep(20); /* PHY needs ~10ms to start responding to MDIO */
  335. err = t3_mdio_read(phy, MDIO_DEVAD_NONE, VSC8211_EXT_CTRL, &val);
  336. if (err)
  337. return err;
  338. if (val & VSC_CTRL_MEDIA_MODE_HI) {
  339. /* copper interface, just need to configure the LEDs */
  340. return t3_mdio_write(phy, MDIO_DEVAD_NONE, VSC8211_LED_CTRL,
  341. 0x100);
  342. }
  343. phy->caps = SUPPORTED_1000baseT_Full | SUPPORTED_Autoneg |
  344. SUPPORTED_MII | SUPPORTED_FIBRE | SUPPORTED_IRQ;
  345. phy->desc = "1000BASE-X";
  346. phy->ops = &vsc8211_fiber_ops;
  347. err = t3_mdio_write(phy, MDIO_DEVAD_NONE, VSC8211_EXT_PAGE_AXS, 1);
  348. if (err)
  349. return err;
  350. err = t3_mdio_write(phy, MDIO_DEVAD_NONE, VSC8211_SIGDET_CTRL, 1);
  351. if (err)
  352. return err;
  353. err = t3_mdio_write(phy, MDIO_DEVAD_NONE, VSC8211_EXT_PAGE_AXS, 0);
  354. if (err)
  355. return err;
  356. err = t3_mdio_write(phy, MDIO_DEVAD_NONE, VSC8211_EXT_CTRL,
  357. val | VSC_CTRL_CLAUSE37_VIEW);
  358. if (err)
  359. return err;
  360. err = vsc8211_reset(phy, 0);
  361. if (err)
  362. return err;
  363. udelay(5); /* delay after reset before next SMI */
  364. return 0;
  365. }