attach.c 9.9 KB

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  1. /*
  2. * Copyright (c) 2004-2008 Reyk Floeter <reyk@openbsd.org>
  3. * Copyright (c) 2006-2008 Nick Kossifidis <mickflemm@gmail.com>
  4. *
  5. * Permission to use, copy, modify, and distribute this software for any
  6. * purpose with or without fee is hereby granted, provided that the above
  7. * copyright notice and this permission notice appear in all copies.
  8. *
  9. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  10. * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  11. * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  12. * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  13. * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  14. * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  15. * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  16. *
  17. */
  18. /*************************************\
  19. * Attach/Detach Functions and helpers *
  20. \*************************************/
  21. #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  22. #include <linux/pci.h>
  23. #include <linux/slab.h>
  24. #include "ath5k.h"
  25. #include "reg.h"
  26. #include "debug.h"
  27. /**
  28. * ath5k_hw_post() - Power On Self Test helper function
  29. * @ah: The &struct ath5k_hw
  30. */
  31. static int ath5k_hw_post(struct ath5k_hw *ah)
  32. {
  33. static const u32 static_pattern[4] = {
  34. 0x55555555, 0xaaaaaaaa,
  35. 0x66666666, 0x99999999
  36. };
  37. static const u16 regs[2] = { AR5K_STA_ID0, AR5K_PHY(8) };
  38. int i, c;
  39. u16 cur_reg;
  40. u32 var_pattern;
  41. u32 init_val;
  42. u32 cur_val;
  43. for (c = 0; c < 2; c++) {
  44. cur_reg = regs[c];
  45. /* Save previous value */
  46. init_val = ath5k_hw_reg_read(ah, cur_reg);
  47. for (i = 0; i < 256; i++) {
  48. var_pattern = i << 16 | i;
  49. ath5k_hw_reg_write(ah, var_pattern, cur_reg);
  50. cur_val = ath5k_hw_reg_read(ah, cur_reg);
  51. if (cur_val != var_pattern) {
  52. ATH5K_ERR(ah, "POST Failed !!!\n");
  53. return -EAGAIN;
  54. }
  55. /* Found on ndiswrapper dumps */
  56. var_pattern = 0x0039080f;
  57. ath5k_hw_reg_write(ah, var_pattern, cur_reg);
  58. }
  59. for (i = 0; i < 4; i++) {
  60. var_pattern = static_pattern[i];
  61. ath5k_hw_reg_write(ah, var_pattern, cur_reg);
  62. cur_val = ath5k_hw_reg_read(ah, cur_reg);
  63. if (cur_val != var_pattern) {
  64. ATH5K_ERR(ah, "POST Failed !!!\n");
  65. return -EAGAIN;
  66. }
  67. /* Found on ndiswrapper dumps */
  68. var_pattern = 0x003b080f;
  69. ath5k_hw_reg_write(ah, var_pattern, cur_reg);
  70. }
  71. /* Restore previous value */
  72. ath5k_hw_reg_write(ah, init_val, cur_reg);
  73. }
  74. return 0;
  75. }
  76. /**
  77. * ath5k_hw_init() - Check if hw is supported and init the needed structs
  78. * @ah: The &struct ath5k_hw associated with the device
  79. *
  80. * Check if the device is supported, perform a POST and initialize the needed
  81. * structs. Returns -ENOMEM if we don't have memory for the needed structs,
  82. * -ENODEV if the device is not supported or prints an error msg if something
  83. * else went wrong.
  84. */
  85. int ath5k_hw_init(struct ath5k_hw *ah)
  86. {
  87. static const u8 zero_mac[ETH_ALEN] = { };
  88. struct ath_common *common = ath5k_hw_common(ah);
  89. struct pci_dev *pdev = ah->pdev;
  90. struct ath5k_eeprom_info *ee;
  91. int ret;
  92. u32 srev;
  93. /*
  94. * HW information
  95. */
  96. ah->ah_bwmode = AR5K_BWMODE_DEFAULT;
  97. ah->ah_txpower.txp_tpc = AR5K_TUNE_TPC_TXPOWER;
  98. ah->ah_imr = 0;
  99. ah->ah_retry_short = AR5K_INIT_RETRY_SHORT;
  100. ah->ah_retry_long = AR5K_INIT_RETRY_LONG;
  101. ah->ah_ant_mode = AR5K_ANTMODE_DEFAULT;
  102. ah->ah_noise_floor = -95; /* until first NF calibration is run */
  103. ah->ani_state.ani_mode = ATH5K_ANI_MODE_AUTO;
  104. ah->ah_current_channel = &ah->channels[0];
  105. /*
  106. * Find the mac version
  107. */
  108. ath5k_hw_read_srev(ah);
  109. srev = ah->ah_mac_srev;
  110. if (srev < AR5K_SREV_AR5311)
  111. ah->ah_version = AR5K_AR5210;
  112. else if (srev < AR5K_SREV_AR5212)
  113. ah->ah_version = AR5K_AR5211;
  114. else
  115. ah->ah_version = AR5K_AR5212;
  116. /* Get the MAC version */
  117. ah->ah_mac_version = AR5K_REG_MS(srev, AR5K_SREV_VER);
  118. /* Fill the ath5k_hw struct with the needed functions */
  119. ret = ath5k_hw_init_desc_functions(ah);
  120. if (ret)
  121. goto err;
  122. /* Bring device out of sleep and reset its units */
  123. ret = ath5k_hw_nic_wakeup(ah, NULL);
  124. if (ret)
  125. goto err;
  126. /* Get PHY and RADIO revisions */
  127. ah->ah_phy_revision = ath5k_hw_reg_read(ah, AR5K_PHY_CHIP_ID) &
  128. 0xffffffff;
  129. ah->ah_radio_5ghz_revision = ath5k_hw_radio_revision(ah,
  130. IEEE80211_BAND_5GHZ);
  131. /* Try to identify radio chip based on its srev */
  132. switch (ah->ah_radio_5ghz_revision & 0xf0) {
  133. case AR5K_SREV_RAD_5111:
  134. ah->ah_radio = AR5K_RF5111;
  135. ah->ah_single_chip = false;
  136. ah->ah_radio_2ghz_revision = ath5k_hw_radio_revision(ah,
  137. IEEE80211_BAND_2GHZ);
  138. break;
  139. case AR5K_SREV_RAD_5112:
  140. case AR5K_SREV_RAD_2112:
  141. ah->ah_radio = AR5K_RF5112;
  142. ah->ah_single_chip = false;
  143. ah->ah_radio_2ghz_revision = ath5k_hw_radio_revision(ah,
  144. IEEE80211_BAND_2GHZ);
  145. break;
  146. case AR5K_SREV_RAD_2413:
  147. ah->ah_radio = AR5K_RF2413;
  148. ah->ah_single_chip = true;
  149. break;
  150. case AR5K_SREV_RAD_5413:
  151. ah->ah_radio = AR5K_RF5413;
  152. ah->ah_single_chip = true;
  153. break;
  154. case AR5K_SREV_RAD_2316:
  155. ah->ah_radio = AR5K_RF2316;
  156. ah->ah_single_chip = true;
  157. break;
  158. case AR5K_SREV_RAD_2317:
  159. ah->ah_radio = AR5K_RF2317;
  160. ah->ah_single_chip = true;
  161. break;
  162. case AR5K_SREV_RAD_5424:
  163. if (ah->ah_mac_version == AR5K_SREV_AR2425 ||
  164. ah->ah_mac_version == AR5K_SREV_AR2417) {
  165. ah->ah_radio = AR5K_RF2425;
  166. ah->ah_single_chip = true;
  167. } else {
  168. ah->ah_radio = AR5K_RF5413;
  169. ah->ah_single_chip = true;
  170. }
  171. break;
  172. default:
  173. /* Identify radio based on mac/phy srev */
  174. if (ah->ah_version == AR5K_AR5210) {
  175. ah->ah_radio = AR5K_RF5110;
  176. ah->ah_single_chip = false;
  177. } else if (ah->ah_version == AR5K_AR5211) {
  178. ah->ah_radio = AR5K_RF5111;
  179. ah->ah_single_chip = false;
  180. ah->ah_radio_2ghz_revision = ath5k_hw_radio_revision(ah,
  181. IEEE80211_BAND_2GHZ);
  182. } else if (ah->ah_mac_version == (AR5K_SREV_AR2425 >> 4) ||
  183. ah->ah_mac_version == (AR5K_SREV_AR2417 >> 4) ||
  184. ah->ah_phy_revision == AR5K_SREV_PHY_2425) {
  185. ah->ah_radio = AR5K_RF2425;
  186. ah->ah_single_chip = true;
  187. ah->ah_radio_5ghz_revision = AR5K_SREV_RAD_2425;
  188. } else if (srev == AR5K_SREV_AR5213A &&
  189. ah->ah_phy_revision == AR5K_SREV_PHY_5212B) {
  190. ah->ah_radio = AR5K_RF5112;
  191. ah->ah_single_chip = false;
  192. ah->ah_radio_5ghz_revision = AR5K_SREV_RAD_5112B;
  193. } else if (ah->ah_mac_version == (AR5K_SREV_AR2415 >> 4) ||
  194. ah->ah_mac_version == (AR5K_SREV_AR2315_R6 >> 4)) {
  195. ah->ah_radio = AR5K_RF2316;
  196. ah->ah_single_chip = true;
  197. ah->ah_radio_5ghz_revision = AR5K_SREV_RAD_2316;
  198. } else if (ah->ah_mac_version == (AR5K_SREV_AR5414 >> 4) ||
  199. ah->ah_phy_revision == AR5K_SREV_PHY_5413) {
  200. ah->ah_radio = AR5K_RF5413;
  201. ah->ah_single_chip = true;
  202. ah->ah_radio_5ghz_revision = AR5K_SREV_RAD_5413;
  203. } else if (ah->ah_mac_version == (AR5K_SREV_AR2414 >> 4) ||
  204. ah->ah_phy_revision == AR5K_SREV_PHY_2413) {
  205. ah->ah_radio = AR5K_RF2413;
  206. ah->ah_single_chip = true;
  207. ah->ah_radio_5ghz_revision = AR5K_SREV_RAD_2413;
  208. } else {
  209. ATH5K_ERR(ah, "Couldn't identify radio revision.\n");
  210. ret = -ENODEV;
  211. goto err;
  212. }
  213. }
  214. /* Return on unsupported chips (unsupported eeprom etc) */
  215. if ((srev >= AR5K_SREV_AR5416) && (srev < AR5K_SREV_AR2425)) {
  216. ATH5K_ERR(ah, "Device not yet supported.\n");
  217. ret = -ENODEV;
  218. goto err;
  219. }
  220. /*
  221. * POST
  222. */
  223. ret = ath5k_hw_post(ah);
  224. if (ret)
  225. goto err;
  226. /* Enable pci core retry fix on Hainan (5213A) and later chips */
  227. if (srev >= AR5K_SREV_AR5213A)
  228. AR5K_REG_ENABLE_BITS(ah, AR5K_PCICFG, AR5K_PCICFG_RETRY_FIX);
  229. /*
  230. * Get card capabilities, calibration values etc
  231. * TODO: EEPROM work
  232. */
  233. ret = ath5k_eeprom_init(ah);
  234. if (ret) {
  235. ATH5K_ERR(ah, "unable to init EEPROM\n");
  236. goto err;
  237. }
  238. ee = &ah->ah_capabilities.cap_eeprom;
  239. /*
  240. * Write PCI-E power save settings
  241. */
  242. if ((ah->ah_version == AR5K_AR5212) && pdev && (pci_is_pcie(pdev))) {
  243. ath5k_hw_reg_write(ah, 0x9248fc00, AR5K_PCIE_SERDES);
  244. ath5k_hw_reg_write(ah, 0x24924924, AR5K_PCIE_SERDES);
  245. /* Shut off RX when elecidle is asserted */
  246. ath5k_hw_reg_write(ah, 0x28000039, AR5K_PCIE_SERDES);
  247. ath5k_hw_reg_write(ah, 0x53160824, AR5K_PCIE_SERDES);
  248. /* If serdes programming is enabled, increase PCI-E
  249. * tx power for systems with long trace from host
  250. * to minicard connector. */
  251. if (ee->ee_serdes)
  252. ath5k_hw_reg_write(ah, 0xe5980579, AR5K_PCIE_SERDES);
  253. else
  254. ath5k_hw_reg_write(ah, 0xf6800579, AR5K_PCIE_SERDES);
  255. /* Shut off PLL and CLKREQ active in L1 */
  256. ath5k_hw_reg_write(ah, 0x001defff, AR5K_PCIE_SERDES);
  257. /* Preserve other settings */
  258. ath5k_hw_reg_write(ah, 0x1aaabe40, AR5K_PCIE_SERDES);
  259. ath5k_hw_reg_write(ah, 0xbe105554, AR5K_PCIE_SERDES);
  260. ath5k_hw_reg_write(ah, 0x000e3007, AR5K_PCIE_SERDES);
  261. /* Reset SERDES to load new settings */
  262. ath5k_hw_reg_write(ah, 0x00000000, AR5K_PCIE_SERDES_RESET);
  263. usleep_range(1000, 1500);
  264. }
  265. /* Get misc capabilities */
  266. ret = ath5k_hw_set_capabilities(ah);
  267. if (ret) {
  268. ATH5K_ERR(ah, "unable to get device capabilities\n");
  269. goto err;
  270. }
  271. /* Crypto settings */
  272. common->keymax = (ah->ah_version == AR5K_AR5210 ?
  273. AR5K_KEYTABLE_SIZE_5210 : AR5K_KEYTABLE_SIZE_5211);
  274. if (srev >= AR5K_SREV_AR5212_V4 &&
  275. (ee->ee_version < AR5K_EEPROM_VERSION_5_0 ||
  276. !AR5K_EEPROM_AES_DIS(ee->ee_misc5)))
  277. common->crypt_caps |= ATH_CRYPT_CAP_CIPHER_AESCCM;
  278. if (srev >= AR5K_SREV_AR2414) {
  279. common->crypt_caps |= ATH_CRYPT_CAP_MIC_COMBINED;
  280. AR5K_REG_ENABLE_BITS(ah, AR5K_MISC_MODE,
  281. AR5K_MISC_MODE_COMBINED_MIC);
  282. }
  283. /* MAC address is cleared until add_interface */
  284. ath5k_hw_set_lladdr(ah, zero_mac);
  285. /* Set BSSID to bcast address: ff:ff:ff:ff:ff:ff for now */
  286. memcpy(common->curbssid, ath_bcast_mac, ETH_ALEN);
  287. ath5k_hw_set_bssid(ah);
  288. ath5k_hw_set_opmode(ah, ah->opmode);
  289. ath5k_hw_rfgain_opt_init(ah);
  290. ath5k_hw_init_nfcal_hist(ah);
  291. /* turn on HW LEDs */
  292. ath5k_hw_set_ledstate(ah, AR5K_LED_INIT);
  293. return 0;
  294. err:
  295. return ret;
  296. }
  297. /**
  298. * ath5k_hw_deinit() - Free the &struct ath5k_hw
  299. * @ah: The &struct ath5k_hw
  300. */
  301. void ath5k_hw_deinit(struct ath5k_hw *ah)
  302. {
  303. __set_bit(ATH_STAT_INVALID, ah->status);
  304. kfree(ah->ah_rf_banks);
  305. ath5k_eeprom_detach(ah);
  306. /* assume interrupts are down */
  307. }