phy.c 108 KB

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  1. /*
  2. * Copyright (c) 2004-2007 Reyk Floeter <reyk@openbsd.org>
  3. * Copyright (c) 2006-2009 Nick Kossifidis <mickflemm@gmail.com>
  4. * Copyright (c) 2007-2008 Jiri Slaby <jirislaby@gmail.com>
  5. * Copyright (c) 2008-2009 Felix Fietkau <nbd@openwrt.org>
  6. *
  7. * Permission to use, copy, modify, and distribute this software for any
  8. * purpose with or without fee is hereby granted, provided that the above
  9. * copyright notice and this permission notice appear in all copies.
  10. *
  11. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  12. * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  13. * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
  14. * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  15. * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
  16. * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
  17. * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  18. *
  19. */
  20. /***********************\
  21. * PHY related functions *
  22. \***********************/
  23. #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  24. #include <linux/delay.h>
  25. #include <linux/slab.h>
  26. #include <asm/unaligned.h>
  27. #include "ath5k.h"
  28. #include "reg.h"
  29. #include "rfbuffer.h"
  30. #include "rfgain.h"
  31. #include "../regd.h"
  32. /**
  33. * DOC: PHY related functions
  34. *
  35. * Here we handle the low-level functions related to baseband
  36. * and analog frontend (RF) parts. This is by far the most complex
  37. * part of the hw code so make sure you know what you are doing.
  38. *
  39. * Here is a list of what this is all about:
  40. *
  41. * - Channel setting/switching
  42. *
  43. * - Automatic Gain Control (AGC) calibration
  44. *
  45. * - Noise Floor calibration
  46. *
  47. * - I/Q imbalance calibration (QAM correction)
  48. *
  49. * - Calibration due to thermal changes (gain_F)
  50. *
  51. * - Spur noise mitigation
  52. *
  53. * - RF/PHY initialization for the various operating modes and bwmodes
  54. *
  55. * - Antenna control
  56. *
  57. * - TX power control per channel/rate/packet type
  58. *
  59. * Also have in mind we never got documentation for most of these
  60. * functions, what we have comes mostly from Atheros's code, reverse
  61. * engineering and patent docs/presentations etc.
  62. */
  63. /******************\
  64. * Helper functions *
  65. \******************/
  66. /**
  67. * ath5k_hw_radio_revision() - Get the PHY Chip revision
  68. * @ah: The &struct ath5k_hw
  69. * @band: One of enum ieee80211_band
  70. *
  71. * Returns the revision number of a 2GHz, 5GHz or single chip
  72. * radio.
  73. */
  74. u16
  75. ath5k_hw_radio_revision(struct ath5k_hw *ah, enum ieee80211_band band)
  76. {
  77. unsigned int i;
  78. u32 srev;
  79. u16 ret;
  80. /*
  81. * Set the radio chip access register
  82. */
  83. switch (band) {
  84. case IEEE80211_BAND_2GHZ:
  85. ath5k_hw_reg_write(ah, AR5K_PHY_SHIFT_2GHZ, AR5K_PHY(0));
  86. break;
  87. case IEEE80211_BAND_5GHZ:
  88. ath5k_hw_reg_write(ah, AR5K_PHY_SHIFT_5GHZ, AR5K_PHY(0));
  89. break;
  90. default:
  91. return 0;
  92. }
  93. usleep_range(2000, 2500);
  94. /* ...wait until PHY is ready and read the selected radio revision */
  95. ath5k_hw_reg_write(ah, 0x00001c16, AR5K_PHY(0x34));
  96. for (i = 0; i < 8; i++)
  97. ath5k_hw_reg_write(ah, 0x00010000, AR5K_PHY(0x20));
  98. if (ah->ah_version == AR5K_AR5210) {
  99. srev = (ath5k_hw_reg_read(ah, AR5K_PHY(256)) >> 28) & 0xf;
  100. ret = (u16)ath5k_hw_bitswap(srev, 4) + 1;
  101. } else {
  102. srev = (ath5k_hw_reg_read(ah, AR5K_PHY(0x100)) >> 24) & 0xff;
  103. ret = (u16)ath5k_hw_bitswap(((srev & 0xf0) >> 4) |
  104. ((srev & 0x0f) << 4), 8);
  105. }
  106. /* Reset to the 5GHz mode */
  107. ath5k_hw_reg_write(ah, AR5K_PHY_SHIFT_5GHZ, AR5K_PHY(0));
  108. return ret;
  109. }
  110. /**
  111. * ath5k_channel_ok() - Check if a channel is supported by the hw
  112. * @ah: The &struct ath5k_hw
  113. * @channel: The &struct ieee80211_channel
  114. *
  115. * Note: We don't do any regulatory domain checks here, it's just
  116. * a sanity check.
  117. */
  118. bool
  119. ath5k_channel_ok(struct ath5k_hw *ah, struct ieee80211_channel *channel)
  120. {
  121. u16 freq = channel->center_freq;
  122. /* Check if the channel is in our supported range */
  123. if (channel->band == IEEE80211_BAND_2GHZ) {
  124. if ((freq >= ah->ah_capabilities.cap_range.range_2ghz_min) &&
  125. (freq <= ah->ah_capabilities.cap_range.range_2ghz_max))
  126. return true;
  127. } else if (channel->band == IEEE80211_BAND_5GHZ)
  128. if ((freq >= ah->ah_capabilities.cap_range.range_5ghz_min) &&
  129. (freq <= ah->ah_capabilities.cap_range.range_5ghz_max))
  130. return true;
  131. return false;
  132. }
  133. /**
  134. * ath5k_hw_chan_has_spur_noise() - Check if channel is sensitive to spur noise
  135. * @ah: The &struct ath5k_hw
  136. * @channel: The &struct ieee80211_channel
  137. */
  138. bool
  139. ath5k_hw_chan_has_spur_noise(struct ath5k_hw *ah,
  140. struct ieee80211_channel *channel)
  141. {
  142. u8 refclk_freq;
  143. if ((ah->ah_radio == AR5K_RF5112) ||
  144. (ah->ah_radio == AR5K_RF5413) ||
  145. (ah->ah_radio == AR5K_RF2413) ||
  146. (ah->ah_mac_version == (AR5K_SREV_AR2417 >> 4)))
  147. refclk_freq = 40;
  148. else
  149. refclk_freq = 32;
  150. if ((channel->center_freq % refclk_freq != 0) &&
  151. ((channel->center_freq % refclk_freq < 10) ||
  152. (channel->center_freq % refclk_freq > 22)))
  153. return true;
  154. else
  155. return false;
  156. }
  157. /**
  158. * ath5k_hw_rfb_op() - Perform an operation on the given RF Buffer
  159. * @ah: The &struct ath5k_hw
  160. * @rf_regs: The struct ath5k_rf_reg
  161. * @val: New value
  162. * @reg_id: RF register ID
  163. * @set: Indicate we need to swap data
  164. *
  165. * This is an internal function used to modify RF Banks before
  166. * writing them to AR5K_RF_BUFFER. Check out rfbuffer.h for more
  167. * infos.
  168. */
  169. static unsigned int
  170. ath5k_hw_rfb_op(struct ath5k_hw *ah, const struct ath5k_rf_reg *rf_regs,
  171. u32 val, u8 reg_id, bool set)
  172. {
  173. const struct ath5k_rf_reg *rfreg = NULL;
  174. u8 offset, bank, num_bits, col, position;
  175. u16 entry;
  176. u32 mask, data, last_bit, bits_shifted, first_bit;
  177. u32 *rfb;
  178. s32 bits_left;
  179. int i;
  180. data = 0;
  181. rfb = ah->ah_rf_banks;
  182. for (i = 0; i < ah->ah_rf_regs_count; i++) {
  183. if (rf_regs[i].index == reg_id) {
  184. rfreg = &rf_regs[i];
  185. break;
  186. }
  187. }
  188. if (rfb == NULL || rfreg == NULL) {
  189. ATH5K_PRINTF("Rf register not found!\n");
  190. /* should not happen */
  191. return 0;
  192. }
  193. bank = rfreg->bank;
  194. num_bits = rfreg->field.len;
  195. first_bit = rfreg->field.pos;
  196. col = rfreg->field.col;
  197. /* first_bit is an offset from bank's
  198. * start. Since we have all banks on
  199. * the same array, we use this offset
  200. * to mark each bank's start */
  201. offset = ah->ah_offset[bank];
  202. /* Boundary check */
  203. if (!(col <= 3 && num_bits <= 32 && first_bit + num_bits <= 319)) {
  204. ATH5K_PRINTF("invalid values at offset %u\n", offset);
  205. return 0;
  206. }
  207. entry = ((first_bit - 1) / 8) + offset;
  208. position = (first_bit - 1) % 8;
  209. if (set)
  210. data = ath5k_hw_bitswap(val, num_bits);
  211. for (bits_shifted = 0, bits_left = num_bits; bits_left > 0;
  212. position = 0, entry++) {
  213. last_bit = (position + bits_left > 8) ? 8 :
  214. position + bits_left;
  215. mask = (((1 << last_bit) - 1) ^ ((1 << position) - 1)) <<
  216. (col * 8);
  217. if (set) {
  218. rfb[entry] &= ~mask;
  219. rfb[entry] |= ((data << position) << (col * 8)) & mask;
  220. data >>= (8 - position);
  221. } else {
  222. data |= (((rfb[entry] & mask) >> (col * 8)) >> position)
  223. << bits_shifted;
  224. bits_shifted += last_bit - position;
  225. }
  226. bits_left -= 8 - position;
  227. }
  228. data = set ? 1 : ath5k_hw_bitswap(data, num_bits);
  229. return data;
  230. }
  231. /**
  232. * ath5k_hw_write_ofdm_timings() - set OFDM timings on AR5212
  233. * @ah: the &struct ath5k_hw
  234. * @channel: the currently set channel upon reset
  235. *
  236. * Write the delta slope coefficient (used on pilot tracking ?) for OFDM
  237. * operation on the AR5212 upon reset. This is a helper for ath5k_hw_phy_init.
  238. *
  239. * Since delta slope is floating point we split it on its exponent and
  240. * mantissa and provide these values on hw.
  241. *
  242. * For more infos i think this patent is related
  243. * "http://www.freepatentsonline.com/7184495.html"
  244. */
  245. static inline int
  246. ath5k_hw_write_ofdm_timings(struct ath5k_hw *ah,
  247. struct ieee80211_channel *channel)
  248. {
  249. /* Get exponent and mantissa and set it */
  250. u32 coef_scaled, coef_exp, coef_man,
  251. ds_coef_exp, ds_coef_man, clock;
  252. BUG_ON(!(ah->ah_version == AR5K_AR5212) ||
  253. (channel->hw_value == AR5K_MODE_11B));
  254. /* Get coefficient
  255. * ALGO: coef = (5 * clock / carrier_freq) / 2
  256. * we scale coef by shifting clock value by 24 for
  257. * better precision since we use integers */
  258. switch (ah->ah_bwmode) {
  259. case AR5K_BWMODE_40MHZ:
  260. clock = 40 * 2;
  261. break;
  262. case AR5K_BWMODE_10MHZ:
  263. clock = 40 / 2;
  264. break;
  265. case AR5K_BWMODE_5MHZ:
  266. clock = 40 / 4;
  267. break;
  268. default:
  269. clock = 40;
  270. break;
  271. }
  272. coef_scaled = ((5 * (clock << 24)) / 2) / channel->center_freq;
  273. /* Get exponent
  274. * ALGO: coef_exp = 14 - highest set bit position */
  275. coef_exp = ilog2(coef_scaled);
  276. /* Doesn't make sense if it's zero*/
  277. if (!coef_scaled || !coef_exp)
  278. return -EINVAL;
  279. /* Note: we've shifted coef_scaled by 24 */
  280. coef_exp = 14 - (coef_exp - 24);
  281. /* Get mantissa (significant digits)
  282. * ALGO: coef_mant = floor(coef_scaled* 2^coef_exp+0.5) */
  283. coef_man = coef_scaled +
  284. (1 << (24 - coef_exp - 1));
  285. /* Calculate delta slope coefficient exponent
  286. * and mantissa (remove scaling) and set them on hw */
  287. ds_coef_man = coef_man >> (24 - coef_exp);
  288. ds_coef_exp = coef_exp - 16;
  289. AR5K_REG_WRITE_BITS(ah, AR5K_PHY_TIMING_3,
  290. AR5K_PHY_TIMING_3_DSC_MAN, ds_coef_man);
  291. AR5K_REG_WRITE_BITS(ah, AR5K_PHY_TIMING_3,
  292. AR5K_PHY_TIMING_3_DSC_EXP, ds_coef_exp);
  293. return 0;
  294. }
  295. /**
  296. * ath5k_hw_phy_disable() - Disable PHY
  297. * @ah: The &struct ath5k_hw
  298. */
  299. int ath5k_hw_phy_disable(struct ath5k_hw *ah)
  300. {
  301. /*Just a try M.F.*/
  302. ath5k_hw_reg_write(ah, AR5K_PHY_ACT_DISABLE, AR5K_PHY_ACT);
  303. return 0;
  304. }
  305. /**
  306. * ath5k_hw_wait_for_synth() - Wait for synth to settle
  307. * @ah: The &struct ath5k_hw
  308. * @channel: The &struct ieee80211_channel
  309. */
  310. static void
  311. ath5k_hw_wait_for_synth(struct ath5k_hw *ah,
  312. struct ieee80211_channel *channel)
  313. {
  314. /*
  315. * On 5211+ read activation -> rx delay
  316. * and use it (100ns steps).
  317. */
  318. if (ah->ah_version != AR5K_AR5210) {
  319. u32 delay;
  320. delay = ath5k_hw_reg_read(ah, AR5K_PHY_RX_DELAY) &
  321. AR5K_PHY_RX_DELAY_M;
  322. delay = (channel->hw_value == AR5K_MODE_11B) ?
  323. ((delay << 2) / 22) : (delay / 10);
  324. if (ah->ah_bwmode == AR5K_BWMODE_10MHZ)
  325. delay = delay << 1;
  326. if (ah->ah_bwmode == AR5K_BWMODE_5MHZ)
  327. delay = delay << 2;
  328. /* XXX: /2 on turbo ? Let's be safe
  329. * for now */
  330. usleep_range(100 + delay, 100 + (2 * delay));
  331. } else {
  332. usleep_range(1000, 1500);
  333. }
  334. }
  335. /**********************\
  336. * RF Gain optimization *
  337. \**********************/
  338. /**
  339. * DOC: RF Gain optimization
  340. *
  341. * This code is used to optimize RF gain on different environments
  342. * (temperature mostly) based on feedback from a power detector.
  343. *
  344. * It's only used on RF5111 and RF5112, later RF chips seem to have
  345. * auto adjustment on hw -notice they have a much smaller BANK 7 and
  346. * no gain optimization ladder-.
  347. *
  348. * For more infos check out this patent doc
  349. * "http://www.freepatentsonline.com/7400691.html"
  350. *
  351. * This paper describes power drops as seen on the receiver due to
  352. * probe packets
  353. * "http://www.cnri.dit.ie/publications/ICT08%20-%20Practical%20Issues
  354. * %20of%20Power%20Control.pdf"
  355. *
  356. * And this is the MadWiFi bug entry related to the above
  357. * "http://madwifi-project.org/ticket/1659"
  358. * with various measurements and diagrams
  359. */
  360. /**
  361. * ath5k_hw_rfgain_opt_init() - Initialize ah_gain during attach
  362. * @ah: The &struct ath5k_hw
  363. */
  364. int ath5k_hw_rfgain_opt_init(struct ath5k_hw *ah)
  365. {
  366. /* Initialize the gain optimization values */
  367. switch (ah->ah_radio) {
  368. case AR5K_RF5111:
  369. ah->ah_gain.g_step_idx = rfgain_opt_5111.go_default;
  370. ah->ah_gain.g_low = 20;
  371. ah->ah_gain.g_high = 35;
  372. ah->ah_gain.g_state = AR5K_RFGAIN_ACTIVE;
  373. break;
  374. case AR5K_RF5112:
  375. ah->ah_gain.g_step_idx = rfgain_opt_5112.go_default;
  376. ah->ah_gain.g_low = 20;
  377. ah->ah_gain.g_high = 85;
  378. ah->ah_gain.g_state = AR5K_RFGAIN_ACTIVE;
  379. break;
  380. default:
  381. return -EINVAL;
  382. }
  383. return 0;
  384. }
  385. /**
  386. * ath5k_hw_request_rfgain_probe() - Request a PAPD probe packet
  387. * @ah: The &struct ath5k_hw
  388. *
  389. * Schedules a gain probe check on the next transmitted packet.
  390. * That means our next packet is going to be sent with lower
  391. * tx power and a Peak to Average Power Detector (PAPD) will try
  392. * to measure the gain.
  393. *
  394. * TODO: Force a tx packet (bypassing PCU arbitrator etc)
  395. * just after we enable the probe so that we don't mess with
  396. * standard traffic.
  397. */
  398. static void
  399. ath5k_hw_request_rfgain_probe(struct ath5k_hw *ah)
  400. {
  401. /* Skip if gain calibration is inactive or
  402. * we already handle a probe request */
  403. if (ah->ah_gain.g_state != AR5K_RFGAIN_ACTIVE)
  404. return;
  405. /* Send the packet with 2dB below max power as
  406. * patent doc suggest */
  407. ath5k_hw_reg_write(ah, AR5K_REG_SM(ah->ah_txpower.txp_ofdm - 4,
  408. AR5K_PHY_PAPD_PROBE_TXPOWER) |
  409. AR5K_PHY_PAPD_PROBE_TX_NEXT, AR5K_PHY_PAPD_PROBE);
  410. ah->ah_gain.g_state = AR5K_RFGAIN_READ_REQUESTED;
  411. }
  412. /**
  413. * ath5k_hw_rf_gainf_corr() - Calculate Gain_F measurement correction
  414. * @ah: The &struct ath5k_hw
  415. *
  416. * Calculate Gain_F measurement correction
  417. * based on the current step for RF5112 rev. 2
  418. */
  419. static u32
  420. ath5k_hw_rf_gainf_corr(struct ath5k_hw *ah)
  421. {
  422. u32 mix, step;
  423. u32 *rf;
  424. const struct ath5k_gain_opt *go;
  425. const struct ath5k_gain_opt_step *g_step;
  426. const struct ath5k_rf_reg *rf_regs;
  427. /* Only RF5112 Rev. 2 supports it */
  428. if ((ah->ah_radio != AR5K_RF5112) ||
  429. (ah->ah_radio_5ghz_revision <= AR5K_SREV_RAD_5112A))
  430. return 0;
  431. go = &rfgain_opt_5112;
  432. rf_regs = rf_regs_5112a;
  433. ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_5112a);
  434. g_step = &go->go_step[ah->ah_gain.g_step_idx];
  435. if (ah->ah_rf_banks == NULL)
  436. return 0;
  437. rf = ah->ah_rf_banks;
  438. ah->ah_gain.g_f_corr = 0;
  439. /* No VGA (Variable Gain Amplifier) override, skip */
  440. if (ath5k_hw_rfb_op(ah, rf_regs, 0, AR5K_RF_MIXVGA_OVR, false) != 1)
  441. return 0;
  442. /* Mix gain stepping */
  443. step = ath5k_hw_rfb_op(ah, rf_regs, 0, AR5K_RF_MIXGAIN_STEP, false);
  444. /* Mix gain override */
  445. mix = g_step->gos_param[0];
  446. switch (mix) {
  447. case 3:
  448. ah->ah_gain.g_f_corr = step * 2;
  449. break;
  450. case 2:
  451. ah->ah_gain.g_f_corr = (step - 5) * 2;
  452. break;
  453. case 1:
  454. ah->ah_gain.g_f_corr = step;
  455. break;
  456. default:
  457. ah->ah_gain.g_f_corr = 0;
  458. break;
  459. }
  460. return ah->ah_gain.g_f_corr;
  461. }
  462. /**
  463. * ath5k_hw_rf_check_gainf_readback() - Validate Gain_F feedback from detector
  464. * @ah: The &struct ath5k_hw
  465. *
  466. * Check if current gain_F measurement is in the range of our
  467. * power detector windows. If we get a measurement outside range
  468. * we know it's not accurate (detectors can't measure anything outside
  469. * their detection window) so we must ignore it.
  470. *
  471. * Returns true if readback was O.K. or false on failure
  472. */
  473. static bool
  474. ath5k_hw_rf_check_gainf_readback(struct ath5k_hw *ah)
  475. {
  476. const struct ath5k_rf_reg *rf_regs;
  477. u32 step, mix_ovr, level[4];
  478. u32 *rf;
  479. if (ah->ah_rf_banks == NULL)
  480. return false;
  481. rf = ah->ah_rf_banks;
  482. if (ah->ah_radio == AR5K_RF5111) {
  483. rf_regs = rf_regs_5111;
  484. ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_5111);
  485. step = ath5k_hw_rfb_op(ah, rf_regs, 0, AR5K_RF_RFGAIN_STEP,
  486. false);
  487. level[0] = 0;
  488. level[1] = (step == 63) ? 50 : step + 4;
  489. level[2] = (step != 63) ? 64 : level[0];
  490. level[3] = level[2] + 50;
  491. ah->ah_gain.g_high = level[3] -
  492. (step == 63 ? AR5K_GAIN_DYN_ADJUST_HI_MARGIN : -5);
  493. ah->ah_gain.g_low = level[0] +
  494. (step == 63 ? AR5K_GAIN_DYN_ADJUST_LO_MARGIN : 0);
  495. } else {
  496. rf_regs = rf_regs_5112;
  497. ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_5112);
  498. mix_ovr = ath5k_hw_rfb_op(ah, rf_regs, 0, AR5K_RF_MIXVGA_OVR,
  499. false);
  500. level[0] = level[2] = 0;
  501. if (mix_ovr == 1) {
  502. level[1] = level[3] = 83;
  503. } else {
  504. level[1] = level[3] = 107;
  505. ah->ah_gain.g_high = 55;
  506. }
  507. }
  508. return (ah->ah_gain.g_current >= level[0] &&
  509. ah->ah_gain.g_current <= level[1]) ||
  510. (ah->ah_gain.g_current >= level[2] &&
  511. ah->ah_gain.g_current <= level[3]);
  512. }
  513. /**
  514. * ath5k_hw_rf_gainf_adjust() - Perform Gain_F adjustment
  515. * @ah: The &struct ath5k_hw
  516. *
  517. * Choose the right target gain based on current gain
  518. * and RF gain optimization ladder
  519. */
  520. static s8
  521. ath5k_hw_rf_gainf_adjust(struct ath5k_hw *ah)
  522. {
  523. const struct ath5k_gain_opt *go;
  524. const struct ath5k_gain_opt_step *g_step;
  525. int ret = 0;
  526. switch (ah->ah_radio) {
  527. case AR5K_RF5111:
  528. go = &rfgain_opt_5111;
  529. break;
  530. case AR5K_RF5112:
  531. go = &rfgain_opt_5112;
  532. break;
  533. default:
  534. return 0;
  535. }
  536. g_step = &go->go_step[ah->ah_gain.g_step_idx];
  537. if (ah->ah_gain.g_current >= ah->ah_gain.g_high) {
  538. /* Reached maximum */
  539. if (ah->ah_gain.g_step_idx == 0)
  540. return -1;
  541. for (ah->ah_gain.g_target = ah->ah_gain.g_current;
  542. ah->ah_gain.g_target >= ah->ah_gain.g_high &&
  543. ah->ah_gain.g_step_idx > 0;
  544. g_step = &go->go_step[ah->ah_gain.g_step_idx])
  545. ah->ah_gain.g_target -= 2 *
  546. (go->go_step[--(ah->ah_gain.g_step_idx)].gos_gain -
  547. g_step->gos_gain);
  548. ret = 1;
  549. goto done;
  550. }
  551. if (ah->ah_gain.g_current <= ah->ah_gain.g_low) {
  552. /* Reached minimum */
  553. if (ah->ah_gain.g_step_idx == (go->go_steps_count - 1))
  554. return -2;
  555. for (ah->ah_gain.g_target = ah->ah_gain.g_current;
  556. ah->ah_gain.g_target <= ah->ah_gain.g_low &&
  557. ah->ah_gain.g_step_idx < go->go_steps_count - 1;
  558. g_step = &go->go_step[ah->ah_gain.g_step_idx])
  559. ah->ah_gain.g_target -= 2 *
  560. (go->go_step[++ah->ah_gain.g_step_idx].gos_gain -
  561. g_step->gos_gain);
  562. ret = 2;
  563. goto done;
  564. }
  565. done:
  566. ATH5K_DBG(ah, ATH5K_DEBUG_CALIBRATE,
  567. "ret %d, gain step %u, current gain %u, target gain %u\n",
  568. ret, ah->ah_gain.g_step_idx, ah->ah_gain.g_current,
  569. ah->ah_gain.g_target);
  570. return ret;
  571. }
  572. /**
  573. * ath5k_hw_gainf_calibrate() - Do a gain_F calibration
  574. * @ah: The &struct ath5k_hw
  575. *
  576. * Main callback for thermal RF gain calibration engine
  577. * Check for a new gain reading and schedule an adjustment
  578. * if needed.
  579. *
  580. * Returns one of enum ath5k_rfgain codes
  581. */
  582. enum ath5k_rfgain
  583. ath5k_hw_gainf_calibrate(struct ath5k_hw *ah)
  584. {
  585. u32 data, type;
  586. struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
  587. if (ah->ah_rf_banks == NULL ||
  588. ah->ah_gain.g_state == AR5K_RFGAIN_INACTIVE)
  589. return AR5K_RFGAIN_INACTIVE;
  590. /* No check requested, either engine is inactive
  591. * or an adjustment is already requested */
  592. if (ah->ah_gain.g_state != AR5K_RFGAIN_READ_REQUESTED)
  593. goto done;
  594. /* Read the PAPD (Peak to Average Power Detector)
  595. * register */
  596. data = ath5k_hw_reg_read(ah, AR5K_PHY_PAPD_PROBE);
  597. /* No probe is scheduled, read gain_F measurement */
  598. if (!(data & AR5K_PHY_PAPD_PROBE_TX_NEXT)) {
  599. ah->ah_gain.g_current = data >> AR5K_PHY_PAPD_PROBE_GAINF_S;
  600. type = AR5K_REG_MS(data, AR5K_PHY_PAPD_PROBE_TYPE);
  601. /* If tx packet is CCK correct the gain_F measurement
  602. * by cck ofdm gain delta */
  603. if (type == AR5K_PHY_PAPD_PROBE_TYPE_CCK) {
  604. if (ah->ah_radio_5ghz_revision >= AR5K_SREV_RAD_5112A)
  605. ah->ah_gain.g_current +=
  606. ee->ee_cck_ofdm_gain_delta;
  607. else
  608. ah->ah_gain.g_current +=
  609. AR5K_GAIN_CCK_PROBE_CORR;
  610. }
  611. /* Further correct gain_F measurement for
  612. * RF5112A radios */
  613. if (ah->ah_radio_5ghz_revision >= AR5K_SREV_RAD_5112A) {
  614. ath5k_hw_rf_gainf_corr(ah);
  615. ah->ah_gain.g_current =
  616. ah->ah_gain.g_current >= ah->ah_gain.g_f_corr ?
  617. (ah->ah_gain.g_current - ah->ah_gain.g_f_corr) :
  618. 0;
  619. }
  620. /* Check if measurement is ok and if we need
  621. * to adjust gain, schedule a gain adjustment,
  622. * else switch back to the active state */
  623. if (ath5k_hw_rf_check_gainf_readback(ah) &&
  624. AR5K_GAIN_CHECK_ADJUST(&ah->ah_gain) &&
  625. ath5k_hw_rf_gainf_adjust(ah)) {
  626. ah->ah_gain.g_state = AR5K_RFGAIN_NEED_CHANGE;
  627. } else {
  628. ah->ah_gain.g_state = AR5K_RFGAIN_ACTIVE;
  629. }
  630. }
  631. done:
  632. return ah->ah_gain.g_state;
  633. }
  634. /**
  635. * ath5k_hw_rfgain_init() - Write initial RF gain settings to hw
  636. * @ah: The &struct ath5k_hw
  637. * @band: One of enum ieee80211_band
  638. *
  639. * Write initial RF gain table to set the RF sensitivity.
  640. *
  641. * NOTE: This one works on all RF chips and has nothing to do
  642. * with Gain_F calibration
  643. */
  644. static int
  645. ath5k_hw_rfgain_init(struct ath5k_hw *ah, enum ieee80211_band band)
  646. {
  647. const struct ath5k_ini_rfgain *ath5k_rfg;
  648. unsigned int i, size, index;
  649. switch (ah->ah_radio) {
  650. case AR5K_RF5111:
  651. ath5k_rfg = rfgain_5111;
  652. size = ARRAY_SIZE(rfgain_5111);
  653. break;
  654. case AR5K_RF5112:
  655. ath5k_rfg = rfgain_5112;
  656. size = ARRAY_SIZE(rfgain_5112);
  657. break;
  658. case AR5K_RF2413:
  659. ath5k_rfg = rfgain_2413;
  660. size = ARRAY_SIZE(rfgain_2413);
  661. break;
  662. case AR5K_RF2316:
  663. ath5k_rfg = rfgain_2316;
  664. size = ARRAY_SIZE(rfgain_2316);
  665. break;
  666. case AR5K_RF5413:
  667. ath5k_rfg = rfgain_5413;
  668. size = ARRAY_SIZE(rfgain_5413);
  669. break;
  670. case AR5K_RF2317:
  671. case AR5K_RF2425:
  672. ath5k_rfg = rfgain_2425;
  673. size = ARRAY_SIZE(rfgain_2425);
  674. break;
  675. default:
  676. return -EINVAL;
  677. }
  678. index = (band == IEEE80211_BAND_2GHZ) ? 1 : 0;
  679. for (i = 0; i < size; i++) {
  680. AR5K_REG_WAIT(i);
  681. ath5k_hw_reg_write(ah, ath5k_rfg[i].rfg_value[index],
  682. (u32)ath5k_rfg[i].rfg_register);
  683. }
  684. return 0;
  685. }
  686. /********************\
  687. * RF Registers setup *
  688. \********************/
  689. /**
  690. * ath5k_hw_rfregs_init() - Initialize RF register settings
  691. * @ah: The &struct ath5k_hw
  692. * @channel: The &struct ieee80211_channel
  693. * @mode: One of enum ath5k_driver_mode
  694. *
  695. * Setup RF registers by writing RF buffer on hw. For
  696. * more infos on this, check out rfbuffer.h
  697. */
  698. static int
  699. ath5k_hw_rfregs_init(struct ath5k_hw *ah,
  700. struct ieee80211_channel *channel,
  701. unsigned int mode)
  702. {
  703. const struct ath5k_rf_reg *rf_regs;
  704. const struct ath5k_ini_rfbuffer *ini_rfb;
  705. const struct ath5k_gain_opt *go = NULL;
  706. const struct ath5k_gain_opt_step *g_step;
  707. struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
  708. u8 ee_mode = 0;
  709. u32 *rfb;
  710. int i, obdb = -1, bank = -1;
  711. switch (ah->ah_radio) {
  712. case AR5K_RF5111:
  713. rf_regs = rf_regs_5111;
  714. ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_5111);
  715. ini_rfb = rfb_5111;
  716. ah->ah_rf_banks_size = ARRAY_SIZE(rfb_5111);
  717. go = &rfgain_opt_5111;
  718. break;
  719. case AR5K_RF5112:
  720. if (ah->ah_radio_5ghz_revision >= AR5K_SREV_RAD_5112A) {
  721. rf_regs = rf_regs_5112a;
  722. ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_5112a);
  723. ini_rfb = rfb_5112a;
  724. ah->ah_rf_banks_size = ARRAY_SIZE(rfb_5112a);
  725. } else {
  726. rf_regs = rf_regs_5112;
  727. ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_5112);
  728. ini_rfb = rfb_5112;
  729. ah->ah_rf_banks_size = ARRAY_SIZE(rfb_5112);
  730. }
  731. go = &rfgain_opt_5112;
  732. break;
  733. case AR5K_RF2413:
  734. rf_regs = rf_regs_2413;
  735. ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_2413);
  736. ini_rfb = rfb_2413;
  737. ah->ah_rf_banks_size = ARRAY_SIZE(rfb_2413);
  738. break;
  739. case AR5K_RF2316:
  740. rf_regs = rf_regs_2316;
  741. ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_2316);
  742. ini_rfb = rfb_2316;
  743. ah->ah_rf_banks_size = ARRAY_SIZE(rfb_2316);
  744. break;
  745. case AR5K_RF5413:
  746. rf_regs = rf_regs_5413;
  747. ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_5413);
  748. ini_rfb = rfb_5413;
  749. ah->ah_rf_banks_size = ARRAY_SIZE(rfb_5413);
  750. break;
  751. case AR5K_RF2317:
  752. rf_regs = rf_regs_2425;
  753. ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_2425);
  754. ini_rfb = rfb_2317;
  755. ah->ah_rf_banks_size = ARRAY_SIZE(rfb_2317);
  756. break;
  757. case AR5K_RF2425:
  758. rf_regs = rf_regs_2425;
  759. ah->ah_rf_regs_count = ARRAY_SIZE(rf_regs_2425);
  760. if (ah->ah_mac_srev < AR5K_SREV_AR2417) {
  761. ini_rfb = rfb_2425;
  762. ah->ah_rf_banks_size = ARRAY_SIZE(rfb_2425);
  763. } else {
  764. ini_rfb = rfb_2417;
  765. ah->ah_rf_banks_size = ARRAY_SIZE(rfb_2417);
  766. }
  767. break;
  768. default:
  769. return -EINVAL;
  770. }
  771. /* If it's the first time we set RF buffer, allocate
  772. * ah->ah_rf_banks based on ah->ah_rf_banks_size
  773. * we set above */
  774. if (ah->ah_rf_banks == NULL) {
  775. ah->ah_rf_banks = kmalloc(sizeof(u32) * ah->ah_rf_banks_size,
  776. GFP_KERNEL);
  777. if (ah->ah_rf_banks == NULL) {
  778. ATH5K_ERR(ah, "out of memory\n");
  779. return -ENOMEM;
  780. }
  781. }
  782. /* Copy values to modify them */
  783. rfb = ah->ah_rf_banks;
  784. for (i = 0; i < ah->ah_rf_banks_size; i++) {
  785. if (ini_rfb[i].rfb_bank >= AR5K_MAX_RF_BANKS) {
  786. ATH5K_ERR(ah, "invalid bank\n");
  787. return -EINVAL;
  788. }
  789. /* Bank changed, write down the offset */
  790. if (bank != ini_rfb[i].rfb_bank) {
  791. bank = ini_rfb[i].rfb_bank;
  792. ah->ah_offset[bank] = i;
  793. }
  794. rfb[i] = ini_rfb[i].rfb_mode_data[mode];
  795. }
  796. /* Set Output and Driver bias current (OB/DB) */
  797. if (channel->band == IEEE80211_BAND_2GHZ) {
  798. if (channel->hw_value == AR5K_MODE_11B)
  799. ee_mode = AR5K_EEPROM_MODE_11B;
  800. else
  801. ee_mode = AR5K_EEPROM_MODE_11G;
  802. /* For RF511X/RF211X combination we
  803. * use b_OB and b_DB parameters stored
  804. * in eeprom on ee->ee_ob[ee_mode][0]
  805. *
  806. * For all other chips we use OB/DB for 2GHz
  807. * stored in the b/g modal section just like
  808. * 802.11a on ee->ee_ob[ee_mode][1] */
  809. if ((ah->ah_radio == AR5K_RF5111) ||
  810. (ah->ah_radio == AR5K_RF5112))
  811. obdb = 0;
  812. else
  813. obdb = 1;
  814. ath5k_hw_rfb_op(ah, rf_regs, ee->ee_ob[ee_mode][obdb],
  815. AR5K_RF_OB_2GHZ, true);
  816. ath5k_hw_rfb_op(ah, rf_regs, ee->ee_db[ee_mode][obdb],
  817. AR5K_RF_DB_2GHZ, true);
  818. /* RF5111 always needs OB/DB for 5GHz, even if we use 2GHz */
  819. } else if ((channel->band == IEEE80211_BAND_5GHZ) ||
  820. (ah->ah_radio == AR5K_RF5111)) {
  821. /* For 11a, Turbo and XR we need to choose
  822. * OB/DB based on frequency range */
  823. ee_mode = AR5K_EEPROM_MODE_11A;
  824. obdb = channel->center_freq >= 5725 ? 3 :
  825. (channel->center_freq >= 5500 ? 2 :
  826. (channel->center_freq >= 5260 ? 1 :
  827. (channel->center_freq > 4000 ? 0 : -1)));
  828. if (obdb < 0)
  829. return -EINVAL;
  830. ath5k_hw_rfb_op(ah, rf_regs, ee->ee_ob[ee_mode][obdb],
  831. AR5K_RF_OB_5GHZ, true);
  832. ath5k_hw_rfb_op(ah, rf_regs, ee->ee_db[ee_mode][obdb],
  833. AR5K_RF_DB_5GHZ, true);
  834. }
  835. g_step = &go->go_step[ah->ah_gain.g_step_idx];
  836. /* Set turbo mode (N/A on RF5413) */
  837. if ((ah->ah_bwmode == AR5K_BWMODE_40MHZ) &&
  838. (ah->ah_radio != AR5K_RF5413))
  839. ath5k_hw_rfb_op(ah, rf_regs, 1, AR5K_RF_TURBO, false);
  840. /* Bank Modifications (chip-specific) */
  841. if (ah->ah_radio == AR5K_RF5111) {
  842. /* Set gain_F settings according to current step */
  843. if (channel->hw_value != AR5K_MODE_11B) {
  844. AR5K_REG_WRITE_BITS(ah, AR5K_PHY_FRAME_CTL,
  845. AR5K_PHY_FRAME_CTL_TX_CLIP,
  846. g_step->gos_param[0]);
  847. ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[1],
  848. AR5K_RF_PWD_90, true);
  849. ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[2],
  850. AR5K_RF_PWD_84, true);
  851. ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[3],
  852. AR5K_RF_RFGAIN_SEL, true);
  853. /* We programmed gain_F parameters, switch back
  854. * to active state */
  855. ah->ah_gain.g_state = AR5K_RFGAIN_ACTIVE;
  856. }
  857. /* Bank 6/7 setup */
  858. ath5k_hw_rfb_op(ah, rf_regs, !ee->ee_xpd[ee_mode],
  859. AR5K_RF_PWD_XPD, true);
  860. ath5k_hw_rfb_op(ah, rf_regs, ee->ee_x_gain[ee_mode],
  861. AR5K_RF_XPD_GAIN, true);
  862. ath5k_hw_rfb_op(ah, rf_regs, ee->ee_i_gain[ee_mode],
  863. AR5K_RF_GAIN_I, true);
  864. ath5k_hw_rfb_op(ah, rf_regs, ee->ee_xpd[ee_mode],
  865. AR5K_RF_PLO_SEL, true);
  866. /* Tweak power detectors for half/quarter rate support */
  867. if (ah->ah_bwmode == AR5K_BWMODE_5MHZ ||
  868. ah->ah_bwmode == AR5K_BWMODE_10MHZ) {
  869. u8 wait_i;
  870. ath5k_hw_rfb_op(ah, rf_regs, 0x1f,
  871. AR5K_RF_WAIT_S, true);
  872. wait_i = (ah->ah_bwmode == AR5K_BWMODE_5MHZ) ?
  873. 0x1f : 0x10;
  874. ath5k_hw_rfb_op(ah, rf_regs, wait_i,
  875. AR5K_RF_WAIT_I, true);
  876. ath5k_hw_rfb_op(ah, rf_regs, 3,
  877. AR5K_RF_MAX_TIME, true);
  878. }
  879. }
  880. if (ah->ah_radio == AR5K_RF5112) {
  881. /* Set gain_F settings according to current step */
  882. if (channel->hw_value != AR5K_MODE_11B) {
  883. ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[0],
  884. AR5K_RF_MIXGAIN_OVR, true);
  885. ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[1],
  886. AR5K_RF_PWD_138, true);
  887. ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[2],
  888. AR5K_RF_PWD_137, true);
  889. ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[3],
  890. AR5K_RF_PWD_136, true);
  891. ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[4],
  892. AR5K_RF_PWD_132, true);
  893. ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[5],
  894. AR5K_RF_PWD_131, true);
  895. ath5k_hw_rfb_op(ah, rf_regs, g_step->gos_param[6],
  896. AR5K_RF_PWD_130, true);
  897. /* We programmed gain_F parameters, switch back
  898. * to active state */
  899. ah->ah_gain.g_state = AR5K_RFGAIN_ACTIVE;
  900. }
  901. /* Bank 6/7 setup */
  902. ath5k_hw_rfb_op(ah, rf_regs, ee->ee_xpd[ee_mode],
  903. AR5K_RF_XPD_SEL, true);
  904. if (ah->ah_radio_5ghz_revision < AR5K_SREV_RAD_5112A) {
  905. /* Rev. 1 supports only one xpd */
  906. ath5k_hw_rfb_op(ah, rf_regs,
  907. ee->ee_x_gain[ee_mode],
  908. AR5K_RF_XPD_GAIN, true);
  909. } else {
  910. u8 *pdg_curve_to_idx = ee->ee_pdc_to_idx[ee_mode];
  911. if (ee->ee_pd_gains[ee_mode] > 1) {
  912. ath5k_hw_rfb_op(ah, rf_regs,
  913. pdg_curve_to_idx[0],
  914. AR5K_RF_PD_GAIN_LO, true);
  915. ath5k_hw_rfb_op(ah, rf_regs,
  916. pdg_curve_to_idx[1],
  917. AR5K_RF_PD_GAIN_HI, true);
  918. } else {
  919. ath5k_hw_rfb_op(ah, rf_regs,
  920. pdg_curve_to_idx[0],
  921. AR5K_RF_PD_GAIN_LO, true);
  922. ath5k_hw_rfb_op(ah, rf_regs,
  923. pdg_curve_to_idx[0],
  924. AR5K_RF_PD_GAIN_HI, true);
  925. }
  926. /* Lower synth voltage on Rev 2 */
  927. if (ah->ah_radio == AR5K_RF5112 &&
  928. (ah->ah_radio_5ghz_revision & AR5K_SREV_REV) > 0) {
  929. ath5k_hw_rfb_op(ah, rf_regs, 2,
  930. AR5K_RF_HIGH_VC_CP, true);
  931. ath5k_hw_rfb_op(ah, rf_regs, 2,
  932. AR5K_RF_MID_VC_CP, true);
  933. ath5k_hw_rfb_op(ah, rf_regs, 2,
  934. AR5K_RF_LOW_VC_CP, true);
  935. ath5k_hw_rfb_op(ah, rf_regs, 2,
  936. AR5K_RF_PUSH_UP, true);
  937. }
  938. /* Decrease power consumption on 5213+ BaseBand */
  939. if (ah->ah_phy_revision >= AR5K_SREV_PHY_5212A) {
  940. ath5k_hw_rfb_op(ah, rf_regs, 1,
  941. AR5K_RF_PAD2GND, true);
  942. ath5k_hw_rfb_op(ah, rf_regs, 1,
  943. AR5K_RF_XB2_LVL, true);
  944. ath5k_hw_rfb_op(ah, rf_regs, 1,
  945. AR5K_RF_XB5_LVL, true);
  946. ath5k_hw_rfb_op(ah, rf_regs, 1,
  947. AR5K_RF_PWD_167, true);
  948. ath5k_hw_rfb_op(ah, rf_regs, 1,
  949. AR5K_RF_PWD_166, true);
  950. }
  951. }
  952. ath5k_hw_rfb_op(ah, rf_regs, ee->ee_i_gain[ee_mode],
  953. AR5K_RF_GAIN_I, true);
  954. /* Tweak power detector for half/quarter rates */
  955. if (ah->ah_bwmode == AR5K_BWMODE_5MHZ ||
  956. ah->ah_bwmode == AR5K_BWMODE_10MHZ) {
  957. u8 pd_delay;
  958. pd_delay = (ah->ah_bwmode == AR5K_BWMODE_5MHZ) ?
  959. 0xf : 0x8;
  960. ath5k_hw_rfb_op(ah, rf_regs, pd_delay,
  961. AR5K_RF_PD_PERIOD_A, true);
  962. ath5k_hw_rfb_op(ah, rf_regs, 0xf,
  963. AR5K_RF_PD_DELAY_A, true);
  964. }
  965. }
  966. if (ah->ah_radio == AR5K_RF5413 &&
  967. channel->band == IEEE80211_BAND_2GHZ) {
  968. ath5k_hw_rfb_op(ah, rf_regs, 1, AR5K_RF_DERBY_CHAN_SEL_MODE,
  969. true);
  970. /* Set optimum value for early revisions (on pci-e chips) */
  971. if (ah->ah_mac_srev >= AR5K_SREV_AR5424 &&
  972. ah->ah_mac_srev < AR5K_SREV_AR5413)
  973. ath5k_hw_rfb_op(ah, rf_regs, ath5k_hw_bitswap(6, 3),
  974. AR5K_RF_PWD_ICLOBUF_2G, true);
  975. }
  976. /* Write RF banks on hw */
  977. for (i = 0; i < ah->ah_rf_banks_size; i++) {
  978. AR5K_REG_WAIT(i);
  979. ath5k_hw_reg_write(ah, rfb[i], ini_rfb[i].rfb_ctrl_register);
  980. }
  981. return 0;
  982. }
  983. /**************************\
  984. PHY/RF channel functions
  985. \**************************/
  986. /**
  987. * ath5k_hw_rf5110_chan2athchan() - Convert channel freq on RF5110
  988. * @channel: The &struct ieee80211_channel
  989. *
  990. * Map channel frequency to IEEE channel number and convert it
  991. * to an internal channel value used by the RF5110 chipset.
  992. */
  993. static u32
  994. ath5k_hw_rf5110_chan2athchan(struct ieee80211_channel *channel)
  995. {
  996. u32 athchan;
  997. athchan = (ath5k_hw_bitswap(
  998. (ieee80211_frequency_to_channel(
  999. channel->center_freq) - 24) / 2, 5)
  1000. << 1) | (1 << 6) | 0x1;
  1001. return athchan;
  1002. }
  1003. /**
  1004. * ath5k_hw_rf5110_channel() - Set channel frequency on RF5110
  1005. * @ah: The &struct ath5k_hw
  1006. * @channel: The &struct ieee80211_channel
  1007. */
  1008. static int
  1009. ath5k_hw_rf5110_channel(struct ath5k_hw *ah,
  1010. struct ieee80211_channel *channel)
  1011. {
  1012. u32 data;
  1013. /*
  1014. * Set the channel and wait
  1015. */
  1016. data = ath5k_hw_rf5110_chan2athchan(channel);
  1017. ath5k_hw_reg_write(ah, data, AR5K_RF_BUFFER);
  1018. ath5k_hw_reg_write(ah, 0, AR5K_RF_BUFFER_CONTROL_0);
  1019. usleep_range(1000, 1500);
  1020. return 0;
  1021. }
  1022. /**
  1023. * ath5k_hw_rf5111_chan2athchan() - Handle 2GHz channels on RF5111/2111
  1024. * @ieee: IEEE channel number
  1025. * @athchan: The &struct ath5k_athchan_2ghz
  1026. *
  1027. * In order to enable the RF2111 frequency converter on RF5111/2111 setups
  1028. * we need to add some offsets and extra flags to the data values we pass
  1029. * on to the PHY. So for every 2GHz channel this function gets called
  1030. * to do the conversion.
  1031. */
  1032. static int
  1033. ath5k_hw_rf5111_chan2athchan(unsigned int ieee,
  1034. struct ath5k_athchan_2ghz *athchan)
  1035. {
  1036. int channel;
  1037. /* Cast this value to catch negative channel numbers (>= -19) */
  1038. channel = (int)ieee;
  1039. /*
  1040. * Map 2GHz IEEE channel to 5GHz Atheros channel
  1041. */
  1042. if (channel <= 13) {
  1043. athchan->a2_athchan = 115 + channel;
  1044. athchan->a2_flags = 0x46;
  1045. } else if (channel == 14) {
  1046. athchan->a2_athchan = 124;
  1047. athchan->a2_flags = 0x44;
  1048. } else if (channel >= 15 && channel <= 26) {
  1049. athchan->a2_athchan = ((channel - 14) * 4) + 132;
  1050. athchan->a2_flags = 0x46;
  1051. } else
  1052. return -EINVAL;
  1053. return 0;
  1054. }
  1055. /**
  1056. * ath5k_hw_rf5111_channel() - Set channel frequency on RF5111/2111
  1057. * @ah: The &struct ath5k_hw
  1058. * @channel: The &struct ieee80211_channel
  1059. */
  1060. static int
  1061. ath5k_hw_rf5111_channel(struct ath5k_hw *ah,
  1062. struct ieee80211_channel *channel)
  1063. {
  1064. struct ath5k_athchan_2ghz ath5k_channel_2ghz;
  1065. unsigned int ath5k_channel =
  1066. ieee80211_frequency_to_channel(channel->center_freq);
  1067. u32 data0, data1, clock;
  1068. int ret;
  1069. /*
  1070. * Set the channel on the RF5111 radio
  1071. */
  1072. data0 = data1 = 0;
  1073. if (channel->band == IEEE80211_BAND_2GHZ) {
  1074. /* Map 2GHz channel to 5GHz Atheros channel ID */
  1075. ret = ath5k_hw_rf5111_chan2athchan(
  1076. ieee80211_frequency_to_channel(channel->center_freq),
  1077. &ath5k_channel_2ghz);
  1078. if (ret)
  1079. return ret;
  1080. ath5k_channel = ath5k_channel_2ghz.a2_athchan;
  1081. data0 = ((ath5k_hw_bitswap(ath5k_channel_2ghz.a2_flags, 8) & 0xff)
  1082. << 5) | (1 << 4);
  1083. }
  1084. if (ath5k_channel < 145 || !(ath5k_channel & 1)) {
  1085. clock = 1;
  1086. data1 = ((ath5k_hw_bitswap(ath5k_channel - 24, 8) & 0xff) << 2) |
  1087. (clock << 1) | (1 << 10) | 1;
  1088. } else {
  1089. clock = 0;
  1090. data1 = ((ath5k_hw_bitswap((ath5k_channel - 24) / 2, 8) & 0xff)
  1091. << 2) | (clock << 1) | (1 << 10) | 1;
  1092. }
  1093. ath5k_hw_reg_write(ah, (data1 & 0xff) | ((data0 & 0xff) << 8),
  1094. AR5K_RF_BUFFER);
  1095. ath5k_hw_reg_write(ah, ((data1 >> 8) & 0xff) | (data0 & 0xff00),
  1096. AR5K_RF_BUFFER_CONTROL_3);
  1097. return 0;
  1098. }
  1099. /**
  1100. * ath5k_hw_rf5112_channel() - Set channel frequency on 5112 and newer
  1101. * @ah: The &struct ath5k_hw
  1102. * @channel: The &struct ieee80211_channel
  1103. *
  1104. * On RF5112/2112 and newer we don't need to do any conversion.
  1105. * We pass the frequency value after a few modifications to the
  1106. * chip directly.
  1107. *
  1108. * NOTE: Make sure channel frequency given is within our range or else
  1109. * we might damage the chip ! Use ath5k_channel_ok before calling this one.
  1110. */
  1111. static int
  1112. ath5k_hw_rf5112_channel(struct ath5k_hw *ah,
  1113. struct ieee80211_channel *channel)
  1114. {
  1115. u32 data, data0, data1, data2;
  1116. u16 c;
  1117. data = data0 = data1 = data2 = 0;
  1118. c = channel->center_freq;
  1119. /* My guess based on code:
  1120. * 2GHz RF has 2 synth modes, one with a Local Oscillator
  1121. * at 2224Hz and one with a LO at 2192Hz. IF is 1520Hz
  1122. * (3040/2). data0 is used to set the PLL divider and data1
  1123. * selects synth mode. */
  1124. if (c < 4800) {
  1125. /* Channel 14 and all frequencies with 2Hz spacing
  1126. * below/above (non-standard channels) */
  1127. if (!((c - 2224) % 5)) {
  1128. /* Same as (c - 2224) / 5 */
  1129. data0 = ((2 * (c - 704)) - 3040) / 10;
  1130. data1 = 1;
  1131. /* Channel 1 and all frequencies with 5Hz spacing
  1132. * below/above (standard channels without channel 14) */
  1133. } else if (!((c - 2192) % 5)) {
  1134. /* Same as (c - 2192) / 5 */
  1135. data0 = ((2 * (c - 672)) - 3040) / 10;
  1136. data1 = 0;
  1137. } else
  1138. return -EINVAL;
  1139. data0 = ath5k_hw_bitswap((data0 << 2) & 0xff, 8);
  1140. /* This is more complex, we have a single synthesizer with
  1141. * 4 reference clock settings (?) based on frequency spacing
  1142. * and set using data2. LO is at 4800Hz and data0 is again used
  1143. * to set some divider.
  1144. *
  1145. * NOTE: There is an old atheros presentation at Stanford
  1146. * that mentions a method called dual direct conversion
  1147. * with 1GHz sliding IF for RF5110. Maybe that's what we
  1148. * have here, or an updated version. */
  1149. } else if ((c % 5) != 2 || c > 5435) {
  1150. if (!(c % 20) && c >= 5120) {
  1151. data0 = ath5k_hw_bitswap(((c - 4800) / 20 << 2), 8);
  1152. data2 = ath5k_hw_bitswap(3, 2);
  1153. } else if (!(c % 10)) {
  1154. data0 = ath5k_hw_bitswap(((c - 4800) / 10 << 1), 8);
  1155. data2 = ath5k_hw_bitswap(2, 2);
  1156. } else if (!(c % 5)) {
  1157. data0 = ath5k_hw_bitswap((c - 4800) / 5, 8);
  1158. data2 = ath5k_hw_bitswap(1, 2);
  1159. } else
  1160. return -EINVAL;
  1161. } else {
  1162. data0 = ath5k_hw_bitswap((10 * (c - 2 - 4800)) / 25 + 1, 8);
  1163. data2 = ath5k_hw_bitswap(0, 2);
  1164. }
  1165. data = (data0 << 4) | (data1 << 1) | (data2 << 2) | 0x1001;
  1166. ath5k_hw_reg_write(ah, data & 0xff, AR5K_RF_BUFFER);
  1167. ath5k_hw_reg_write(ah, (data >> 8) & 0x7f, AR5K_RF_BUFFER_CONTROL_5);
  1168. return 0;
  1169. }
  1170. /**
  1171. * ath5k_hw_rf2425_channel() - Set channel frequency on RF2425
  1172. * @ah: The &struct ath5k_hw
  1173. * @channel: The &struct ieee80211_channel
  1174. *
  1175. * AR2425/2417 have a different 2GHz RF so code changes
  1176. * a little bit from RF5112.
  1177. */
  1178. static int
  1179. ath5k_hw_rf2425_channel(struct ath5k_hw *ah,
  1180. struct ieee80211_channel *channel)
  1181. {
  1182. u32 data, data0, data2;
  1183. u16 c;
  1184. data = data0 = data2 = 0;
  1185. c = channel->center_freq;
  1186. if (c < 4800) {
  1187. data0 = ath5k_hw_bitswap((c - 2272), 8);
  1188. data2 = 0;
  1189. /* ? 5GHz ? */
  1190. } else if ((c % 5) != 2 || c > 5435) {
  1191. if (!(c % 20) && c < 5120)
  1192. data0 = ath5k_hw_bitswap(((c - 4800) / 20 << 2), 8);
  1193. else if (!(c % 10))
  1194. data0 = ath5k_hw_bitswap(((c - 4800) / 10 << 1), 8);
  1195. else if (!(c % 5))
  1196. data0 = ath5k_hw_bitswap((c - 4800) / 5, 8);
  1197. else
  1198. return -EINVAL;
  1199. data2 = ath5k_hw_bitswap(1, 2);
  1200. } else {
  1201. data0 = ath5k_hw_bitswap((10 * (c - 2 - 4800)) / 25 + 1, 8);
  1202. data2 = ath5k_hw_bitswap(0, 2);
  1203. }
  1204. data = (data0 << 4) | data2 << 2 | 0x1001;
  1205. ath5k_hw_reg_write(ah, data & 0xff, AR5K_RF_BUFFER);
  1206. ath5k_hw_reg_write(ah, (data >> 8) & 0x7f, AR5K_RF_BUFFER_CONTROL_5);
  1207. return 0;
  1208. }
  1209. /**
  1210. * ath5k_hw_channel() - Set a channel on the radio chip
  1211. * @ah: The &struct ath5k_hw
  1212. * @channel: The &struct ieee80211_channel
  1213. *
  1214. * This is the main function called to set a channel on the
  1215. * radio chip based on the radio chip version.
  1216. */
  1217. static int
  1218. ath5k_hw_channel(struct ath5k_hw *ah,
  1219. struct ieee80211_channel *channel)
  1220. {
  1221. int ret;
  1222. /*
  1223. * Check bounds supported by the PHY (we don't care about regulatory
  1224. * restrictions at this point).
  1225. */
  1226. if (!ath5k_channel_ok(ah, channel)) {
  1227. ATH5K_ERR(ah,
  1228. "channel frequency (%u MHz) out of supported "
  1229. "band range\n",
  1230. channel->center_freq);
  1231. return -EINVAL;
  1232. }
  1233. /*
  1234. * Set the channel and wait
  1235. */
  1236. switch (ah->ah_radio) {
  1237. case AR5K_RF5110:
  1238. ret = ath5k_hw_rf5110_channel(ah, channel);
  1239. break;
  1240. case AR5K_RF5111:
  1241. ret = ath5k_hw_rf5111_channel(ah, channel);
  1242. break;
  1243. case AR5K_RF2317:
  1244. case AR5K_RF2425:
  1245. ret = ath5k_hw_rf2425_channel(ah, channel);
  1246. break;
  1247. default:
  1248. ret = ath5k_hw_rf5112_channel(ah, channel);
  1249. break;
  1250. }
  1251. if (ret)
  1252. return ret;
  1253. /* Set JAPAN setting for channel 14 */
  1254. if (channel->center_freq == 2484) {
  1255. AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_CCKTXCTL,
  1256. AR5K_PHY_CCKTXCTL_JAPAN);
  1257. } else {
  1258. AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_CCKTXCTL,
  1259. AR5K_PHY_CCKTXCTL_WORLD);
  1260. }
  1261. ah->ah_current_channel = channel;
  1262. return 0;
  1263. }
  1264. /*****************\
  1265. PHY calibration
  1266. \*****************/
  1267. /**
  1268. * DOC: PHY Calibration routines
  1269. *
  1270. * Noise floor calibration: When we tell the hardware to
  1271. * perform a noise floor calibration by setting the
  1272. * AR5K_PHY_AGCCTL_NF bit on AR5K_PHY_AGCCTL, it will periodically
  1273. * sample-and-hold the minimum noise level seen at the antennas.
  1274. * This value is then stored in a ring buffer of recently measured
  1275. * noise floor values so we have a moving window of the last few
  1276. * samples. The median of the values in the history is then loaded
  1277. * into the hardware for its own use for RSSI and CCA measurements.
  1278. * This type of calibration doesn't interfere with traffic.
  1279. *
  1280. * AGC calibration: When we tell the hardware to perform
  1281. * an AGC (Automatic Gain Control) calibration by setting the
  1282. * AR5K_PHY_AGCCTL_CAL, hw disconnects the antennas and does
  1283. * a calibration on the DC offsets of ADCs. During this period
  1284. * rx/tx gets disabled so we have to deal with it on the driver
  1285. * part.
  1286. *
  1287. * I/Q calibration: When we tell the hardware to perform
  1288. * an I/Q calibration, it tries to correct I/Q imbalance and
  1289. * fix QAM constellation by sampling data from rxed frames.
  1290. * It doesn't interfere with traffic.
  1291. *
  1292. * For more infos on AGC and I/Q calibration check out patent doc
  1293. * #03/094463.
  1294. */
  1295. /**
  1296. * ath5k_hw_read_measured_noise_floor() - Read measured NF from hw
  1297. * @ah: The &struct ath5k_hw
  1298. */
  1299. static s32
  1300. ath5k_hw_read_measured_noise_floor(struct ath5k_hw *ah)
  1301. {
  1302. s32 val;
  1303. val = ath5k_hw_reg_read(ah, AR5K_PHY_NF);
  1304. return sign_extend32(AR5K_REG_MS(val, AR5K_PHY_NF_MINCCA_PWR), 8);
  1305. }
  1306. /**
  1307. * ath5k_hw_init_nfcal_hist() - Initialize NF calibration history buffer
  1308. * @ah: The &struct ath5k_hw
  1309. */
  1310. void
  1311. ath5k_hw_init_nfcal_hist(struct ath5k_hw *ah)
  1312. {
  1313. int i;
  1314. ah->ah_nfcal_hist.index = 0;
  1315. for (i = 0; i < ATH5K_NF_CAL_HIST_MAX; i++)
  1316. ah->ah_nfcal_hist.nfval[i] = AR5K_TUNE_CCA_MAX_GOOD_VALUE;
  1317. }
  1318. /**
  1319. * ath5k_hw_update_nfcal_hist() - Update NF calibration history buffer
  1320. * @ah: The &struct ath5k_hw
  1321. * @noise_floor: The NF we got from hw
  1322. */
  1323. static void ath5k_hw_update_nfcal_hist(struct ath5k_hw *ah, s16 noise_floor)
  1324. {
  1325. struct ath5k_nfcal_hist *hist = &ah->ah_nfcal_hist;
  1326. hist->index = (hist->index + 1) & (ATH5K_NF_CAL_HIST_MAX - 1);
  1327. hist->nfval[hist->index] = noise_floor;
  1328. }
  1329. /**
  1330. * ath5k_hw_get_median_noise_floor() - Get median NF from history buffer
  1331. * @ah: The &struct ath5k_hw
  1332. */
  1333. static s16
  1334. ath5k_hw_get_median_noise_floor(struct ath5k_hw *ah)
  1335. {
  1336. s16 sort[ATH5K_NF_CAL_HIST_MAX];
  1337. s16 tmp;
  1338. int i, j;
  1339. memcpy(sort, ah->ah_nfcal_hist.nfval, sizeof(sort));
  1340. for (i = 0; i < ATH5K_NF_CAL_HIST_MAX - 1; i++) {
  1341. for (j = 1; j < ATH5K_NF_CAL_HIST_MAX - i; j++) {
  1342. if (sort[j] > sort[j - 1]) {
  1343. tmp = sort[j];
  1344. sort[j] = sort[j - 1];
  1345. sort[j - 1] = tmp;
  1346. }
  1347. }
  1348. }
  1349. for (i = 0; i < ATH5K_NF_CAL_HIST_MAX; i++) {
  1350. ATH5K_DBG(ah, ATH5K_DEBUG_CALIBRATE,
  1351. "cal %d:%d\n", i, sort[i]);
  1352. }
  1353. return sort[(ATH5K_NF_CAL_HIST_MAX - 1) / 2];
  1354. }
  1355. /**
  1356. * ath5k_hw_update_noise_floor() - Update NF on hardware
  1357. * @ah: The &struct ath5k_hw
  1358. *
  1359. * This is the main function we call to perform a NF calibration,
  1360. * it reads NF from hardware, calculates the median and updates
  1361. * NF on hw.
  1362. */
  1363. void
  1364. ath5k_hw_update_noise_floor(struct ath5k_hw *ah)
  1365. {
  1366. struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
  1367. u32 val;
  1368. s16 nf, threshold;
  1369. u8 ee_mode;
  1370. /* keep last value if calibration hasn't completed */
  1371. if (ath5k_hw_reg_read(ah, AR5K_PHY_AGCCTL) & AR5K_PHY_AGCCTL_NF) {
  1372. ATH5K_DBG(ah, ATH5K_DEBUG_CALIBRATE,
  1373. "NF did not complete in calibration window\n");
  1374. return;
  1375. }
  1376. ah->ah_cal_mask |= AR5K_CALIBRATION_NF;
  1377. ee_mode = ath5k_eeprom_mode_from_channel(ah, ah->ah_current_channel);
  1378. /* completed NF calibration, test threshold */
  1379. nf = ath5k_hw_read_measured_noise_floor(ah);
  1380. threshold = ee->ee_noise_floor_thr[ee_mode];
  1381. if (nf > threshold) {
  1382. ATH5K_DBG(ah, ATH5K_DEBUG_CALIBRATE,
  1383. "noise floor failure detected; "
  1384. "read %d, threshold %d\n",
  1385. nf, threshold);
  1386. nf = AR5K_TUNE_CCA_MAX_GOOD_VALUE;
  1387. }
  1388. ath5k_hw_update_nfcal_hist(ah, nf);
  1389. nf = ath5k_hw_get_median_noise_floor(ah);
  1390. /* load noise floor (in .5 dBm) so the hardware will use it */
  1391. val = ath5k_hw_reg_read(ah, AR5K_PHY_NF) & ~AR5K_PHY_NF_M;
  1392. val |= (nf * 2) & AR5K_PHY_NF_M;
  1393. ath5k_hw_reg_write(ah, val, AR5K_PHY_NF);
  1394. AR5K_REG_MASKED_BITS(ah, AR5K_PHY_AGCCTL, AR5K_PHY_AGCCTL_NF,
  1395. ~(AR5K_PHY_AGCCTL_NF_EN | AR5K_PHY_AGCCTL_NF_NOUPDATE));
  1396. ath5k_hw_register_timeout(ah, AR5K_PHY_AGCCTL, AR5K_PHY_AGCCTL_NF,
  1397. 0, false);
  1398. /*
  1399. * Load a high max CCA Power value (-50 dBm in .5 dBm units)
  1400. * so that we're not capped by the median we just loaded.
  1401. * This will be used as the initial value for the next noise
  1402. * floor calibration.
  1403. */
  1404. val = (val & ~AR5K_PHY_NF_M) | ((-50 * 2) & AR5K_PHY_NF_M);
  1405. ath5k_hw_reg_write(ah, val, AR5K_PHY_NF);
  1406. AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGCCTL,
  1407. AR5K_PHY_AGCCTL_NF_EN |
  1408. AR5K_PHY_AGCCTL_NF_NOUPDATE |
  1409. AR5K_PHY_AGCCTL_NF);
  1410. ah->ah_noise_floor = nf;
  1411. ah->ah_cal_mask &= ~AR5K_CALIBRATION_NF;
  1412. ATH5K_DBG(ah, ATH5K_DEBUG_CALIBRATE,
  1413. "noise floor calibrated: %d\n", nf);
  1414. }
  1415. /**
  1416. * ath5k_hw_rf5110_calibrate() - Perform a PHY calibration on RF5110
  1417. * @ah: The &struct ath5k_hw
  1418. * @channel: The &struct ieee80211_channel
  1419. *
  1420. * Do a complete PHY calibration (AGC + NF + I/Q) on RF5110
  1421. */
  1422. static int
  1423. ath5k_hw_rf5110_calibrate(struct ath5k_hw *ah,
  1424. struct ieee80211_channel *channel)
  1425. {
  1426. u32 phy_sig, phy_agc, phy_sat, beacon;
  1427. int ret;
  1428. if (!(ah->ah_cal_mask & AR5K_CALIBRATION_FULL))
  1429. return 0;
  1430. /*
  1431. * Disable beacons and RX/TX queues, wait
  1432. */
  1433. AR5K_REG_ENABLE_BITS(ah, AR5K_DIAG_SW_5210,
  1434. AR5K_DIAG_SW_DIS_TX_5210 | AR5K_DIAG_SW_DIS_RX_5210);
  1435. beacon = ath5k_hw_reg_read(ah, AR5K_BEACON_5210);
  1436. ath5k_hw_reg_write(ah, beacon & ~AR5K_BEACON_ENABLE, AR5K_BEACON_5210);
  1437. usleep_range(2000, 2500);
  1438. /*
  1439. * Set the channel (with AGC turned off)
  1440. */
  1441. AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGC, AR5K_PHY_AGC_DISABLE);
  1442. udelay(10);
  1443. ret = ath5k_hw_channel(ah, channel);
  1444. /*
  1445. * Activate PHY and wait
  1446. */
  1447. ath5k_hw_reg_write(ah, AR5K_PHY_ACT_ENABLE, AR5K_PHY_ACT);
  1448. usleep_range(1000, 1500);
  1449. AR5K_REG_DISABLE_BITS(ah, AR5K_PHY_AGC, AR5K_PHY_AGC_DISABLE);
  1450. if (ret)
  1451. return ret;
  1452. /*
  1453. * Calibrate the radio chip
  1454. */
  1455. /* Remember normal state */
  1456. phy_sig = ath5k_hw_reg_read(ah, AR5K_PHY_SIG);
  1457. phy_agc = ath5k_hw_reg_read(ah, AR5K_PHY_AGCCOARSE);
  1458. phy_sat = ath5k_hw_reg_read(ah, AR5K_PHY_ADCSAT);
  1459. /* Update radio registers */
  1460. ath5k_hw_reg_write(ah, (phy_sig & ~(AR5K_PHY_SIG_FIRPWR)) |
  1461. AR5K_REG_SM(-1, AR5K_PHY_SIG_FIRPWR), AR5K_PHY_SIG);
  1462. ath5k_hw_reg_write(ah, (phy_agc & ~(AR5K_PHY_AGCCOARSE_HI |
  1463. AR5K_PHY_AGCCOARSE_LO)) |
  1464. AR5K_REG_SM(-1, AR5K_PHY_AGCCOARSE_HI) |
  1465. AR5K_REG_SM(-127, AR5K_PHY_AGCCOARSE_LO), AR5K_PHY_AGCCOARSE);
  1466. ath5k_hw_reg_write(ah, (phy_sat & ~(AR5K_PHY_ADCSAT_ICNT |
  1467. AR5K_PHY_ADCSAT_THR)) |
  1468. AR5K_REG_SM(2, AR5K_PHY_ADCSAT_ICNT) |
  1469. AR5K_REG_SM(12, AR5K_PHY_ADCSAT_THR), AR5K_PHY_ADCSAT);
  1470. udelay(20);
  1471. AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGC, AR5K_PHY_AGC_DISABLE);
  1472. udelay(10);
  1473. ath5k_hw_reg_write(ah, AR5K_PHY_RFSTG_DISABLE, AR5K_PHY_RFSTG);
  1474. AR5K_REG_DISABLE_BITS(ah, AR5K_PHY_AGC, AR5K_PHY_AGC_DISABLE);
  1475. usleep_range(1000, 1500);
  1476. /*
  1477. * Enable calibration and wait until completion
  1478. */
  1479. AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGCCTL, AR5K_PHY_AGCCTL_CAL);
  1480. ret = ath5k_hw_register_timeout(ah, AR5K_PHY_AGCCTL,
  1481. AR5K_PHY_AGCCTL_CAL, 0, false);
  1482. /* Reset to normal state */
  1483. ath5k_hw_reg_write(ah, phy_sig, AR5K_PHY_SIG);
  1484. ath5k_hw_reg_write(ah, phy_agc, AR5K_PHY_AGCCOARSE);
  1485. ath5k_hw_reg_write(ah, phy_sat, AR5K_PHY_ADCSAT);
  1486. if (ret) {
  1487. ATH5K_ERR(ah, "calibration timeout (%uMHz)\n",
  1488. channel->center_freq);
  1489. return ret;
  1490. }
  1491. /*
  1492. * Re-enable RX/TX and beacons
  1493. */
  1494. AR5K_REG_DISABLE_BITS(ah, AR5K_DIAG_SW_5210,
  1495. AR5K_DIAG_SW_DIS_TX_5210 | AR5K_DIAG_SW_DIS_RX_5210);
  1496. ath5k_hw_reg_write(ah, beacon, AR5K_BEACON_5210);
  1497. return 0;
  1498. }
  1499. /**
  1500. * ath5k_hw_rf511x_iq_calibrate() - Perform I/Q calibration on RF5111 and newer
  1501. * @ah: The &struct ath5k_hw
  1502. */
  1503. static int
  1504. ath5k_hw_rf511x_iq_calibrate(struct ath5k_hw *ah)
  1505. {
  1506. u32 i_pwr, q_pwr;
  1507. s32 iq_corr, i_coff, i_coffd, q_coff, q_coffd;
  1508. int i;
  1509. /* Skip if I/Q calibration is not needed or if it's still running */
  1510. if (!ah->ah_iq_cal_needed)
  1511. return -EINVAL;
  1512. else if (ath5k_hw_reg_read(ah, AR5K_PHY_IQ) & AR5K_PHY_IQ_RUN) {
  1513. ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_CALIBRATE,
  1514. "I/Q calibration still running");
  1515. return -EBUSY;
  1516. }
  1517. /* Calibration has finished, get the results and re-run */
  1518. /* Work around for empty results which can apparently happen on 5212:
  1519. * Read registers up to 10 times until we get both i_pr and q_pwr */
  1520. for (i = 0; i <= 10; i++) {
  1521. iq_corr = ath5k_hw_reg_read(ah, AR5K_PHY_IQRES_CAL_CORR);
  1522. i_pwr = ath5k_hw_reg_read(ah, AR5K_PHY_IQRES_CAL_PWR_I);
  1523. q_pwr = ath5k_hw_reg_read(ah, AR5K_PHY_IQRES_CAL_PWR_Q);
  1524. ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_CALIBRATE,
  1525. "iq_corr:%x i_pwr:%x q_pwr:%x", iq_corr, i_pwr, q_pwr);
  1526. if (i_pwr && q_pwr)
  1527. break;
  1528. }
  1529. i_coffd = ((i_pwr >> 1) + (q_pwr >> 1)) >> 7;
  1530. if (ah->ah_version == AR5K_AR5211)
  1531. q_coffd = q_pwr >> 6;
  1532. else
  1533. q_coffd = q_pwr >> 7;
  1534. /* In case i_coffd became zero, cancel calibration
  1535. * not only it's too small, it'll also result a divide
  1536. * by zero later on. */
  1537. if (i_coffd == 0 || q_coffd < 2)
  1538. return -ECANCELED;
  1539. /* Protect against loss of sign bits */
  1540. i_coff = (-iq_corr) / i_coffd;
  1541. i_coff = clamp(i_coff, -32, 31); /* signed 6 bit */
  1542. if (ah->ah_version == AR5K_AR5211)
  1543. q_coff = (i_pwr / q_coffd) - 64;
  1544. else
  1545. q_coff = (i_pwr / q_coffd) - 128;
  1546. q_coff = clamp(q_coff, -16, 15); /* signed 5 bit */
  1547. ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_CALIBRATE,
  1548. "new I:%d Q:%d (i_coffd:%x q_coffd:%x)",
  1549. i_coff, q_coff, i_coffd, q_coffd);
  1550. /* Commit new I/Q values (set enable bit last to match HAL sources) */
  1551. AR5K_REG_WRITE_BITS(ah, AR5K_PHY_IQ, AR5K_PHY_IQ_CORR_Q_I_COFF, i_coff);
  1552. AR5K_REG_WRITE_BITS(ah, AR5K_PHY_IQ, AR5K_PHY_IQ_CORR_Q_Q_COFF, q_coff);
  1553. AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_IQ, AR5K_PHY_IQ_CORR_ENABLE);
  1554. /* Re-enable calibration -if we don't we'll commit
  1555. * the same values again and again */
  1556. AR5K_REG_WRITE_BITS(ah, AR5K_PHY_IQ,
  1557. AR5K_PHY_IQ_CAL_NUM_LOG_MAX, 15);
  1558. AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_IQ, AR5K_PHY_IQ_RUN);
  1559. return 0;
  1560. }
  1561. /**
  1562. * ath5k_hw_phy_calibrate() - Perform a PHY calibration
  1563. * @ah: The &struct ath5k_hw
  1564. * @channel: The &struct ieee80211_channel
  1565. *
  1566. * The main function we call from above to perform
  1567. * a short or full PHY calibration based on RF chip
  1568. * and current channel
  1569. */
  1570. int
  1571. ath5k_hw_phy_calibrate(struct ath5k_hw *ah,
  1572. struct ieee80211_channel *channel)
  1573. {
  1574. int ret;
  1575. if (ah->ah_radio == AR5K_RF5110)
  1576. return ath5k_hw_rf5110_calibrate(ah, channel);
  1577. ret = ath5k_hw_rf511x_iq_calibrate(ah);
  1578. if (ret) {
  1579. ATH5K_DBG_UNLIMIT(ah, ATH5K_DEBUG_CALIBRATE,
  1580. "No I/Q correction performed (%uMHz)\n",
  1581. channel->center_freq);
  1582. /* Happens all the time if there is not much
  1583. * traffic, consider it normal behaviour. */
  1584. ret = 0;
  1585. }
  1586. /* On full calibration request a PAPD probe for
  1587. * gainf calibration if needed */
  1588. if ((ah->ah_cal_mask & AR5K_CALIBRATION_FULL) &&
  1589. (ah->ah_radio == AR5K_RF5111 ||
  1590. ah->ah_radio == AR5K_RF5112) &&
  1591. channel->hw_value != AR5K_MODE_11B)
  1592. ath5k_hw_request_rfgain_probe(ah);
  1593. /* Update noise floor */
  1594. if (!(ah->ah_cal_mask & AR5K_CALIBRATION_NF))
  1595. ath5k_hw_update_noise_floor(ah);
  1596. return ret;
  1597. }
  1598. /***************************\
  1599. * Spur mitigation functions *
  1600. \***************************/
  1601. /**
  1602. * ath5k_hw_set_spur_mitigation_filter() - Configure SPUR filter
  1603. * @ah: The &struct ath5k_hw
  1604. * @channel: The &struct ieee80211_channel
  1605. *
  1606. * This function gets called during PHY initialization to
  1607. * configure the spur filter for the given channel. Spur is noise
  1608. * generated due to "reflection" effects, for more information on this
  1609. * method check out patent US7643810
  1610. */
  1611. static void
  1612. ath5k_hw_set_spur_mitigation_filter(struct ath5k_hw *ah,
  1613. struct ieee80211_channel *channel)
  1614. {
  1615. struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
  1616. u32 mag_mask[4] = {0, 0, 0, 0};
  1617. u32 pilot_mask[2] = {0, 0};
  1618. /* Note: fbin values are scaled up by 2 */
  1619. u16 spur_chan_fbin, chan_fbin, symbol_width, spur_detection_window;
  1620. s32 spur_delta_phase, spur_freq_sigma_delta;
  1621. s32 spur_offset, num_symbols_x16;
  1622. u8 num_symbol_offsets, i, freq_band;
  1623. /* Convert current frequency to fbin value (the same way channels
  1624. * are stored on EEPROM, check out ath5k_eeprom_bin2freq) and scale
  1625. * up by 2 so we can compare it later */
  1626. if (channel->band == IEEE80211_BAND_2GHZ) {
  1627. chan_fbin = (channel->center_freq - 2300) * 10;
  1628. freq_band = AR5K_EEPROM_BAND_2GHZ;
  1629. } else {
  1630. chan_fbin = (channel->center_freq - 4900) * 10;
  1631. freq_band = AR5K_EEPROM_BAND_5GHZ;
  1632. }
  1633. /* Check if any spur_chan_fbin from EEPROM is
  1634. * within our current channel's spur detection range */
  1635. spur_chan_fbin = AR5K_EEPROM_NO_SPUR;
  1636. spur_detection_window = AR5K_SPUR_CHAN_WIDTH;
  1637. /* XXX: Half/Quarter channels ?*/
  1638. if (ah->ah_bwmode == AR5K_BWMODE_40MHZ)
  1639. spur_detection_window *= 2;
  1640. for (i = 0; i < AR5K_EEPROM_N_SPUR_CHANS; i++) {
  1641. spur_chan_fbin = ee->ee_spur_chans[i][freq_band];
  1642. /* Note: mask cleans AR5K_EEPROM_NO_SPUR flag
  1643. * so it's zero if we got nothing from EEPROM */
  1644. if (spur_chan_fbin == AR5K_EEPROM_NO_SPUR) {
  1645. spur_chan_fbin &= AR5K_EEPROM_SPUR_CHAN_MASK;
  1646. break;
  1647. }
  1648. if ((chan_fbin - spur_detection_window <=
  1649. (spur_chan_fbin & AR5K_EEPROM_SPUR_CHAN_MASK)) &&
  1650. (chan_fbin + spur_detection_window >=
  1651. (spur_chan_fbin & AR5K_EEPROM_SPUR_CHAN_MASK))) {
  1652. spur_chan_fbin &= AR5K_EEPROM_SPUR_CHAN_MASK;
  1653. break;
  1654. }
  1655. }
  1656. /* We need to enable spur filter for this channel */
  1657. if (spur_chan_fbin) {
  1658. spur_offset = spur_chan_fbin - chan_fbin;
  1659. /*
  1660. * Calculate deltas:
  1661. * spur_freq_sigma_delta -> spur_offset / sample_freq << 21
  1662. * spur_delta_phase -> spur_offset / chip_freq << 11
  1663. * Note: Both values have 100Hz resolution
  1664. */
  1665. switch (ah->ah_bwmode) {
  1666. case AR5K_BWMODE_40MHZ:
  1667. /* Both sample_freq and chip_freq are 80MHz */
  1668. spur_delta_phase = (spur_offset << 16) / 25;
  1669. spur_freq_sigma_delta = (spur_delta_phase >> 10);
  1670. symbol_width = AR5K_SPUR_SYMBOL_WIDTH_BASE_100Hz * 2;
  1671. break;
  1672. case AR5K_BWMODE_10MHZ:
  1673. /* Both sample_freq and chip_freq are 20MHz (?) */
  1674. spur_delta_phase = (spur_offset << 18) / 25;
  1675. spur_freq_sigma_delta = (spur_delta_phase >> 10);
  1676. symbol_width = AR5K_SPUR_SYMBOL_WIDTH_BASE_100Hz / 2;
  1677. break;
  1678. case AR5K_BWMODE_5MHZ:
  1679. /* Both sample_freq and chip_freq are 10MHz (?) */
  1680. spur_delta_phase = (spur_offset << 19) / 25;
  1681. spur_freq_sigma_delta = (spur_delta_phase >> 10);
  1682. symbol_width = AR5K_SPUR_SYMBOL_WIDTH_BASE_100Hz / 4;
  1683. break;
  1684. default:
  1685. if (channel->band == IEEE80211_BAND_5GHZ) {
  1686. /* Both sample_freq and chip_freq are 40MHz */
  1687. spur_delta_phase = (spur_offset << 17) / 25;
  1688. spur_freq_sigma_delta =
  1689. (spur_delta_phase >> 10);
  1690. symbol_width =
  1691. AR5K_SPUR_SYMBOL_WIDTH_BASE_100Hz;
  1692. } else {
  1693. /* sample_freq -> 40MHz chip_freq -> 44MHz
  1694. * (for b compatibility) */
  1695. spur_delta_phase = (spur_offset << 17) / 25;
  1696. spur_freq_sigma_delta =
  1697. (spur_offset << 8) / 55;
  1698. symbol_width =
  1699. AR5K_SPUR_SYMBOL_WIDTH_BASE_100Hz;
  1700. }
  1701. break;
  1702. }
  1703. /* Calculate pilot and magnitude masks */
  1704. /* Scale up spur_offset by 1000 to switch to 100HZ resolution
  1705. * and divide by symbol_width to find how many symbols we have
  1706. * Note: number of symbols is scaled up by 16 */
  1707. num_symbols_x16 = ((spur_offset * 1000) << 4) / symbol_width;
  1708. /* Spur is on a symbol if num_symbols_x16 % 16 is zero */
  1709. if (!(num_symbols_x16 & 0xF))
  1710. /* _X_ */
  1711. num_symbol_offsets = 3;
  1712. else
  1713. /* _xx_ */
  1714. num_symbol_offsets = 4;
  1715. for (i = 0; i < num_symbol_offsets; i++) {
  1716. /* Calculate pilot mask */
  1717. s32 curr_sym_off =
  1718. (num_symbols_x16 / 16) + i + 25;
  1719. /* Pilot magnitude mask seems to be a way to
  1720. * declare the boundaries for our detection
  1721. * window or something, it's 2 for the middle
  1722. * value(s) where the symbol is expected to be
  1723. * and 1 on the boundary values */
  1724. u8 plt_mag_map =
  1725. (i == 0 || i == (num_symbol_offsets - 1))
  1726. ? 1 : 2;
  1727. if (curr_sym_off >= 0 && curr_sym_off <= 32) {
  1728. if (curr_sym_off <= 25)
  1729. pilot_mask[0] |= 1 << curr_sym_off;
  1730. else if (curr_sym_off >= 27)
  1731. pilot_mask[0] |= 1 << (curr_sym_off - 1);
  1732. } else if (curr_sym_off >= 33 && curr_sym_off <= 52)
  1733. pilot_mask[1] |= 1 << (curr_sym_off - 33);
  1734. /* Calculate magnitude mask (for viterbi decoder) */
  1735. if (curr_sym_off >= -1 && curr_sym_off <= 14)
  1736. mag_mask[0] |=
  1737. plt_mag_map << (curr_sym_off + 1) * 2;
  1738. else if (curr_sym_off >= 15 && curr_sym_off <= 30)
  1739. mag_mask[1] |=
  1740. plt_mag_map << (curr_sym_off - 15) * 2;
  1741. else if (curr_sym_off >= 31 && curr_sym_off <= 46)
  1742. mag_mask[2] |=
  1743. plt_mag_map << (curr_sym_off - 31) * 2;
  1744. else if (curr_sym_off >= 47 && curr_sym_off <= 53)
  1745. mag_mask[3] |=
  1746. plt_mag_map << (curr_sym_off - 47) * 2;
  1747. }
  1748. /* Write settings on hw to enable spur filter */
  1749. AR5K_REG_WRITE_BITS(ah, AR5K_PHY_BIN_MASK_CTL,
  1750. AR5K_PHY_BIN_MASK_CTL_RATE, 0xff);
  1751. /* XXX: Self correlator also ? */
  1752. AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_IQ,
  1753. AR5K_PHY_IQ_PILOT_MASK_EN |
  1754. AR5K_PHY_IQ_CHAN_MASK_EN |
  1755. AR5K_PHY_IQ_SPUR_FILT_EN);
  1756. /* Set delta phase and freq sigma delta */
  1757. ath5k_hw_reg_write(ah,
  1758. AR5K_REG_SM(spur_delta_phase,
  1759. AR5K_PHY_TIMING_11_SPUR_DELTA_PHASE) |
  1760. AR5K_REG_SM(spur_freq_sigma_delta,
  1761. AR5K_PHY_TIMING_11_SPUR_FREQ_SD) |
  1762. AR5K_PHY_TIMING_11_USE_SPUR_IN_AGC,
  1763. AR5K_PHY_TIMING_11);
  1764. /* Write pilot masks */
  1765. ath5k_hw_reg_write(ah, pilot_mask[0], AR5K_PHY_TIMING_7);
  1766. AR5K_REG_WRITE_BITS(ah, AR5K_PHY_TIMING_8,
  1767. AR5K_PHY_TIMING_8_PILOT_MASK_2,
  1768. pilot_mask[1]);
  1769. ath5k_hw_reg_write(ah, pilot_mask[0], AR5K_PHY_TIMING_9);
  1770. AR5K_REG_WRITE_BITS(ah, AR5K_PHY_TIMING_10,
  1771. AR5K_PHY_TIMING_10_PILOT_MASK_2,
  1772. pilot_mask[1]);
  1773. /* Write magnitude masks */
  1774. ath5k_hw_reg_write(ah, mag_mask[0], AR5K_PHY_BIN_MASK_1);
  1775. ath5k_hw_reg_write(ah, mag_mask[1], AR5K_PHY_BIN_MASK_2);
  1776. ath5k_hw_reg_write(ah, mag_mask[2], AR5K_PHY_BIN_MASK_3);
  1777. AR5K_REG_WRITE_BITS(ah, AR5K_PHY_BIN_MASK_CTL,
  1778. AR5K_PHY_BIN_MASK_CTL_MASK_4,
  1779. mag_mask[3]);
  1780. ath5k_hw_reg_write(ah, mag_mask[0], AR5K_PHY_BIN_MASK2_1);
  1781. ath5k_hw_reg_write(ah, mag_mask[1], AR5K_PHY_BIN_MASK2_2);
  1782. ath5k_hw_reg_write(ah, mag_mask[2], AR5K_PHY_BIN_MASK2_3);
  1783. AR5K_REG_WRITE_BITS(ah, AR5K_PHY_BIN_MASK2_4,
  1784. AR5K_PHY_BIN_MASK2_4_MASK_4,
  1785. mag_mask[3]);
  1786. } else if (ath5k_hw_reg_read(ah, AR5K_PHY_IQ) &
  1787. AR5K_PHY_IQ_SPUR_FILT_EN) {
  1788. /* Clean up spur mitigation settings and disable filter */
  1789. AR5K_REG_WRITE_BITS(ah, AR5K_PHY_BIN_MASK_CTL,
  1790. AR5K_PHY_BIN_MASK_CTL_RATE, 0);
  1791. AR5K_REG_DISABLE_BITS(ah, AR5K_PHY_IQ,
  1792. AR5K_PHY_IQ_PILOT_MASK_EN |
  1793. AR5K_PHY_IQ_CHAN_MASK_EN |
  1794. AR5K_PHY_IQ_SPUR_FILT_EN);
  1795. ath5k_hw_reg_write(ah, 0, AR5K_PHY_TIMING_11);
  1796. /* Clear pilot masks */
  1797. ath5k_hw_reg_write(ah, 0, AR5K_PHY_TIMING_7);
  1798. AR5K_REG_WRITE_BITS(ah, AR5K_PHY_TIMING_8,
  1799. AR5K_PHY_TIMING_8_PILOT_MASK_2,
  1800. 0);
  1801. ath5k_hw_reg_write(ah, 0, AR5K_PHY_TIMING_9);
  1802. AR5K_REG_WRITE_BITS(ah, AR5K_PHY_TIMING_10,
  1803. AR5K_PHY_TIMING_10_PILOT_MASK_2,
  1804. 0);
  1805. /* Clear magnitude masks */
  1806. ath5k_hw_reg_write(ah, 0, AR5K_PHY_BIN_MASK_1);
  1807. ath5k_hw_reg_write(ah, 0, AR5K_PHY_BIN_MASK_2);
  1808. ath5k_hw_reg_write(ah, 0, AR5K_PHY_BIN_MASK_3);
  1809. AR5K_REG_WRITE_BITS(ah, AR5K_PHY_BIN_MASK_CTL,
  1810. AR5K_PHY_BIN_MASK_CTL_MASK_4,
  1811. 0);
  1812. ath5k_hw_reg_write(ah, 0, AR5K_PHY_BIN_MASK2_1);
  1813. ath5k_hw_reg_write(ah, 0, AR5K_PHY_BIN_MASK2_2);
  1814. ath5k_hw_reg_write(ah, 0, AR5K_PHY_BIN_MASK2_3);
  1815. AR5K_REG_WRITE_BITS(ah, AR5K_PHY_BIN_MASK2_4,
  1816. AR5K_PHY_BIN_MASK2_4_MASK_4,
  1817. 0);
  1818. }
  1819. }
  1820. /*****************\
  1821. * Antenna control *
  1822. \*****************/
  1823. /**
  1824. * DOC: Antenna control
  1825. *
  1826. * Hw supports up to 14 antennas ! I haven't found any card that implements
  1827. * that. The maximum number of antennas I've seen is up to 4 (2 for 2GHz and 2
  1828. * for 5GHz). Antenna 1 (MAIN) should be omnidirectional, 2 (AUX)
  1829. * omnidirectional or sectorial and antennas 3-14 sectorial (or directional).
  1830. *
  1831. * We can have a single antenna for RX and multiple antennas for TX.
  1832. * RX antenna is our "default" antenna (usually antenna 1) set on
  1833. * DEFAULT_ANTENNA register and TX antenna is set on each TX control descriptor
  1834. * (0 for automatic selection, 1 - 14 antenna number).
  1835. *
  1836. * We can let hw do all the work doing fast antenna diversity for both
  1837. * tx and rx or we can do things manually. Here are the options we have
  1838. * (all are bits of STA_ID1 register):
  1839. *
  1840. * AR5K_STA_ID1_DEFAULT_ANTENNA -> When 0 is set as the TX antenna on TX
  1841. * control descriptor, use the default antenna to transmit or else use the last
  1842. * antenna on which we received an ACK.
  1843. *
  1844. * AR5K_STA_ID1_DESC_ANTENNA -> Update default antenna after each TX frame to
  1845. * the antenna on which we got the ACK for that frame.
  1846. *
  1847. * AR5K_STA_ID1_RTS_DEF_ANTENNA -> Use default antenna for RTS or else use the
  1848. * one on the TX descriptor.
  1849. *
  1850. * AR5K_STA_ID1_SELFGEN_DEF_ANT -> Use default antenna for self generated frames
  1851. * (ACKs etc), or else use current antenna (the one we just used for TX).
  1852. *
  1853. * Using the above we support the following scenarios:
  1854. *
  1855. * AR5K_ANTMODE_DEFAULT -> Hw handles antenna diversity etc automatically
  1856. *
  1857. * AR5K_ANTMODE_FIXED_A -> Only antenna A (MAIN) is present
  1858. *
  1859. * AR5K_ANTMODE_FIXED_B -> Only antenna B (AUX) is present
  1860. *
  1861. * AR5K_ANTMODE_SINGLE_AP -> Sta locked on a single ap
  1862. *
  1863. * AR5K_ANTMODE_SECTOR_AP -> AP with tx antenna set on tx desc
  1864. *
  1865. * AR5K_ANTMODE_SECTOR_STA -> STA with tx antenna set on tx desc
  1866. *
  1867. * AR5K_ANTMODE_DEBUG Debug mode -A -> Rx, B-> Tx-
  1868. *
  1869. * Also note that when setting antenna to F on tx descriptor card inverts
  1870. * current tx antenna.
  1871. */
  1872. /**
  1873. * ath5k_hw_set_def_antenna() - Set default rx antenna on AR5211/5212 and newer
  1874. * @ah: The &struct ath5k_hw
  1875. * @ant: Antenna number
  1876. */
  1877. static void
  1878. ath5k_hw_set_def_antenna(struct ath5k_hw *ah, u8 ant)
  1879. {
  1880. if (ah->ah_version != AR5K_AR5210)
  1881. ath5k_hw_reg_write(ah, ant & 0x7, AR5K_DEFAULT_ANTENNA);
  1882. }
  1883. /**
  1884. * ath5k_hw_set_fast_div() - Enable/disable fast rx antenna diversity
  1885. * @ah: The &struct ath5k_hw
  1886. * @ee_mode: One of enum ath5k_driver_mode
  1887. * @enable: True to enable, false to disable
  1888. */
  1889. static void
  1890. ath5k_hw_set_fast_div(struct ath5k_hw *ah, u8 ee_mode, bool enable)
  1891. {
  1892. switch (ee_mode) {
  1893. case AR5K_EEPROM_MODE_11G:
  1894. /* XXX: This is set to
  1895. * disabled on initvals !!! */
  1896. case AR5K_EEPROM_MODE_11A:
  1897. if (enable)
  1898. AR5K_REG_DISABLE_BITS(ah, AR5K_PHY_AGCCTL,
  1899. AR5K_PHY_AGCCTL_OFDM_DIV_DIS);
  1900. else
  1901. AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGCCTL,
  1902. AR5K_PHY_AGCCTL_OFDM_DIV_DIS);
  1903. break;
  1904. case AR5K_EEPROM_MODE_11B:
  1905. AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGCCTL,
  1906. AR5K_PHY_AGCCTL_OFDM_DIV_DIS);
  1907. break;
  1908. default:
  1909. return;
  1910. }
  1911. if (enable) {
  1912. AR5K_REG_WRITE_BITS(ah, AR5K_PHY_RESTART,
  1913. AR5K_PHY_RESTART_DIV_GC, 4);
  1914. AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_FAST_ANT_DIV,
  1915. AR5K_PHY_FAST_ANT_DIV_EN);
  1916. } else {
  1917. AR5K_REG_WRITE_BITS(ah, AR5K_PHY_RESTART,
  1918. AR5K_PHY_RESTART_DIV_GC, 0);
  1919. AR5K_REG_DISABLE_BITS(ah, AR5K_PHY_FAST_ANT_DIV,
  1920. AR5K_PHY_FAST_ANT_DIV_EN);
  1921. }
  1922. }
  1923. /**
  1924. * ath5k_hw_set_antenna_switch() - Set up antenna switch table
  1925. * @ah: The &struct ath5k_hw
  1926. * @ee_mode: One of enum ath5k_driver_mode
  1927. *
  1928. * Switch table comes from EEPROM and includes information on controlling
  1929. * the 2 antenna RX attenuators
  1930. */
  1931. void
  1932. ath5k_hw_set_antenna_switch(struct ath5k_hw *ah, u8 ee_mode)
  1933. {
  1934. u8 ant0, ant1;
  1935. /*
  1936. * In case a fixed antenna was set as default
  1937. * use the same switch table twice.
  1938. */
  1939. if (ah->ah_ant_mode == AR5K_ANTMODE_FIXED_A)
  1940. ant0 = ant1 = AR5K_ANT_SWTABLE_A;
  1941. else if (ah->ah_ant_mode == AR5K_ANTMODE_FIXED_B)
  1942. ant0 = ant1 = AR5K_ANT_SWTABLE_B;
  1943. else {
  1944. ant0 = AR5K_ANT_SWTABLE_A;
  1945. ant1 = AR5K_ANT_SWTABLE_B;
  1946. }
  1947. /* Set antenna idle switch table */
  1948. AR5K_REG_WRITE_BITS(ah, AR5K_PHY_ANT_CTL,
  1949. AR5K_PHY_ANT_CTL_SWTABLE_IDLE,
  1950. (ah->ah_ant_ctl[ee_mode][AR5K_ANT_CTL] |
  1951. AR5K_PHY_ANT_CTL_TXRX_EN));
  1952. /* Set antenna switch tables */
  1953. ath5k_hw_reg_write(ah, ah->ah_ant_ctl[ee_mode][ant0],
  1954. AR5K_PHY_ANT_SWITCH_TABLE_0);
  1955. ath5k_hw_reg_write(ah, ah->ah_ant_ctl[ee_mode][ant1],
  1956. AR5K_PHY_ANT_SWITCH_TABLE_1);
  1957. }
  1958. /**
  1959. * ath5k_hw_set_antenna_mode() - Set antenna operating mode
  1960. * @ah: The &struct ath5k_hw
  1961. * @ant_mode: One of enum ath5k_ant_mode
  1962. */
  1963. void
  1964. ath5k_hw_set_antenna_mode(struct ath5k_hw *ah, u8 ant_mode)
  1965. {
  1966. struct ieee80211_channel *channel = ah->ah_current_channel;
  1967. bool use_def_for_tx, update_def_on_tx, use_def_for_rts, fast_div;
  1968. bool use_def_for_sg;
  1969. int ee_mode;
  1970. u8 def_ant, tx_ant;
  1971. u32 sta_id1 = 0;
  1972. /* if channel is not initialized yet we can't set the antennas
  1973. * so just store the mode. it will be set on the next reset */
  1974. if (channel == NULL) {
  1975. ah->ah_ant_mode = ant_mode;
  1976. return;
  1977. }
  1978. def_ant = ah->ah_def_ant;
  1979. ee_mode = ath5k_eeprom_mode_from_channel(ah, channel);
  1980. switch (ant_mode) {
  1981. case AR5K_ANTMODE_DEFAULT:
  1982. tx_ant = 0;
  1983. use_def_for_tx = false;
  1984. update_def_on_tx = false;
  1985. use_def_for_rts = false;
  1986. use_def_for_sg = false;
  1987. fast_div = true;
  1988. break;
  1989. case AR5K_ANTMODE_FIXED_A:
  1990. def_ant = 1;
  1991. tx_ant = 1;
  1992. use_def_for_tx = true;
  1993. update_def_on_tx = false;
  1994. use_def_for_rts = true;
  1995. use_def_for_sg = true;
  1996. fast_div = false;
  1997. break;
  1998. case AR5K_ANTMODE_FIXED_B:
  1999. def_ant = 2;
  2000. tx_ant = 2;
  2001. use_def_for_tx = true;
  2002. update_def_on_tx = false;
  2003. use_def_for_rts = true;
  2004. use_def_for_sg = true;
  2005. fast_div = false;
  2006. break;
  2007. case AR5K_ANTMODE_SINGLE_AP:
  2008. def_ant = 1; /* updated on tx */
  2009. tx_ant = 0;
  2010. use_def_for_tx = true;
  2011. update_def_on_tx = true;
  2012. use_def_for_rts = true;
  2013. use_def_for_sg = true;
  2014. fast_div = true;
  2015. break;
  2016. case AR5K_ANTMODE_SECTOR_AP:
  2017. tx_ant = 1; /* variable */
  2018. use_def_for_tx = false;
  2019. update_def_on_tx = false;
  2020. use_def_for_rts = true;
  2021. use_def_for_sg = false;
  2022. fast_div = false;
  2023. break;
  2024. case AR5K_ANTMODE_SECTOR_STA:
  2025. tx_ant = 1; /* variable */
  2026. use_def_for_tx = true;
  2027. update_def_on_tx = false;
  2028. use_def_for_rts = true;
  2029. use_def_for_sg = false;
  2030. fast_div = true;
  2031. break;
  2032. case AR5K_ANTMODE_DEBUG:
  2033. def_ant = 1;
  2034. tx_ant = 2;
  2035. use_def_for_tx = false;
  2036. update_def_on_tx = false;
  2037. use_def_for_rts = false;
  2038. use_def_for_sg = false;
  2039. fast_div = false;
  2040. break;
  2041. default:
  2042. return;
  2043. }
  2044. ah->ah_tx_ant = tx_ant;
  2045. ah->ah_ant_mode = ant_mode;
  2046. ah->ah_def_ant = def_ant;
  2047. sta_id1 |= use_def_for_tx ? AR5K_STA_ID1_DEFAULT_ANTENNA : 0;
  2048. sta_id1 |= update_def_on_tx ? AR5K_STA_ID1_DESC_ANTENNA : 0;
  2049. sta_id1 |= use_def_for_rts ? AR5K_STA_ID1_RTS_DEF_ANTENNA : 0;
  2050. sta_id1 |= use_def_for_sg ? AR5K_STA_ID1_SELFGEN_DEF_ANT : 0;
  2051. AR5K_REG_DISABLE_BITS(ah, AR5K_STA_ID1, AR5K_STA_ID1_ANTENNA_SETTINGS);
  2052. if (sta_id1)
  2053. AR5K_REG_ENABLE_BITS(ah, AR5K_STA_ID1, sta_id1);
  2054. ath5k_hw_set_antenna_switch(ah, ee_mode);
  2055. /* Note: set diversity before default antenna
  2056. * because it won't work correctly */
  2057. ath5k_hw_set_fast_div(ah, ee_mode, fast_div);
  2058. ath5k_hw_set_def_antenna(ah, def_ant);
  2059. }
  2060. /****************\
  2061. * TX power setup *
  2062. \****************/
  2063. /*
  2064. * Helper functions
  2065. */
  2066. /**
  2067. * ath5k_get_interpolated_value() - Get interpolated Y val between two points
  2068. * @target: X value of the middle point
  2069. * @x_left: X value of the left point
  2070. * @x_right: X value of the right point
  2071. * @y_left: Y value of the left point
  2072. * @y_right: Y value of the right point
  2073. */
  2074. static s16
  2075. ath5k_get_interpolated_value(s16 target, s16 x_left, s16 x_right,
  2076. s16 y_left, s16 y_right)
  2077. {
  2078. s16 ratio, result;
  2079. /* Avoid divide by zero and skip interpolation
  2080. * if we have the same point */
  2081. if ((x_left == x_right) || (y_left == y_right))
  2082. return y_left;
  2083. /*
  2084. * Since we use ints and not fps, we need to scale up in
  2085. * order to get a sane ratio value (or else we 'll eg. get
  2086. * always 1 instead of 1.25, 1.75 etc). We scale up by 100
  2087. * to have some accuracy both for 0.5 and 0.25 steps.
  2088. */
  2089. ratio = ((100 * y_right - 100 * y_left) / (x_right - x_left));
  2090. /* Now scale down to be in range */
  2091. result = y_left + (ratio * (target - x_left) / 100);
  2092. return result;
  2093. }
  2094. /**
  2095. * ath5k_get_linear_pcdac_min() - Find vertical boundary (min pwr) for the
  2096. * linear PCDAC curve
  2097. * @stepL: Left array with y values (pcdac steps)
  2098. * @stepR: Right array with y values (pcdac steps)
  2099. * @pwrL: Left array with x values (power steps)
  2100. * @pwrR: Right array with x values (power steps)
  2101. *
  2102. * Since we have the top of the curve and we draw the line below
  2103. * until we reach 1 (1 pcdac step) we need to know which point
  2104. * (x value) that is so that we don't go below x axis and have negative
  2105. * pcdac values when creating the curve, or fill the table with zeros.
  2106. */
  2107. static s16
  2108. ath5k_get_linear_pcdac_min(const u8 *stepL, const u8 *stepR,
  2109. const s16 *pwrL, const s16 *pwrR)
  2110. {
  2111. s8 tmp;
  2112. s16 min_pwrL, min_pwrR;
  2113. s16 pwr_i;
  2114. /* Some vendors write the same pcdac value twice !!! */
  2115. if (stepL[0] == stepL[1] || stepR[0] == stepR[1])
  2116. return max(pwrL[0], pwrR[0]);
  2117. if (pwrL[0] == pwrL[1])
  2118. min_pwrL = pwrL[0];
  2119. else {
  2120. pwr_i = pwrL[0];
  2121. do {
  2122. pwr_i--;
  2123. tmp = (s8) ath5k_get_interpolated_value(pwr_i,
  2124. pwrL[0], pwrL[1],
  2125. stepL[0], stepL[1]);
  2126. } while (tmp > 1);
  2127. min_pwrL = pwr_i;
  2128. }
  2129. if (pwrR[0] == pwrR[1])
  2130. min_pwrR = pwrR[0];
  2131. else {
  2132. pwr_i = pwrR[0];
  2133. do {
  2134. pwr_i--;
  2135. tmp = (s8) ath5k_get_interpolated_value(pwr_i,
  2136. pwrR[0], pwrR[1],
  2137. stepR[0], stepR[1]);
  2138. } while (tmp > 1);
  2139. min_pwrR = pwr_i;
  2140. }
  2141. /* Keep the right boundary so that it works for both curves */
  2142. return max(min_pwrL, min_pwrR);
  2143. }
  2144. /**
  2145. * ath5k_create_power_curve() - Create a Power to PDADC or PCDAC curve
  2146. * @pmin: Minimum power value (xmin)
  2147. * @pmax: Maximum power value (xmax)
  2148. * @pwr: Array of power steps (x values)
  2149. * @vpd: Array of matching PCDAC/PDADC steps (y values)
  2150. * @num_points: Number of provided points
  2151. * @vpd_table: Array to fill with the full PCDAC/PDADC values (y values)
  2152. * @type: One of enum ath5k_powertable_type (eeprom.h)
  2153. *
  2154. * Interpolate (pwr,vpd) points to create a Power to PDADC or a
  2155. * Power to PCDAC curve.
  2156. *
  2157. * Each curve has power on x axis (in 0.5dB units) and PCDAC/PDADC
  2158. * steps (offsets) on y axis. Power can go up to 31.5dB and max
  2159. * PCDAC/PDADC step for each curve is 64 but we can write more than
  2160. * one curves on hw so we can go up to 128 (which is the max step we
  2161. * can write on the final table).
  2162. *
  2163. * We write y values (PCDAC/PDADC steps) on hw.
  2164. */
  2165. static void
  2166. ath5k_create_power_curve(s16 pmin, s16 pmax,
  2167. const s16 *pwr, const u8 *vpd,
  2168. u8 num_points,
  2169. u8 *vpd_table, u8 type)
  2170. {
  2171. u8 idx[2] = { 0, 1 };
  2172. s16 pwr_i = 2 * pmin;
  2173. int i;
  2174. if (num_points < 2)
  2175. return;
  2176. /* We want the whole line, so adjust boundaries
  2177. * to cover the entire power range. Note that
  2178. * power values are already 0.25dB so no need
  2179. * to multiply pwr_i by 2 */
  2180. if (type == AR5K_PWRTABLE_LINEAR_PCDAC) {
  2181. pwr_i = pmin;
  2182. pmin = 0;
  2183. pmax = 63;
  2184. }
  2185. /* Find surrounding turning points (TPs)
  2186. * and interpolate between them */
  2187. for (i = 0; (i <= (u16) (pmax - pmin)) &&
  2188. (i < AR5K_EEPROM_POWER_TABLE_SIZE); i++) {
  2189. /* We passed the right TP, move to the next set of TPs
  2190. * if we pass the last TP, extrapolate above using the last
  2191. * two TPs for ratio */
  2192. if ((pwr_i > pwr[idx[1]]) && (idx[1] < num_points - 1)) {
  2193. idx[0]++;
  2194. idx[1]++;
  2195. }
  2196. vpd_table[i] = (u8) ath5k_get_interpolated_value(pwr_i,
  2197. pwr[idx[0]], pwr[idx[1]],
  2198. vpd[idx[0]], vpd[idx[1]]);
  2199. /* Increase by 0.5dB
  2200. * (0.25 dB units) */
  2201. pwr_i += 2;
  2202. }
  2203. }
  2204. /**
  2205. * ath5k_get_chan_pcal_surrounding_piers() - Get surrounding calibration piers
  2206. * for a given channel.
  2207. * @ah: The &struct ath5k_hw
  2208. * @channel: The &struct ieee80211_channel
  2209. * @pcinfo_l: The &struct ath5k_chan_pcal_info to put the left cal. pier
  2210. * @pcinfo_r: The &struct ath5k_chan_pcal_info to put the right cal. pier
  2211. *
  2212. * Get the surrounding per-channel power calibration piers
  2213. * for a given frequency so that we can interpolate between
  2214. * them and come up with an appropriate dataset for our current
  2215. * channel.
  2216. */
  2217. static void
  2218. ath5k_get_chan_pcal_surrounding_piers(struct ath5k_hw *ah,
  2219. struct ieee80211_channel *channel,
  2220. struct ath5k_chan_pcal_info **pcinfo_l,
  2221. struct ath5k_chan_pcal_info **pcinfo_r)
  2222. {
  2223. struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
  2224. struct ath5k_chan_pcal_info *pcinfo;
  2225. u8 idx_l, idx_r;
  2226. u8 mode, max, i;
  2227. u32 target = channel->center_freq;
  2228. idx_l = 0;
  2229. idx_r = 0;
  2230. switch (channel->hw_value) {
  2231. case AR5K_EEPROM_MODE_11A:
  2232. pcinfo = ee->ee_pwr_cal_a;
  2233. mode = AR5K_EEPROM_MODE_11A;
  2234. break;
  2235. case AR5K_EEPROM_MODE_11B:
  2236. pcinfo = ee->ee_pwr_cal_b;
  2237. mode = AR5K_EEPROM_MODE_11B;
  2238. break;
  2239. case AR5K_EEPROM_MODE_11G:
  2240. default:
  2241. pcinfo = ee->ee_pwr_cal_g;
  2242. mode = AR5K_EEPROM_MODE_11G;
  2243. break;
  2244. }
  2245. max = ee->ee_n_piers[mode] - 1;
  2246. /* Frequency is below our calibrated
  2247. * range. Use the lowest power curve
  2248. * we have */
  2249. if (target < pcinfo[0].freq) {
  2250. idx_l = idx_r = 0;
  2251. goto done;
  2252. }
  2253. /* Frequency is above our calibrated
  2254. * range. Use the highest power curve
  2255. * we have */
  2256. if (target > pcinfo[max].freq) {
  2257. idx_l = idx_r = max;
  2258. goto done;
  2259. }
  2260. /* Frequency is inside our calibrated
  2261. * channel range. Pick the surrounding
  2262. * calibration piers so that we can
  2263. * interpolate */
  2264. for (i = 0; i <= max; i++) {
  2265. /* Frequency matches one of our calibration
  2266. * piers, no need to interpolate, just use
  2267. * that calibration pier */
  2268. if (pcinfo[i].freq == target) {
  2269. idx_l = idx_r = i;
  2270. goto done;
  2271. }
  2272. /* We found a calibration pier that's above
  2273. * frequency, use this pier and the previous
  2274. * one to interpolate */
  2275. if (target < pcinfo[i].freq) {
  2276. idx_r = i;
  2277. idx_l = idx_r - 1;
  2278. goto done;
  2279. }
  2280. }
  2281. done:
  2282. *pcinfo_l = &pcinfo[idx_l];
  2283. *pcinfo_r = &pcinfo[idx_r];
  2284. }
  2285. /**
  2286. * ath5k_get_rate_pcal_data() - Get the interpolated per-rate power
  2287. * calibration data
  2288. * @ah: The &struct ath5k_hw *ah,
  2289. * @channel: The &struct ieee80211_channel
  2290. * @rates: The &struct ath5k_rate_pcal_info to fill
  2291. *
  2292. * Get the surrounding per-rate power calibration data
  2293. * for a given frequency and interpolate between power
  2294. * values to set max target power supported by hw for
  2295. * each rate on this frequency.
  2296. */
  2297. static void
  2298. ath5k_get_rate_pcal_data(struct ath5k_hw *ah,
  2299. struct ieee80211_channel *channel,
  2300. struct ath5k_rate_pcal_info *rates)
  2301. {
  2302. struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
  2303. struct ath5k_rate_pcal_info *rpinfo;
  2304. u8 idx_l, idx_r;
  2305. u8 mode, max, i;
  2306. u32 target = channel->center_freq;
  2307. idx_l = 0;
  2308. idx_r = 0;
  2309. switch (channel->hw_value) {
  2310. case AR5K_MODE_11A:
  2311. rpinfo = ee->ee_rate_tpwr_a;
  2312. mode = AR5K_EEPROM_MODE_11A;
  2313. break;
  2314. case AR5K_MODE_11B:
  2315. rpinfo = ee->ee_rate_tpwr_b;
  2316. mode = AR5K_EEPROM_MODE_11B;
  2317. break;
  2318. case AR5K_MODE_11G:
  2319. default:
  2320. rpinfo = ee->ee_rate_tpwr_g;
  2321. mode = AR5K_EEPROM_MODE_11G;
  2322. break;
  2323. }
  2324. max = ee->ee_rate_target_pwr_num[mode] - 1;
  2325. /* Get the surrounding calibration
  2326. * piers - same as above */
  2327. if (target < rpinfo[0].freq) {
  2328. idx_l = idx_r = 0;
  2329. goto done;
  2330. }
  2331. if (target > rpinfo[max].freq) {
  2332. idx_l = idx_r = max;
  2333. goto done;
  2334. }
  2335. for (i = 0; i <= max; i++) {
  2336. if (rpinfo[i].freq == target) {
  2337. idx_l = idx_r = i;
  2338. goto done;
  2339. }
  2340. if (target < rpinfo[i].freq) {
  2341. idx_r = i;
  2342. idx_l = idx_r - 1;
  2343. goto done;
  2344. }
  2345. }
  2346. done:
  2347. /* Now interpolate power value, based on the frequency */
  2348. rates->freq = target;
  2349. rates->target_power_6to24 =
  2350. ath5k_get_interpolated_value(target, rpinfo[idx_l].freq,
  2351. rpinfo[idx_r].freq,
  2352. rpinfo[idx_l].target_power_6to24,
  2353. rpinfo[idx_r].target_power_6to24);
  2354. rates->target_power_36 =
  2355. ath5k_get_interpolated_value(target, rpinfo[idx_l].freq,
  2356. rpinfo[idx_r].freq,
  2357. rpinfo[idx_l].target_power_36,
  2358. rpinfo[idx_r].target_power_36);
  2359. rates->target_power_48 =
  2360. ath5k_get_interpolated_value(target, rpinfo[idx_l].freq,
  2361. rpinfo[idx_r].freq,
  2362. rpinfo[idx_l].target_power_48,
  2363. rpinfo[idx_r].target_power_48);
  2364. rates->target_power_54 =
  2365. ath5k_get_interpolated_value(target, rpinfo[idx_l].freq,
  2366. rpinfo[idx_r].freq,
  2367. rpinfo[idx_l].target_power_54,
  2368. rpinfo[idx_r].target_power_54);
  2369. }
  2370. /**
  2371. * ath5k_get_max_ctl_power() - Get max edge power for a given frequency
  2372. * @ah: the &struct ath5k_hw
  2373. * @channel: The &struct ieee80211_channel
  2374. *
  2375. * Get the max edge power for this channel if
  2376. * we have such data from EEPROM's Conformance Test
  2377. * Limits (CTL), and limit max power if needed.
  2378. */
  2379. static void
  2380. ath5k_get_max_ctl_power(struct ath5k_hw *ah,
  2381. struct ieee80211_channel *channel)
  2382. {
  2383. struct ath_regulatory *regulatory = ath5k_hw_regulatory(ah);
  2384. struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
  2385. struct ath5k_edge_power *rep = ee->ee_ctl_pwr;
  2386. u8 *ctl_val = ee->ee_ctl;
  2387. s16 max_chan_pwr = ah->ah_txpower.txp_max_pwr / 4;
  2388. s16 edge_pwr = 0;
  2389. u8 rep_idx;
  2390. u8 i, ctl_mode;
  2391. u8 ctl_idx = 0xFF;
  2392. u32 target = channel->center_freq;
  2393. ctl_mode = ath_regd_get_band_ctl(regulatory, channel->band);
  2394. switch (channel->hw_value) {
  2395. case AR5K_MODE_11A:
  2396. if (ah->ah_bwmode == AR5K_BWMODE_40MHZ)
  2397. ctl_mode |= AR5K_CTL_TURBO;
  2398. else
  2399. ctl_mode |= AR5K_CTL_11A;
  2400. break;
  2401. case AR5K_MODE_11G:
  2402. if (ah->ah_bwmode == AR5K_BWMODE_40MHZ)
  2403. ctl_mode |= AR5K_CTL_TURBOG;
  2404. else
  2405. ctl_mode |= AR5K_CTL_11G;
  2406. break;
  2407. case AR5K_MODE_11B:
  2408. ctl_mode |= AR5K_CTL_11B;
  2409. break;
  2410. default:
  2411. return;
  2412. }
  2413. for (i = 0; i < ee->ee_ctls; i++) {
  2414. if (ctl_val[i] == ctl_mode) {
  2415. ctl_idx = i;
  2416. break;
  2417. }
  2418. }
  2419. /* If we have a CTL dataset available grab it and find the
  2420. * edge power for our frequency */
  2421. if (ctl_idx == 0xFF)
  2422. return;
  2423. /* Edge powers are sorted by frequency from lower
  2424. * to higher. Each CTL corresponds to 8 edge power
  2425. * measurements. */
  2426. rep_idx = ctl_idx * AR5K_EEPROM_N_EDGES;
  2427. /* Don't do boundaries check because we
  2428. * might have more that one bands defined
  2429. * for this mode */
  2430. /* Get the edge power that's closer to our
  2431. * frequency */
  2432. for (i = 0; i < AR5K_EEPROM_N_EDGES; i++) {
  2433. rep_idx += i;
  2434. if (target <= rep[rep_idx].freq)
  2435. edge_pwr = (s16) rep[rep_idx].edge;
  2436. }
  2437. if (edge_pwr)
  2438. ah->ah_txpower.txp_max_pwr = 4 * min(edge_pwr, max_chan_pwr);
  2439. }
  2440. /*
  2441. * Power to PCDAC table functions
  2442. */
  2443. /**
  2444. * DOC: Power to PCDAC table functions
  2445. *
  2446. * For RF5111 we have an XPD -eXternal Power Detector- curve
  2447. * for each calibrated channel. Each curve has 0,5dB Power steps
  2448. * on x axis and PCDAC steps (offsets) on y axis and looks like an
  2449. * exponential function. To recreate the curve we read 11 points
  2450. * from eeprom (eeprom.c) and interpolate here.
  2451. *
  2452. * For RF5112 we have 4 XPD -eXternal Power Detector- curves
  2453. * for each calibrated channel on 0, -6, -12 and -18dBm but we only
  2454. * use the higher (3) and the lower (0) curves. Each curve again has 0.5dB
  2455. * power steps on x axis and PCDAC steps on y axis and looks like a
  2456. * linear function. To recreate the curve and pass the power values
  2457. * on hw, we get 4 points for xpd 0 (lower gain -> max power)
  2458. * and 3 points for xpd 3 (higher gain -> lower power) from eeprom (eeprom.c)
  2459. * and interpolate here.
  2460. *
  2461. * For a given channel we get the calibrated points (piers) for it or
  2462. * -if we don't have calibration data for this specific channel- from the
  2463. * available surrounding channels we have calibration data for, after we do a
  2464. * linear interpolation between them. Then since we have our calibrated points
  2465. * for this channel, we do again a linear interpolation between them to get the
  2466. * whole curve.
  2467. *
  2468. * We finally write the Y values of the curve(s) (the PCDAC values) on hw
  2469. */
  2470. /**
  2471. * ath5k_fill_pwr_to_pcdac_table() - Fill Power to PCDAC table on RF5111
  2472. * @ah: The &struct ath5k_hw
  2473. * @table_min: Minimum power (x min)
  2474. * @table_max: Maximum power (x max)
  2475. *
  2476. * No further processing is needed for RF5111, the only thing we have to
  2477. * do is fill the values below and above calibration range since eeprom data
  2478. * may not cover the entire PCDAC table.
  2479. */
  2480. static void
  2481. ath5k_fill_pwr_to_pcdac_table(struct ath5k_hw *ah, s16* table_min,
  2482. s16 *table_max)
  2483. {
  2484. u8 *pcdac_out = ah->ah_txpower.txp_pd_table;
  2485. u8 *pcdac_tmp = ah->ah_txpower.tmpL[0];
  2486. u8 pcdac_0, pcdac_n, pcdac_i, pwr_idx, i;
  2487. s16 min_pwr, max_pwr;
  2488. /* Get table boundaries */
  2489. min_pwr = table_min[0];
  2490. pcdac_0 = pcdac_tmp[0];
  2491. max_pwr = table_max[0];
  2492. pcdac_n = pcdac_tmp[table_max[0] - table_min[0]];
  2493. /* Extrapolate below minimum using pcdac_0 */
  2494. pcdac_i = 0;
  2495. for (i = 0; i < min_pwr; i++)
  2496. pcdac_out[pcdac_i++] = pcdac_0;
  2497. /* Copy values from pcdac_tmp */
  2498. pwr_idx = min_pwr;
  2499. for (i = 0; pwr_idx <= max_pwr &&
  2500. pcdac_i < AR5K_EEPROM_POWER_TABLE_SIZE; i++) {
  2501. pcdac_out[pcdac_i++] = pcdac_tmp[i];
  2502. pwr_idx++;
  2503. }
  2504. /* Extrapolate above maximum */
  2505. while (pcdac_i < AR5K_EEPROM_POWER_TABLE_SIZE)
  2506. pcdac_out[pcdac_i++] = pcdac_n;
  2507. }
  2508. /**
  2509. * ath5k_combine_linear_pcdac_curves() - Combine available PCDAC Curves
  2510. * @ah: The &struct ath5k_hw
  2511. * @table_min: Minimum power (x min)
  2512. * @table_max: Maximum power (x max)
  2513. * @pdcurves: Number of pd curves
  2514. *
  2515. * Combine available XPD Curves and fill Linear Power to PCDAC table on RF5112
  2516. * RFX112 can have up to 2 curves (one for low txpower range and one for
  2517. * higher txpower range). We need to put them both on pcdac_out and place
  2518. * them in the correct location. In case we only have one curve available
  2519. * just fit it on pcdac_out (it's supposed to cover the entire range of
  2520. * available pwr levels since it's always the higher power curve). Extrapolate
  2521. * below and above final table if needed.
  2522. */
  2523. static void
  2524. ath5k_combine_linear_pcdac_curves(struct ath5k_hw *ah, s16* table_min,
  2525. s16 *table_max, u8 pdcurves)
  2526. {
  2527. u8 *pcdac_out = ah->ah_txpower.txp_pd_table;
  2528. u8 *pcdac_low_pwr;
  2529. u8 *pcdac_high_pwr;
  2530. u8 *pcdac_tmp;
  2531. u8 pwr;
  2532. s16 max_pwr_idx;
  2533. s16 min_pwr_idx;
  2534. s16 mid_pwr_idx = 0;
  2535. /* Edge flag turns on the 7nth bit on the PCDAC
  2536. * to declare the higher power curve (force values
  2537. * to be greater than 64). If we only have one curve
  2538. * we don't need to set this, if we have 2 curves and
  2539. * fill the table backwards this can also be used to
  2540. * switch from higher power curve to lower power curve */
  2541. u8 edge_flag;
  2542. int i;
  2543. /* When we have only one curve available
  2544. * that's the higher power curve. If we have
  2545. * two curves the first is the high power curve
  2546. * and the next is the low power curve. */
  2547. if (pdcurves > 1) {
  2548. pcdac_low_pwr = ah->ah_txpower.tmpL[1];
  2549. pcdac_high_pwr = ah->ah_txpower.tmpL[0];
  2550. mid_pwr_idx = table_max[1] - table_min[1] - 1;
  2551. max_pwr_idx = (table_max[0] - table_min[0]) / 2;
  2552. /* If table size goes beyond 31.5dB, keep the
  2553. * upper 31.5dB range when setting tx power.
  2554. * Note: 126 = 31.5 dB in quarter dB steps */
  2555. if (table_max[0] - table_min[1] > 126)
  2556. min_pwr_idx = table_max[0] - 126;
  2557. else
  2558. min_pwr_idx = table_min[1];
  2559. /* Since we fill table backwards
  2560. * start from high power curve */
  2561. pcdac_tmp = pcdac_high_pwr;
  2562. edge_flag = 0x40;
  2563. } else {
  2564. pcdac_low_pwr = ah->ah_txpower.tmpL[1]; /* Zeroed */
  2565. pcdac_high_pwr = ah->ah_txpower.tmpL[0];
  2566. min_pwr_idx = table_min[0];
  2567. max_pwr_idx = (table_max[0] - table_min[0]) / 2;
  2568. pcdac_tmp = pcdac_high_pwr;
  2569. edge_flag = 0;
  2570. }
  2571. /* This is used when setting tx power*/
  2572. ah->ah_txpower.txp_min_idx = min_pwr_idx / 2;
  2573. /* Fill Power to PCDAC table backwards */
  2574. pwr = max_pwr_idx;
  2575. for (i = 63; i >= 0; i--) {
  2576. /* Entering lower power range, reset
  2577. * edge flag and set pcdac_tmp to lower
  2578. * power curve.*/
  2579. if (edge_flag == 0x40 &&
  2580. (2 * pwr <= (table_max[1] - table_min[0]) || pwr == 0)) {
  2581. edge_flag = 0x00;
  2582. pcdac_tmp = pcdac_low_pwr;
  2583. pwr = mid_pwr_idx / 2;
  2584. }
  2585. /* Don't go below 1, extrapolate below if we have
  2586. * already switched to the lower power curve -or
  2587. * we only have one curve and edge_flag is zero
  2588. * anyway */
  2589. if (pcdac_tmp[pwr] < 1 && (edge_flag == 0x00)) {
  2590. while (i >= 0) {
  2591. pcdac_out[i] = pcdac_out[i + 1];
  2592. i--;
  2593. }
  2594. break;
  2595. }
  2596. pcdac_out[i] = pcdac_tmp[pwr] | edge_flag;
  2597. /* Extrapolate above if pcdac is greater than
  2598. * 126 -this can happen because we OR pcdac_out
  2599. * value with edge_flag on high power curve */
  2600. if (pcdac_out[i] > 126)
  2601. pcdac_out[i] = 126;
  2602. /* Decrease by a 0.5dB step */
  2603. pwr--;
  2604. }
  2605. }
  2606. /**
  2607. * ath5k_write_pcdac_table() - Write the PCDAC values on hw
  2608. * @ah: The &struct ath5k_hw
  2609. */
  2610. static void
  2611. ath5k_write_pcdac_table(struct ath5k_hw *ah)
  2612. {
  2613. u8 *pcdac_out = ah->ah_txpower.txp_pd_table;
  2614. int i;
  2615. /*
  2616. * Write TX power values
  2617. */
  2618. for (i = 0; i < (AR5K_EEPROM_POWER_TABLE_SIZE / 2); i++) {
  2619. ath5k_hw_reg_write(ah,
  2620. (((pcdac_out[2 * i + 0] << 8 | 0xff) & 0xffff) << 0) |
  2621. (((pcdac_out[2 * i + 1] << 8 | 0xff) & 0xffff) << 16),
  2622. AR5K_PHY_PCDAC_TXPOWER(i));
  2623. }
  2624. }
  2625. /*
  2626. * Power to PDADC table functions
  2627. */
  2628. /**
  2629. * DOC: Power to PDADC table functions
  2630. *
  2631. * For RF2413 and later we have a Power to PDADC table (Power Detector)
  2632. * instead of a PCDAC (Power Control) and 4 pd gain curves for each
  2633. * calibrated channel. Each curve has power on x axis in 0.5 db steps and
  2634. * PDADC steps on y axis and looks like an exponential function like the
  2635. * RF5111 curve.
  2636. *
  2637. * To recreate the curves we read the points from eeprom (eeprom.c)
  2638. * and interpolate here. Note that in most cases only 2 (higher and lower)
  2639. * curves are used (like RF5112) but vendors have the opportunity to include
  2640. * all 4 curves on eeprom. The final curve (higher power) has an extra
  2641. * point for better accuracy like RF5112.
  2642. *
  2643. * The process is similar to what we do above for RF5111/5112
  2644. */
  2645. /**
  2646. * ath5k_combine_pwr_to_pdadc_curves() - Combine the various PDADC curves
  2647. * @ah: The &struct ath5k_hw
  2648. * @pwr_min: Minimum power (x min)
  2649. * @pwr_max: Maximum power (x max)
  2650. * @pdcurves: Number of available curves
  2651. *
  2652. * Combine the various pd curves and create the final Power to PDADC table
  2653. * We can have up to 4 pd curves, we need to do a similar process
  2654. * as we do for RF5112. This time we don't have an edge_flag but we
  2655. * set the gain boundaries on a separate register.
  2656. */
  2657. static void
  2658. ath5k_combine_pwr_to_pdadc_curves(struct ath5k_hw *ah,
  2659. s16 *pwr_min, s16 *pwr_max, u8 pdcurves)
  2660. {
  2661. u8 gain_boundaries[AR5K_EEPROM_N_PD_GAINS];
  2662. u8 *pdadc_out = ah->ah_txpower.txp_pd_table;
  2663. u8 *pdadc_tmp;
  2664. s16 pdadc_0;
  2665. u8 pdadc_i, pdadc_n, pwr_step, pdg, max_idx, table_size;
  2666. u8 pd_gain_overlap;
  2667. /* Note: Register value is initialized on initvals
  2668. * there is no feedback from hw.
  2669. * XXX: What about pd_gain_overlap from EEPROM ? */
  2670. pd_gain_overlap = (u8) ath5k_hw_reg_read(ah, AR5K_PHY_TPC_RG5) &
  2671. AR5K_PHY_TPC_RG5_PD_GAIN_OVERLAP;
  2672. /* Create final PDADC table */
  2673. for (pdg = 0, pdadc_i = 0; pdg < pdcurves; pdg++) {
  2674. pdadc_tmp = ah->ah_txpower.tmpL[pdg];
  2675. if (pdg == pdcurves - 1)
  2676. /* 2 dB boundary stretch for last
  2677. * (higher power) curve */
  2678. gain_boundaries[pdg] = pwr_max[pdg] + 4;
  2679. else
  2680. /* Set gain boundary in the middle
  2681. * between this curve and the next one */
  2682. gain_boundaries[pdg] =
  2683. (pwr_max[pdg] + pwr_min[pdg + 1]) / 2;
  2684. /* Sanity check in case our 2 db stretch got out of
  2685. * range. */
  2686. if (gain_boundaries[pdg] > AR5K_TUNE_MAX_TXPOWER)
  2687. gain_boundaries[pdg] = AR5K_TUNE_MAX_TXPOWER;
  2688. /* For the first curve (lower power)
  2689. * start from 0 dB */
  2690. if (pdg == 0)
  2691. pdadc_0 = 0;
  2692. else
  2693. /* For the other curves use the gain overlap */
  2694. pdadc_0 = (gain_boundaries[pdg - 1] - pwr_min[pdg]) -
  2695. pd_gain_overlap;
  2696. /* Force each power step to be at least 0.5 dB */
  2697. if ((pdadc_tmp[1] - pdadc_tmp[0]) > 1)
  2698. pwr_step = pdadc_tmp[1] - pdadc_tmp[0];
  2699. else
  2700. pwr_step = 1;
  2701. /* If pdadc_0 is negative, we need to extrapolate
  2702. * below this pdgain by a number of pwr_steps */
  2703. while ((pdadc_0 < 0) && (pdadc_i < 128)) {
  2704. s16 tmp = pdadc_tmp[0] + pdadc_0 * pwr_step;
  2705. pdadc_out[pdadc_i++] = (tmp < 0) ? 0 : (u8) tmp;
  2706. pdadc_0++;
  2707. }
  2708. /* Set last pwr level, using gain boundaries */
  2709. pdadc_n = gain_boundaries[pdg] + pd_gain_overlap - pwr_min[pdg];
  2710. /* Limit it to be inside pwr range */
  2711. table_size = pwr_max[pdg] - pwr_min[pdg];
  2712. max_idx = (pdadc_n < table_size) ? pdadc_n : table_size;
  2713. /* Fill pdadc_out table */
  2714. while (pdadc_0 < max_idx && pdadc_i < 128)
  2715. pdadc_out[pdadc_i++] = pdadc_tmp[pdadc_0++];
  2716. /* Need to extrapolate above this pdgain? */
  2717. if (pdadc_n <= max_idx)
  2718. continue;
  2719. /* Force each power step to be at least 0.5 dB */
  2720. if ((pdadc_tmp[table_size - 1] - pdadc_tmp[table_size - 2]) > 1)
  2721. pwr_step = pdadc_tmp[table_size - 1] -
  2722. pdadc_tmp[table_size - 2];
  2723. else
  2724. pwr_step = 1;
  2725. /* Extrapolate above */
  2726. while ((pdadc_0 < (s16) pdadc_n) &&
  2727. (pdadc_i < AR5K_EEPROM_POWER_TABLE_SIZE * 2)) {
  2728. s16 tmp = pdadc_tmp[table_size - 1] +
  2729. (pdadc_0 - max_idx) * pwr_step;
  2730. pdadc_out[pdadc_i++] = (tmp > 127) ? 127 : (u8) tmp;
  2731. pdadc_0++;
  2732. }
  2733. }
  2734. while (pdg < AR5K_EEPROM_N_PD_GAINS) {
  2735. gain_boundaries[pdg] = gain_boundaries[pdg - 1];
  2736. pdg++;
  2737. }
  2738. while (pdadc_i < AR5K_EEPROM_POWER_TABLE_SIZE * 2) {
  2739. pdadc_out[pdadc_i] = pdadc_out[pdadc_i - 1];
  2740. pdadc_i++;
  2741. }
  2742. /* Set gain boundaries */
  2743. ath5k_hw_reg_write(ah,
  2744. AR5K_REG_SM(pd_gain_overlap,
  2745. AR5K_PHY_TPC_RG5_PD_GAIN_OVERLAP) |
  2746. AR5K_REG_SM(gain_boundaries[0],
  2747. AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDARY_1) |
  2748. AR5K_REG_SM(gain_boundaries[1],
  2749. AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDARY_2) |
  2750. AR5K_REG_SM(gain_boundaries[2],
  2751. AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDARY_3) |
  2752. AR5K_REG_SM(gain_boundaries[3],
  2753. AR5K_PHY_TPC_RG5_PD_GAIN_BOUNDARY_4),
  2754. AR5K_PHY_TPC_RG5);
  2755. /* Used for setting rate power table */
  2756. ah->ah_txpower.txp_min_idx = pwr_min[0];
  2757. }
  2758. /**
  2759. * ath5k_write_pwr_to_pdadc_table() - Write the PDADC values on hw
  2760. * @ah: The &struct ath5k_hw
  2761. * @ee_mode: One of enum ath5k_driver_mode
  2762. */
  2763. static void
  2764. ath5k_write_pwr_to_pdadc_table(struct ath5k_hw *ah, u8 ee_mode)
  2765. {
  2766. struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
  2767. u8 *pdadc_out = ah->ah_txpower.txp_pd_table;
  2768. u8 *pdg_to_idx = ee->ee_pdc_to_idx[ee_mode];
  2769. u8 pdcurves = ee->ee_pd_gains[ee_mode];
  2770. u32 reg;
  2771. u8 i;
  2772. /* Select the right pdgain curves */
  2773. /* Clear current settings */
  2774. reg = ath5k_hw_reg_read(ah, AR5K_PHY_TPC_RG1);
  2775. reg &= ~(AR5K_PHY_TPC_RG1_PDGAIN_1 |
  2776. AR5K_PHY_TPC_RG1_PDGAIN_2 |
  2777. AR5K_PHY_TPC_RG1_PDGAIN_3 |
  2778. AR5K_PHY_TPC_RG1_NUM_PD_GAIN);
  2779. /*
  2780. * Use pd_gains curve from eeprom
  2781. *
  2782. * This overrides the default setting from initvals
  2783. * in case some vendors (e.g. Zcomax) don't use the default
  2784. * curves. If we don't honor their settings we 'll get a
  2785. * 5dB (1 * gain overlap ?) drop.
  2786. */
  2787. reg |= AR5K_REG_SM(pdcurves, AR5K_PHY_TPC_RG1_NUM_PD_GAIN);
  2788. switch (pdcurves) {
  2789. case 3:
  2790. reg |= AR5K_REG_SM(pdg_to_idx[2], AR5K_PHY_TPC_RG1_PDGAIN_3);
  2791. /* Fall through */
  2792. case 2:
  2793. reg |= AR5K_REG_SM(pdg_to_idx[1], AR5K_PHY_TPC_RG1_PDGAIN_2);
  2794. /* Fall through */
  2795. case 1:
  2796. reg |= AR5K_REG_SM(pdg_to_idx[0], AR5K_PHY_TPC_RG1_PDGAIN_1);
  2797. break;
  2798. }
  2799. ath5k_hw_reg_write(ah, reg, AR5K_PHY_TPC_RG1);
  2800. /*
  2801. * Write TX power values
  2802. */
  2803. for (i = 0; i < (AR5K_EEPROM_POWER_TABLE_SIZE / 2); i++) {
  2804. u32 val = get_unaligned_le32(&pdadc_out[4 * i]);
  2805. ath5k_hw_reg_write(ah, val, AR5K_PHY_PDADC_TXPOWER(i));
  2806. }
  2807. }
  2808. /*
  2809. * Common code for PCDAC/PDADC tables
  2810. */
  2811. /**
  2812. * ath5k_setup_channel_powertable() - Set up power table for this channel
  2813. * @ah: The &struct ath5k_hw
  2814. * @channel: The &struct ieee80211_channel
  2815. * @ee_mode: One of enum ath5k_driver_mode
  2816. * @type: One of enum ath5k_powertable_type (eeprom.h)
  2817. *
  2818. * This is the main function that uses all of the above
  2819. * to set PCDAC/PDADC table on hw for the current channel.
  2820. * This table is used for tx power calibration on the baseband,
  2821. * without it we get weird tx power levels and in some cases
  2822. * distorted spectral mask
  2823. */
  2824. static int
  2825. ath5k_setup_channel_powertable(struct ath5k_hw *ah,
  2826. struct ieee80211_channel *channel,
  2827. u8 ee_mode, u8 type)
  2828. {
  2829. struct ath5k_pdgain_info *pdg_L, *pdg_R;
  2830. struct ath5k_chan_pcal_info *pcinfo_L;
  2831. struct ath5k_chan_pcal_info *pcinfo_R;
  2832. struct ath5k_eeprom_info *ee = &ah->ah_capabilities.cap_eeprom;
  2833. u8 *pdg_curve_to_idx = ee->ee_pdc_to_idx[ee_mode];
  2834. s16 table_min[AR5K_EEPROM_N_PD_GAINS];
  2835. s16 table_max[AR5K_EEPROM_N_PD_GAINS];
  2836. u8 *tmpL;
  2837. u8 *tmpR;
  2838. u32 target = channel->center_freq;
  2839. int pdg, i;
  2840. /* Get surrounding freq piers for this channel */
  2841. ath5k_get_chan_pcal_surrounding_piers(ah, channel,
  2842. &pcinfo_L,
  2843. &pcinfo_R);
  2844. /* Loop over pd gain curves on
  2845. * surrounding freq piers by index */
  2846. for (pdg = 0; pdg < ee->ee_pd_gains[ee_mode]; pdg++) {
  2847. /* Fill curves in reverse order
  2848. * from lower power (max gain)
  2849. * to higher power. Use curve -> idx
  2850. * backmapping we did on eeprom init */
  2851. u8 idx = pdg_curve_to_idx[pdg];
  2852. /* Grab the needed curves by index */
  2853. pdg_L = &pcinfo_L->pd_curves[idx];
  2854. pdg_R = &pcinfo_R->pd_curves[idx];
  2855. /* Initialize the temp tables */
  2856. tmpL = ah->ah_txpower.tmpL[pdg];
  2857. tmpR = ah->ah_txpower.tmpR[pdg];
  2858. /* Set curve's x boundaries and create
  2859. * curves so that they cover the same
  2860. * range (if we don't do that one table
  2861. * will have values on some range and the
  2862. * other one won't have any so interpolation
  2863. * will fail) */
  2864. table_min[pdg] = min(pdg_L->pd_pwr[0],
  2865. pdg_R->pd_pwr[0]) / 2;
  2866. table_max[pdg] = max(pdg_L->pd_pwr[pdg_L->pd_points - 1],
  2867. pdg_R->pd_pwr[pdg_R->pd_points - 1]) / 2;
  2868. /* Now create the curves on surrounding channels
  2869. * and interpolate if needed to get the final
  2870. * curve for this gain on this channel */
  2871. switch (type) {
  2872. case AR5K_PWRTABLE_LINEAR_PCDAC:
  2873. /* Override min/max so that we don't loose
  2874. * accuracy (don't divide by 2) */
  2875. table_min[pdg] = min(pdg_L->pd_pwr[0],
  2876. pdg_R->pd_pwr[0]);
  2877. table_max[pdg] =
  2878. max(pdg_L->pd_pwr[pdg_L->pd_points - 1],
  2879. pdg_R->pd_pwr[pdg_R->pd_points - 1]);
  2880. /* Override minimum so that we don't get
  2881. * out of bounds while extrapolating
  2882. * below. Don't do this when we have 2
  2883. * curves and we are on the high power curve
  2884. * because table_min is ok in this case */
  2885. if (!(ee->ee_pd_gains[ee_mode] > 1 && pdg == 0)) {
  2886. table_min[pdg] =
  2887. ath5k_get_linear_pcdac_min(pdg_L->pd_step,
  2888. pdg_R->pd_step,
  2889. pdg_L->pd_pwr,
  2890. pdg_R->pd_pwr);
  2891. /* Don't go too low because we will
  2892. * miss the upper part of the curve.
  2893. * Note: 126 = 31.5dB (max power supported)
  2894. * in 0.25dB units */
  2895. if (table_max[pdg] - table_min[pdg] > 126)
  2896. table_min[pdg] = table_max[pdg] - 126;
  2897. }
  2898. /* Fall through */
  2899. case AR5K_PWRTABLE_PWR_TO_PCDAC:
  2900. case AR5K_PWRTABLE_PWR_TO_PDADC:
  2901. ath5k_create_power_curve(table_min[pdg],
  2902. table_max[pdg],
  2903. pdg_L->pd_pwr,
  2904. pdg_L->pd_step,
  2905. pdg_L->pd_points, tmpL, type);
  2906. /* We are in a calibration
  2907. * pier, no need to interpolate
  2908. * between freq piers */
  2909. if (pcinfo_L == pcinfo_R)
  2910. continue;
  2911. ath5k_create_power_curve(table_min[pdg],
  2912. table_max[pdg],
  2913. pdg_R->pd_pwr,
  2914. pdg_R->pd_step,
  2915. pdg_R->pd_points, tmpR, type);
  2916. break;
  2917. default:
  2918. return -EINVAL;
  2919. }
  2920. /* Interpolate between curves
  2921. * of surrounding freq piers to
  2922. * get the final curve for this
  2923. * pd gain. Re-use tmpL for interpolation
  2924. * output */
  2925. for (i = 0; (i < (u16) (table_max[pdg] - table_min[pdg])) &&
  2926. (i < AR5K_EEPROM_POWER_TABLE_SIZE); i++) {
  2927. tmpL[i] = (u8) ath5k_get_interpolated_value(target,
  2928. (s16) pcinfo_L->freq,
  2929. (s16) pcinfo_R->freq,
  2930. (s16) tmpL[i],
  2931. (s16) tmpR[i]);
  2932. }
  2933. }
  2934. /* Now we have a set of curves for this
  2935. * channel on tmpL (x range is table_max - table_min
  2936. * and y values are tmpL[pdg][]) sorted in the same
  2937. * order as EEPROM (because we've used the backmapping).
  2938. * So for RF5112 it's from higher power to lower power
  2939. * and for RF2413 it's from lower power to higher power.
  2940. * For RF5111 we only have one curve. */
  2941. /* Fill min and max power levels for this
  2942. * channel by interpolating the values on
  2943. * surrounding channels to complete the dataset */
  2944. ah->ah_txpower.txp_min_pwr = ath5k_get_interpolated_value(target,
  2945. (s16) pcinfo_L->freq,
  2946. (s16) pcinfo_R->freq,
  2947. pcinfo_L->min_pwr, pcinfo_R->min_pwr);
  2948. ah->ah_txpower.txp_max_pwr = ath5k_get_interpolated_value(target,
  2949. (s16) pcinfo_L->freq,
  2950. (s16) pcinfo_R->freq,
  2951. pcinfo_L->max_pwr, pcinfo_R->max_pwr);
  2952. /* Fill PCDAC/PDADC table */
  2953. switch (type) {
  2954. case AR5K_PWRTABLE_LINEAR_PCDAC:
  2955. /* For RF5112 we can have one or two curves
  2956. * and each curve covers a certain power lvl
  2957. * range so we need to do some more processing */
  2958. ath5k_combine_linear_pcdac_curves(ah, table_min, table_max,
  2959. ee->ee_pd_gains[ee_mode]);
  2960. /* Set txp.offset so that we can
  2961. * match max power value with max
  2962. * table index */
  2963. ah->ah_txpower.txp_offset = 64 - (table_max[0] / 2);
  2964. break;
  2965. case AR5K_PWRTABLE_PWR_TO_PCDAC:
  2966. /* We are done for RF5111 since it has only
  2967. * one curve, just fit the curve on the table */
  2968. ath5k_fill_pwr_to_pcdac_table(ah, table_min, table_max);
  2969. /* No rate powertable adjustment for RF5111 */
  2970. ah->ah_txpower.txp_min_idx = 0;
  2971. ah->ah_txpower.txp_offset = 0;
  2972. break;
  2973. case AR5K_PWRTABLE_PWR_TO_PDADC:
  2974. /* Set PDADC boundaries and fill
  2975. * final PDADC table */
  2976. ath5k_combine_pwr_to_pdadc_curves(ah, table_min, table_max,
  2977. ee->ee_pd_gains[ee_mode]);
  2978. /* Set txp.offset, note that table_min
  2979. * can be negative */
  2980. ah->ah_txpower.txp_offset = table_min[0];
  2981. break;
  2982. default:
  2983. return -EINVAL;
  2984. }
  2985. ah->ah_txpower.txp_setup = true;
  2986. return 0;
  2987. }
  2988. /**
  2989. * ath5k_write_channel_powertable() - Set power table for current channel on hw
  2990. * @ah: The &struct ath5k_hw
  2991. * @ee_mode: One of enum ath5k_driver_mode
  2992. * @type: One of enum ath5k_powertable_type (eeprom.h)
  2993. */
  2994. static void
  2995. ath5k_write_channel_powertable(struct ath5k_hw *ah, u8 ee_mode, u8 type)
  2996. {
  2997. if (type == AR5K_PWRTABLE_PWR_TO_PDADC)
  2998. ath5k_write_pwr_to_pdadc_table(ah, ee_mode);
  2999. else
  3000. ath5k_write_pcdac_table(ah);
  3001. }
  3002. /**
  3003. * DOC: Per-rate tx power setting
  3004. *
  3005. * This is the code that sets the desired tx power limit (below
  3006. * maximum) on hw for each rate (we also have TPC that sets
  3007. * power per packet type). We do that by providing an index on the
  3008. * PCDAC/PDADC table we set up above, for each rate.
  3009. *
  3010. * For now we only limit txpower based on maximum tx power
  3011. * supported by hw (what's inside rate_info) + conformance test
  3012. * limits. We need to limit this even more, based on regulatory domain
  3013. * etc to be safe. Normally this is done from above so we don't care
  3014. * here, all we care is that the tx power we set will be O.K.
  3015. * for the hw (e.g. won't create noise on PA etc).
  3016. *
  3017. * Rate power table contains indices to PCDAC/PDADC table (0.5dB steps -
  3018. * x values) and is indexed as follows:
  3019. * rates[0] - rates[7] -> OFDM rates
  3020. * rates[8] - rates[14] -> CCK rates
  3021. * rates[15] -> XR rates (they all have the same power)
  3022. */
  3023. /**
  3024. * ath5k_setup_rate_powertable() - Set up rate power table for a given tx power
  3025. * @ah: The &struct ath5k_hw
  3026. * @max_pwr: The maximum tx power requested in 0.5dB steps
  3027. * @rate_info: The &struct ath5k_rate_pcal_info to fill
  3028. * @ee_mode: One of enum ath5k_driver_mode
  3029. */
  3030. static void
  3031. ath5k_setup_rate_powertable(struct ath5k_hw *ah, u16 max_pwr,
  3032. struct ath5k_rate_pcal_info *rate_info,
  3033. u8 ee_mode)
  3034. {
  3035. unsigned int i;
  3036. u16 *rates;
  3037. s16 rate_idx_scaled = 0;
  3038. /* max_pwr is power level we got from driver/user in 0.5dB
  3039. * units, switch to 0.25dB units so we can compare */
  3040. max_pwr *= 2;
  3041. max_pwr = min(max_pwr, (u16) ah->ah_txpower.txp_max_pwr) / 2;
  3042. /* apply rate limits */
  3043. rates = ah->ah_txpower.txp_rates_power_table;
  3044. /* OFDM rates 6 to 24Mb/s */
  3045. for (i = 0; i < 5; i++)
  3046. rates[i] = min(max_pwr, rate_info->target_power_6to24);
  3047. /* Rest OFDM rates */
  3048. rates[5] = min(rates[0], rate_info->target_power_36);
  3049. rates[6] = min(rates[0], rate_info->target_power_48);
  3050. rates[7] = min(rates[0], rate_info->target_power_54);
  3051. /* CCK rates */
  3052. /* 1L */
  3053. rates[8] = min(rates[0], rate_info->target_power_6to24);
  3054. /* 2L */
  3055. rates[9] = min(rates[0], rate_info->target_power_36);
  3056. /* 2S */
  3057. rates[10] = min(rates[0], rate_info->target_power_36);
  3058. /* 5L */
  3059. rates[11] = min(rates[0], rate_info->target_power_48);
  3060. /* 5S */
  3061. rates[12] = min(rates[0], rate_info->target_power_48);
  3062. /* 11L */
  3063. rates[13] = min(rates[0], rate_info->target_power_54);
  3064. /* 11S */
  3065. rates[14] = min(rates[0], rate_info->target_power_54);
  3066. /* XR rates */
  3067. rates[15] = min(rates[0], rate_info->target_power_6to24);
  3068. /* CCK rates have different peak to average ratio
  3069. * so we have to tweak their power so that gainf
  3070. * correction works ok. For this we use OFDM to
  3071. * CCK delta from eeprom */
  3072. if ((ee_mode == AR5K_EEPROM_MODE_11G) &&
  3073. (ah->ah_phy_revision < AR5K_SREV_PHY_5212A))
  3074. for (i = 8; i <= 15; i++)
  3075. rates[i] -= ah->ah_txpower.txp_cck_ofdm_gainf_delta;
  3076. /* Save min/max and current tx power for this channel
  3077. * in 0.25dB units.
  3078. *
  3079. * Note: We use rates[0] for current tx power because
  3080. * it covers most of the rates, in most cases. It's our
  3081. * tx power limit and what the user expects to see. */
  3082. ah->ah_txpower.txp_min_pwr = 2 * rates[7];
  3083. ah->ah_txpower.txp_cur_pwr = 2 * rates[0];
  3084. /* Set max txpower for correct OFDM operation on all rates
  3085. * -that is the txpower for 54Mbit-, it's used for the PAPD
  3086. * gain probe and it's in 0.5dB units */
  3087. ah->ah_txpower.txp_ofdm = rates[7];
  3088. /* Now that we have all rates setup use table offset to
  3089. * match the power range set by user with the power indices
  3090. * on PCDAC/PDADC table */
  3091. for (i = 0; i < 16; i++) {
  3092. rate_idx_scaled = rates[i] + ah->ah_txpower.txp_offset;
  3093. /* Don't get out of bounds */
  3094. if (rate_idx_scaled > 63)
  3095. rate_idx_scaled = 63;
  3096. if (rate_idx_scaled < 0)
  3097. rate_idx_scaled = 0;
  3098. rates[i] = rate_idx_scaled;
  3099. }
  3100. }
  3101. /**
  3102. * ath5k_hw_txpower() - Set transmission power limit for a given channel
  3103. * @ah: The &struct ath5k_hw
  3104. * @channel: The &struct ieee80211_channel
  3105. * @txpower: Requested tx power in 0.5dB steps
  3106. *
  3107. * Combines all of the above to set the requested tx power limit
  3108. * on hw.
  3109. */
  3110. static int
  3111. ath5k_hw_txpower(struct ath5k_hw *ah, struct ieee80211_channel *channel,
  3112. u8 txpower)
  3113. {
  3114. struct ath5k_rate_pcal_info rate_info;
  3115. struct ieee80211_channel *curr_channel = ah->ah_current_channel;
  3116. int ee_mode;
  3117. u8 type;
  3118. int ret;
  3119. if (txpower > AR5K_TUNE_MAX_TXPOWER) {
  3120. ATH5K_ERR(ah, "invalid tx power: %u\n", txpower);
  3121. return -EINVAL;
  3122. }
  3123. ee_mode = ath5k_eeprom_mode_from_channel(ah, channel);
  3124. /* Initialize TX power table */
  3125. switch (ah->ah_radio) {
  3126. case AR5K_RF5110:
  3127. /* TODO */
  3128. return 0;
  3129. case AR5K_RF5111:
  3130. type = AR5K_PWRTABLE_PWR_TO_PCDAC;
  3131. break;
  3132. case AR5K_RF5112:
  3133. type = AR5K_PWRTABLE_LINEAR_PCDAC;
  3134. break;
  3135. case AR5K_RF2413:
  3136. case AR5K_RF5413:
  3137. case AR5K_RF2316:
  3138. case AR5K_RF2317:
  3139. case AR5K_RF2425:
  3140. type = AR5K_PWRTABLE_PWR_TO_PDADC;
  3141. break;
  3142. default:
  3143. return -EINVAL;
  3144. }
  3145. /*
  3146. * If we don't change channel/mode skip tx powertable calculation
  3147. * and use the cached one.
  3148. */
  3149. if (!ah->ah_txpower.txp_setup ||
  3150. (channel->hw_value != curr_channel->hw_value) ||
  3151. (channel->center_freq != curr_channel->center_freq)) {
  3152. /* Reset TX power values but preserve requested
  3153. * tx power from above */
  3154. int requested_txpower = ah->ah_txpower.txp_requested;
  3155. memset(&ah->ah_txpower, 0, sizeof(ah->ah_txpower));
  3156. /* Restore TPC setting and requested tx power */
  3157. ah->ah_txpower.txp_tpc = AR5K_TUNE_TPC_TXPOWER;
  3158. ah->ah_txpower.txp_requested = requested_txpower;
  3159. /* Calculate the powertable */
  3160. ret = ath5k_setup_channel_powertable(ah, channel,
  3161. ee_mode, type);
  3162. if (ret)
  3163. return ret;
  3164. }
  3165. /* Write table on hw */
  3166. ath5k_write_channel_powertable(ah, ee_mode, type);
  3167. /* Limit max power if we have a CTL available */
  3168. ath5k_get_max_ctl_power(ah, channel);
  3169. /* FIXME: Antenna reduction stuff */
  3170. /* FIXME: Limit power on turbo modes */
  3171. /* FIXME: TPC scale reduction */
  3172. /* Get surrounding channels for per-rate power table
  3173. * calibration */
  3174. ath5k_get_rate_pcal_data(ah, channel, &rate_info);
  3175. /* Setup rate power table */
  3176. ath5k_setup_rate_powertable(ah, txpower, &rate_info, ee_mode);
  3177. /* Write rate power table on hw */
  3178. ath5k_hw_reg_write(ah, AR5K_TXPOWER_OFDM(3, 24) |
  3179. AR5K_TXPOWER_OFDM(2, 16) | AR5K_TXPOWER_OFDM(1, 8) |
  3180. AR5K_TXPOWER_OFDM(0, 0), AR5K_PHY_TXPOWER_RATE1);
  3181. ath5k_hw_reg_write(ah, AR5K_TXPOWER_OFDM(7, 24) |
  3182. AR5K_TXPOWER_OFDM(6, 16) | AR5K_TXPOWER_OFDM(5, 8) |
  3183. AR5K_TXPOWER_OFDM(4, 0), AR5K_PHY_TXPOWER_RATE2);
  3184. ath5k_hw_reg_write(ah, AR5K_TXPOWER_CCK(10, 24) |
  3185. AR5K_TXPOWER_CCK(9, 16) | AR5K_TXPOWER_CCK(15, 8) |
  3186. AR5K_TXPOWER_CCK(8, 0), AR5K_PHY_TXPOWER_RATE3);
  3187. ath5k_hw_reg_write(ah, AR5K_TXPOWER_CCK(14, 24) |
  3188. AR5K_TXPOWER_CCK(13, 16) | AR5K_TXPOWER_CCK(12, 8) |
  3189. AR5K_TXPOWER_CCK(11, 0), AR5K_PHY_TXPOWER_RATE4);
  3190. /* FIXME: TPC support */
  3191. if (ah->ah_txpower.txp_tpc) {
  3192. ath5k_hw_reg_write(ah, AR5K_PHY_TXPOWER_RATE_MAX_TPC_ENABLE |
  3193. AR5K_TUNE_MAX_TXPOWER, AR5K_PHY_TXPOWER_RATE_MAX);
  3194. ath5k_hw_reg_write(ah,
  3195. AR5K_REG_MS(AR5K_TUNE_MAX_TXPOWER, AR5K_TPC_ACK) |
  3196. AR5K_REG_MS(AR5K_TUNE_MAX_TXPOWER, AR5K_TPC_CTS) |
  3197. AR5K_REG_MS(AR5K_TUNE_MAX_TXPOWER, AR5K_TPC_CHIRP),
  3198. AR5K_TPC);
  3199. } else {
  3200. ath5k_hw_reg_write(ah, AR5K_TUNE_MAX_TXPOWER,
  3201. AR5K_PHY_TXPOWER_RATE_MAX);
  3202. }
  3203. return 0;
  3204. }
  3205. /**
  3206. * ath5k_hw_set_txpower_limit() - Set txpower limit for the current channel
  3207. * @ah: The &struct ath5k_hw
  3208. * @txpower: The requested tx power limit in 0.5dB steps
  3209. *
  3210. * This function provides access to ath5k_hw_txpower to the driver in
  3211. * case user or an application changes it while PHY is running.
  3212. */
  3213. int
  3214. ath5k_hw_set_txpower_limit(struct ath5k_hw *ah, u8 txpower)
  3215. {
  3216. ATH5K_DBG(ah, ATH5K_DEBUG_TXPOWER,
  3217. "changing txpower to %d\n", txpower);
  3218. return ath5k_hw_txpower(ah, ah->ah_current_channel, txpower);
  3219. }
  3220. /*************\
  3221. Init function
  3222. \*************/
  3223. /**
  3224. * ath5k_hw_phy_init() - Initialize PHY
  3225. * @ah: The &struct ath5k_hw
  3226. * @channel: The @struct ieee80211_channel
  3227. * @mode: One of enum ath5k_driver_mode
  3228. * @fast: Try a fast channel switch instead
  3229. *
  3230. * This is the main function used during reset to initialize PHY
  3231. * or do a fast channel change if possible.
  3232. *
  3233. * NOTE: Do not call this one from the driver, it assumes PHY is in a
  3234. * warm reset state !
  3235. */
  3236. int
  3237. ath5k_hw_phy_init(struct ath5k_hw *ah, struct ieee80211_channel *channel,
  3238. u8 mode, bool fast)
  3239. {
  3240. struct ieee80211_channel *curr_channel;
  3241. int ret, i;
  3242. u32 phy_tst1;
  3243. ret = 0;
  3244. /*
  3245. * Sanity check for fast flag
  3246. * Don't try fast channel change when changing modulation
  3247. * mode/band. We check for chip compatibility on
  3248. * ath5k_hw_reset.
  3249. */
  3250. curr_channel = ah->ah_current_channel;
  3251. if (fast && (channel->hw_value != curr_channel->hw_value))
  3252. return -EINVAL;
  3253. /*
  3254. * On fast channel change we only set the synth parameters
  3255. * while PHY is running, enable calibration and skip the rest.
  3256. */
  3257. if (fast) {
  3258. AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_RFBUS_REQ,
  3259. AR5K_PHY_RFBUS_REQ_REQUEST);
  3260. for (i = 0; i < 100; i++) {
  3261. if (ath5k_hw_reg_read(ah, AR5K_PHY_RFBUS_GRANT))
  3262. break;
  3263. udelay(5);
  3264. }
  3265. /* Failed */
  3266. if (i >= 100)
  3267. return -EIO;
  3268. /* Set channel and wait for synth */
  3269. ret = ath5k_hw_channel(ah, channel);
  3270. if (ret)
  3271. return ret;
  3272. ath5k_hw_wait_for_synth(ah, channel);
  3273. }
  3274. /*
  3275. * Set TX power
  3276. *
  3277. * Note: We need to do that before we set
  3278. * RF buffer settings on 5211/5212+ so that we
  3279. * properly set curve indices.
  3280. */
  3281. ret = ath5k_hw_txpower(ah, channel, ah->ah_txpower.txp_requested ?
  3282. ah->ah_txpower.txp_requested * 2 :
  3283. AR5K_TUNE_MAX_TXPOWER);
  3284. if (ret)
  3285. return ret;
  3286. /* Write OFDM timings on 5212*/
  3287. if (ah->ah_version == AR5K_AR5212 &&
  3288. channel->hw_value != AR5K_MODE_11B) {
  3289. ret = ath5k_hw_write_ofdm_timings(ah, channel);
  3290. if (ret)
  3291. return ret;
  3292. /* Spur info is available only from EEPROM versions
  3293. * greater than 5.3, but the EEPROM routines will use
  3294. * static values for older versions */
  3295. if (ah->ah_mac_srev >= AR5K_SREV_AR5424)
  3296. ath5k_hw_set_spur_mitigation_filter(ah,
  3297. channel);
  3298. }
  3299. /* If we used fast channel switching
  3300. * we are done, release RF bus and
  3301. * fire up NF calibration.
  3302. *
  3303. * Note: Only NF calibration due to
  3304. * channel change, not AGC calibration
  3305. * since AGC is still running !
  3306. */
  3307. if (fast) {
  3308. /*
  3309. * Release RF Bus grant
  3310. */
  3311. AR5K_REG_DISABLE_BITS(ah, AR5K_PHY_RFBUS_REQ,
  3312. AR5K_PHY_RFBUS_REQ_REQUEST);
  3313. /*
  3314. * Start NF calibration
  3315. */
  3316. AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGCCTL,
  3317. AR5K_PHY_AGCCTL_NF);
  3318. return ret;
  3319. }
  3320. /*
  3321. * For 5210 we do all initialization using
  3322. * initvals, so we don't have to modify
  3323. * any settings (5210 also only supports
  3324. * a/aturbo modes)
  3325. */
  3326. if (ah->ah_version != AR5K_AR5210) {
  3327. /*
  3328. * Write initial RF gain settings
  3329. * This should work for both 5111/5112
  3330. */
  3331. ret = ath5k_hw_rfgain_init(ah, channel->band);
  3332. if (ret)
  3333. return ret;
  3334. usleep_range(1000, 1500);
  3335. /*
  3336. * Write RF buffer
  3337. */
  3338. ret = ath5k_hw_rfregs_init(ah, channel, mode);
  3339. if (ret)
  3340. return ret;
  3341. /*Enable/disable 802.11b mode on 5111
  3342. (enable 2111 frequency converter + CCK)*/
  3343. if (ah->ah_radio == AR5K_RF5111) {
  3344. if (mode == AR5K_MODE_11B)
  3345. AR5K_REG_ENABLE_BITS(ah, AR5K_TXCFG,
  3346. AR5K_TXCFG_B_MODE);
  3347. else
  3348. AR5K_REG_DISABLE_BITS(ah, AR5K_TXCFG,
  3349. AR5K_TXCFG_B_MODE);
  3350. }
  3351. } else if (ah->ah_version == AR5K_AR5210) {
  3352. usleep_range(1000, 1500);
  3353. /* Disable phy and wait */
  3354. ath5k_hw_reg_write(ah, AR5K_PHY_ACT_DISABLE, AR5K_PHY_ACT);
  3355. usleep_range(1000, 1500);
  3356. }
  3357. /* Set channel on PHY */
  3358. ret = ath5k_hw_channel(ah, channel);
  3359. if (ret)
  3360. return ret;
  3361. /*
  3362. * Enable the PHY and wait until completion
  3363. * This includes BaseBand and Synthesizer
  3364. * activation.
  3365. */
  3366. ath5k_hw_reg_write(ah, AR5K_PHY_ACT_ENABLE, AR5K_PHY_ACT);
  3367. ath5k_hw_wait_for_synth(ah, channel);
  3368. /*
  3369. * Perform ADC test to see if baseband is ready
  3370. * Set tx hold and check adc test register
  3371. */
  3372. phy_tst1 = ath5k_hw_reg_read(ah, AR5K_PHY_TST1);
  3373. ath5k_hw_reg_write(ah, AR5K_PHY_TST1_TXHOLD, AR5K_PHY_TST1);
  3374. for (i = 0; i <= 20; i++) {
  3375. if (!(ath5k_hw_reg_read(ah, AR5K_PHY_ADC_TEST) & 0x10))
  3376. break;
  3377. usleep_range(200, 250);
  3378. }
  3379. ath5k_hw_reg_write(ah, phy_tst1, AR5K_PHY_TST1);
  3380. /*
  3381. * Start automatic gain control calibration
  3382. *
  3383. * During AGC calibration RX path is re-routed to
  3384. * a power detector so we don't receive anything.
  3385. *
  3386. * This method is used to calibrate some static offsets
  3387. * used together with on-the fly I/Q calibration (the
  3388. * one performed via ath5k_hw_phy_calibrate), which doesn't
  3389. * interrupt rx path.
  3390. *
  3391. * While rx path is re-routed to the power detector we also
  3392. * start a noise floor calibration to measure the
  3393. * card's noise floor (the noise we measure when we are not
  3394. * transmitting or receiving anything).
  3395. *
  3396. * If we are in a noisy environment, AGC calibration may time
  3397. * out and/or noise floor calibration might timeout.
  3398. */
  3399. AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_AGCCTL,
  3400. AR5K_PHY_AGCCTL_CAL | AR5K_PHY_AGCCTL_NF);
  3401. /* At the same time start I/Q calibration for QAM constellation
  3402. * -no need for CCK- */
  3403. ah->ah_iq_cal_needed = false;
  3404. if (!(mode == AR5K_MODE_11B)) {
  3405. ah->ah_iq_cal_needed = true;
  3406. AR5K_REG_WRITE_BITS(ah, AR5K_PHY_IQ,
  3407. AR5K_PHY_IQ_CAL_NUM_LOG_MAX, 15);
  3408. AR5K_REG_ENABLE_BITS(ah, AR5K_PHY_IQ,
  3409. AR5K_PHY_IQ_RUN);
  3410. }
  3411. /* Wait for gain calibration to finish (we check for I/Q calibration
  3412. * during ath5k_phy_calibrate) */
  3413. if (ath5k_hw_register_timeout(ah, AR5K_PHY_AGCCTL,
  3414. AR5K_PHY_AGCCTL_CAL, 0, false)) {
  3415. ATH5K_ERR(ah, "gain calibration timeout (%uMHz)\n",
  3416. channel->center_freq);
  3417. }
  3418. /* Restore antenna mode */
  3419. ath5k_hw_set_antenna_mode(ah, ah->ah_ant_mode);
  3420. return ret;
  3421. }