phy_cmn.c 71 KB

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  1. /*
  2. * Copyright (c) 2010 Broadcom Corporation
  3. *
  4. * Permission to use, copy, modify, and/or distribute this software for any
  5. * purpose with or without fee is hereby granted, provided that the above
  6. * copyright notice and this permission notice appear in all copies.
  7. *
  8. * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
  9. * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
  10. * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY
  11. * SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
  12. * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION
  13. * OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN
  14. * CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
  15. */
  16. #include <linux/kernel.h>
  17. #include <linux/delay.h>
  18. #include <linux/bitops.h>
  19. #include <brcm_hw_ids.h>
  20. #include <chipcommon.h>
  21. #include <aiutils.h>
  22. #include <d11.h>
  23. #include <phy_shim.h>
  24. #include "phy_hal.h"
  25. #include "phy_int.h"
  26. #include "phy_radio.h"
  27. #include "phy_lcn.h"
  28. #include "phyreg_n.h"
  29. #define VALID_N_RADIO(radioid) ((radioid == BCM2055_ID) || \
  30. (radioid == BCM2056_ID) || \
  31. (radioid == BCM2057_ID))
  32. #define VALID_LCN_RADIO(radioid) (radioid == BCM2064_ID)
  33. #define VALID_RADIO(pi, radioid) ( \
  34. (ISNPHY(pi) ? VALID_N_RADIO(radioid) : false) || \
  35. (ISLCNPHY(pi) ? VALID_LCN_RADIO(radioid) : false))
  36. /* basic mux operation - can be optimized on several architectures */
  37. #define MUX(pred, true, false) ((pred) ? (true) : (false))
  38. /* modulo inc/dec - assumes x E [0, bound - 1] */
  39. #define MODINC(x, bound) MUX((x) == (bound) - 1, 0, (x) + 1)
  40. /* modulo inc/dec, bound = 2^k */
  41. #define MODDEC_POW2(x, bound) (((x) - 1) & ((bound) - 1))
  42. #define MODINC_POW2(x, bound) (((x) + 1) & ((bound) - 1))
  43. struct chan_info_basic {
  44. u16 chan;
  45. u16 freq;
  46. };
  47. static const struct chan_info_basic chan_info_all[] = {
  48. {1, 2412},
  49. {2, 2417},
  50. {3, 2422},
  51. {4, 2427},
  52. {5, 2432},
  53. {6, 2437},
  54. {7, 2442},
  55. {8, 2447},
  56. {9, 2452},
  57. {10, 2457},
  58. {11, 2462},
  59. {12, 2467},
  60. {13, 2472},
  61. {14, 2484},
  62. {34, 5170},
  63. {38, 5190},
  64. {42, 5210},
  65. {46, 5230},
  66. {36, 5180},
  67. {40, 5200},
  68. {44, 5220},
  69. {48, 5240},
  70. {52, 5260},
  71. {56, 5280},
  72. {60, 5300},
  73. {64, 5320},
  74. {100, 5500},
  75. {104, 5520},
  76. {108, 5540},
  77. {112, 5560},
  78. {116, 5580},
  79. {120, 5600},
  80. {124, 5620},
  81. {128, 5640},
  82. {132, 5660},
  83. {136, 5680},
  84. {140, 5700},
  85. {149, 5745},
  86. {153, 5765},
  87. {157, 5785},
  88. {161, 5805},
  89. {165, 5825},
  90. {184, 4920},
  91. {188, 4940},
  92. {192, 4960},
  93. {196, 4980},
  94. {200, 5000},
  95. {204, 5020},
  96. {208, 5040},
  97. {212, 5060},
  98. {216, 5080}
  99. };
  100. static const u8 ofdm_rate_lookup[] = {
  101. BRCM_RATE_48M,
  102. BRCM_RATE_24M,
  103. BRCM_RATE_12M,
  104. BRCM_RATE_6M,
  105. BRCM_RATE_54M,
  106. BRCM_RATE_36M,
  107. BRCM_RATE_18M,
  108. BRCM_RATE_9M
  109. };
  110. #define PHY_WREG_LIMIT 24
  111. void wlc_phyreg_enter(struct brcms_phy_pub *pih)
  112. {
  113. struct brcms_phy *pi = container_of(pih, struct brcms_phy, pubpi_ro);
  114. wlapi_bmac_ucode_wake_override_phyreg_set(pi->sh->physhim);
  115. }
  116. void wlc_phyreg_exit(struct brcms_phy_pub *pih)
  117. {
  118. struct brcms_phy *pi = container_of(pih, struct brcms_phy, pubpi_ro);
  119. wlapi_bmac_ucode_wake_override_phyreg_clear(pi->sh->physhim);
  120. }
  121. void wlc_radioreg_enter(struct brcms_phy_pub *pih)
  122. {
  123. struct brcms_phy *pi = container_of(pih, struct brcms_phy, pubpi_ro);
  124. wlapi_bmac_mctrl(pi->sh->physhim, MCTL_LOCK_RADIO, MCTL_LOCK_RADIO);
  125. udelay(10);
  126. }
  127. void wlc_radioreg_exit(struct brcms_phy_pub *pih)
  128. {
  129. struct brcms_phy *pi = container_of(pih, struct brcms_phy, pubpi_ro);
  130. (void)bcma_read16(pi->d11core, D11REGOFFS(phyversion));
  131. pi->phy_wreg = 0;
  132. wlapi_bmac_mctrl(pi->sh->physhim, MCTL_LOCK_RADIO, 0);
  133. }
  134. u16 read_radio_reg(struct brcms_phy *pi, u16 addr)
  135. {
  136. u16 data;
  137. if ((addr == RADIO_IDCODE))
  138. return 0xffff;
  139. switch (pi->pubpi.phy_type) {
  140. case PHY_TYPE_N:
  141. if (!CONF_HAS(PHYTYPE, PHY_TYPE_N))
  142. break;
  143. if (NREV_GE(pi->pubpi.phy_rev, 7))
  144. addr |= RADIO_2057_READ_OFF;
  145. else
  146. addr |= RADIO_2055_READ_OFF;
  147. break;
  148. case PHY_TYPE_LCN:
  149. if (!CONF_HAS(PHYTYPE, PHY_TYPE_LCN))
  150. break;
  151. addr |= RADIO_2064_READ_OFF;
  152. break;
  153. default:
  154. break;
  155. }
  156. if ((D11REV_GE(pi->sh->corerev, 24)) ||
  157. (D11REV_IS(pi->sh->corerev, 22)
  158. && (pi->pubpi.phy_type != PHY_TYPE_SSN))) {
  159. bcma_wflush16(pi->d11core, D11REGOFFS(radioregaddr), addr);
  160. data = bcma_read16(pi->d11core, D11REGOFFS(radioregdata));
  161. } else {
  162. bcma_wflush16(pi->d11core, D11REGOFFS(phy4waddr), addr);
  163. data = bcma_read16(pi->d11core, D11REGOFFS(phy4wdatalo));
  164. }
  165. pi->phy_wreg = 0;
  166. return data;
  167. }
  168. void write_radio_reg(struct brcms_phy *pi, u16 addr, u16 val)
  169. {
  170. if ((D11REV_GE(pi->sh->corerev, 24)) ||
  171. (D11REV_IS(pi->sh->corerev, 22)
  172. && (pi->pubpi.phy_type != PHY_TYPE_SSN))) {
  173. bcma_wflush16(pi->d11core, D11REGOFFS(radioregaddr), addr);
  174. bcma_write16(pi->d11core, D11REGOFFS(radioregdata), val);
  175. } else {
  176. bcma_wflush16(pi->d11core, D11REGOFFS(phy4waddr), addr);
  177. bcma_write16(pi->d11core, D11REGOFFS(phy4wdatalo), val);
  178. }
  179. if ((pi->d11core->bus->hosttype == BCMA_HOSTTYPE_PCI) &&
  180. (++pi->phy_wreg >= pi->phy_wreg_limit)) {
  181. (void)bcma_read32(pi->d11core, D11REGOFFS(maccontrol));
  182. pi->phy_wreg = 0;
  183. }
  184. }
  185. static u32 read_radio_id(struct brcms_phy *pi)
  186. {
  187. u32 id;
  188. if (D11REV_GE(pi->sh->corerev, 24)) {
  189. u32 b0, b1, b2;
  190. bcma_wflush16(pi->d11core, D11REGOFFS(radioregaddr), 0);
  191. b0 = (u32) bcma_read16(pi->d11core, D11REGOFFS(radioregdata));
  192. bcma_wflush16(pi->d11core, D11REGOFFS(radioregaddr), 1);
  193. b1 = (u32) bcma_read16(pi->d11core, D11REGOFFS(radioregdata));
  194. bcma_wflush16(pi->d11core, D11REGOFFS(radioregaddr), 2);
  195. b2 = (u32) bcma_read16(pi->d11core, D11REGOFFS(radioregdata));
  196. id = ((b0 & 0xf) << 28) | (((b2 << 8) | b1) << 12) | ((b0 >> 4)
  197. & 0xf);
  198. } else {
  199. bcma_wflush16(pi->d11core, D11REGOFFS(phy4waddr), RADIO_IDCODE);
  200. id = (u32) bcma_read16(pi->d11core, D11REGOFFS(phy4wdatalo));
  201. id |= (u32) bcma_read16(pi->d11core,
  202. D11REGOFFS(phy4wdatahi)) << 16;
  203. }
  204. pi->phy_wreg = 0;
  205. return id;
  206. }
  207. void and_radio_reg(struct brcms_phy *pi, u16 addr, u16 val)
  208. {
  209. u16 rval;
  210. rval = read_radio_reg(pi, addr);
  211. write_radio_reg(pi, addr, (rval & val));
  212. }
  213. void or_radio_reg(struct brcms_phy *pi, u16 addr, u16 val)
  214. {
  215. u16 rval;
  216. rval = read_radio_reg(pi, addr);
  217. write_radio_reg(pi, addr, (rval | val));
  218. }
  219. void xor_radio_reg(struct brcms_phy *pi, u16 addr, u16 mask)
  220. {
  221. u16 rval;
  222. rval = read_radio_reg(pi, addr);
  223. write_radio_reg(pi, addr, (rval ^ mask));
  224. }
  225. void mod_radio_reg(struct brcms_phy *pi, u16 addr, u16 mask, u16 val)
  226. {
  227. u16 rval;
  228. rval = read_radio_reg(pi, addr);
  229. write_radio_reg(pi, addr, (rval & ~mask) | (val & mask));
  230. }
  231. void write_phy_channel_reg(struct brcms_phy *pi, uint val)
  232. {
  233. bcma_write16(pi->d11core, D11REGOFFS(phychannel), val);
  234. }
  235. u16 read_phy_reg(struct brcms_phy *pi, u16 addr)
  236. {
  237. bcma_wflush16(pi->d11core, D11REGOFFS(phyregaddr), addr);
  238. pi->phy_wreg = 0;
  239. return bcma_read16(pi->d11core, D11REGOFFS(phyregdata));
  240. }
  241. void write_phy_reg(struct brcms_phy *pi, u16 addr, u16 val)
  242. {
  243. #ifdef CONFIG_BCM47XX
  244. bcma_wflush16(pi->d11core, D11REGOFFS(phyregaddr), addr);
  245. bcma_write16(pi->d11core, D11REGOFFS(phyregdata), val);
  246. if (addr == 0x72)
  247. (void)bcma_read16(pi->d11core, D11REGOFFS(phyregdata));
  248. #else
  249. bcma_write32(pi->d11core, D11REGOFFS(phyregaddr), addr | (val << 16));
  250. if ((pi->d11core->bus->hosttype == BCMA_HOSTTYPE_PCI) &&
  251. (++pi->phy_wreg >= pi->phy_wreg_limit)) {
  252. pi->phy_wreg = 0;
  253. (void)bcma_read16(pi->d11core, D11REGOFFS(phyversion));
  254. }
  255. #endif
  256. }
  257. void and_phy_reg(struct brcms_phy *pi, u16 addr, u16 val)
  258. {
  259. bcma_wflush16(pi->d11core, D11REGOFFS(phyregaddr), addr);
  260. bcma_mask16(pi->d11core, D11REGOFFS(phyregdata), val);
  261. pi->phy_wreg = 0;
  262. }
  263. void or_phy_reg(struct brcms_phy *pi, u16 addr, u16 val)
  264. {
  265. bcma_wflush16(pi->d11core, D11REGOFFS(phyregaddr), addr);
  266. bcma_set16(pi->d11core, D11REGOFFS(phyregdata), val);
  267. pi->phy_wreg = 0;
  268. }
  269. void mod_phy_reg(struct brcms_phy *pi, u16 addr, u16 mask, u16 val)
  270. {
  271. val &= mask;
  272. bcma_wflush16(pi->d11core, D11REGOFFS(phyregaddr), addr);
  273. bcma_maskset16(pi->d11core, D11REGOFFS(phyregdata), ~mask, val);
  274. pi->phy_wreg = 0;
  275. }
  276. static void wlc_set_phy_uninitted(struct brcms_phy *pi)
  277. {
  278. int i, j;
  279. pi->initialized = false;
  280. pi->tx_vos = 0xffff;
  281. pi->nrssi_table_delta = 0x7fffffff;
  282. pi->rc_cal = 0xffff;
  283. pi->mintxbias = 0xffff;
  284. pi->txpwridx = -1;
  285. if (ISNPHY(pi)) {
  286. pi->phy_spuravoid = SPURAVOID_DISABLE;
  287. if (NREV_GE(pi->pubpi.phy_rev, 3)
  288. && NREV_LT(pi->pubpi.phy_rev, 7))
  289. pi->phy_spuravoid = SPURAVOID_AUTO;
  290. pi->nphy_papd_skip = 0;
  291. pi->nphy_papd_epsilon_offset[0] = 0xf588;
  292. pi->nphy_papd_epsilon_offset[1] = 0xf588;
  293. pi->nphy_txpwr_idx[0] = 128;
  294. pi->nphy_txpwr_idx[1] = 128;
  295. pi->nphy_txpwrindex[0].index_internal = 40;
  296. pi->nphy_txpwrindex[1].index_internal = 40;
  297. pi->phy_pabias = 0;
  298. } else {
  299. pi->phy_spuravoid = SPURAVOID_AUTO;
  300. }
  301. pi->radiopwr = 0xffff;
  302. for (i = 0; i < STATIC_NUM_RF; i++) {
  303. for (j = 0; j < STATIC_NUM_BB; j++)
  304. pi->stats_11b_txpower[i][j] = -1;
  305. }
  306. }
  307. struct shared_phy *wlc_phy_shared_attach(struct shared_phy_params *shp)
  308. {
  309. struct shared_phy *sh;
  310. sh = kzalloc(sizeof(struct shared_phy), GFP_ATOMIC);
  311. if (sh == NULL)
  312. return NULL;
  313. sh->physhim = shp->physhim;
  314. sh->unit = shp->unit;
  315. sh->corerev = shp->corerev;
  316. sh->vid = shp->vid;
  317. sh->did = shp->did;
  318. sh->chip = shp->chip;
  319. sh->chiprev = shp->chiprev;
  320. sh->chippkg = shp->chippkg;
  321. sh->sromrev = shp->sromrev;
  322. sh->boardtype = shp->boardtype;
  323. sh->boardrev = shp->boardrev;
  324. sh->boardflags = shp->boardflags;
  325. sh->boardflags2 = shp->boardflags2;
  326. sh->fast_timer = PHY_SW_TIMER_FAST;
  327. sh->slow_timer = PHY_SW_TIMER_SLOW;
  328. sh->glacial_timer = PHY_SW_TIMER_GLACIAL;
  329. sh->rssi_mode = RSSI_ANT_MERGE_MAX;
  330. return sh;
  331. }
  332. static void wlc_phy_timercb_phycal(struct brcms_phy *pi)
  333. {
  334. uint delay = 5;
  335. if (PHY_PERICAL_MPHASE_PENDING(pi)) {
  336. if (!pi->sh->up) {
  337. wlc_phy_cal_perical_mphase_reset(pi);
  338. return;
  339. }
  340. if (SCAN_RM_IN_PROGRESS(pi) || PLT_INPROG_PHY(pi)) {
  341. delay = 1000;
  342. wlc_phy_cal_perical_mphase_restart(pi);
  343. } else
  344. wlc_phy_cal_perical_nphy_run(pi, PHY_PERICAL_AUTO);
  345. wlapi_add_timer(pi->phycal_timer, delay, 0);
  346. return;
  347. }
  348. }
  349. static u32 wlc_phy_get_radio_ver(struct brcms_phy *pi)
  350. {
  351. u32 ver;
  352. ver = read_radio_id(pi);
  353. return ver;
  354. }
  355. struct brcms_phy_pub *
  356. wlc_phy_attach(struct shared_phy *sh, struct bcma_device *d11core,
  357. int bandtype, struct wiphy *wiphy)
  358. {
  359. struct brcms_phy *pi;
  360. u32 sflags = 0;
  361. uint phyversion;
  362. u32 idcode;
  363. int i;
  364. if (D11REV_IS(sh->corerev, 4))
  365. sflags = SISF_2G_PHY | SISF_5G_PHY;
  366. else
  367. sflags = bcma_aread32(d11core, BCMA_IOST);
  368. if (bandtype == BRCM_BAND_5G) {
  369. if ((sflags & (SISF_5G_PHY | SISF_DB_PHY)) == 0)
  370. return NULL;
  371. }
  372. pi = sh->phy_head;
  373. if ((sflags & SISF_DB_PHY) && pi) {
  374. wlapi_bmac_corereset(pi->sh->physhim, pi->pubpi.coreflags);
  375. pi->refcnt++;
  376. return &pi->pubpi_ro;
  377. }
  378. pi = kzalloc(sizeof(struct brcms_phy), GFP_ATOMIC);
  379. if (pi == NULL)
  380. return NULL;
  381. pi->wiphy = wiphy;
  382. pi->d11core = d11core;
  383. pi->sh = sh;
  384. pi->phy_init_por = true;
  385. pi->phy_wreg_limit = PHY_WREG_LIMIT;
  386. pi->txpwr_percent = 100;
  387. pi->do_initcal = true;
  388. pi->phycal_tempdelta = 0;
  389. if (bandtype == BRCM_BAND_2G && (sflags & SISF_2G_PHY))
  390. pi->pubpi.coreflags = SICF_GMODE;
  391. wlapi_bmac_corereset(pi->sh->physhim, pi->pubpi.coreflags);
  392. phyversion = bcma_read16(pi->d11core, D11REGOFFS(phyversion));
  393. pi->pubpi.phy_type = PHY_TYPE(phyversion);
  394. pi->pubpi.phy_rev = phyversion & PV_PV_MASK;
  395. if (pi->pubpi.phy_type == PHY_TYPE_LCNXN) {
  396. pi->pubpi.phy_type = PHY_TYPE_N;
  397. pi->pubpi.phy_rev += LCNXN_BASEREV;
  398. }
  399. pi->pubpi.phy_corenum = PHY_CORE_NUM_2;
  400. pi->pubpi.ana_rev = (phyversion & PV_AV_MASK) >> PV_AV_SHIFT;
  401. if (pi->pubpi.phy_type != PHY_TYPE_N &&
  402. pi->pubpi.phy_type != PHY_TYPE_LCN)
  403. goto err;
  404. if (bandtype == BRCM_BAND_5G) {
  405. if (!ISNPHY(pi))
  406. goto err;
  407. } else if (!ISNPHY(pi) && !ISLCNPHY(pi)) {
  408. goto err;
  409. }
  410. wlc_phy_anacore((struct brcms_phy_pub *) pi, ON);
  411. idcode = wlc_phy_get_radio_ver(pi);
  412. pi->pubpi.radioid =
  413. (idcode & IDCODE_ID_MASK) >> IDCODE_ID_SHIFT;
  414. pi->pubpi.radiorev =
  415. (idcode & IDCODE_REV_MASK) >> IDCODE_REV_SHIFT;
  416. pi->pubpi.radiover =
  417. (idcode & IDCODE_VER_MASK) >> IDCODE_VER_SHIFT;
  418. if (!VALID_RADIO(pi, pi->pubpi.radioid))
  419. goto err;
  420. wlc_phy_switch_radio((struct brcms_phy_pub *) pi, OFF);
  421. wlc_set_phy_uninitted(pi);
  422. pi->bw = WL_CHANSPEC_BW_20;
  423. pi->radio_chanspec = (bandtype == BRCM_BAND_2G) ?
  424. ch20mhz_chspec(1) : ch20mhz_chspec(36);
  425. pi->rxiq_samps = PHY_NOISE_SAMPLE_LOG_NUM_NPHY;
  426. pi->rxiq_antsel = ANT_RX_DIV_DEF;
  427. pi->watchdog_override = true;
  428. pi->cal_type_override = PHY_PERICAL_AUTO;
  429. pi->nphy_saved_noisevars.bufcount = 0;
  430. if (ISNPHY(pi))
  431. pi->min_txpower = PHY_TXPWR_MIN_NPHY;
  432. else
  433. pi->min_txpower = PHY_TXPWR_MIN;
  434. pi->sh->phyrxchain = 0x3;
  435. pi->rx2tx_biasentry = -1;
  436. pi->phy_txcore_disable_temp = PHY_CHAIN_TX_DISABLE_TEMP;
  437. pi->phy_txcore_enable_temp =
  438. PHY_CHAIN_TX_DISABLE_TEMP - PHY_HYSTERESIS_DELTATEMP;
  439. pi->phy_tempsense_offset = 0;
  440. pi->phy_txcore_heatedup = false;
  441. pi->nphy_lastcal_temp = -50;
  442. pi->phynoise_polling = true;
  443. if (ISNPHY(pi) || ISLCNPHY(pi))
  444. pi->phynoise_polling = false;
  445. for (i = 0; i < TXP_NUM_RATES; i++) {
  446. pi->txpwr_limit[i] = BRCMS_TXPWR_MAX;
  447. pi->txpwr_env_limit[i] = BRCMS_TXPWR_MAX;
  448. pi->tx_user_target[i] = BRCMS_TXPWR_MAX;
  449. }
  450. pi->radiopwr_override = RADIOPWR_OVERRIDE_DEF;
  451. pi->user_txpwr_at_rfport = false;
  452. if (ISNPHY(pi)) {
  453. pi->phycal_timer = wlapi_init_timer(pi->sh->physhim,
  454. wlc_phy_timercb_phycal,
  455. pi, "phycal");
  456. if (!pi->phycal_timer)
  457. goto err;
  458. if (!wlc_phy_attach_nphy(pi))
  459. goto err;
  460. } else if (ISLCNPHY(pi)) {
  461. if (!wlc_phy_attach_lcnphy(pi))
  462. goto err;
  463. }
  464. pi->refcnt++;
  465. pi->next = pi->sh->phy_head;
  466. sh->phy_head = pi;
  467. memcpy(&pi->pubpi_ro, &pi->pubpi, sizeof(struct brcms_phy_pub));
  468. return &pi->pubpi_ro;
  469. err:
  470. kfree(pi);
  471. return NULL;
  472. }
  473. void wlc_phy_detach(struct brcms_phy_pub *pih)
  474. {
  475. struct brcms_phy *pi = container_of(pih, struct brcms_phy, pubpi_ro);
  476. if (pih) {
  477. if (--pi->refcnt)
  478. return;
  479. if (pi->phycal_timer) {
  480. wlapi_free_timer(pi->phycal_timer);
  481. pi->phycal_timer = NULL;
  482. }
  483. if (pi->sh->phy_head == pi)
  484. pi->sh->phy_head = pi->next;
  485. else if (pi->sh->phy_head->next == pi)
  486. pi->sh->phy_head->next = NULL;
  487. if (pi->pi_fptr.detach)
  488. (pi->pi_fptr.detach)(pi);
  489. kfree(pi);
  490. }
  491. }
  492. bool
  493. wlc_phy_get_phyversion(struct brcms_phy_pub *pih, u16 *phytype, u16 *phyrev,
  494. u16 *radioid, u16 *radiover)
  495. {
  496. struct brcms_phy *pi = container_of(pih, struct brcms_phy, pubpi_ro);
  497. *phytype = (u16) pi->pubpi.phy_type;
  498. *phyrev = (u16) pi->pubpi.phy_rev;
  499. *radioid = pi->pubpi.radioid;
  500. *radiover = pi->pubpi.radiorev;
  501. return true;
  502. }
  503. bool wlc_phy_get_encore(struct brcms_phy_pub *pih)
  504. {
  505. struct brcms_phy *pi = container_of(pih, struct brcms_phy, pubpi_ro);
  506. return pi->pubpi.abgphy_encore;
  507. }
  508. u32 wlc_phy_get_coreflags(struct brcms_phy_pub *pih)
  509. {
  510. struct brcms_phy *pi = container_of(pih, struct brcms_phy, pubpi_ro);
  511. return pi->pubpi.coreflags;
  512. }
  513. void wlc_phy_anacore(struct brcms_phy_pub *pih, bool on)
  514. {
  515. struct brcms_phy *pi = container_of(pih, struct brcms_phy, pubpi_ro);
  516. if (ISNPHY(pi)) {
  517. if (on) {
  518. if (NREV_GE(pi->pubpi.phy_rev, 3)) {
  519. write_phy_reg(pi, 0xa6, 0x0d);
  520. write_phy_reg(pi, 0x8f, 0x0);
  521. write_phy_reg(pi, 0xa7, 0x0d);
  522. write_phy_reg(pi, 0xa5, 0x0);
  523. } else {
  524. write_phy_reg(pi, 0xa5, 0x0);
  525. }
  526. } else {
  527. if (NREV_GE(pi->pubpi.phy_rev, 3)) {
  528. write_phy_reg(pi, 0x8f, 0x07ff);
  529. write_phy_reg(pi, 0xa6, 0x0fd);
  530. write_phy_reg(pi, 0xa5, 0x07ff);
  531. write_phy_reg(pi, 0xa7, 0x0fd);
  532. } else {
  533. write_phy_reg(pi, 0xa5, 0x7fff);
  534. }
  535. }
  536. } else if (ISLCNPHY(pi)) {
  537. if (on) {
  538. and_phy_reg(pi, 0x43b,
  539. ~((0x1 << 0) | (0x1 << 1) | (0x1 << 2)));
  540. } else {
  541. or_phy_reg(pi, 0x43c,
  542. (0x1 << 0) | (0x1 << 1) | (0x1 << 2));
  543. or_phy_reg(pi, 0x43b,
  544. (0x1 << 0) | (0x1 << 1) | (0x1 << 2));
  545. }
  546. }
  547. }
  548. u32 wlc_phy_clk_bwbits(struct brcms_phy_pub *pih)
  549. {
  550. struct brcms_phy *pi = container_of(pih, struct brcms_phy, pubpi_ro);
  551. u32 phy_bw_clkbits = 0;
  552. if (pi && (ISNPHY(pi) || ISLCNPHY(pi))) {
  553. switch (pi->bw) {
  554. case WL_CHANSPEC_BW_10:
  555. phy_bw_clkbits = SICF_BW10;
  556. break;
  557. case WL_CHANSPEC_BW_20:
  558. phy_bw_clkbits = SICF_BW20;
  559. break;
  560. case WL_CHANSPEC_BW_40:
  561. phy_bw_clkbits = SICF_BW40;
  562. break;
  563. default:
  564. break;
  565. }
  566. }
  567. return phy_bw_clkbits;
  568. }
  569. void wlc_phy_por_inform(struct brcms_phy_pub *ppi)
  570. {
  571. struct brcms_phy *pi = container_of(ppi, struct brcms_phy, pubpi_ro);
  572. pi->phy_init_por = true;
  573. }
  574. void wlc_phy_edcrs_lock(struct brcms_phy_pub *pih, bool lock)
  575. {
  576. struct brcms_phy *pi = container_of(pih, struct brcms_phy, pubpi_ro);
  577. pi->edcrs_threshold_lock = lock;
  578. write_phy_reg(pi, 0x22c, 0x46b);
  579. write_phy_reg(pi, 0x22d, 0x46b);
  580. write_phy_reg(pi, 0x22e, 0x3c0);
  581. write_phy_reg(pi, 0x22f, 0x3c0);
  582. }
  583. void wlc_phy_initcal_enable(struct brcms_phy_pub *pih, bool initcal)
  584. {
  585. struct brcms_phy *pi = container_of(pih, struct brcms_phy, pubpi_ro);
  586. pi->do_initcal = initcal;
  587. }
  588. void wlc_phy_hw_clk_state_upd(struct brcms_phy_pub *pih, bool newstate)
  589. {
  590. struct brcms_phy *pi = container_of(pih, struct brcms_phy, pubpi_ro);
  591. if (!pi || !pi->sh)
  592. return;
  593. pi->sh->clk = newstate;
  594. }
  595. void wlc_phy_hw_state_upd(struct brcms_phy_pub *pih, bool newstate)
  596. {
  597. struct brcms_phy *pi = container_of(pih, struct brcms_phy, pubpi_ro);
  598. if (!pi || !pi->sh)
  599. return;
  600. pi->sh->up = newstate;
  601. }
  602. void wlc_phy_init(struct brcms_phy_pub *pih, u16 chanspec)
  603. {
  604. u32 mc;
  605. void (*phy_init)(struct brcms_phy *) = NULL;
  606. struct brcms_phy *pi = container_of(pih, struct brcms_phy, pubpi_ro);
  607. if (pi->init_in_progress)
  608. return;
  609. pi->init_in_progress = true;
  610. pi->radio_chanspec = chanspec;
  611. mc = bcma_read32(pi->d11core, D11REGOFFS(maccontrol));
  612. if (WARN(mc & MCTL_EN_MAC, "HW error MAC running on init"))
  613. return;
  614. if (!(pi->measure_hold & PHY_HOLD_FOR_SCAN))
  615. pi->measure_hold |= PHY_HOLD_FOR_NOT_ASSOC;
  616. if (WARN(!(bcma_aread32(pi->d11core, BCMA_IOST) & SISF_FCLKA),
  617. "HW error SISF_FCLKA\n"))
  618. return;
  619. phy_init = pi->pi_fptr.init;
  620. if (phy_init == NULL)
  621. return;
  622. wlc_phy_anacore(pih, ON);
  623. if (CHSPEC_BW(pi->radio_chanspec) != pi->bw)
  624. wlapi_bmac_bw_set(pi->sh->physhim,
  625. CHSPEC_BW(pi->radio_chanspec));
  626. pi->nphy_gain_boost = true;
  627. wlc_phy_switch_radio((struct brcms_phy_pub *) pi, ON);
  628. (*phy_init)(pi);
  629. pi->phy_init_por = false;
  630. if (D11REV_IS(pi->sh->corerev, 11) || D11REV_IS(pi->sh->corerev, 12))
  631. wlc_phy_do_dummy_tx(pi, true, OFF);
  632. if (!(ISNPHY(pi)))
  633. wlc_phy_txpower_update_shm(pi);
  634. wlc_phy_ant_rxdiv_set((struct brcms_phy_pub *) pi, pi->sh->rx_antdiv);
  635. pi->init_in_progress = false;
  636. }
  637. void wlc_phy_cal_init(struct brcms_phy_pub *pih)
  638. {
  639. struct brcms_phy *pi = container_of(pih, struct brcms_phy, pubpi_ro);
  640. void (*cal_init)(struct brcms_phy *) = NULL;
  641. if (WARN((bcma_read32(pi->d11core, D11REGOFFS(maccontrol)) &
  642. MCTL_EN_MAC) != 0, "HW error: MAC enabled during phy cal\n"))
  643. return;
  644. if (!pi->initialized) {
  645. cal_init = pi->pi_fptr.calinit;
  646. if (cal_init)
  647. (*cal_init)(pi);
  648. pi->initialized = true;
  649. }
  650. }
  651. int wlc_phy_down(struct brcms_phy_pub *pih)
  652. {
  653. struct brcms_phy *pi = container_of(pih, struct brcms_phy, pubpi_ro);
  654. int callbacks = 0;
  655. if (pi->phycal_timer
  656. && !wlapi_del_timer(pi->phycal_timer))
  657. callbacks++;
  658. pi->nphy_iqcal_chanspec_2G = 0;
  659. pi->nphy_iqcal_chanspec_5G = 0;
  660. return callbacks;
  661. }
  662. void
  663. wlc_phy_table_addr(struct brcms_phy *pi, uint tbl_id, uint tbl_offset,
  664. u16 tblAddr, u16 tblDataHi, u16 tblDataLo)
  665. {
  666. write_phy_reg(pi, tblAddr, (tbl_id << 10) | tbl_offset);
  667. pi->tbl_data_hi = tblDataHi;
  668. pi->tbl_data_lo = tblDataLo;
  669. if (pi->sh->chip == BCMA_CHIP_ID_BCM43224 &&
  670. pi->sh->chiprev == 1) {
  671. pi->tbl_addr = tblAddr;
  672. pi->tbl_save_id = tbl_id;
  673. pi->tbl_save_offset = tbl_offset;
  674. }
  675. }
  676. void wlc_phy_table_data_write(struct brcms_phy *pi, uint width, u32 val)
  677. {
  678. if ((pi->sh->chip == BCMA_CHIP_ID_BCM43224) &&
  679. (pi->sh->chiprev == 1) &&
  680. (pi->tbl_save_id == NPHY_TBL_ID_ANTSWCTRLLUT)) {
  681. read_phy_reg(pi, pi->tbl_data_lo);
  682. write_phy_reg(pi, pi->tbl_addr,
  683. (pi->tbl_save_id << 10) | pi->tbl_save_offset);
  684. pi->tbl_save_offset++;
  685. }
  686. if (width == 32) {
  687. write_phy_reg(pi, pi->tbl_data_hi, (u16) (val >> 16));
  688. write_phy_reg(pi, pi->tbl_data_lo, (u16) val);
  689. } else {
  690. write_phy_reg(pi, pi->tbl_data_lo, (u16) val);
  691. }
  692. }
  693. void
  694. wlc_phy_write_table(struct brcms_phy *pi, const struct phytbl_info *ptbl_info,
  695. u16 tblAddr, u16 tblDataHi, u16 tblDataLo)
  696. {
  697. uint idx;
  698. uint tbl_id = ptbl_info->tbl_id;
  699. uint tbl_offset = ptbl_info->tbl_offset;
  700. uint tbl_width = ptbl_info->tbl_width;
  701. const u8 *ptbl_8b = (const u8 *)ptbl_info->tbl_ptr;
  702. const u16 *ptbl_16b = (const u16 *)ptbl_info->tbl_ptr;
  703. const u32 *ptbl_32b = (const u32 *)ptbl_info->tbl_ptr;
  704. write_phy_reg(pi, tblAddr, (tbl_id << 10) | tbl_offset);
  705. for (idx = 0; idx < ptbl_info->tbl_len; idx++) {
  706. if ((pi->sh->chip == BCMA_CHIP_ID_BCM43224) &&
  707. (pi->sh->chiprev == 1) &&
  708. (tbl_id == NPHY_TBL_ID_ANTSWCTRLLUT)) {
  709. read_phy_reg(pi, tblDataLo);
  710. write_phy_reg(pi, tblAddr,
  711. (tbl_id << 10) | (tbl_offset + idx));
  712. }
  713. if (tbl_width == 32) {
  714. write_phy_reg(pi, tblDataHi,
  715. (u16) (ptbl_32b[idx] >> 16));
  716. write_phy_reg(pi, tblDataLo, (u16) ptbl_32b[idx]);
  717. } else if (tbl_width == 16) {
  718. write_phy_reg(pi, tblDataLo, ptbl_16b[idx]);
  719. } else {
  720. write_phy_reg(pi, tblDataLo, ptbl_8b[idx]);
  721. }
  722. }
  723. }
  724. void
  725. wlc_phy_read_table(struct brcms_phy *pi, const struct phytbl_info *ptbl_info,
  726. u16 tblAddr, u16 tblDataHi, u16 tblDataLo)
  727. {
  728. uint idx;
  729. uint tbl_id = ptbl_info->tbl_id;
  730. uint tbl_offset = ptbl_info->tbl_offset;
  731. uint tbl_width = ptbl_info->tbl_width;
  732. u8 *ptbl_8b = (u8 *)ptbl_info->tbl_ptr;
  733. u16 *ptbl_16b = (u16 *)ptbl_info->tbl_ptr;
  734. u32 *ptbl_32b = (u32 *)ptbl_info->tbl_ptr;
  735. write_phy_reg(pi, tblAddr, (tbl_id << 10) | tbl_offset);
  736. for (idx = 0; idx < ptbl_info->tbl_len; idx++) {
  737. if ((pi->sh->chip == BCMA_CHIP_ID_BCM43224) &&
  738. (pi->sh->chiprev == 1)) {
  739. (void)read_phy_reg(pi, tblDataLo);
  740. write_phy_reg(pi, tblAddr,
  741. (tbl_id << 10) | (tbl_offset + idx));
  742. }
  743. if (tbl_width == 32) {
  744. ptbl_32b[idx] = read_phy_reg(pi, tblDataLo);
  745. ptbl_32b[idx] |= (read_phy_reg(pi, tblDataHi) << 16);
  746. } else if (tbl_width == 16) {
  747. ptbl_16b[idx] = read_phy_reg(pi, tblDataLo);
  748. } else {
  749. ptbl_8b[idx] = (u8) read_phy_reg(pi, tblDataLo);
  750. }
  751. }
  752. }
  753. uint
  754. wlc_phy_init_radio_regs_allbands(struct brcms_phy *pi,
  755. struct radio_20xx_regs *radioregs)
  756. {
  757. uint i = 0;
  758. do {
  759. if (radioregs[i].do_init)
  760. write_radio_reg(pi, radioregs[i].address,
  761. (u16) radioregs[i].init);
  762. i++;
  763. } while (radioregs[i].address != 0xffff);
  764. return i;
  765. }
  766. uint
  767. wlc_phy_init_radio_regs(struct brcms_phy *pi,
  768. const struct radio_regs *radioregs,
  769. u16 core_offset)
  770. {
  771. uint i = 0;
  772. uint count = 0;
  773. do {
  774. if (CHSPEC_IS5G(pi->radio_chanspec)) {
  775. if (radioregs[i].do_init_a) {
  776. write_radio_reg(pi,
  777. radioregs[i].
  778. address | core_offset,
  779. (u16) radioregs[i].init_a);
  780. if (ISNPHY(pi) && (++count % 4 == 0))
  781. BRCMS_PHY_WAR_PR51571(pi);
  782. }
  783. } else {
  784. if (radioregs[i].do_init_g) {
  785. write_radio_reg(pi,
  786. radioregs[i].
  787. address | core_offset,
  788. (u16) radioregs[i].init_g);
  789. if (ISNPHY(pi) && (++count % 4 == 0))
  790. BRCMS_PHY_WAR_PR51571(pi);
  791. }
  792. }
  793. i++;
  794. } while (radioregs[i].address != 0xffff);
  795. return i;
  796. }
  797. void wlc_phy_do_dummy_tx(struct brcms_phy *pi, bool ofdm, bool pa_on)
  798. {
  799. #define DUMMY_PKT_LEN 20
  800. struct bcma_device *core = pi->d11core;
  801. int i, count;
  802. u8 ofdmpkt[DUMMY_PKT_LEN] = {
  803. 0xcc, 0x01, 0x02, 0x00, 0x00, 0x00, 0xd4, 0x00, 0x00, 0x00,
  804. 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00
  805. };
  806. u8 cckpkt[DUMMY_PKT_LEN] = {
  807. 0x6e, 0x84, 0x0b, 0x00, 0x00, 0x00, 0xd4, 0x00, 0x00, 0x00,
  808. 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00
  809. };
  810. u32 *dummypkt;
  811. dummypkt = (u32 *) (ofdm ? ofdmpkt : cckpkt);
  812. wlapi_bmac_write_template_ram(pi->sh->physhim, 0, DUMMY_PKT_LEN,
  813. dummypkt);
  814. bcma_write16(core, D11REGOFFS(xmtsel), 0);
  815. if (D11REV_GE(pi->sh->corerev, 11))
  816. bcma_write16(core, D11REGOFFS(wepctl), 0x100);
  817. else
  818. bcma_write16(core, D11REGOFFS(wepctl), 0);
  819. bcma_write16(core, D11REGOFFS(txe_phyctl),
  820. (ofdm ? 1 : 0) | PHY_TXC_ANT_0);
  821. if (ISNPHY(pi) || ISLCNPHY(pi))
  822. bcma_write16(core, D11REGOFFS(txe_phyctl1), 0x1A02);
  823. bcma_write16(core, D11REGOFFS(txe_wm_0), 0);
  824. bcma_write16(core, D11REGOFFS(txe_wm_1), 0);
  825. bcma_write16(core, D11REGOFFS(xmttplatetxptr), 0);
  826. bcma_write16(core, D11REGOFFS(xmttxcnt), DUMMY_PKT_LEN);
  827. bcma_write16(core, D11REGOFFS(xmtsel),
  828. ((8 << 8) | (1 << 5) | (1 << 2) | 2));
  829. bcma_write16(core, D11REGOFFS(txe_ctl), 0);
  830. if (!pa_on) {
  831. if (ISNPHY(pi))
  832. wlc_phy_pa_override_nphy(pi, OFF);
  833. }
  834. if (ISNPHY(pi) || ISLCNPHY(pi))
  835. bcma_write16(core, D11REGOFFS(txe_aux), 0xD0);
  836. else
  837. bcma_write16(core, D11REGOFFS(txe_aux), ((1 << 5) | (1 << 4)));
  838. (void)bcma_read16(core, D11REGOFFS(txe_aux));
  839. i = 0;
  840. count = ofdm ? 30 : 250;
  841. while ((i++ < count)
  842. && (bcma_read16(core, D11REGOFFS(txe_status)) & (1 << 7)))
  843. udelay(10);
  844. i = 0;
  845. while ((i++ < 10) &&
  846. ((bcma_read16(core, D11REGOFFS(txe_status)) & (1 << 10)) == 0))
  847. udelay(10);
  848. i = 0;
  849. while ((i++ < 10) &&
  850. ((bcma_read16(core, D11REGOFFS(ifsstat)) & (1 << 8))))
  851. udelay(10);
  852. if (!pa_on) {
  853. if (ISNPHY(pi))
  854. wlc_phy_pa_override_nphy(pi, ON);
  855. }
  856. }
  857. void wlc_phy_hold_upd(struct brcms_phy_pub *pih, u32 id, bool set)
  858. {
  859. struct brcms_phy *pi = container_of(pih, struct brcms_phy, pubpi_ro);
  860. if (set)
  861. mboolset(pi->measure_hold, id);
  862. else
  863. mboolclr(pi->measure_hold, id);
  864. return;
  865. }
  866. void wlc_phy_mute_upd(struct brcms_phy_pub *pih, bool mute, u32 flags)
  867. {
  868. struct brcms_phy *pi = container_of(pih, struct brcms_phy, pubpi_ro);
  869. if (mute)
  870. mboolset(pi->measure_hold, PHY_HOLD_FOR_MUTE);
  871. else
  872. mboolclr(pi->measure_hold, PHY_HOLD_FOR_MUTE);
  873. if (!mute && (flags & PHY_MUTE_FOR_PREISM))
  874. pi->nphy_perical_last = pi->sh->now - pi->sh->glacial_timer;
  875. return;
  876. }
  877. void wlc_phy_clear_tssi(struct brcms_phy_pub *pih)
  878. {
  879. struct brcms_phy *pi = container_of(pih, struct brcms_phy, pubpi_ro);
  880. if (ISNPHY(pi)) {
  881. return;
  882. } else {
  883. wlapi_bmac_write_shm(pi->sh->physhim, M_B_TSSI_0, NULL_TSSI_W);
  884. wlapi_bmac_write_shm(pi->sh->physhim, M_B_TSSI_1, NULL_TSSI_W);
  885. wlapi_bmac_write_shm(pi->sh->physhim, M_G_TSSI_0, NULL_TSSI_W);
  886. wlapi_bmac_write_shm(pi->sh->physhim, M_G_TSSI_1, NULL_TSSI_W);
  887. }
  888. }
  889. static bool wlc_phy_cal_txpower_recalc_sw(struct brcms_phy *pi)
  890. {
  891. return false;
  892. }
  893. void wlc_phy_switch_radio(struct brcms_phy_pub *pih, bool on)
  894. {
  895. struct brcms_phy *pi = container_of(pih, struct brcms_phy, pubpi_ro);
  896. (void)bcma_read32(pi->d11core, D11REGOFFS(maccontrol));
  897. if (ISNPHY(pi)) {
  898. wlc_phy_switch_radio_nphy(pi, on);
  899. } else if (ISLCNPHY(pi)) {
  900. if (on) {
  901. and_phy_reg(pi, 0x44c,
  902. ~((0x1 << 8) |
  903. (0x1 << 9) |
  904. (0x1 << 10) | (0x1 << 11) | (0x1 << 12)));
  905. and_phy_reg(pi, 0x4b0, ~((0x1 << 3) | (0x1 << 11)));
  906. and_phy_reg(pi, 0x4f9, ~(0x1 << 3));
  907. } else {
  908. and_phy_reg(pi, 0x44d,
  909. ~((0x1 << 10) |
  910. (0x1 << 11) |
  911. (0x1 << 12) | (0x1 << 13) | (0x1 << 14)));
  912. or_phy_reg(pi, 0x44c,
  913. (0x1 << 8) |
  914. (0x1 << 9) |
  915. (0x1 << 10) | (0x1 << 11) | (0x1 << 12));
  916. and_phy_reg(pi, 0x4b7, ~((0x7f << 8)));
  917. and_phy_reg(pi, 0x4b1, ~((0x1 << 13)));
  918. or_phy_reg(pi, 0x4b0, (0x1 << 3) | (0x1 << 11));
  919. and_phy_reg(pi, 0x4fa, ~((0x1 << 3)));
  920. or_phy_reg(pi, 0x4f9, (0x1 << 3));
  921. }
  922. }
  923. }
  924. u16 wlc_phy_bw_state_get(struct brcms_phy_pub *ppi)
  925. {
  926. struct brcms_phy *pi = container_of(ppi, struct brcms_phy, pubpi_ro);
  927. return pi->bw;
  928. }
  929. void wlc_phy_bw_state_set(struct brcms_phy_pub *ppi, u16 bw)
  930. {
  931. struct brcms_phy *pi = container_of(ppi, struct brcms_phy, pubpi_ro);
  932. pi->bw = bw;
  933. }
  934. void wlc_phy_chanspec_radio_set(struct brcms_phy_pub *ppi, u16 newch)
  935. {
  936. struct brcms_phy *pi = container_of(ppi, struct brcms_phy, pubpi_ro);
  937. pi->radio_chanspec = newch;
  938. }
  939. u16 wlc_phy_chanspec_get(struct brcms_phy_pub *ppi)
  940. {
  941. struct brcms_phy *pi = container_of(ppi, struct brcms_phy, pubpi_ro);
  942. return pi->radio_chanspec;
  943. }
  944. void wlc_phy_chanspec_set(struct brcms_phy_pub *ppi, u16 chanspec)
  945. {
  946. struct brcms_phy *pi = container_of(ppi, struct brcms_phy, pubpi_ro);
  947. u16 m_cur_channel;
  948. void (*chanspec_set)(struct brcms_phy *, u16) = NULL;
  949. m_cur_channel = CHSPEC_CHANNEL(chanspec);
  950. if (CHSPEC_IS5G(chanspec))
  951. m_cur_channel |= D11_CURCHANNEL_5G;
  952. if (CHSPEC_IS40(chanspec))
  953. m_cur_channel |= D11_CURCHANNEL_40;
  954. wlapi_bmac_write_shm(pi->sh->physhim, M_CURCHANNEL, m_cur_channel);
  955. chanspec_set = pi->pi_fptr.chanset;
  956. if (chanspec_set)
  957. (*chanspec_set)(pi, chanspec);
  958. }
  959. int wlc_phy_chanspec_freq2bandrange_lpssn(uint freq)
  960. {
  961. int range = -1;
  962. if (freq < 2500)
  963. range = WL_CHAN_FREQ_RANGE_2G;
  964. else if (freq <= 5320)
  965. range = WL_CHAN_FREQ_RANGE_5GL;
  966. else if (freq <= 5700)
  967. range = WL_CHAN_FREQ_RANGE_5GM;
  968. else
  969. range = WL_CHAN_FREQ_RANGE_5GH;
  970. return range;
  971. }
  972. int wlc_phy_chanspec_bandrange_get(struct brcms_phy *pi, u16 chanspec)
  973. {
  974. int range = -1;
  975. uint channel = CHSPEC_CHANNEL(chanspec);
  976. uint freq = wlc_phy_channel2freq(channel);
  977. if (ISNPHY(pi))
  978. range = wlc_phy_get_chan_freq_range_nphy(pi, channel);
  979. else if (ISLCNPHY(pi))
  980. range = wlc_phy_chanspec_freq2bandrange_lpssn(freq);
  981. return range;
  982. }
  983. void wlc_phy_chanspec_ch14_widefilter_set(struct brcms_phy_pub *ppi,
  984. bool wide_filter)
  985. {
  986. struct brcms_phy *pi = container_of(ppi, struct brcms_phy, pubpi_ro);
  987. pi->channel_14_wide_filter = wide_filter;
  988. }
  989. int wlc_phy_channel2freq(uint channel)
  990. {
  991. uint i;
  992. for (i = 0; i < ARRAY_SIZE(chan_info_all); i++)
  993. if (chan_info_all[i].chan == channel)
  994. return chan_info_all[i].freq;
  995. return 0;
  996. }
  997. void
  998. wlc_phy_chanspec_band_validch(struct brcms_phy_pub *ppi, uint band,
  999. struct brcms_chanvec *channels)
  1000. {
  1001. struct brcms_phy *pi = container_of(ppi, struct brcms_phy, pubpi_ro);
  1002. uint i;
  1003. uint channel;
  1004. memset(channels, 0, sizeof(struct brcms_chanvec));
  1005. for (i = 0; i < ARRAY_SIZE(chan_info_all); i++) {
  1006. channel = chan_info_all[i].chan;
  1007. if ((pi->a_band_high_disable) && (channel >= FIRST_REF5_CHANNUM)
  1008. && (channel <= LAST_REF5_CHANNUM))
  1009. continue;
  1010. if ((band == BRCM_BAND_2G && channel <= CH_MAX_2G_CHANNEL) ||
  1011. (band == BRCM_BAND_5G && channel > CH_MAX_2G_CHANNEL))
  1012. setbit(channels->vec, channel);
  1013. }
  1014. }
  1015. u16 wlc_phy_chanspec_band_firstch(struct brcms_phy_pub *ppi, uint band)
  1016. {
  1017. struct brcms_phy *pi = container_of(ppi, struct brcms_phy, pubpi_ro);
  1018. uint i;
  1019. uint channel;
  1020. u16 chspec;
  1021. for (i = 0; i < ARRAY_SIZE(chan_info_all); i++) {
  1022. channel = chan_info_all[i].chan;
  1023. if (ISNPHY(pi) && pi->bw == WL_CHANSPEC_BW_40) {
  1024. uint j;
  1025. for (j = 0; j < ARRAY_SIZE(chan_info_all); j++) {
  1026. if (chan_info_all[j].chan ==
  1027. channel + CH_10MHZ_APART)
  1028. break;
  1029. }
  1030. if (j == ARRAY_SIZE(chan_info_all))
  1031. continue;
  1032. channel = upper_20_sb(channel);
  1033. chspec = channel | WL_CHANSPEC_BW_40 |
  1034. WL_CHANSPEC_CTL_SB_LOWER;
  1035. if (band == BRCM_BAND_2G)
  1036. chspec |= WL_CHANSPEC_BAND_2G;
  1037. else
  1038. chspec |= WL_CHANSPEC_BAND_5G;
  1039. } else
  1040. chspec = ch20mhz_chspec(channel);
  1041. if ((pi->a_band_high_disable) && (channel >= FIRST_REF5_CHANNUM)
  1042. && (channel <= LAST_REF5_CHANNUM))
  1043. continue;
  1044. if ((band == BRCM_BAND_2G && channel <= CH_MAX_2G_CHANNEL) ||
  1045. (band == BRCM_BAND_5G && channel > CH_MAX_2G_CHANNEL))
  1046. return chspec;
  1047. }
  1048. return (u16) INVCHANSPEC;
  1049. }
  1050. int wlc_phy_txpower_get(struct brcms_phy_pub *ppi, uint *qdbm, bool *override)
  1051. {
  1052. struct brcms_phy *pi = container_of(ppi, struct brcms_phy, pubpi_ro);
  1053. *qdbm = pi->tx_user_target[0];
  1054. if (override != NULL)
  1055. *override = pi->txpwroverride;
  1056. return 0;
  1057. }
  1058. void wlc_phy_txpower_target_set(struct brcms_phy_pub *ppi,
  1059. struct txpwr_limits *txpwr)
  1060. {
  1061. bool mac_enabled = false;
  1062. struct brcms_phy *pi = container_of(ppi, struct brcms_phy, pubpi_ro);
  1063. memcpy(&pi->tx_user_target[TXP_FIRST_CCK],
  1064. &txpwr->cck[0], BRCMS_NUM_RATES_CCK);
  1065. memcpy(&pi->tx_user_target[TXP_FIRST_OFDM],
  1066. &txpwr->ofdm[0], BRCMS_NUM_RATES_OFDM);
  1067. memcpy(&pi->tx_user_target[TXP_FIRST_OFDM_20_CDD],
  1068. &txpwr->ofdm_cdd[0], BRCMS_NUM_RATES_OFDM);
  1069. memcpy(&pi->tx_user_target[TXP_FIRST_OFDM_40_SISO],
  1070. &txpwr->ofdm_40_siso[0], BRCMS_NUM_RATES_OFDM);
  1071. memcpy(&pi->tx_user_target[TXP_FIRST_OFDM_40_CDD],
  1072. &txpwr->ofdm_40_cdd[0], BRCMS_NUM_RATES_OFDM);
  1073. memcpy(&pi->tx_user_target[TXP_FIRST_MCS_20_SISO],
  1074. &txpwr->mcs_20_siso[0], BRCMS_NUM_RATES_MCS_1_STREAM);
  1075. memcpy(&pi->tx_user_target[TXP_FIRST_MCS_20_CDD],
  1076. &txpwr->mcs_20_cdd[0], BRCMS_NUM_RATES_MCS_1_STREAM);
  1077. memcpy(&pi->tx_user_target[TXP_FIRST_MCS_20_STBC],
  1078. &txpwr->mcs_20_stbc[0], BRCMS_NUM_RATES_MCS_1_STREAM);
  1079. memcpy(&pi->tx_user_target[TXP_FIRST_MCS_20_SDM],
  1080. &txpwr->mcs_20_mimo[0], BRCMS_NUM_RATES_MCS_2_STREAM);
  1081. memcpy(&pi->tx_user_target[TXP_FIRST_MCS_40_SISO],
  1082. &txpwr->mcs_40_siso[0], BRCMS_NUM_RATES_MCS_1_STREAM);
  1083. memcpy(&pi->tx_user_target[TXP_FIRST_MCS_40_CDD],
  1084. &txpwr->mcs_40_cdd[0], BRCMS_NUM_RATES_MCS_1_STREAM);
  1085. memcpy(&pi->tx_user_target[TXP_FIRST_MCS_40_STBC],
  1086. &txpwr->mcs_40_stbc[0], BRCMS_NUM_RATES_MCS_1_STREAM);
  1087. memcpy(&pi->tx_user_target[TXP_FIRST_MCS_40_SDM],
  1088. &txpwr->mcs_40_mimo[0], BRCMS_NUM_RATES_MCS_2_STREAM);
  1089. if (bcma_read32(pi->d11core, D11REGOFFS(maccontrol)) & MCTL_EN_MAC)
  1090. mac_enabled = true;
  1091. if (mac_enabled)
  1092. wlapi_suspend_mac_and_wait(pi->sh->physhim);
  1093. wlc_phy_txpower_recalc_target(pi);
  1094. wlc_phy_cal_txpower_recalc_sw(pi);
  1095. if (mac_enabled)
  1096. wlapi_enable_mac(pi->sh->physhim);
  1097. }
  1098. int wlc_phy_txpower_set(struct brcms_phy_pub *ppi, uint qdbm, bool override)
  1099. {
  1100. struct brcms_phy *pi = container_of(ppi, struct brcms_phy, pubpi_ro);
  1101. int i;
  1102. if (qdbm > 127)
  1103. return -EINVAL;
  1104. for (i = 0; i < TXP_NUM_RATES; i++)
  1105. pi->tx_user_target[i] = (u8) qdbm;
  1106. pi->txpwroverride = false;
  1107. if (pi->sh->up) {
  1108. if (!SCAN_INPROG_PHY(pi)) {
  1109. bool suspend;
  1110. suspend = (0 == (bcma_read32(pi->d11core,
  1111. D11REGOFFS(maccontrol)) &
  1112. MCTL_EN_MAC));
  1113. if (!suspend)
  1114. wlapi_suspend_mac_and_wait(pi->sh->physhim);
  1115. wlc_phy_txpower_recalc_target(pi);
  1116. wlc_phy_cal_txpower_recalc_sw(pi);
  1117. if (!suspend)
  1118. wlapi_enable_mac(pi->sh->physhim);
  1119. }
  1120. }
  1121. return 0;
  1122. }
  1123. void
  1124. wlc_phy_txpower_sromlimit(struct brcms_phy_pub *ppi, uint channel, u8 *min_pwr,
  1125. u8 *max_pwr, int txp_rate_idx)
  1126. {
  1127. struct brcms_phy *pi = container_of(ppi, struct brcms_phy, pubpi_ro);
  1128. uint i;
  1129. *min_pwr = pi->min_txpower * BRCMS_TXPWR_DB_FACTOR;
  1130. if (ISNPHY(pi)) {
  1131. if (txp_rate_idx < 0)
  1132. txp_rate_idx = TXP_FIRST_CCK;
  1133. wlc_phy_txpower_sromlimit_get_nphy(pi, channel, max_pwr,
  1134. (u8) txp_rate_idx);
  1135. } else if ((channel <= CH_MAX_2G_CHANNEL)) {
  1136. if (txp_rate_idx < 0)
  1137. txp_rate_idx = TXP_FIRST_CCK;
  1138. *max_pwr = pi->tx_srom_max_rate_2g[txp_rate_idx];
  1139. } else {
  1140. *max_pwr = BRCMS_TXPWR_MAX;
  1141. if (txp_rate_idx < 0)
  1142. txp_rate_idx = TXP_FIRST_OFDM;
  1143. for (i = 0; i < ARRAY_SIZE(chan_info_all); i++) {
  1144. if (channel == chan_info_all[i].chan)
  1145. break;
  1146. }
  1147. if (pi->hwtxpwr) {
  1148. *max_pwr = pi->hwtxpwr[i];
  1149. } else {
  1150. if ((i >= FIRST_MID_5G_CHAN) && (i <= LAST_MID_5G_CHAN))
  1151. *max_pwr =
  1152. pi->tx_srom_max_rate_5g_mid[txp_rate_idx];
  1153. if ((i >= FIRST_HIGH_5G_CHAN)
  1154. && (i <= LAST_HIGH_5G_CHAN))
  1155. *max_pwr =
  1156. pi->tx_srom_max_rate_5g_hi[txp_rate_idx];
  1157. if ((i >= FIRST_LOW_5G_CHAN) && (i <= LAST_LOW_5G_CHAN))
  1158. *max_pwr =
  1159. pi->tx_srom_max_rate_5g_low[txp_rate_idx];
  1160. }
  1161. }
  1162. }
  1163. void
  1164. wlc_phy_txpower_sromlimit_max_get(struct brcms_phy_pub *ppi, uint chan,
  1165. u8 *max_txpwr, u8 *min_txpwr)
  1166. {
  1167. struct brcms_phy *pi = container_of(ppi, struct brcms_phy, pubpi_ro);
  1168. u8 tx_pwr_max = 0;
  1169. u8 tx_pwr_min = 255;
  1170. u8 max_num_rate;
  1171. u8 maxtxpwr, mintxpwr, rate, pactrl;
  1172. pactrl = 0;
  1173. max_num_rate = ISNPHY(pi) ? TXP_NUM_RATES :
  1174. ISLCNPHY(pi) ? (TXP_LAST_SISO_MCS_20 +
  1175. 1) : (TXP_LAST_OFDM + 1);
  1176. for (rate = 0; rate < max_num_rate; rate++) {
  1177. wlc_phy_txpower_sromlimit(ppi, chan, &mintxpwr, &maxtxpwr,
  1178. rate);
  1179. maxtxpwr = (maxtxpwr > pactrl) ? (maxtxpwr - pactrl) : 0;
  1180. maxtxpwr = (maxtxpwr > 6) ? (maxtxpwr - 6) : 0;
  1181. tx_pwr_max = max(tx_pwr_max, maxtxpwr);
  1182. tx_pwr_min = min(tx_pwr_min, maxtxpwr);
  1183. }
  1184. *max_txpwr = tx_pwr_max;
  1185. *min_txpwr = tx_pwr_min;
  1186. }
  1187. void
  1188. wlc_phy_txpower_boardlimit_band(struct brcms_phy_pub *ppi, uint bandunit,
  1189. s32 *max_pwr, s32 *min_pwr, u32 *step_pwr)
  1190. {
  1191. return;
  1192. }
  1193. u8 wlc_phy_txpower_get_target_min(struct brcms_phy_pub *ppi)
  1194. {
  1195. struct brcms_phy *pi = container_of(ppi, struct brcms_phy, pubpi_ro);
  1196. return pi->tx_power_min;
  1197. }
  1198. u8 wlc_phy_txpower_get_target_max(struct brcms_phy_pub *ppi)
  1199. {
  1200. struct brcms_phy *pi = container_of(ppi, struct brcms_phy, pubpi_ro);
  1201. return pi->tx_power_max;
  1202. }
  1203. static s8 wlc_phy_env_measure_vbat(struct brcms_phy *pi)
  1204. {
  1205. if (ISLCNPHY(pi))
  1206. return wlc_lcnphy_vbatsense(pi, 0);
  1207. else
  1208. return 0;
  1209. }
  1210. static s8 wlc_phy_env_measure_temperature(struct brcms_phy *pi)
  1211. {
  1212. if (ISLCNPHY(pi))
  1213. return wlc_lcnphy_tempsense_degree(pi, 0);
  1214. else
  1215. return 0;
  1216. }
  1217. static void wlc_phy_upd_env_txpwr_rate_limits(struct brcms_phy *pi, u32 band)
  1218. {
  1219. u8 i;
  1220. s8 temp, vbat;
  1221. for (i = 0; i < TXP_NUM_RATES; i++)
  1222. pi->txpwr_env_limit[i] = BRCMS_TXPWR_MAX;
  1223. vbat = wlc_phy_env_measure_vbat(pi);
  1224. temp = wlc_phy_env_measure_temperature(pi);
  1225. }
  1226. static s8
  1227. wlc_user_txpwr_antport_to_rfport(struct brcms_phy *pi, uint chan, u32 band,
  1228. u8 rate)
  1229. {
  1230. return 0;
  1231. }
  1232. void wlc_phy_txpower_recalc_target(struct brcms_phy *pi)
  1233. {
  1234. u8 maxtxpwr, mintxpwr, rate, pactrl;
  1235. uint target_chan;
  1236. u8 tx_pwr_target[TXP_NUM_RATES];
  1237. u8 tx_pwr_max = 0;
  1238. u8 tx_pwr_min = 255;
  1239. u8 tx_pwr_max_rate_ind = 0;
  1240. u8 max_num_rate;
  1241. u8 start_rate = 0;
  1242. u16 chspec;
  1243. u32 band = CHSPEC2BAND(pi->radio_chanspec);
  1244. void (*txpwr_recalc_fn)(struct brcms_phy *) = NULL;
  1245. chspec = pi->radio_chanspec;
  1246. if (CHSPEC_CTL_SB(chspec) == WL_CHANSPEC_CTL_SB_NONE)
  1247. target_chan = CHSPEC_CHANNEL(chspec);
  1248. else if (CHSPEC_CTL_SB(chspec) == WL_CHANSPEC_CTL_SB_UPPER)
  1249. target_chan = upper_20_sb(CHSPEC_CHANNEL(chspec));
  1250. else
  1251. target_chan = lower_20_sb(CHSPEC_CHANNEL(chspec));
  1252. pactrl = 0;
  1253. if (ISLCNPHY(pi)) {
  1254. u32 offset_mcs, i;
  1255. if (CHSPEC_IS40(pi->radio_chanspec)) {
  1256. offset_mcs = pi->mcs40_po;
  1257. for (i = TXP_FIRST_SISO_MCS_20;
  1258. i <= TXP_LAST_SISO_MCS_20; i++) {
  1259. pi->tx_srom_max_rate_2g[i - 8] =
  1260. pi->tx_srom_max_2g -
  1261. ((offset_mcs & 0xf) * 2);
  1262. offset_mcs >>= 4;
  1263. }
  1264. } else {
  1265. offset_mcs = pi->mcs20_po;
  1266. for (i = TXP_FIRST_SISO_MCS_20;
  1267. i <= TXP_LAST_SISO_MCS_20; i++) {
  1268. pi->tx_srom_max_rate_2g[i - 8] =
  1269. pi->tx_srom_max_2g -
  1270. ((offset_mcs & 0xf) * 2);
  1271. offset_mcs >>= 4;
  1272. }
  1273. }
  1274. }
  1275. max_num_rate = ((ISNPHY(pi)) ? (TXP_NUM_RATES) :
  1276. ((ISLCNPHY(pi)) ?
  1277. (TXP_LAST_SISO_MCS_20 + 1) : (TXP_LAST_OFDM + 1)));
  1278. wlc_phy_upd_env_txpwr_rate_limits(pi, band);
  1279. for (rate = start_rate; rate < max_num_rate; rate++) {
  1280. tx_pwr_target[rate] = pi->tx_user_target[rate];
  1281. if (pi->user_txpwr_at_rfport)
  1282. tx_pwr_target[rate] +=
  1283. wlc_user_txpwr_antport_to_rfport(pi,
  1284. target_chan,
  1285. band,
  1286. rate);
  1287. wlc_phy_txpower_sromlimit((struct brcms_phy_pub *) pi,
  1288. target_chan,
  1289. &mintxpwr, &maxtxpwr, rate);
  1290. maxtxpwr = min(maxtxpwr, pi->txpwr_limit[rate]);
  1291. maxtxpwr = (maxtxpwr > pactrl) ? (maxtxpwr - pactrl) : 0;
  1292. maxtxpwr = (maxtxpwr > 6) ? (maxtxpwr - 6) : 0;
  1293. maxtxpwr = min(maxtxpwr, tx_pwr_target[rate]);
  1294. if (pi->txpwr_percent <= 100)
  1295. maxtxpwr = (maxtxpwr * pi->txpwr_percent) / 100;
  1296. tx_pwr_target[rate] = max(maxtxpwr, mintxpwr);
  1297. tx_pwr_target[rate] =
  1298. min(tx_pwr_target[rate], pi->txpwr_env_limit[rate]);
  1299. if (tx_pwr_target[rate] > tx_pwr_max)
  1300. tx_pwr_max_rate_ind = rate;
  1301. tx_pwr_max = max(tx_pwr_max, tx_pwr_target[rate]);
  1302. tx_pwr_min = min(tx_pwr_min, tx_pwr_target[rate]);
  1303. }
  1304. memset(pi->tx_power_offset, 0, sizeof(pi->tx_power_offset));
  1305. pi->tx_power_max = tx_pwr_max;
  1306. pi->tx_power_min = tx_pwr_min;
  1307. pi->tx_power_max_rate_ind = tx_pwr_max_rate_ind;
  1308. for (rate = 0; rate < max_num_rate; rate++) {
  1309. pi->tx_power_target[rate] = tx_pwr_target[rate];
  1310. if (!pi->hwpwrctrl || ISNPHY(pi))
  1311. pi->tx_power_offset[rate] =
  1312. pi->tx_power_max - pi->tx_power_target[rate];
  1313. else
  1314. pi->tx_power_offset[rate] =
  1315. pi->tx_power_target[rate] - pi->tx_power_min;
  1316. }
  1317. txpwr_recalc_fn = pi->pi_fptr.txpwrrecalc;
  1318. if (txpwr_recalc_fn)
  1319. (*txpwr_recalc_fn)(pi);
  1320. }
  1321. static void
  1322. wlc_phy_txpower_reg_limit_calc(struct brcms_phy *pi, struct txpwr_limits *txpwr,
  1323. u16 chanspec)
  1324. {
  1325. u8 tmp_txpwr_limit[2 * BRCMS_NUM_RATES_OFDM];
  1326. u8 *txpwr_ptr1 = NULL, *txpwr_ptr2 = NULL;
  1327. int rate_start_index = 0, rate1, rate2, k;
  1328. for (rate1 = WL_TX_POWER_CCK_FIRST, rate2 = 0;
  1329. rate2 < WL_TX_POWER_CCK_NUM; rate1++, rate2++)
  1330. pi->txpwr_limit[rate1] = txpwr->cck[rate2];
  1331. for (rate1 = WL_TX_POWER_OFDM_FIRST, rate2 = 0;
  1332. rate2 < WL_TX_POWER_OFDM_NUM; rate1++, rate2++)
  1333. pi->txpwr_limit[rate1] = txpwr->ofdm[rate2];
  1334. if (ISNPHY(pi)) {
  1335. for (k = 0; k < 4; k++) {
  1336. switch (k) {
  1337. case 0:
  1338. txpwr_ptr1 = txpwr->mcs_20_siso;
  1339. txpwr_ptr2 = txpwr->ofdm;
  1340. rate_start_index = WL_TX_POWER_OFDM_FIRST;
  1341. break;
  1342. case 1:
  1343. txpwr_ptr1 = txpwr->mcs_20_cdd;
  1344. txpwr_ptr2 = txpwr->ofdm_cdd;
  1345. rate_start_index = WL_TX_POWER_OFDM20_CDD_FIRST;
  1346. break;
  1347. case 2:
  1348. txpwr_ptr1 = txpwr->mcs_40_siso;
  1349. txpwr_ptr2 = txpwr->ofdm_40_siso;
  1350. rate_start_index =
  1351. WL_TX_POWER_OFDM40_SISO_FIRST;
  1352. break;
  1353. case 3:
  1354. txpwr_ptr1 = txpwr->mcs_40_cdd;
  1355. txpwr_ptr2 = txpwr->ofdm_40_cdd;
  1356. rate_start_index = WL_TX_POWER_OFDM40_CDD_FIRST;
  1357. break;
  1358. }
  1359. for (rate2 = 0; rate2 < BRCMS_NUM_RATES_OFDM;
  1360. rate2++) {
  1361. tmp_txpwr_limit[rate2] = 0;
  1362. tmp_txpwr_limit[BRCMS_NUM_RATES_OFDM + rate2] =
  1363. txpwr_ptr1[rate2];
  1364. }
  1365. wlc_phy_mcs_to_ofdm_powers_nphy(
  1366. tmp_txpwr_limit, 0,
  1367. BRCMS_NUM_RATES_OFDM -
  1368. 1, BRCMS_NUM_RATES_OFDM);
  1369. for (rate1 = rate_start_index, rate2 = 0;
  1370. rate2 < BRCMS_NUM_RATES_OFDM; rate1++, rate2++)
  1371. pi->txpwr_limit[rate1] =
  1372. min(txpwr_ptr2[rate2],
  1373. tmp_txpwr_limit[rate2]);
  1374. }
  1375. for (k = 0; k < 4; k++) {
  1376. switch (k) {
  1377. case 0:
  1378. txpwr_ptr1 = txpwr->ofdm;
  1379. txpwr_ptr2 = txpwr->mcs_20_siso;
  1380. rate_start_index = WL_TX_POWER_MCS20_SISO_FIRST;
  1381. break;
  1382. case 1:
  1383. txpwr_ptr1 = txpwr->ofdm_cdd;
  1384. txpwr_ptr2 = txpwr->mcs_20_cdd;
  1385. rate_start_index = WL_TX_POWER_MCS20_CDD_FIRST;
  1386. break;
  1387. case 2:
  1388. txpwr_ptr1 = txpwr->ofdm_40_siso;
  1389. txpwr_ptr2 = txpwr->mcs_40_siso;
  1390. rate_start_index = WL_TX_POWER_MCS40_SISO_FIRST;
  1391. break;
  1392. case 3:
  1393. txpwr_ptr1 = txpwr->ofdm_40_cdd;
  1394. txpwr_ptr2 = txpwr->mcs_40_cdd;
  1395. rate_start_index = WL_TX_POWER_MCS40_CDD_FIRST;
  1396. break;
  1397. }
  1398. for (rate2 = 0; rate2 < BRCMS_NUM_RATES_OFDM;
  1399. rate2++) {
  1400. tmp_txpwr_limit[rate2] = 0;
  1401. tmp_txpwr_limit[BRCMS_NUM_RATES_OFDM + rate2] =
  1402. txpwr_ptr1[rate2];
  1403. }
  1404. wlc_phy_ofdm_to_mcs_powers_nphy(
  1405. tmp_txpwr_limit, 0,
  1406. BRCMS_NUM_RATES_OFDM -
  1407. 1, BRCMS_NUM_RATES_OFDM);
  1408. for (rate1 = rate_start_index, rate2 = 0;
  1409. rate2 < BRCMS_NUM_RATES_MCS_1_STREAM;
  1410. rate1++, rate2++)
  1411. pi->txpwr_limit[rate1] =
  1412. min(txpwr_ptr2[rate2],
  1413. tmp_txpwr_limit[rate2]);
  1414. }
  1415. for (k = 0; k < 2; k++) {
  1416. switch (k) {
  1417. case 0:
  1418. rate_start_index = WL_TX_POWER_MCS20_STBC_FIRST;
  1419. txpwr_ptr1 = txpwr->mcs_20_stbc;
  1420. break;
  1421. case 1:
  1422. rate_start_index = WL_TX_POWER_MCS40_STBC_FIRST;
  1423. txpwr_ptr1 = txpwr->mcs_40_stbc;
  1424. break;
  1425. }
  1426. for (rate1 = rate_start_index, rate2 = 0;
  1427. rate2 < BRCMS_NUM_RATES_MCS_1_STREAM;
  1428. rate1++, rate2++)
  1429. pi->txpwr_limit[rate1] = txpwr_ptr1[rate2];
  1430. }
  1431. for (k = 0; k < 2; k++) {
  1432. switch (k) {
  1433. case 0:
  1434. rate_start_index = WL_TX_POWER_MCS20_SDM_FIRST;
  1435. txpwr_ptr1 = txpwr->mcs_20_mimo;
  1436. break;
  1437. case 1:
  1438. rate_start_index = WL_TX_POWER_MCS40_SDM_FIRST;
  1439. txpwr_ptr1 = txpwr->mcs_40_mimo;
  1440. break;
  1441. }
  1442. for (rate1 = rate_start_index, rate2 = 0;
  1443. rate2 < BRCMS_NUM_RATES_MCS_2_STREAM;
  1444. rate1++, rate2++)
  1445. pi->txpwr_limit[rate1] = txpwr_ptr1[rate2];
  1446. }
  1447. pi->txpwr_limit[WL_TX_POWER_MCS_32] = txpwr->mcs32;
  1448. pi->txpwr_limit[WL_TX_POWER_MCS40_CDD_FIRST] =
  1449. min(pi->txpwr_limit[WL_TX_POWER_MCS40_CDD_FIRST],
  1450. pi->txpwr_limit[WL_TX_POWER_MCS_32]);
  1451. pi->txpwr_limit[WL_TX_POWER_MCS_32] =
  1452. pi->txpwr_limit[WL_TX_POWER_MCS40_CDD_FIRST];
  1453. }
  1454. }
  1455. void wlc_phy_txpwr_percent_set(struct brcms_phy_pub *ppi, u8 txpwr_percent)
  1456. {
  1457. struct brcms_phy *pi = container_of(ppi, struct brcms_phy, pubpi_ro);
  1458. pi->txpwr_percent = txpwr_percent;
  1459. }
  1460. void wlc_phy_machwcap_set(struct brcms_phy_pub *ppi, u32 machwcap)
  1461. {
  1462. struct brcms_phy *pi = container_of(ppi, struct brcms_phy, pubpi_ro);
  1463. pi->sh->machwcap = machwcap;
  1464. }
  1465. void wlc_phy_runbist_config(struct brcms_phy_pub *ppi, bool start_end)
  1466. {
  1467. struct brcms_phy *pi = container_of(ppi, struct brcms_phy, pubpi_ro);
  1468. u16 rxc;
  1469. rxc = 0;
  1470. if (start_end == ON) {
  1471. if (!ISNPHY(pi))
  1472. return;
  1473. if (NREV_IS(pi->pubpi.phy_rev, 3)
  1474. || NREV_IS(pi->pubpi.phy_rev, 4)) {
  1475. bcma_wflush16(pi->d11core, D11REGOFFS(phyregaddr),
  1476. 0xa0);
  1477. bcma_set16(pi->d11core, D11REGOFFS(phyregdata),
  1478. 0x1 << 15);
  1479. }
  1480. } else {
  1481. if (NREV_IS(pi->pubpi.phy_rev, 3)
  1482. || NREV_IS(pi->pubpi.phy_rev, 4)) {
  1483. bcma_wflush16(pi->d11core, D11REGOFFS(phyregaddr),
  1484. 0xa0);
  1485. bcma_write16(pi->d11core, D11REGOFFS(phyregdata), rxc);
  1486. }
  1487. wlc_phy_por_inform(ppi);
  1488. }
  1489. }
  1490. void
  1491. wlc_phy_txpower_limit_set(struct brcms_phy_pub *ppi, struct txpwr_limits *txpwr,
  1492. u16 chanspec)
  1493. {
  1494. struct brcms_phy *pi = container_of(ppi, struct brcms_phy, pubpi_ro);
  1495. wlc_phy_txpower_reg_limit_calc(pi, txpwr, chanspec);
  1496. if (ISLCNPHY(pi)) {
  1497. int i, j;
  1498. for (i = TXP_FIRST_OFDM_20_CDD, j = 0;
  1499. j < BRCMS_NUM_RATES_MCS_1_STREAM; i++, j++) {
  1500. if (txpwr->mcs_20_siso[j])
  1501. pi->txpwr_limit[i] = txpwr->mcs_20_siso[j];
  1502. else
  1503. pi->txpwr_limit[i] = txpwr->ofdm[j];
  1504. }
  1505. }
  1506. wlapi_suspend_mac_and_wait(pi->sh->physhim);
  1507. wlc_phy_txpower_recalc_target(pi);
  1508. wlc_phy_cal_txpower_recalc_sw(pi);
  1509. wlapi_enable_mac(pi->sh->physhim);
  1510. }
  1511. void wlc_phy_ofdm_rateset_war(struct brcms_phy_pub *pih, bool war)
  1512. {
  1513. struct brcms_phy *pi = container_of(pih, struct brcms_phy, pubpi_ro);
  1514. pi->ofdm_rateset_war = war;
  1515. }
  1516. void wlc_phy_bf_preempt_enable(struct brcms_phy_pub *pih, bool bf_preempt)
  1517. {
  1518. struct brcms_phy *pi = container_of(pih, struct brcms_phy, pubpi_ro);
  1519. pi->bf_preempt_4306 = bf_preempt;
  1520. }
  1521. void wlc_phy_txpower_update_shm(struct brcms_phy *pi)
  1522. {
  1523. int j;
  1524. if (ISNPHY(pi))
  1525. return;
  1526. if (!pi->sh->clk)
  1527. return;
  1528. if (pi->hwpwrctrl) {
  1529. u16 offset;
  1530. wlapi_bmac_write_shm(pi->sh->physhim, M_TXPWR_MAX, 63);
  1531. wlapi_bmac_write_shm(pi->sh->physhim, M_TXPWR_N,
  1532. 1 << NUM_TSSI_FRAMES);
  1533. wlapi_bmac_write_shm(pi->sh->physhim, M_TXPWR_TARGET,
  1534. pi->tx_power_min << NUM_TSSI_FRAMES);
  1535. wlapi_bmac_write_shm(pi->sh->physhim, M_TXPWR_CUR,
  1536. pi->hwpwr_txcur);
  1537. for (j = TXP_FIRST_OFDM; j <= TXP_LAST_OFDM; j++) {
  1538. const u8 ucode_ofdm_rates[] = {
  1539. 0x0c, 0x12, 0x18, 0x24, 0x30, 0x48, 0x60, 0x6c
  1540. };
  1541. offset = wlapi_bmac_rate_shm_offset(
  1542. pi->sh->physhim,
  1543. ucode_ofdm_rates[j - TXP_FIRST_OFDM]);
  1544. wlapi_bmac_write_shm(pi->sh->physhim, offset + 6,
  1545. pi->tx_power_offset[j]);
  1546. wlapi_bmac_write_shm(pi->sh->physhim, offset + 14,
  1547. -(pi->tx_power_offset[j] / 2));
  1548. }
  1549. wlapi_bmac_mhf(pi->sh->physhim, MHF2, MHF2_HWPWRCTL,
  1550. MHF2_HWPWRCTL, BRCM_BAND_ALL);
  1551. } else {
  1552. int i;
  1553. for (i = TXP_FIRST_OFDM; i <= TXP_LAST_OFDM; i++)
  1554. pi->tx_power_offset[i] =
  1555. (u8) roundup(pi->tx_power_offset[i], 8);
  1556. wlapi_bmac_write_shm(pi->sh->physhim, M_OFDM_OFFSET,
  1557. (u16)
  1558. ((pi->tx_power_offset[TXP_FIRST_OFDM]
  1559. + 7) >> 3));
  1560. }
  1561. }
  1562. bool wlc_phy_txpower_hw_ctrl_get(struct brcms_phy_pub *ppi)
  1563. {
  1564. struct brcms_phy *pi = container_of(ppi, struct brcms_phy, pubpi_ro);
  1565. if (ISNPHY(pi))
  1566. return pi->nphy_txpwrctrl;
  1567. else
  1568. return pi->hwpwrctrl;
  1569. }
  1570. void wlc_phy_txpower_hw_ctrl_set(struct brcms_phy_pub *ppi, bool hwpwrctrl)
  1571. {
  1572. struct brcms_phy *pi = container_of(ppi, struct brcms_phy, pubpi_ro);
  1573. bool suspend;
  1574. if (!pi->hwpwrctrl_capable)
  1575. return;
  1576. pi->hwpwrctrl = hwpwrctrl;
  1577. pi->nphy_txpwrctrl = hwpwrctrl;
  1578. pi->txpwrctrl = hwpwrctrl;
  1579. if (ISNPHY(pi)) {
  1580. suspend = (0 == (bcma_read32(pi->d11core,
  1581. D11REGOFFS(maccontrol)) &
  1582. MCTL_EN_MAC));
  1583. if (!suspend)
  1584. wlapi_suspend_mac_and_wait(pi->sh->physhim);
  1585. wlc_phy_txpwrctrl_enable_nphy(pi, pi->nphy_txpwrctrl);
  1586. if (pi->nphy_txpwrctrl == PHY_TPC_HW_OFF)
  1587. wlc_phy_txpwr_fixpower_nphy(pi);
  1588. else
  1589. mod_phy_reg(pi, 0x1e7, (0x7f << 0),
  1590. pi->saved_txpwr_idx);
  1591. if (!suspend)
  1592. wlapi_enable_mac(pi->sh->physhim);
  1593. }
  1594. }
  1595. void wlc_phy_txpower_ipa_upd(struct brcms_phy *pi)
  1596. {
  1597. if (NREV_GE(pi->pubpi.phy_rev, 3)) {
  1598. pi->ipa2g_on = (pi->srom_fem2g.extpagain == 2);
  1599. pi->ipa5g_on = (pi->srom_fem5g.extpagain == 2);
  1600. } else {
  1601. pi->ipa2g_on = false;
  1602. pi->ipa5g_on = false;
  1603. }
  1604. }
  1605. static u32 wlc_phy_txpower_est_power_nphy(struct brcms_phy *pi)
  1606. {
  1607. s16 tx0_status, tx1_status;
  1608. u16 estPower1, estPower2;
  1609. u8 pwr0, pwr1, adj_pwr0, adj_pwr1;
  1610. u32 est_pwr;
  1611. estPower1 = read_phy_reg(pi, 0x118);
  1612. estPower2 = read_phy_reg(pi, 0x119);
  1613. if ((estPower1 & (0x1 << 8)) == (0x1 << 8))
  1614. pwr0 = (u8) (estPower1 & (0xff << 0)) >> 0;
  1615. else
  1616. pwr0 = 0x80;
  1617. if ((estPower2 & (0x1 << 8)) == (0x1 << 8))
  1618. pwr1 = (u8) (estPower2 & (0xff << 0)) >> 0;
  1619. else
  1620. pwr1 = 0x80;
  1621. tx0_status = read_phy_reg(pi, 0x1ed);
  1622. tx1_status = read_phy_reg(pi, 0x1ee);
  1623. if ((tx0_status & (0x1 << 15)) == (0x1 << 15))
  1624. adj_pwr0 = (u8) (tx0_status & (0xff << 0)) >> 0;
  1625. else
  1626. adj_pwr0 = 0x80;
  1627. if ((tx1_status & (0x1 << 15)) == (0x1 << 15))
  1628. adj_pwr1 = (u8) (tx1_status & (0xff << 0)) >> 0;
  1629. else
  1630. adj_pwr1 = 0x80;
  1631. est_pwr = (u32) ((pwr0 << 24) | (pwr1 << 16) | (adj_pwr0 << 8) |
  1632. adj_pwr1);
  1633. return est_pwr;
  1634. }
  1635. void
  1636. wlc_phy_txpower_get_current(struct brcms_phy_pub *ppi, struct tx_power *power,
  1637. uint channel)
  1638. {
  1639. struct brcms_phy *pi = container_of(ppi, struct brcms_phy, pubpi_ro);
  1640. uint rate, num_rates;
  1641. u8 min_pwr, max_pwr;
  1642. #if WL_TX_POWER_RATES != TXP_NUM_RATES
  1643. #error "struct tx_power out of sync with this fn"
  1644. #endif
  1645. if (ISNPHY(pi)) {
  1646. power->rf_cores = 2;
  1647. power->flags |= (WL_TX_POWER_F_MIMO);
  1648. if (pi->nphy_txpwrctrl == PHY_TPC_HW_ON)
  1649. power->flags |=
  1650. (WL_TX_POWER_F_ENABLED | WL_TX_POWER_F_HW);
  1651. } else if (ISLCNPHY(pi)) {
  1652. power->rf_cores = 1;
  1653. power->flags |= (WL_TX_POWER_F_SISO);
  1654. if (pi->radiopwr_override == RADIOPWR_OVERRIDE_DEF)
  1655. power->flags |= WL_TX_POWER_F_ENABLED;
  1656. if (pi->hwpwrctrl)
  1657. power->flags |= WL_TX_POWER_F_HW;
  1658. }
  1659. num_rates = ((ISNPHY(pi)) ? (TXP_NUM_RATES) :
  1660. ((ISLCNPHY(pi)) ?
  1661. (TXP_LAST_OFDM_20_CDD + 1) : (TXP_LAST_OFDM + 1)));
  1662. for (rate = 0; rate < num_rates; rate++) {
  1663. power->user_limit[rate] = pi->tx_user_target[rate];
  1664. wlc_phy_txpower_sromlimit(ppi, channel, &min_pwr, &max_pwr,
  1665. rate);
  1666. power->board_limit[rate] = (u8) max_pwr;
  1667. power->target[rate] = pi->tx_power_target[rate];
  1668. }
  1669. if (ISNPHY(pi)) {
  1670. u32 est_pout;
  1671. wlapi_suspend_mac_and_wait(pi->sh->physhim);
  1672. wlc_phyreg_enter((struct brcms_phy_pub *) pi);
  1673. est_pout = wlc_phy_txpower_est_power_nphy(pi);
  1674. wlc_phyreg_exit((struct brcms_phy_pub *) pi);
  1675. wlapi_enable_mac(pi->sh->physhim);
  1676. power->est_Pout[0] = (est_pout >> 8) & 0xff;
  1677. power->est_Pout[1] = est_pout & 0xff;
  1678. power->est_Pout_act[0] = est_pout >> 24;
  1679. power->est_Pout_act[1] = (est_pout >> 16) & 0xff;
  1680. if (power->est_Pout[0] == 0x80)
  1681. power->est_Pout[0] = 0;
  1682. if (power->est_Pout[1] == 0x80)
  1683. power->est_Pout[1] = 0;
  1684. if (power->est_Pout_act[0] == 0x80)
  1685. power->est_Pout_act[0] = 0;
  1686. if (power->est_Pout_act[1] == 0x80)
  1687. power->est_Pout_act[1] = 0;
  1688. power->est_Pout_cck = 0;
  1689. power->tx_power_max[0] = pi->tx_power_max;
  1690. power->tx_power_max[1] = pi->tx_power_max;
  1691. power->tx_power_max_rate_ind[0] = pi->tx_power_max_rate_ind;
  1692. power->tx_power_max_rate_ind[1] = pi->tx_power_max_rate_ind;
  1693. } else if (pi->hwpwrctrl && pi->sh->up) {
  1694. wlc_phyreg_enter(ppi);
  1695. if (ISLCNPHY(pi)) {
  1696. power->tx_power_max[0] = pi->tx_power_max;
  1697. power->tx_power_max[1] = pi->tx_power_max;
  1698. power->tx_power_max_rate_ind[0] =
  1699. pi->tx_power_max_rate_ind;
  1700. power->tx_power_max_rate_ind[1] =
  1701. pi->tx_power_max_rate_ind;
  1702. if (wlc_phy_tpc_isenabled_lcnphy(pi))
  1703. power->flags |=
  1704. (WL_TX_POWER_F_HW |
  1705. WL_TX_POWER_F_ENABLED);
  1706. else
  1707. power->flags &=
  1708. ~(WL_TX_POWER_F_HW |
  1709. WL_TX_POWER_F_ENABLED);
  1710. wlc_lcnphy_get_tssi(pi, (s8 *) &power->est_Pout[0],
  1711. (s8 *) &power->est_Pout_cck);
  1712. }
  1713. wlc_phyreg_exit(ppi);
  1714. }
  1715. }
  1716. void wlc_phy_antsel_type_set(struct brcms_phy_pub *ppi, u8 antsel_type)
  1717. {
  1718. struct brcms_phy *pi = container_of(ppi, struct brcms_phy, pubpi_ro);
  1719. pi->antsel_type = antsel_type;
  1720. }
  1721. bool wlc_phy_test_ison(struct brcms_phy_pub *ppi)
  1722. {
  1723. struct brcms_phy *pi = container_of(ppi, struct brcms_phy, pubpi_ro);
  1724. return pi->phytest_on;
  1725. }
  1726. void wlc_phy_ant_rxdiv_set(struct brcms_phy_pub *ppi, u8 val)
  1727. {
  1728. struct brcms_phy *pi = container_of(ppi, struct brcms_phy, pubpi_ro);
  1729. bool suspend;
  1730. pi->sh->rx_antdiv = val;
  1731. if (!(ISNPHY(pi) && D11REV_IS(pi->sh->corerev, 16))) {
  1732. if (val > ANT_RX_DIV_FORCE_1)
  1733. wlapi_bmac_mhf(pi->sh->physhim, MHF1, MHF1_ANTDIV,
  1734. MHF1_ANTDIV, BRCM_BAND_ALL);
  1735. else
  1736. wlapi_bmac_mhf(pi->sh->physhim, MHF1, MHF1_ANTDIV, 0,
  1737. BRCM_BAND_ALL);
  1738. }
  1739. if (ISNPHY(pi))
  1740. return;
  1741. if (!pi->sh->clk)
  1742. return;
  1743. suspend = (0 == (bcma_read32(pi->d11core, D11REGOFFS(maccontrol)) &
  1744. MCTL_EN_MAC));
  1745. if (!suspend)
  1746. wlapi_suspend_mac_and_wait(pi->sh->physhim);
  1747. if (ISLCNPHY(pi)) {
  1748. if (val > ANT_RX_DIV_FORCE_1) {
  1749. mod_phy_reg(pi, 0x410, (0x1 << 1), 0x01 << 1);
  1750. mod_phy_reg(pi, 0x410,
  1751. (0x1 << 0),
  1752. ((ANT_RX_DIV_START_1 == val) ? 1 : 0) << 0);
  1753. } else {
  1754. mod_phy_reg(pi, 0x410, (0x1 << 1), 0x00 << 1);
  1755. mod_phy_reg(pi, 0x410, (0x1 << 0), (u16) val << 0);
  1756. }
  1757. }
  1758. if (!suspend)
  1759. wlapi_enable_mac(pi->sh->physhim);
  1760. return;
  1761. }
  1762. static bool
  1763. wlc_phy_noise_calc_phy(struct brcms_phy *pi, u32 *cmplx_pwr, s8 *pwr_ant)
  1764. {
  1765. s8 cmplx_pwr_dbm[PHY_CORE_MAX];
  1766. u8 i;
  1767. memset((u8 *) cmplx_pwr_dbm, 0, sizeof(cmplx_pwr_dbm));
  1768. wlc_phy_compute_dB(cmplx_pwr, cmplx_pwr_dbm, pi->pubpi.phy_corenum);
  1769. for (i = 0; i < pi->pubpi.phy_corenum; i++) {
  1770. if (NREV_GE(pi->pubpi.phy_rev, 3))
  1771. cmplx_pwr_dbm[i] += (s8) PHY_NOISE_OFFSETFACT_4322;
  1772. else
  1773. cmplx_pwr_dbm[i] += (s8) (16 - (15) * 3 - 70);
  1774. }
  1775. for (i = 0; i < pi->pubpi.phy_corenum; i++) {
  1776. pi->nphy_noise_win[i][pi->nphy_noise_index] = cmplx_pwr_dbm[i];
  1777. pwr_ant[i] = cmplx_pwr_dbm[i];
  1778. }
  1779. pi->nphy_noise_index =
  1780. MODINC_POW2(pi->nphy_noise_index, PHY_NOISE_WINDOW_SZ);
  1781. return true;
  1782. }
  1783. static void wlc_phy_noise_cb(struct brcms_phy *pi, u8 channel, s8 noise_dbm)
  1784. {
  1785. if (!pi->phynoise_state)
  1786. return;
  1787. if (pi->phynoise_state & PHY_NOISE_STATE_MON) {
  1788. if (pi->phynoise_chan_watchdog == channel) {
  1789. pi->sh->phy_noise_window[pi->sh->phy_noise_index] =
  1790. noise_dbm;
  1791. pi->sh->phy_noise_index =
  1792. MODINC(pi->sh->phy_noise_index, MA_WINDOW_SZ);
  1793. }
  1794. pi->phynoise_state &= ~PHY_NOISE_STATE_MON;
  1795. }
  1796. if (pi->phynoise_state & PHY_NOISE_STATE_EXTERNAL)
  1797. pi->phynoise_state &= ~PHY_NOISE_STATE_EXTERNAL;
  1798. }
  1799. static s8 wlc_phy_noise_read_shmem(struct brcms_phy *pi)
  1800. {
  1801. u32 cmplx_pwr[PHY_CORE_MAX];
  1802. s8 noise_dbm_ant[PHY_CORE_MAX];
  1803. u16 lo, hi;
  1804. u32 cmplx_pwr_tot = 0;
  1805. s8 noise_dbm = PHY_NOISE_FIXED_VAL_NPHY;
  1806. u8 idx, core;
  1807. memset((u8 *) cmplx_pwr, 0, sizeof(cmplx_pwr));
  1808. memset((u8 *) noise_dbm_ant, 0, sizeof(noise_dbm_ant));
  1809. for (idx = 0, core = 0; core < pi->pubpi.phy_corenum; idx += 2,
  1810. core++) {
  1811. lo = wlapi_bmac_read_shm(pi->sh->physhim, M_PWRIND_MAP(idx));
  1812. hi = wlapi_bmac_read_shm(pi->sh->physhim,
  1813. M_PWRIND_MAP(idx + 1));
  1814. cmplx_pwr[core] = (hi << 16) + lo;
  1815. cmplx_pwr_tot += cmplx_pwr[core];
  1816. if (cmplx_pwr[core] == 0)
  1817. noise_dbm_ant[core] = PHY_NOISE_FIXED_VAL_NPHY;
  1818. else
  1819. cmplx_pwr[core] >>= PHY_NOISE_SAMPLE_LOG_NUM_UCODE;
  1820. }
  1821. if (cmplx_pwr_tot != 0)
  1822. wlc_phy_noise_calc_phy(pi, cmplx_pwr, noise_dbm_ant);
  1823. for (core = 0; core < pi->pubpi.phy_corenum; core++) {
  1824. pi->nphy_noise_win[core][pi->nphy_noise_index] =
  1825. noise_dbm_ant[core];
  1826. if (noise_dbm_ant[core] > noise_dbm)
  1827. noise_dbm = noise_dbm_ant[core];
  1828. }
  1829. pi->nphy_noise_index =
  1830. MODINC_POW2(pi->nphy_noise_index, PHY_NOISE_WINDOW_SZ);
  1831. return noise_dbm;
  1832. }
  1833. void wlc_phy_noise_sample_intr(struct brcms_phy_pub *pih)
  1834. {
  1835. struct brcms_phy *pi = container_of(pih, struct brcms_phy, pubpi_ro);
  1836. u16 jssi_aux;
  1837. u8 channel = 0;
  1838. s8 noise_dbm = PHY_NOISE_FIXED_VAL_NPHY;
  1839. if (ISLCNPHY(pi)) {
  1840. u32 cmplx_pwr, cmplx_pwr0, cmplx_pwr1;
  1841. u16 lo, hi;
  1842. s32 pwr_offset_dB, gain_dB;
  1843. u16 status_0, status_1;
  1844. jssi_aux = wlapi_bmac_read_shm(pi->sh->physhim, M_JSSI_AUX);
  1845. channel = jssi_aux & D11_CURCHANNEL_MAX;
  1846. lo = wlapi_bmac_read_shm(pi->sh->physhim, M_PWRIND_MAP0);
  1847. hi = wlapi_bmac_read_shm(pi->sh->physhim, M_PWRIND_MAP1);
  1848. cmplx_pwr0 = (hi << 16) + lo;
  1849. lo = wlapi_bmac_read_shm(pi->sh->physhim, M_PWRIND_MAP2);
  1850. hi = wlapi_bmac_read_shm(pi->sh->physhim, M_PWRIND_MAP3);
  1851. cmplx_pwr1 = (hi << 16) + lo;
  1852. cmplx_pwr = (cmplx_pwr0 + cmplx_pwr1) >> 6;
  1853. status_0 = 0x44;
  1854. status_1 = wlapi_bmac_read_shm(pi->sh->physhim, M_JSSI_0);
  1855. if ((cmplx_pwr > 0 && cmplx_pwr < 500)
  1856. && ((status_1 & 0xc000) == 0x4000)) {
  1857. wlc_phy_compute_dB(&cmplx_pwr, &noise_dbm,
  1858. pi->pubpi.phy_corenum);
  1859. pwr_offset_dB = (read_phy_reg(pi, 0x434) & 0xFF);
  1860. if (pwr_offset_dB > 127)
  1861. pwr_offset_dB -= 256;
  1862. noise_dbm += (s8) (pwr_offset_dB - 30);
  1863. gain_dB = (status_0 & 0x1ff);
  1864. noise_dbm -= (s8) (gain_dB);
  1865. } else {
  1866. noise_dbm = PHY_NOISE_FIXED_VAL_LCNPHY;
  1867. }
  1868. } else if (ISNPHY(pi)) {
  1869. jssi_aux = wlapi_bmac_read_shm(pi->sh->physhim, M_JSSI_AUX);
  1870. channel = jssi_aux & D11_CURCHANNEL_MAX;
  1871. noise_dbm = wlc_phy_noise_read_shmem(pi);
  1872. }
  1873. wlc_phy_noise_cb(pi, channel, noise_dbm);
  1874. }
  1875. static void
  1876. wlc_phy_noise_sample_request(struct brcms_phy_pub *pih, u8 reason, u8 ch)
  1877. {
  1878. struct brcms_phy *pi = container_of(pih, struct brcms_phy, pubpi_ro);
  1879. s8 noise_dbm = PHY_NOISE_FIXED_VAL_NPHY;
  1880. bool sampling_in_progress = (pi->phynoise_state != 0);
  1881. bool wait_for_intr = true;
  1882. switch (reason) {
  1883. case PHY_NOISE_SAMPLE_MON:
  1884. pi->phynoise_chan_watchdog = ch;
  1885. pi->phynoise_state |= PHY_NOISE_STATE_MON;
  1886. break;
  1887. case PHY_NOISE_SAMPLE_EXTERNAL:
  1888. pi->phynoise_state |= PHY_NOISE_STATE_EXTERNAL;
  1889. break;
  1890. default:
  1891. break;
  1892. }
  1893. if (sampling_in_progress)
  1894. return;
  1895. pi->phynoise_now = pi->sh->now;
  1896. if (pi->phy_fixed_noise) {
  1897. if (ISNPHY(pi)) {
  1898. pi->nphy_noise_win[WL_ANT_IDX_1][pi->nphy_noise_index] =
  1899. PHY_NOISE_FIXED_VAL_NPHY;
  1900. pi->nphy_noise_win[WL_ANT_IDX_2][pi->nphy_noise_index] =
  1901. PHY_NOISE_FIXED_VAL_NPHY;
  1902. pi->nphy_noise_index = MODINC_POW2(pi->nphy_noise_index,
  1903. PHY_NOISE_WINDOW_SZ);
  1904. noise_dbm = PHY_NOISE_FIXED_VAL_NPHY;
  1905. } else {
  1906. noise_dbm = PHY_NOISE_FIXED_VAL;
  1907. }
  1908. wait_for_intr = false;
  1909. goto done;
  1910. }
  1911. if (ISLCNPHY(pi)) {
  1912. if (!pi->phynoise_polling
  1913. || (reason == PHY_NOISE_SAMPLE_EXTERNAL)) {
  1914. wlapi_bmac_write_shm(pi->sh->physhim, M_JSSI_0, 0);
  1915. wlapi_bmac_write_shm(pi->sh->physhim, M_PWRIND_MAP0, 0);
  1916. wlapi_bmac_write_shm(pi->sh->physhim, M_PWRIND_MAP1, 0);
  1917. wlapi_bmac_write_shm(pi->sh->physhim, M_PWRIND_MAP2, 0);
  1918. wlapi_bmac_write_shm(pi->sh->physhim, M_PWRIND_MAP3, 0);
  1919. bcma_set32(pi->d11core, D11REGOFFS(maccommand),
  1920. MCMD_BG_NOISE);
  1921. } else {
  1922. wlapi_suspend_mac_and_wait(pi->sh->physhim);
  1923. wlc_lcnphy_deaf_mode(pi, (bool) 0);
  1924. noise_dbm = (s8) wlc_lcnphy_rx_signal_power(pi, 20);
  1925. wlc_lcnphy_deaf_mode(pi, (bool) 1);
  1926. wlapi_enable_mac(pi->sh->physhim);
  1927. wait_for_intr = false;
  1928. }
  1929. } else if (ISNPHY(pi)) {
  1930. if (!pi->phynoise_polling
  1931. || (reason == PHY_NOISE_SAMPLE_EXTERNAL)) {
  1932. wlapi_bmac_write_shm(pi->sh->physhim, M_PWRIND_MAP0, 0);
  1933. wlapi_bmac_write_shm(pi->sh->physhim, M_PWRIND_MAP1, 0);
  1934. wlapi_bmac_write_shm(pi->sh->physhim, M_PWRIND_MAP2, 0);
  1935. wlapi_bmac_write_shm(pi->sh->physhim, M_PWRIND_MAP3, 0);
  1936. bcma_set32(pi->d11core, D11REGOFFS(maccommand),
  1937. MCMD_BG_NOISE);
  1938. } else {
  1939. struct phy_iq_est est[PHY_CORE_MAX];
  1940. u32 cmplx_pwr[PHY_CORE_MAX];
  1941. s8 noise_dbm_ant[PHY_CORE_MAX];
  1942. u16 log_num_samps, num_samps, classif_state = 0;
  1943. u8 wait_time = 32;
  1944. u8 wait_crs = 0;
  1945. u8 i;
  1946. memset((u8 *) est, 0, sizeof(est));
  1947. memset((u8 *) cmplx_pwr, 0, sizeof(cmplx_pwr));
  1948. memset((u8 *) noise_dbm_ant, 0, sizeof(noise_dbm_ant));
  1949. log_num_samps = PHY_NOISE_SAMPLE_LOG_NUM_NPHY;
  1950. num_samps = 1 << log_num_samps;
  1951. wlapi_suspend_mac_and_wait(pi->sh->physhim);
  1952. classif_state = wlc_phy_classifier_nphy(pi, 0, 0);
  1953. wlc_phy_classifier_nphy(pi, 3, 0);
  1954. wlc_phy_rx_iq_est_nphy(pi, est, num_samps, wait_time,
  1955. wait_crs);
  1956. wlc_phy_classifier_nphy(pi, (0x7 << 0), classif_state);
  1957. wlapi_enable_mac(pi->sh->physhim);
  1958. for (i = 0; i < pi->pubpi.phy_corenum; i++)
  1959. cmplx_pwr[i] = (est[i].i_pwr + est[i].q_pwr) >>
  1960. log_num_samps;
  1961. wlc_phy_noise_calc_phy(pi, cmplx_pwr, noise_dbm_ant);
  1962. for (i = 0; i < pi->pubpi.phy_corenum; i++) {
  1963. pi->nphy_noise_win[i][pi->nphy_noise_index] =
  1964. noise_dbm_ant[i];
  1965. if (noise_dbm_ant[i] > noise_dbm)
  1966. noise_dbm = noise_dbm_ant[i];
  1967. }
  1968. pi->nphy_noise_index = MODINC_POW2(pi->nphy_noise_index,
  1969. PHY_NOISE_WINDOW_SZ);
  1970. wait_for_intr = false;
  1971. }
  1972. }
  1973. done:
  1974. if (!wait_for_intr)
  1975. wlc_phy_noise_cb(pi, ch, noise_dbm);
  1976. }
  1977. void wlc_phy_noise_sample_request_external(struct brcms_phy_pub *pih)
  1978. {
  1979. u8 channel;
  1980. channel = CHSPEC_CHANNEL(wlc_phy_chanspec_get(pih));
  1981. wlc_phy_noise_sample_request(pih, PHY_NOISE_SAMPLE_EXTERNAL, channel);
  1982. }
  1983. static const s8 lcnphy_gain_index_offset_for_pkt_rssi[] = {
  1984. 8,
  1985. 8,
  1986. 8,
  1987. 8,
  1988. 8,
  1989. 8,
  1990. 8,
  1991. 9,
  1992. 10,
  1993. 8,
  1994. 8,
  1995. 7,
  1996. 7,
  1997. 1,
  1998. 2,
  1999. 2,
  2000. 2,
  2001. 2,
  2002. 2,
  2003. 2,
  2004. 2,
  2005. 2,
  2006. 2,
  2007. 2,
  2008. 2,
  2009. 2,
  2010. 2,
  2011. 2,
  2012. 2,
  2013. 2,
  2014. 2,
  2015. 2,
  2016. 1,
  2017. 1,
  2018. 0,
  2019. 0,
  2020. 0,
  2021. 0
  2022. };
  2023. void wlc_phy_compute_dB(u32 *cmplx_pwr, s8 *p_cmplx_pwr_dB, u8 core)
  2024. {
  2025. u8 msb, secondmsb, i;
  2026. u32 tmp;
  2027. for (i = 0; i < core; i++) {
  2028. secondmsb = 0;
  2029. tmp = cmplx_pwr[i];
  2030. msb = fls(tmp);
  2031. if (msb)
  2032. secondmsb = (u8) ((tmp >> (--msb - 1)) & 1);
  2033. p_cmplx_pwr_dB[i] = (s8) (3 * msb + 2 * secondmsb);
  2034. }
  2035. }
  2036. int wlc_phy_rssi_compute(struct brcms_phy_pub *pih,
  2037. struct d11rxhdr *rxh)
  2038. {
  2039. int rssi = rxh->PhyRxStatus_1 & PRXS1_JSSI_MASK;
  2040. uint radioid = pih->radioid;
  2041. struct brcms_phy *pi = container_of(pih, struct brcms_phy, pubpi_ro);
  2042. if ((pi->sh->corerev >= 11)
  2043. && !(rxh->RxStatus2 & RXS_PHYRXST_VALID)) {
  2044. rssi = BRCMS_RSSI_INVALID;
  2045. goto end;
  2046. }
  2047. if (ISLCNPHY(pi)) {
  2048. u8 gidx = (rxh->PhyRxStatus_2 & 0xFC00) >> 10;
  2049. struct brcms_phy_lcnphy *pi_lcn = pi->u.pi_lcnphy;
  2050. if (rssi > 127)
  2051. rssi -= 256;
  2052. rssi = rssi + lcnphy_gain_index_offset_for_pkt_rssi[gidx];
  2053. if ((rssi > -46) && (gidx > 18))
  2054. rssi = rssi + 7;
  2055. rssi = rssi + pi_lcn->lcnphy_pkteng_rssi_slope;
  2056. rssi = rssi + 2;
  2057. }
  2058. if (ISLCNPHY(pi)) {
  2059. if (rssi > 127)
  2060. rssi -= 256;
  2061. } else if (radioid == BCM2055_ID || radioid == BCM2056_ID
  2062. || radioid == BCM2057_ID) {
  2063. rssi = wlc_phy_rssi_compute_nphy(pi, rxh);
  2064. }
  2065. end:
  2066. return rssi;
  2067. }
  2068. void wlc_phy_freqtrack_start(struct brcms_phy_pub *pih)
  2069. {
  2070. return;
  2071. }
  2072. void wlc_phy_freqtrack_end(struct brcms_phy_pub *pih)
  2073. {
  2074. return;
  2075. }
  2076. void wlc_phy_set_deaf(struct brcms_phy_pub *ppi, bool user_flag)
  2077. {
  2078. struct brcms_phy *pi;
  2079. pi = (struct brcms_phy *) ppi;
  2080. if (ISLCNPHY(pi))
  2081. wlc_lcnphy_deaf_mode(pi, true);
  2082. else if (ISNPHY(pi))
  2083. wlc_nphy_deaf_mode(pi, true);
  2084. }
  2085. void wlc_phy_watchdog(struct brcms_phy_pub *pih)
  2086. {
  2087. struct brcms_phy *pi = container_of(pih, struct brcms_phy, pubpi_ro);
  2088. bool delay_phy_cal = false;
  2089. pi->sh->now++;
  2090. if (!pi->watchdog_override)
  2091. return;
  2092. if (!(SCAN_RM_IN_PROGRESS(pi) || PLT_INPROG_PHY(pi)))
  2093. wlc_phy_noise_sample_request((struct brcms_phy_pub *) pi,
  2094. PHY_NOISE_SAMPLE_MON,
  2095. CHSPEC_CHANNEL(pi->
  2096. radio_chanspec));
  2097. if (pi->phynoise_state && (pi->sh->now - pi->phynoise_now) > 5)
  2098. pi->phynoise_state = 0;
  2099. if ((!pi->phycal_txpower) ||
  2100. ((pi->sh->now - pi->phycal_txpower) >= pi->sh->fast_timer)) {
  2101. if (!SCAN_INPROG_PHY(pi) && wlc_phy_cal_txpower_recalc_sw(pi))
  2102. pi->phycal_txpower = pi->sh->now;
  2103. }
  2104. if ((SCAN_RM_IN_PROGRESS(pi) || PLT_INPROG_PHY(pi)
  2105. || ASSOC_INPROG_PHY(pi)))
  2106. return;
  2107. if (ISNPHY(pi) && !pi->disable_percal && !delay_phy_cal) {
  2108. if ((pi->nphy_perical != PHY_PERICAL_DISABLE) &&
  2109. (pi->nphy_perical != PHY_PERICAL_MANUAL) &&
  2110. ((pi->sh->now - pi->nphy_perical_last) >=
  2111. pi->sh->glacial_timer))
  2112. wlc_phy_cal_perical((struct brcms_phy_pub *) pi,
  2113. PHY_PERICAL_WATCHDOG);
  2114. wlc_phy_txpwr_papd_cal_nphy(pi);
  2115. }
  2116. if (ISLCNPHY(pi)) {
  2117. if (pi->phy_forcecal ||
  2118. ((pi->sh->now - pi->phy_lastcal) >=
  2119. pi->sh->glacial_timer)) {
  2120. if (!(SCAN_RM_IN_PROGRESS(pi) || ASSOC_INPROG_PHY(pi)))
  2121. wlc_lcnphy_calib_modes(
  2122. pi,
  2123. LCNPHY_PERICAL_TEMPBASED_TXPWRCTRL);
  2124. if (!
  2125. (SCAN_RM_IN_PROGRESS(pi) || PLT_INPROG_PHY(pi)
  2126. || ASSOC_INPROG_PHY(pi)
  2127. || pi->carrier_suppr_disable
  2128. || pi->disable_percal))
  2129. wlc_lcnphy_calib_modes(pi,
  2130. PHY_PERICAL_WATCHDOG);
  2131. }
  2132. }
  2133. }
  2134. void wlc_phy_BSSinit(struct brcms_phy_pub *pih, bool bonlyap, int rssi)
  2135. {
  2136. struct brcms_phy *pi = container_of(pih, struct brcms_phy, pubpi_ro);
  2137. uint i;
  2138. uint k;
  2139. for (i = 0; i < MA_WINDOW_SZ; i++)
  2140. pi->sh->phy_noise_window[i] = (s8) (rssi & 0xff);
  2141. if (ISLCNPHY(pi)) {
  2142. for (i = 0; i < MA_WINDOW_SZ; i++)
  2143. pi->sh->phy_noise_window[i] =
  2144. PHY_NOISE_FIXED_VAL_LCNPHY;
  2145. }
  2146. pi->sh->phy_noise_index = 0;
  2147. for (i = 0; i < PHY_NOISE_WINDOW_SZ; i++) {
  2148. for (k = WL_ANT_IDX_1; k < WL_ANT_RX_MAX; k++)
  2149. pi->nphy_noise_win[k][i] = PHY_NOISE_FIXED_VAL_NPHY;
  2150. }
  2151. pi->nphy_noise_index = 0;
  2152. }
  2153. void
  2154. wlc_phy_papd_decode_epsilon(u32 epsilon, s32 *eps_real, s32 *eps_imag)
  2155. {
  2156. *eps_imag = (epsilon >> 13);
  2157. if (*eps_imag > 0xfff)
  2158. *eps_imag -= 0x2000;
  2159. *eps_real = (epsilon & 0x1fff);
  2160. if (*eps_real > 0xfff)
  2161. *eps_real -= 0x2000;
  2162. }
  2163. void wlc_phy_cal_perical_mphase_reset(struct brcms_phy *pi)
  2164. {
  2165. wlapi_del_timer(pi->phycal_timer);
  2166. pi->cal_type_override = PHY_PERICAL_AUTO;
  2167. pi->mphase_cal_phase_id = MPHASE_CAL_STATE_IDLE;
  2168. pi->mphase_txcal_cmdidx = 0;
  2169. }
  2170. static void
  2171. wlc_phy_cal_perical_mphase_schedule(struct brcms_phy *pi, uint delay)
  2172. {
  2173. if ((pi->nphy_perical != PHY_PERICAL_MPHASE) &&
  2174. (pi->nphy_perical != PHY_PERICAL_MANUAL))
  2175. return;
  2176. wlapi_del_timer(pi->phycal_timer);
  2177. pi->mphase_cal_phase_id = MPHASE_CAL_STATE_INIT;
  2178. wlapi_add_timer(pi->phycal_timer, delay, 0);
  2179. }
  2180. void wlc_phy_cal_perical(struct brcms_phy_pub *pih, u8 reason)
  2181. {
  2182. s16 nphy_currtemp = 0;
  2183. s16 delta_temp = 0;
  2184. bool do_periodic_cal = true;
  2185. struct brcms_phy *pi = container_of(pih, struct brcms_phy, pubpi_ro);
  2186. if (!ISNPHY(pi))
  2187. return;
  2188. if ((pi->nphy_perical == PHY_PERICAL_DISABLE) ||
  2189. (pi->nphy_perical == PHY_PERICAL_MANUAL))
  2190. return;
  2191. switch (reason) {
  2192. case PHY_PERICAL_DRIVERUP:
  2193. break;
  2194. case PHY_PERICAL_PHYINIT:
  2195. if (pi->nphy_perical == PHY_PERICAL_MPHASE) {
  2196. if (PHY_PERICAL_MPHASE_PENDING(pi))
  2197. wlc_phy_cal_perical_mphase_reset(pi);
  2198. wlc_phy_cal_perical_mphase_schedule(
  2199. pi,
  2200. PHY_PERICAL_INIT_DELAY);
  2201. }
  2202. break;
  2203. case PHY_PERICAL_JOIN_BSS:
  2204. case PHY_PERICAL_START_IBSS:
  2205. case PHY_PERICAL_UP_BSS:
  2206. if ((pi->nphy_perical == PHY_PERICAL_MPHASE) &&
  2207. PHY_PERICAL_MPHASE_PENDING(pi))
  2208. wlc_phy_cal_perical_mphase_reset(pi);
  2209. pi->first_cal_after_assoc = true;
  2210. pi->cal_type_override = PHY_PERICAL_FULL;
  2211. if (pi->phycal_tempdelta)
  2212. pi->nphy_lastcal_temp = wlc_phy_tempsense_nphy(pi);
  2213. wlc_phy_cal_perical_nphy_run(pi, PHY_PERICAL_FULL);
  2214. break;
  2215. case PHY_PERICAL_WATCHDOG:
  2216. if (pi->phycal_tempdelta) {
  2217. nphy_currtemp = wlc_phy_tempsense_nphy(pi);
  2218. delta_temp =
  2219. (nphy_currtemp > pi->nphy_lastcal_temp) ?
  2220. nphy_currtemp - pi->nphy_lastcal_temp :
  2221. pi->nphy_lastcal_temp - nphy_currtemp;
  2222. if ((delta_temp < (s16) pi->phycal_tempdelta) &&
  2223. (pi->nphy_txiqlocal_chanspec ==
  2224. pi->radio_chanspec))
  2225. do_periodic_cal = false;
  2226. else
  2227. pi->nphy_lastcal_temp = nphy_currtemp;
  2228. }
  2229. if (do_periodic_cal) {
  2230. if (pi->nphy_perical == PHY_PERICAL_MPHASE) {
  2231. if (!PHY_PERICAL_MPHASE_PENDING(pi))
  2232. wlc_phy_cal_perical_mphase_schedule(
  2233. pi,
  2234. PHY_PERICAL_WDOG_DELAY);
  2235. } else if (pi->nphy_perical == PHY_PERICAL_SPHASE)
  2236. wlc_phy_cal_perical_nphy_run(pi,
  2237. PHY_PERICAL_AUTO);
  2238. }
  2239. break;
  2240. default:
  2241. break;
  2242. }
  2243. }
  2244. void wlc_phy_cal_perical_mphase_restart(struct brcms_phy *pi)
  2245. {
  2246. pi->mphase_cal_phase_id = MPHASE_CAL_STATE_INIT;
  2247. pi->mphase_txcal_cmdidx = 0;
  2248. }
  2249. u8 wlc_phy_nbits(s32 value)
  2250. {
  2251. s32 abs_val;
  2252. u8 nbits = 0;
  2253. abs_val = abs(value);
  2254. while ((abs_val >> nbits) > 0)
  2255. nbits++;
  2256. return nbits;
  2257. }
  2258. void wlc_phy_stf_chain_init(struct brcms_phy_pub *pih, u8 txchain, u8 rxchain)
  2259. {
  2260. struct brcms_phy *pi = container_of(pih, struct brcms_phy, pubpi_ro);
  2261. pi->sh->hw_phytxchain = txchain;
  2262. pi->sh->hw_phyrxchain = rxchain;
  2263. pi->sh->phytxchain = txchain;
  2264. pi->sh->phyrxchain = rxchain;
  2265. pi->pubpi.phy_corenum = (u8)hweight8(pi->sh->phyrxchain);
  2266. }
  2267. void wlc_phy_stf_chain_set(struct brcms_phy_pub *pih, u8 txchain, u8 rxchain)
  2268. {
  2269. struct brcms_phy *pi = container_of(pih, struct brcms_phy, pubpi_ro);
  2270. pi->sh->phytxchain = txchain;
  2271. if (ISNPHY(pi))
  2272. wlc_phy_rxcore_setstate_nphy(pih, rxchain);
  2273. pi->pubpi.phy_corenum = (u8)hweight8(pi->sh->phyrxchain);
  2274. }
  2275. void wlc_phy_stf_chain_get(struct brcms_phy_pub *pih, u8 *txchain, u8 *rxchain)
  2276. {
  2277. struct brcms_phy *pi = container_of(pih, struct brcms_phy, pubpi_ro);
  2278. *txchain = pi->sh->phytxchain;
  2279. *rxchain = pi->sh->phyrxchain;
  2280. }
  2281. u8 wlc_phy_stf_chain_active_get(struct brcms_phy_pub *pih)
  2282. {
  2283. s16 nphy_currtemp;
  2284. u8 active_bitmap;
  2285. struct brcms_phy *pi = container_of(pih, struct brcms_phy, pubpi_ro);
  2286. active_bitmap = (pi->phy_txcore_heatedup) ? 0x31 : 0x33;
  2287. if (!pi->watchdog_override)
  2288. return active_bitmap;
  2289. if (NREV_GE(pi->pubpi.phy_rev, 6)) {
  2290. wlapi_suspend_mac_and_wait(pi->sh->physhim);
  2291. nphy_currtemp = wlc_phy_tempsense_nphy(pi);
  2292. wlapi_enable_mac(pi->sh->physhim);
  2293. if (!pi->phy_txcore_heatedup) {
  2294. if (nphy_currtemp >= pi->phy_txcore_disable_temp) {
  2295. active_bitmap &= 0xFD;
  2296. pi->phy_txcore_heatedup = true;
  2297. }
  2298. } else {
  2299. if (nphy_currtemp <= pi->phy_txcore_enable_temp) {
  2300. active_bitmap |= 0x2;
  2301. pi->phy_txcore_heatedup = false;
  2302. }
  2303. }
  2304. }
  2305. return active_bitmap;
  2306. }
  2307. s8 wlc_phy_stf_ssmode_get(struct brcms_phy_pub *pih, u16 chanspec)
  2308. {
  2309. struct brcms_phy *pi = container_of(pih, struct brcms_phy, pubpi_ro);
  2310. u8 siso_mcs_id, cdd_mcs_id;
  2311. siso_mcs_id =
  2312. (CHSPEC_IS40(chanspec)) ? TXP_FIRST_MCS_40_SISO :
  2313. TXP_FIRST_MCS_20_SISO;
  2314. cdd_mcs_id =
  2315. (CHSPEC_IS40(chanspec)) ? TXP_FIRST_MCS_40_CDD :
  2316. TXP_FIRST_MCS_20_CDD;
  2317. if (pi->tx_power_target[siso_mcs_id] >
  2318. (pi->tx_power_target[cdd_mcs_id] + 12))
  2319. return PHY_TXC1_MODE_SISO;
  2320. else
  2321. return PHY_TXC1_MODE_CDD;
  2322. }
  2323. const u8 *wlc_phy_get_ofdm_rate_lookup(void)
  2324. {
  2325. return ofdm_rate_lookup;
  2326. }
  2327. void wlc_lcnphy_epa_switch(struct brcms_phy *pi, bool mode)
  2328. {
  2329. if ((pi->sh->chip == BCMA_CHIP_ID_BCM4313) &&
  2330. (pi->sh->boardflags & BFL_FEM)) {
  2331. if (mode) {
  2332. u16 txant = 0;
  2333. txant = wlapi_bmac_get_txant(pi->sh->physhim);
  2334. if (txant == 1) {
  2335. mod_phy_reg(pi, 0x44d, (0x1 << 2), (1) << 2);
  2336. mod_phy_reg(pi, 0x44c, (0x1 << 2), (1) << 2);
  2337. }
  2338. bcma_chipco_gpio_control(&pi->d11core->bus->drv_cc,
  2339. 0x0, 0x0);
  2340. bcma_chipco_gpio_out(&pi->d11core->bus->drv_cc,
  2341. ~0x40, 0x40);
  2342. bcma_chipco_gpio_outen(&pi->d11core->bus->drv_cc,
  2343. ~0x40, 0x40);
  2344. } else {
  2345. mod_phy_reg(pi, 0x44c, (0x1 << 2), (0) << 2);
  2346. mod_phy_reg(pi, 0x44d, (0x1 << 2), (0) << 2);
  2347. bcma_chipco_gpio_out(&pi->d11core->bus->drv_cc,
  2348. ~0x40, 0x00);
  2349. bcma_chipco_gpio_outen(&pi->d11core->bus->drv_cc,
  2350. ~0x40, 0x00);
  2351. bcma_chipco_gpio_control(&pi->d11core->bus->drv_cc,
  2352. 0x0, 0x40);
  2353. }
  2354. }
  2355. }
  2356. void wlc_phy_ldpc_override_set(struct brcms_phy_pub *ppi, bool ldpc)
  2357. {
  2358. return;
  2359. }
  2360. void
  2361. wlc_phy_get_pwrdet_offsets(struct brcms_phy *pi, s8 *cckoffset, s8 *ofdmoffset)
  2362. {
  2363. *cckoffset = 0;
  2364. *ofdmoffset = 0;
  2365. }
  2366. s8 wlc_phy_upd_rssi_offset(struct brcms_phy *pi, s8 rssi, u16 chanspec)
  2367. {
  2368. return rssi;
  2369. }
  2370. bool wlc_phy_txpower_ipa_ison(struct brcms_phy_pub *ppi)
  2371. {
  2372. struct brcms_phy *pi = container_of(ppi, struct brcms_phy, pubpi_ro);
  2373. if (ISNPHY(pi))
  2374. return wlc_phy_n_txpower_ipa_ison(pi);
  2375. else
  2376. return false;
  2377. }