bh.c 14 KB

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  1. /*
  2. * Device handling thread implementation for mac80211 ST-Ericsson CW1200 drivers
  3. *
  4. * Copyright (c) 2010, ST-Ericsson
  5. * Author: Dmitry Tarnyagin <dmitry.tarnyagin@lockless.no>
  6. *
  7. * Based on:
  8. * ST-Ericsson UMAC CW1200 driver, which is
  9. * Copyright (c) 2010, ST-Ericsson
  10. * Author: Ajitpal Singh <ajitpal.singh@stericsson.com>
  11. *
  12. * This program is free software; you can redistribute it and/or modify
  13. * it under the terms of the GNU General Public License version 2 as
  14. * published by the Free Software Foundation.
  15. */
  16. #include <linux/module.h>
  17. #include <net/mac80211.h>
  18. #include <linux/kthread.h>
  19. #include <linux/timer.h>
  20. #include "cw1200.h"
  21. #include "bh.h"
  22. #include "hwio.h"
  23. #include "wsm.h"
  24. #include "hwbus.h"
  25. #include "debug.h"
  26. #include "fwio.h"
  27. static int cw1200_bh(void *arg);
  28. #define DOWNLOAD_BLOCK_SIZE_WR (0x1000 - 4)
  29. /* an SPI message cannot be bigger than (2"12-1)*2 bytes
  30. * "*2" to cvt to bytes
  31. */
  32. #define MAX_SZ_RD_WR_BUFFERS (DOWNLOAD_BLOCK_SIZE_WR*2)
  33. #define PIGGYBACK_CTRL_REG (2)
  34. #define EFFECTIVE_BUF_SIZE (MAX_SZ_RD_WR_BUFFERS - PIGGYBACK_CTRL_REG)
  35. /* Suspend state privates */
  36. enum cw1200_bh_pm_state {
  37. CW1200_BH_RESUMED = 0,
  38. CW1200_BH_SUSPEND,
  39. CW1200_BH_SUSPENDED,
  40. CW1200_BH_RESUME,
  41. };
  42. typedef int (*cw1200_wsm_handler)(struct cw1200_common *priv,
  43. u8 *data, size_t size);
  44. static void cw1200_bh_work(struct work_struct *work)
  45. {
  46. struct cw1200_common *priv =
  47. container_of(work, struct cw1200_common, bh_work);
  48. cw1200_bh(priv);
  49. }
  50. int cw1200_register_bh(struct cw1200_common *priv)
  51. {
  52. int err = 0;
  53. /* Realtime workqueue */
  54. priv->bh_workqueue = alloc_workqueue("cw1200_bh",
  55. WQ_MEM_RECLAIM | WQ_HIGHPRI
  56. | WQ_CPU_INTENSIVE, 1);
  57. if (!priv->bh_workqueue)
  58. return -ENOMEM;
  59. INIT_WORK(&priv->bh_work, cw1200_bh_work);
  60. pr_debug("[BH] register.\n");
  61. atomic_set(&priv->bh_rx, 0);
  62. atomic_set(&priv->bh_tx, 0);
  63. atomic_set(&priv->bh_term, 0);
  64. atomic_set(&priv->bh_suspend, CW1200_BH_RESUMED);
  65. priv->bh_error = 0;
  66. priv->hw_bufs_used = 0;
  67. priv->buf_id_tx = 0;
  68. priv->buf_id_rx = 0;
  69. init_waitqueue_head(&priv->bh_wq);
  70. init_waitqueue_head(&priv->bh_evt_wq);
  71. err = !queue_work(priv->bh_workqueue, &priv->bh_work);
  72. WARN_ON(err);
  73. return err;
  74. }
  75. void cw1200_unregister_bh(struct cw1200_common *priv)
  76. {
  77. atomic_add(1, &priv->bh_term);
  78. wake_up(&priv->bh_wq);
  79. flush_workqueue(priv->bh_workqueue);
  80. destroy_workqueue(priv->bh_workqueue);
  81. priv->bh_workqueue = NULL;
  82. pr_debug("[BH] unregistered.\n");
  83. }
  84. void cw1200_irq_handler(struct cw1200_common *priv)
  85. {
  86. pr_debug("[BH] irq.\n");
  87. /* Disable Interrupts! */
  88. /* NOTE: hwbus_ops->lock already held */
  89. __cw1200_irq_enable(priv, 0);
  90. if (/* WARN_ON */(priv->bh_error))
  91. return;
  92. if (atomic_add_return(1, &priv->bh_rx) == 1)
  93. wake_up(&priv->bh_wq);
  94. }
  95. EXPORT_SYMBOL_GPL(cw1200_irq_handler);
  96. void cw1200_bh_wakeup(struct cw1200_common *priv)
  97. {
  98. pr_debug("[BH] wakeup.\n");
  99. if (priv->bh_error) {
  100. pr_err("[BH] wakeup failed (BH error)\n");
  101. return;
  102. }
  103. if (atomic_add_return(1, &priv->bh_tx) == 1)
  104. wake_up(&priv->bh_wq);
  105. }
  106. int cw1200_bh_suspend(struct cw1200_common *priv)
  107. {
  108. pr_debug("[BH] suspend.\n");
  109. if (priv->bh_error) {
  110. wiphy_warn(priv->hw->wiphy, "BH error -- can't suspend\n");
  111. return -EINVAL;
  112. }
  113. atomic_set(&priv->bh_suspend, CW1200_BH_SUSPEND);
  114. wake_up(&priv->bh_wq);
  115. return wait_event_timeout(priv->bh_evt_wq, priv->bh_error ||
  116. (CW1200_BH_SUSPENDED == atomic_read(&priv->bh_suspend)),
  117. 1 * HZ) ? 0 : -ETIMEDOUT;
  118. }
  119. int cw1200_bh_resume(struct cw1200_common *priv)
  120. {
  121. pr_debug("[BH] resume.\n");
  122. if (priv->bh_error) {
  123. wiphy_warn(priv->hw->wiphy, "BH error -- can't resume\n");
  124. return -EINVAL;
  125. }
  126. atomic_set(&priv->bh_suspend, CW1200_BH_RESUME);
  127. wake_up(&priv->bh_wq);
  128. return wait_event_timeout(priv->bh_evt_wq, priv->bh_error ||
  129. (CW1200_BH_RESUMED == atomic_read(&priv->bh_suspend)),
  130. 1 * HZ) ? 0 : -ETIMEDOUT;
  131. }
  132. static inline void wsm_alloc_tx_buffer(struct cw1200_common *priv)
  133. {
  134. ++priv->hw_bufs_used;
  135. }
  136. int wsm_release_tx_buffer(struct cw1200_common *priv, int count)
  137. {
  138. int ret = 0;
  139. int hw_bufs_used = priv->hw_bufs_used;
  140. priv->hw_bufs_used -= count;
  141. if (WARN_ON(priv->hw_bufs_used < 0))
  142. ret = -1;
  143. else if (hw_bufs_used >= priv->wsm_caps.input_buffers)
  144. ret = 1;
  145. if (!priv->hw_bufs_used)
  146. wake_up(&priv->bh_evt_wq);
  147. return ret;
  148. }
  149. static int cw1200_bh_read_ctrl_reg(struct cw1200_common *priv,
  150. u16 *ctrl_reg)
  151. {
  152. int ret;
  153. ret = cw1200_reg_read_16(priv,
  154. ST90TDS_CONTROL_REG_ID, ctrl_reg);
  155. if (ret) {
  156. ret = cw1200_reg_read_16(priv,
  157. ST90TDS_CONTROL_REG_ID, ctrl_reg);
  158. if (ret)
  159. pr_err("[BH] Failed to read control register.\n");
  160. }
  161. return ret;
  162. }
  163. static int cw1200_device_wakeup(struct cw1200_common *priv)
  164. {
  165. u16 ctrl_reg;
  166. int ret;
  167. pr_debug("[BH] Device wakeup.\n");
  168. /* First, set the dpll register */
  169. ret = cw1200_reg_write_32(priv, ST90TDS_TSET_GEN_R_W_REG_ID,
  170. cw1200_dpll_from_clk(priv->hw_refclk));
  171. if (WARN_ON(ret))
  172. return ret;
  173. /* To force the device to be always-on, the host sets WLAN_UP to 1 */
  174. ret = cw1200_reg_write_16(priv, ST90TDS_CONTROL_REG_ID,
  175. ST90TDS_CONT_WUP_BIT);
  176. if (WARN_ON(ret))
  177. return ret;
  178. ret = cw1200_bh_read_ctrl_reg(priv, &ctrl_reg);
  179. if (WARN_ON(ret))
  180. return ret;
  181. /* If the device returns WLAN_RDY as 1, the device is active and will
  182. * remain active.
  183. */
  184. if (ctrl_reg & ST90TDS_CONT_RDY_BIT) {
  185. pr_debug("[BH] Device awake.\n");
  186. return 1;
  187. }
  188. return 0;
  189. }
  190. /* Must be called from BH thraed. */
  191. void cw1200_enable_powersave(struct cw1200_common *priv,
  192. bool enable)
  193. {
  194. pr_debug("[BH] Powerave is %s.\n",
  195. enable ? "enabled" : "disabled");
  196. priv->powersave_enabled = enable;
  197. }
  198. static int cw1200_bh_rx_helper(struct cw1200_common *priv,
  199. uint16_t *ctrl_reg,
  200. int *tx)
  201. {
  202. size_t read_len = 0;
  203. struct sk_buff *skb_rx = NULL;
  204. struct wsm_hdr *wsm;
  205. size_t wsm_len;
  206. u16 wsm_id;
  207. u8 wsm_seq;
  208. int rx_resync = 1;
  209. size_t alloc_len;
  210. u8 *data;
  211. read_len = (*ctrl_reg & ST90TDS_CONT_NEXT_LEN_MASK) * 2;
  212. if (!read_len)
  213. return 0; /* No more work */
  214. if (WARN_ON((read_len < sizeof(struct wsm_hdr)) ||
  215. (read_len > EFFECTIVE_BUF_SIZE))) {
  216. pr_debug("Invalid read len: %zu (%04x)",
  217. read_len, *ctrl_reg);
  218. goto err;
  219. }
  220. /* Add SIZE of PIGGYBACK reg (CONTROL Reg)
  221. * to the NEXT Message length + 2 Bytes for SKB
  222. */
  223. read_len = read_len + 2;
  224. alloc_len = priv->hwbus_ops->align_size(
  225. priv->hwbus_priv, read_len);
  226. /* Check if not exceeding CW1200 capabilities */
  227. if (WARN_ON_ONCE(alloc_len > EFFECTIVE_BUF_SIZE)) {
  228. pr_debug("Read aligned len: %zu\n",
  229. alloc_len);
  230. }
  231. skb_rx = dev_alloc_skb(alloc_len);
  232. if (WARN_ON(!skb_rx))
  233. goto err;
  234. skb_trim(skb_rx, 0);
  235. skb_put(skb_rx, read_len);
  236. data = skb_rx->data;
  237. if (WARN_ON(!data))
  238. goto err;
  239. if (WARN_ON(cw1200_data_read(priv, data, alloc_len))) {
  240. pr_err("rx blew up, len %zu\n", alloc_len);
  241. goto err;
  242. }
  243. /* Piggyback */
  244. *ctrl_reg = __le16_to_cpu(
  245. ((__le16 *)data)[alloc_len / 2 - 1]);
  246. wsm = (struct wsm_hdr *)data;
  247. wsm_len = __le16_to_cpu(wsm->len);
  248. if (WARN_ON(wsm_len > read_len))
  249. goto err;
  250. if (priv->wsm_enable_wsm_dumps)
  251. print_hex_dump_bytes("<-- ",
  252. DUMP_PREFIX_NONE,
  253. data, wsm_len);
  254. wsm_id = __le16_to_cpu(wsm->id) & 0xFFF;
  255. wsm_seq = (__le16_to_cpu(wsm->id) >> 13) & 7;
  256. skb_trim(skb_rx, wsm_len);
  257. if (wsm_id == 0x0800) {
  258. wsm_handle_exception(priv,
  259. &data[sizeof(*wsm)],
  260. wsm_len - sizeof(*wsm));
  261. goto err;
  262. } else if (!rx_resync) {
  263. if (WARN_ON(wsm_seq != priv->wsm_rx_seq))
  264. goto err;
  265. }
  266. priv->wsm_rx_seq = (wsm_seq + 1) & 7;
  267. rx_resync = 0;
  268. if (wsm_id & 0x0400) {
  269. int rc = wsm_release_tx_buffer(priv, 1);
  270. if (WARN_ON(rc < 0))
  271. return rc;
  272. else if (rc > 0)
  273. *tx = 1;
  274. }
  275. /* cw1200_wsm_rx takes care on SKB livetime */
  276. if (WARN_ON(wsm_handle_rx(priv, wsm_id, wsm, &skb_rx)))
  277. goto err;
  278. if (skb_rx) {
  279. dev_kfree_skb(skb_rx);
  280. skb_rx = NULL;
  281. }
  282. return 0;
  283. err:
  284. if (skb_rx) {
  285. dev_kfree_skb(skb_rx);
  286. skb_rx = NULL;
  287. }
  288. return -1;
  289. }
  290. static int cw1200_bh_tx_helper(struct cw1200_common *priv,
  291. int *pending_tx,
  292. int *tx_burst)
  293. {
  294. size_t tx_len;
  295. u8 *data;
  296. int ret;
  297. struct wsm_hdr *wsm;
  298. if (priv->device_can_sleep) {
  299. ret = cw1200_device_wakeup(priv);
  300. if (WARN_ON(ret < 0)) { /* Error in wakeup */
  301. *pending_tx = 1;
  302. return 0;
  303. } else if (ret) { /* Woke up */
  304. priv->device_can_sleep = false;
  305. } else { /* Did not awake */
  306. *pending_tx = 1;
  307. return 0;
  308. }
  309. }
  310. wsm_alloc_tx_buffer(priv);
  311. ret = wsm_get_tx(priv, &data, &tx_len, tx_burst);
  312. if (ret <= 0) {
  313. wsm_release_tx_buffer(priv, 1);
  314. if (WARN_ON(ret < 0))
  315. return ret; /* Error */
  316. return 0; /* No work */
  317. }
  318. wsm = (struct wsm_hdr *)data;
  319. BUG_ON(tx_len < sizeof(*wsm));
  320. BUG_ON(__le16_to_cpu(wsm->len) != tx_len);
  321. atomic_add(1, &priv->bh_tx);
  322. tx_len = priv->hwbus_ops->align_size(
  323. priv->hwbus_priv, tx_len);
  324. /* Check if not exceeding CW1200 capabilities */
  325. if (WARN_ON_ONCE(tx_len > EFFECTIVE_BUF_SIZE))
  326. pr_debug("Write aligned len: %zu\n", tx_len);
  327. wsm->id &= __cpu_to_le16(0xffff ^ WSM_TX_SEQ(WSM_TX_SEQ_MAX));
  328. wsm->id |= __cpu_to_le16(WSM_TX_SEQ(priv->wsm_tx_seq));
  329. if (WARN_ON(cw1200_data_write(priv, data, tx_len))) {
  330. pr_err("tx blew up, len %zu\n", tx_len);
  331. wsm_release_tx_buffer(priv, 1);
  332. return -1; /* Error */
  333. }
  334. if (priv->wsm_enable_wsm_dumps)
  335. print_hex_dump_bytes("--> ",
  336. DUMP_PREFIX_NONE,
  337. data,
  338. __le16_to_cpu(wsm->len));
  339. wsm_txed(priv, data);
  340. priv->wsm_tx_seq = (priv->wsm_tx_seq + 1) & WSM_TX_SEQ_MAX;
  341. if (*tx_burst > 1) {
  342. cw1200_debug_tx_burst(priv);
  343. return 1; /* Work remains */
  344. }
  345. return 0;
  346. }
  347. static int cw1200_bh(void *arg)
  348. {
  349. struct cw1200_common *priv = arg;
  350. int rx, tx, term, suspend;
  351. u16 ctrl_reg = 0;
  352. int tx_allowed;
  353. int pending_tx = 0;
  354. int tx_burst;
  355. long status;
  356. u32 dummy;
  357. int ret;
  358. for (;;) {
  359. if (!priv->hw_bufs_used &&
  360. priv->powersave_enabled &&
  361. !priv->device_can_sleep &&
  362. !atomic_read(&priv->recent_scan)) {
  363. status = 1 * HZ;
  364. pr_debug("[BH] Device wakedown. No data.\n");
  365. cw1200_reg_write_16(priv, ST90TDS_CONTROL_REG_ID, 0);
  366. priv->device_can_sleep = true;
  367. } else if (priv->hw_bufs_used) {
  368. /* Interrupt loss detection */
  369. status = 1 * HZ;
  370. } else {
  371. status = MAX_SCHEDULE_TIMEOUT;
  372. }
  373. /* Dummy Read for SDIO retry mechanism*/
  374. if ((priv->hw_type != -1) &&
  375. (atomic_read(&priv->bh_rx) == 0) &&
  376. (atomic_read(&priv->bh_tx) == 0))
  377. cw1200_reg_read(priv, ST90TDS_CONFIG_REG_ID,
  378. &dummy, sizeof(dummy));
  379. pr_debug("[BH] waiting ...\n");
  380. status = wait_event_interruptible_timeout(priv->bh_wq, ({
  381. rx = atomic_xchg(&priv->bh_rx, 0);
  382. tx = atomic_xchg(&priv->bh_tx, 0);
  383. term = atomic_xchg(&priv->bh_term, 0);
  384. suspend = pending_tx ?
  385. 0 : atomic_read(&priv->bh_suspend);
  386. (rx || tx || term || suspend || priv->bh_error);
  387. }), status);
  388. pr_debug("[BH] - rx: %d, tx: %d, term: %d, bh_err: %d, suspend: %d, status: %ld\n",
  389. rx, tx, term, suspend, priv->bh_error, status);
  390. /* Did an error occur? */
  391. if ((status < 0 && status != -ERESTARTSYS) ||
  392. term || priv->bh_error) {
  393. break;
  394. }
  395. if (!status) { /* wait_event timed out */
  396. unsigned long timestamp = jiffies;
  397. long timeout;
  398. int pending = 0;
  399. int i;
  400. /* Check to see if we have any outstanding frames */
  401. if (priv->hw_bufs_used && (!rx || !tx)) {
  402. wiphy_warn(priv->hw->wiphy,
  403. "Missed interrupt? (%d frames outstanding)\n",
  404. priv->hw_bufs_used);
  405. rx = 1;
  406. /* Get a timestamp of "oldest" frame */
  407. for (i = 0; i < 4; ++i)
  408. pending += cw1200_queue_get_xmit_timestamp(
  409. &priv->tx_queue[i],
  410. &timestamp,
  411. priv->pending_frame_id);
  412. /* Check if frame transmission is timed out.
  413. * Add an extra second with respect to possible
  414. * interrupt loss.
  415. */
  416. timeout = timestamp +
  417. WSM_CMD_LAST_CHANCE_TIMEOUT +
  418. 1 * HZ -
  419. jiffies;
  420. /* And terminate BH thread if the frame is "stuck" */
  421. if (pending && timeout < 0) {
  422. wiphy_warn(priv->hw->wiphy,
  423. "Timeout waiting for TX confirm (%d/%d pending, %ld vs %lu).\n",
  424. priv->hw_bufs_used, pending,
  425. timestamp, jiffies);
  426. break;
  427. }
  428. } else if (!priv->device_can_sleep &&
  429. !atomic_read(&priv->recent_scan)) {
  430. pr_debug("[BH] Device wakedown. Timeout.\n");
  431. cw1200_reg_write_16(priv,
  432. ST90TDS_CONTROL_REG_ID, 0);
  433. priv->device_can_sleep = true;
  434. }
  435. goto done;
  436. } else if (suspend) {
  437. pr_debug("[BH] Device suspend.\n");
  438. if (priv->powersave_enabled) {
  439. pr_debug("[BH] Device wakedown. Suspend.\n");
  440. cw1200_reg_write_16(priv,
  441. ST90TDS_CONTROL_REG_ID, 0);
  442. priv->device_can_sleep = true;
  443. }
  444. atomic_set(&priv->bh_suspend, CW1200_BH_SUSPENDED);
  445. wake_up(&priv->bh_evt_wq);
  446. status = wait_event_interruptible(priv->bh_wq,
  447. CW1200_BH_RESUME == atomic_read(&priv->bh_suspend));
  448. if (status < 0) {
  449. wiphy_err(priv->hw->wiphy,
  450. "Failed to wait for resume: %ld.\n",
  451. status);
  452. break;
  453. }
  454. pr_debug("[BH] Device resume.\n");
  455. atomic_set(&priv->bh_suspend, CW1200_BH_RESUMED);
  456. wake_up(&priv->bh_evt_wq);
  457. atomic_add(1, &priv->bh_rx);
  458. goto done;
  459. }
  460. rx:
  461. tx += pending_tx;
  462. pending_tx = 0;
  463. if (cw1200_bh_read_ctrl_reg(priv, &ctrl_reg))
  464. break;
  465. /* Don't bother trying to rx unless we have data to read */
  466. if (ctrl_reg & ST90TDS_CONT_NEXT_LEN_MASK) {
  467. ret = cw1200_bh_rx_helper(priv, &ctrl_reg, &tx);
  468. if (ret < 0)
  469. break;
  470. /* Double up here if there's more data.. */
  471. if (ctrl_reg & ST90TDS_CONT_NEXT_LEN_MASK) {
  472. ret = cw1200_bh_rx_helper(priv, &ctrl_reg, &tx);
  473. if (ret < 0)
  474. break;
  475. }
  476. }
  477. tx:
  478. if (tx) {
  479. tx = 0;
  480. BUG_ON(priv->hw_bufs_used > priv->wsm_caps.input_buffers);
  481. tx_burst = priv->wsm_caps.input_buffers - priv->hw_bufs_used;
  482. tx_allowed = tx_burst > 0;
  483. if (!tx_allowed) {
  484. /* Buffers full. Ensure we process tx
  485. * after we handle rx..
  486. */
  487. pending_tx = tx;
  488. goto done_rx;
  489. }
  490. ret = cw1200_bh_tx_helper(priv, &pending_tx, &tx_burst);
  491. if (ret < 0)
  492. break;
  493. if (ret > 0) /* More to transmit */
  494. tx = ret;
  495. /* Re-read ctrl reg */
  496. if (cw1200_bh_read_ctrl_reg(priv, &ctrl_reg))
  497. break;
  498. }
  499. done_rx:
  500. if (priv->bh_error)
  501. break;
  502. if (ctrl_reg & ST90TDS_CONT_NEXT_LEN_MASK)
  503. goto rx;
  504. if (tx)
  505. goto tx;
  506. done:
  507. /* Re-enable device interrupts */
  508. priv->hwbus_ops->lock(priv->hwbus_priv);
  509. __cw1200_irq_enable(priv, 1);
  510. priv->hwbus_ops->unlock(priv->hwbus_priv);
  511. }
  512. /* Explicitly disable device interrupts */
  513. priv->hwbus_ops->lock(priv->hwbus_priv);
  514. __cw1200_irq_enable(priv, 0);
  515. priv->hwbus_ops->unlock(priv->hwbus_priv);
  516. if (!term) {
  517. pr_err("[BH] Fatal error, exiting.\n");
  518. priv->bh_error = 1;
  519. /* TODO: schedule_work(recovery) */
  520. }
  521. return 0;
  522. }