pinctrl-mtk-common.c 36 KB

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  1. /*
  2. * mt65xx pinctrl driver based on Allwinner A1X pinctrl driver.
  3. * Copyright (c) 2014 MediaTek Inc.
  4. * Author: Hongzhou.Yang <hongzhou.yang@mediatek.com>
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License version 2 as
  8. * published by the Free Software Foundation.
  9. *
  10. * This program is distributed in the hope that it will be useful,
  11. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  13. * GNU General Public License for more details.
  14. */
  15. #include <linux/io.h>
  16. #include <linux/gpio.h>
  17. #include <linux/module.h>
  18. #include <linux/of.h>
  19. #include <linux/of_address.h>
  20. #include <linux/of_device.h>
  21. #include <linux/of_irq.h>
  22. #include <linux/pinctrl/consumer.h>
  23. #include <linux/pinctrl/machine.h>
  24. #include <linux/pinctrl/pinconf.h>
  25. #include <linux/pinctrl/pinconf-generic.h>
  26. #include <linux/pinctrl/pinctrl.h>
  27. #include <linux/pinctrl/pinmux.h>
  28. #include <linux/platform_device.h>
  29. #include <linux/slab.h>
  30. #include <linux/bitops.h>
  31. #include <linux/regmap.h>
  32. #include <linux/mfd/syscon.h>
  33. #include <linux/delay.h>
  34. #include <linux/interrupt.h>
  35. #include <linux/pm.h>
  36. #include <dt-bindings/pinctrl/mt65xx.h>
  37. #include "../core.h"
  38. #include "../pinconf.h"
  39. #include "../pinctrl-utils.h"
  40. #include "pinctrl-mtk-common.h"
  41. #define MAX_GPIO_MODE_PER_REG 5
  42. #define GPIO_MODE_BITS 3
  43. static const char * const mtk_gpio_functions[] = {
  44. "func0", "func1", "func2", "func3",
  45. "func4", "func5", "func6", "func7",
  46. };
  47. /*
  48. * There are two base address for pull related configuration
  49. * in mt8135, and different GPIO pins use different base address.
  50. * When pin number greater than type1_start and less than type1_end,
  51. * should use the second base address.
  52. */
  53. static struct regmap *mtk_get_regmap(struct mtk_pinctrl *pctl,
  54. unsigned long pin)
  55. {
  56. if (pin >= pctl->devdata->type1_start && pin < pctl->devdata->type1_end)
  57. return pctl->regmap2;
  58. return pctl->regmap1;
  59. }
  60. static unsigned int mtk_get_port(struct mtk_pinctrl *pctl, unsigned long pin)
  61. {
  62. /* Different SoC has different mask and port shift. */
  63. return ((pin >> 4) & pctl->devdata->port_mask)
  64. << pctl->devdata->port_shf;
  65. }
  66. static int mtk_pmx_gpio_set_direction(struct pinctrl_dev *pctldev,
  67. struct pinctrl_gpio_range *range, unsigned offset,
  68. bool input)
  69. {
  70. unsigned int reg_addr;
  71. unsigned int bit;
  72. struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
  73. reg_addr = mtk_get_port(pctl, offset) + pctl->devdata->dir_offset;
  74. bit = BIT(offset & 0xf);
  75. if (input)
  76. /* Different SoC has different alignment offset. */
  77. reg_addr = CLR_ADDR(reg_addr, pctl);
  78. else
  79. reg_addr = SET_ADDR(reg_addr, pctl);
  80. regmap_write(mtk_get_regmap(pctl, offset), reg_addr, bit);
  81. return 0;
  82. }
  83. static void mtk_gpio_set(struct gpio_chip *chip, unsigned offset, int value)
  84. {
  85. unsigned int reg_addr;
  86. unsigned int bit;
  87. struct mtk_pinctrl *pctl = dev_get_drvdata(chip->dev);
  88. reg_addr = mtk_get_port(pctl, offset) + pctl->devdata->dout_offset;
  89. bit = BIT(offset & 0xf);
  90. if (value)
  91. reg_addr = SET_ADDR(reg_addr, pctl);
  92. else
  93. reg_addr = CLR_ADDR(reg_addr, pctl);
  94. regmap_write(mtk_get_regmap(pctl, offset), reg_addr, bit);
  95. }
  96. static int mtk_pconf_set_ies_smt(struct mtk_pinctrl *pctl, unsigned pin,
  97. int value, enum pin_config_param arg)
  98. {
  99. unsigned int reg_addr, offset;
  100. unsigned int bit;
  101. /**
  102. * Due to some soc are not support ies/smt config, add this special
  103. * control to handle it.
  104. */
  105. if (!pctl->devdata->spec_ies_smt_set &&
  106. pctl->devdata->ies_offset == MTK_PINCTRL_NOT_SUPPORT &&
  107. arg == PIN_CONFIG_INPUT_ENABLE)
  108. return -EINVAL;
  109. if (!pctl->devdata->spec_ies_smt_set &&
  110. pctl->devdata->smt_offset == MTK_PINCTRL_NOT_SUPPORT &&
  111. arg == PIN_CONFIG_INPUT_SCHMITT_ENABLE)
  112. return -EINVAL;
  113. /*
  114. * Due to some pins are irregular, their input enable and smt
  115. * control register are discontinuous, so we need this special handle.
  116. */
  117. if (pctl->devdata->spec_ies_smt_set) {
  118. return pctl->devdata->spec_ies_smt_set(mtk_get_regmap(pctl, pin),
  119. pin, pctl->devdata->port_align, value, arg);
  120. }
  121. bit = BIT(pin & 0xf);
  122. if (arg == PIN_CONFIG_INPUT_ENABLE)
  123. offset = pctl->devdata->ies_offset;
  124. else
  125. offset = pctl->devdata->smt_offset;
  126. if (value)
  127. reg_addr = SET_ADDR(mtk_get_port(pctl, pin) + offset, pctl);
  128. else
  129. reg_addr = CLR_ADDR(mtk_get_port(pctl, pin) + offset, pctl);
  130. regmap_write(mtk_get_regmap(pctl, pin), reg_addr, bit);
  131. return 0;
  132. }
  133. int mtk_pconf_spec_set_ies_smt_range(struct regmap *regmap,
  134. const struct mtk_pin_ies_smt_set *ies_smt_infos, unsigned int info_num,
  135. unsigned int pin, unsigned char align, int value)
  136. {
  137. unsigned int i, reg_addr, bit;
  138. for (i = 0; i < info_num; i++) {
  139. if (pin >= ies_smt_infos[i].start &&
  140. pin <= ies_smt_infos[i].end) {
  141. break;
  142. }
  143. }
  144. if (i == info_num)
  145. return -EINVAL;
  146. if (value)
  147. reg_addr = ies_smt_infos[i].offset + align;
  148. else
  149. reg_addr = ies_smt_infos[i].offset + (align << 1);
  150. bit = BIT(ies_smt_infos[i].bit);
  151. regmap_write(regmap, reg_addr, bit);
  152. return 0;
  153. }
  154. static const struct mtk_pin_drv_grp *mtk_find_pin_drv_grp_by_pin(
  155. struct mtk_pinctrl *pctl, unsigned long pin) {
  156. int i;
  157. for (i = 0; i < pctl->devdata->n_pin_drv_grps; i++) {
  158. const struct mtk_pin_drv_grp *pin_drv =
  159. pctl->devdata->pin_drv_grp + i;
  160. if (pin == pin_drv->pin)
  161. return pin_drv;
  162. }
  163. return NULL;
  164. }
  165. static int mtk_pconf_set_driving(struct mtk_pinctrl *pctl,
  166. unsigned int pin, unsigned char driving)
  167. {
  168. const struct mtk_pin_drv_grp *pin_drv;
  169. unsigned int val;
  170. unsigned int bits, mask, shift;
  171. const struct mtk_drv_group_desc *drv_grp;
  172. if (pin >= pctl->devdata->npins)
  173. return -EINVAL;
  174. pin_drv = mtk_find_pin_drv_grp_by_pin(pctl, pin);
  175. if (!pin_drv || pin_drv->grp > pctl->devdata->n_grp_cls)
  176. return -EINVAL;
  177. drv_grp = pctl->devdata->grp_desc + pin_drv->grp;
  178. if (driving >= drv_grp->min_drv && driving <= drv_grp->max_drv
  179. && !(driving % drv_grp->step)) {
  180. val = driving / drv_grp->step - 1;
  181. bits = drv_grp->high_bit - drv_grp->low_bit + 1;
  182. mask = BIT(bits) - 1;
  183. shift = pin_drv->bit + drv_grp->low_bit;
  184. mask <<= shift;
  185. val <<= shift;
  186. return regmap_update_bits(mtk_get_regmap(pctl, pin),
  187. pin_drv->offset, mask, val);
  188. }
  189. return -EINVAL;
  190. }
  191. int mtk_pctrl_spec_pull_set_samereg(struct regmap *regmap,
  192. const struct mtk_pin_spec_pupd_set_samereg *pupd_infos,
  193. unsigned int info_num, unsigned int pin,
  194. unsigned char align, bool isup, unsigned int r1r0)
  195. {
  196. unsigned int i;
  197. unsigned int reg_pupd, reg_set, reg_rst;
  198. unsigned int bit_pupd, bit_r0, bit_r1;
  199. const struct mtk_pin_spec_pupd_set_samereg *spec_pupd_pin;
  200. bool find = false;
  201. for (i = 0; i < info_num; i++) {
  202. if (pin == pupd_infos[i].pin) {
  203. find = true;
  204. break;
  205. }
  206. }
  207. if (!find)
  208. return -EINVAL;
  209. spec_pupd_pin = pupd_infos + i;
  210. reg_set = spec_pupd_pin->offset + align;
  211. reg_rst = spec_pupd_pin->offset + (align << 1);
  212. if (isup)
  213. reg_pupd = reg_rst;
  214. else
  215. reg_pupd = reg_set;
  216. bit_pupd = BIT(spec_pupd_pin->pupd_bit);
  217. regmap_write(regmap, reg_pupd, bit_pupd);
  218. bit_r0 = BIT(spec_pupd_pin->r0_bit);
  219. bit_r1 = BIT(spec_pupd_pin->r1_bit);
  220. switch (r1r0) {
  221. case MTK_PUPD_SET_R1R0_00:
  222. regmap_write(regmap, reg_rst, bit_r0);
  223. regmap_write(regmap, reg_rst, bit_r1);
  224. break;
  225. case MTK_PUPD_SET_R1R0_01:
  226. regmap_write(regmap, reg_set, bit_r0);
  227. regmap_write(regmap, reg_rst, bit_r1);
  228. break;
  229. case MTK_PUPD_SET_R1R0_10:
  230. regmap_write(regmap, reg_rst, bit_r0);
  231. regmap_write(regmap, reg_set, bit_r1);
  232. break;
  233. case MTK_PUPD_SET_R1R0_11:
  234. regmap_write(regmap, reg_set, bit_r0);
  235. regmap_write(regmap, reg_set, bit_r1);
  236. break;
  237. default:
  238. return -EINVAL;
  239. }
  240. return 0;
  241. }
  242. static int mtk_pconf_set_pull_select(struct mtk_pinctrl *pctl,
  243. unsigned int pin, bool enable, bool isup, unsigned int arg)
  244. {
  245. unsigned int bit;
  246. unsigned int reg_pullen, reg_pullsel;
  247. int ret;
  248. /* Some pins' pull setting are very different,
  249. * they have separate pull up/down bit, R0 and R1
  250. * resistor bit, so we need this special handle.
  251. */
  252. if (pctl->devdata->spec_pull_set) {
  253. ret = pctl->devdata->spec_pull_set(mtk_get_regmap(pctl, pin),
  254. pin, pctl->devdata->port_align, isup, arg);
  255. if (!ret)
  256. return 0;
  257. }
  258. /* For generic pull config, default arg value should be 0 or 1. */
  259. if (arg != 0 && arg != 1) {
  260. dev_err(pctl->dev, "invalid pull-up argument %d on pin %d .\n",
  261. arg, pin);
  262. return -EINVAL;
  263. }
  264. bit = BIT(pin & 0xf);
  265. if (enable)
  266. reg_pullen = SET_ADDR(mtk_get_port(pctl, pin) +
  267. pctl->devdata->pullen_offset, pctl);
  268. else
  269. reg_pullen = CLR_ADDR(mtk_get_port(pctl, pin) +
  270. pctl->devdata->pullen_offset, pctl);
  271. if (isup)
  272. reg_pullsel = SET_ADDR(mtk_get_port(pctl, pin) +
  273. pctl->devdata->pullsel_offset, pctl);
  274. else
  275. reg_pullsel = CLR_ADDR(mtk_get_port(pctl, pin) +
  276. pctl->devdata->pullsel_offset, pctl);
  277. regmap_write(mtk_get_regmap(pctl, pin), reg_pullen, bit);
  278. regmap_write(mtk_get_regmap(pctl, pin), reg_pullsel, bit);
  279. return 0;
  280. }
  281. static int mtk_pconf_parse_conf(struct pinctrl_dev *pctldev,
  282. unsigned int pin, enum pin_config_param param,
  283. enum pin_config_param arg)
  284. {
  285. int ret = 0;
  286. struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
  287. switch (param) {
  288. case PIN_CONFIG_BIAS_DISABLE:
  289. ret = mtk_pconf_set_pull_select(pctl, pin, false, false, arg);
  290. break;
  291. case PIN_CONFIG_BIAS_PULL_UP:
  292. ret = mtk_pconf_set_pull_select(pctl, pin, true, true, arg);
  293. break;
  294. case PIN_CONFIG_BIAS_PULL_DOWN:
  295. ret = mtk_pconf_set_pull_select(pctl, pin, true, false, arg);
  296. break;
  297. case PIN_CONFIG_INPUT_ENABLE:
  298. ret = mtk_pconf_set_ies_smt(pctl, pin, arg, param);
  299. break;
  300. case PIN_CONFIG_OUTPUT:
  301. mtk_gpio_set(pctl->chip, pin, arg);
  302. ret = mtk_pmx_gpio_set_direction(pctldev, NULL, pin, false);
  303. break;
  304. case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
  305. ret = mtk_pconf_set_ies_smt(pctl, pin, arg, param);
  306. break;
  307. case PIN_CONFIG_DRIVE_STRENGTH:
  308. ret = mtk_pconf_set_driving(pctl, pin, arg);
  309. break;
  310. default:
  311. ret = -EINVAL;
  312. }
  313. return ret;
  314. }
  315. static int mtk_pconf_group_get(struct pinctrl_dev *pctldev,
  316. unsigned group,
  317. unsigned long *config)
  318. {
  319. struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
  320. *config = pctl->groups[group].config;
  321. return 0;
  322. }
  323. static int mtk_pconf_group_set(struct pinctrl_dev *pctldev, unsigned group,
  324. unsigned long *configs, unsigned num_configs)
  325. {
  326. struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
  327. struct mtk_pinctrl_group *g = &pctl->groups[group];
  328. int i, ret;
  329. for (i = 0; i < num_configs; i++) {
  330. ret = mtk_pconf_parse_conf(pctldev, g->pin,
  331. pinconf_to_config_param(configs[i]),
  332. pinconf_to_config_argument(configs[i]));
  333. if (ret < 0)
  334. return ret;
  335. g->config = configs[i];
  336. }
  337. return 0;
  338. }
  339. static const struct pinconf_ops mtk_pconf_ops = {
  340. .pin_config_group_get = mtk_pconf_group_get,
  341. .pin_config_group_set = mtk_pconf_group_set,
  342. };
  343. static struct mtk_pinctrl_group *
  344. mtk_pctrl_find_group_by_pin(struct mtk_pinctrl *pctl, u32 pin)
  345. {
  346. int i;
  347. for (i = 0; i < pctl->ngroups; i++) {
  348. struct mtk_pinctrl_group *grp = pctl->groups + i;
  349. if (grp->pin == pin)
  350. return grp;
  351. }
  352. return NULL;
  353. }
  354. static const struct mtk_desc_function *mtk_pctrl_find_function_by_pin(
  355. struct mtk_pinctrl *pctl, u32 pin_num, u32 fnum)
  356. {
  357. const struct mtk_desc_pin *pin = pctl->devdata->pins + pin_num;
  358. const struct mtk_desc_function *func = pin->functions;
  359. while (func && func->name) {
  360. if (func->muxval == fnum)
  361. return func;
  362. func++;
  363. }
  364. return NULL;
  365. }
  366. static bool mtk_pctrl_is_function_valid(struct mtk_pinctrl *pctl,
  367. u32 pin_num, u32 fnum)
  368. {
  369. int i;
  370. for (i = 0; i < pctl->devdata->npins; i++) {
  371. const struct mtk_desc_pin *pin = pctl->devdata->pins + i;
  372. if (pin->pin.number == pin_num) {
  373. const struct mtk_desc_function *func =
  374. pin->functions;
  375. while (func && func->name) {
  376. if (func->muxval == fnum)
  377. return true;
  378. func++;
  379. }
  380. break;
  381. }
  382. }
  383. return false;
  384. }
  385. static int mtk_pctrl_dt_node_to_map_func(struct mtk_pinctrl *pctl,
  386. u32 pin, u32 fnum, struct mtk_pinctrl_group *grp,
  387. struct pinctrl_map **map, unsigned *reserved_maps,
  388. unsigned *num_maps)
  389. {
  390. bool ret;
  391. if (*num_maps == *reserved_maps)
  392. return -ENOSPC;
  393. (*map)[*num_maps].type = PIN_MAP_TYPE_MUX_GROUP;
  394. (*map)[*num_maps].data.mux.group = grp->name;
  395. ret = mtk_pctrl_is_function_valid(pctl, pin, fnum);
  396. if (!ret) {
  397. dev_err(pctl->dev, "invalid function %d on pin %d .\n",
  398. fnum, pin);
  399. return -EINVAL;
  400. }
  401. (*map)[*num_maps].data.mux.function = mtk_gpio_functions[fnum];
  402. (*num_maps)++;
  403. return 0;
  404. }
  405. static int mtk_pctrl_dt_subnode_to_map(struct pinctrl_dev *pctldev,
  406. struct device_node *node,
  407. struct pinctrl_map **map,
  408. unsigned *reserved_maps,
  409. unsigned *num_maps)
  410. {
  411. struct property *pins;
  412. u32 pinfunc, pin, func;
  413. int num_pins, num_funcs, maps_per_pin;
  414. unsigned long *configs;
  415. unsigned int num_configs;
  416. bool has_config = 0;
  417. int i, err;
  418. unsigned reserve = 0;
  419. struct mtk_pinctrl_group *grp;
  420. struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
  421. pins = of_find_property(node, "pinmux", NULL);
  422. if (!pins) {
  423. dev_err(pctl->dev, "missing pins property in node %s .\n",
  424. node->name);
  425. return -EINVAL;
  426. }
  427. err = pinconf_generic_parse_dt_config(node, pctldev, &configs,
  428. &num_configs);
  429. if (num_configs)
  430. has_config = 1;
  431. num_pins = pins->length / sizeof(u32);
  432. num_funcs = num_pins;
  433. maps_per_pin = 0;
  434. if (num_funcs)
  435. maps_per_pin++;
  436. if (has_config && num_pins >= 1)
  437. maps_per_pin++;
  438. if (!num_pins || !maps_per_pin)
  439. return -EINVAL;
  440. reserve = num_pins * maps_per_pin;
  441. err = pinctrl_utils_reserve_map(pctldev, map,
  442. reserved_maps, num_maps, reserve);
  443. if (err < 0)
  444. goto fail;
  445. for (i = 0; i < num_pins; i++) {
  446. err = of_property_read_u32_index(node, "pinmux",
  447. i, &pinfunc);
  448. if (err)
  449. goto fail;
  450. pin = MTK_GET_PIN_NO(pinfunc);
  451. func = MTK_GET_PIN_FUNC(pinfunc);
  452. if (pin >= pctl->devdata->npins ||
  453. func >= ARRAY_SIZE(mtk_gpio_functions)) {
  454. dev_err(pctl->dev, "invalid pins value.\n");
  455. err = -EINVAL;
  456. goto fail;
  457. }
  458. grp = mtk_pctrl_find_group_by_pin(pctl, pin);
  459. if (!grp) {
  460. dev_err(pctl->dev, "unable to match pin %d to group\n",
  461. pin);
  462. return -EINVAL;
  463. }
  464. err = mtk_pctrl_dt_node_to_map_func(pctl, pin, func, grp, map,
  465. reserved_maps, num_maps);
  466. if (err < 0)
  467. goto fail;
  468. if (has_config) {
  469. err = pinctrl_utils_add_map_configs(pctldev, map,
  470. reserved_maps, num_maps, grp->name,
  471. configs, num_configs,
  472. PIN_MAP_TYPE_CONFIGS_GROUP);
  473. if (err < 0)
  474. goto fail;
  475. }
  476. }
  477. return 0;
  478. fail:
  479. return err;
  480. }
  481. static int mtk_pctrl_dt_node_to_map(struct pinctrl_dev *pctldev,
  482. struct device_node *np_config,
  483. struct pinctrl_map **map, unsigned *num_maps)
  484. {
  485. struct device_node *np;
  486. unsigned reserved_maps;
  487. int ret;
  488. *map = NULL;
  489. *num_maps = 0;
  490. reserved_maps = 0;
  491. for_each_child_of_node(np_config, np) {
  492. ret = mtk_pctrl_dt_subnode_to_map(pctldev, np, map,
  493. &reserved_maps, num_maps);
  494. if (ret < 0) {
  495. pinctrl_utils_dt_free_map(pctldev, *map, *num_maps);
  496. return ret;
  497. }
  498. }
  499. return 0;
  500. }
  501. static int mtk_pctrl_get_groups_count(struct pinctrl_dev *pctldev)
  502. {
  503. struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
  504. return pctl->ngroups;
  505. }
  506. static const char *mtk_pctrl_get_group_name(struct pinctrl_dev *pctldev,
  507. unsigned group)
  508. {
  509. struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
  510. return pctl->groups[group].name;
  511. }
  512. static int mtk_pctrl_get_group_pins(struct pinctrl_dev *pctldev,
  513. unsigned group,
  514. const unsigned **pins,
  515. unsigned *num_pins)
  516. {
  517. struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
  518. *pins = (unsigned *)&pctl->groups[group].pin;
  519. *num_pins = 1;
  520. return 0;
  521. }
  522. static const struct pinctrl_ops mtk_pctrl_ops = {
  523. .dt_node_to_map = mtk_pctrl_dt_node_to_map,
  524. .dt_free_map = pinctrl_utils_dt_free_map,
  525. .get_groups_count = mtk_pctrl_get_groups_count,
  526. .get_group_name = mtk_pctrl_get_group_name,
  527. .get_group_pins = mtk_pctrl_get_group_pins,
  528. };
  529. static int mtk_pmx_get_funcs_cnt(struct pinctrl_dev *pctldev)
  530. {
  531. return ARRAY_SIZE(mtk_gpio_functions);
  532. }
  533. static const char *mtk_pmx_get_func_name(struct pinctrl_dev *pctldev,
  534. unsigned selector)
  535. {
  536. return mtk_gpio_functions[selector];
  537. }
  538. static int mtk_pmx_get_func_groups(struct pinctrl_dev *pctldev,
  539. unsigned function,
  540. const char * const **groups,
  541. unsigned * const num_groups)
  542. {
  543. struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
  544. *groups = pctl->grp_names;
  545. *num_groups = pctl->ngroups;
  546. return 0;
  547. }
  548. static int mtk_pmx_set_mode(struct pinctrl_dev *pctldev,
  549. unsigned long pin, unsigned long mode)
  550. {
  551. unsigned int reg_addr;
  552. unsigned char bit;
  553. unsigned int val;
  554. unsigned int mask = (1L << GPIO_MODE_BITS) - 1;
  555. struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
  556. reg_addr = ((pin / MAX_GPIO_MODE_PER_REG) << pctl->devdata->port_shf)
  557. + pctl->devdata->pinmux_offset;
  558. bit = pin % MAX_GPIO_MODE_PER_REG;
  559. mask <<= (GPIO_MODE_BITS * bit);
  560. val = (mode << (GPIO_MODE_BITS * bit));
  561. return regmap_update_bits(mtk_get_regmap(pctl, pin),
  562. reg_addr, mask, val);
  563. }
  564. static const struct mtk_desc_pin *
  565. mtk_find_pin_by_eint_num(struct mtk_pinctrl *pctl, unsigned int eint_num)
  566. {
  567. int i;
  568. const struct mtk_desc_pin *pin;
  569. for (i = 0; i < pctl->devdata->npins; i++) {
  570. pin = pctl->devdata->pins + i;
  571. if (pin->eint.eintnum == eint_num)
  572. return pin;
  573. }
  574. return NULL;
  575. }
  576. static int mtk_pmx_set_mux(struct pinctrl_dev *pctldev,
  577. unsigned function,
  578. unsigned group)
  579. {
  580. bool ret;
  581. const struct mtk_desc_function *desc;
  582. struct mtk_pinctrl *pctl = pinctrl_dev_get_drvdata(pctldev);
  583. struct mtk_pinctrl_group *g = pctl->groups + group;
  584. ret = mtk_pctrl_is_function_valid(pctl, g->pin, function);
  585. if (!ret) {
  586. dev_err(pctl->dev, "invalid function %d on group %d .\n",
  587. function, group);
  588. return -EINVAL;
  589. }
  590. desc = mtk_pctrl_find_function_by_pin(pctl, g->pin, function);
  591. if (!desc)
  592. return -EINVAL;
  593. mtk_pmx_set_mode(pctldev, g->pin, desc->muxval);
  594. return 0;
  595. }
  596. static const struct pinmux_ops mtk_pmx_ops = {
  597. .get_functions_count = mtk_pmx_get_funcs_cnt,
  598. .get_function_name = mtk_pmx_get_func_name,
  599. .get_function_groups = mtk_pmx_get_func_groups,
  600. .set_mux = mtk_pmx_set_mux,
  601. .gpio_set_direction = mtk_pmx_gpio_set_direction,
  602. };
  603. static int mtk_gpio_direction_input(struct gpio_chip *chip,
  604. unsigned offset)
  605. {
  606. return pinctrl_gpio_direction_input(chip->base + offset);
  607. }
  608. static int mtk_gpio_direction_output(struct gpio_chip *chip,
  609. unsigned offset, int value)
  610. {
  611. mtk_gpio_set(chip, offset, value);
  612. return pinctrl_gpio_direction_output(chip->base + offset);
  613. }
  614. static int mtk_gpio_get_direction(struct gpio_chip *chip, unsigned offset)
  615. {
  616. unsigned int reg_addr;
  617. unsigned int bit;
  618. unsigned int read_val = 0;
  619. struct mtk_pinctrl *pctl = dev_get_drvdata(chip->dev);
  620. reg_addr = mtk_get_port(pctl, offset) + pctl->devdata->dir_offset;
  621. bit = BIT(offset & 0xf);
  622. regmap_read(pctl->regmap1, reg_addr, &read_val);
  623. return !(read_val & bit);
  624. }
  625. static int mtk_gpio_get(struct gpio_chip *chip, unsigned offset)
  626. {
  627. unsigned int reg_addr;
  628. unsigned int bit;
  629. unsigned int read_val = 0;
  630. struct mtk_pinctrl *pctl = dev_get_drvdata(chip->dev);
  631. reg_addr = mtk_get_port(pctl, offset) +
  632. pctl->devdata->din_offset;
  633. bit = BIT(offset & 0xf);
  634. regmap_read(pctl->regmap1, reg_addr, &read_val);
  635. return !!(read_val & bit);
  636. }
  637. static int mtk_gpio_to_irq(struct gpio_chip *chip, unsigned offset)
  638. {
  639. const struct mtk_desc_pin *pin;
  640. struct mtk_pinctrl *pctl = dev_get_drvdata(chip->dev);
  641. int irq;
  642. pin = pctl->devdata->pins + offset;
  643. if (pin->eint.eintnum == NO_EINT_SUPPORT)
  644. return -EINVAL;
  645. irq = irq_find_mapping(pctl->domain, pin->eint.eintnum);
  646. if (!irq)
  647. return -EINVAL;
  648. return irq;
  649. }
  650. static int mtk_pinctrl_irq_request_resources(struct irq_data *d)
  651. {
  652. struct mtk_pinctrl *pctl = irq_data_get_irq_chip_data(d);
  653. const struct mtk_desc_pin *pin;
  654. int ret;
  655. pin = mtk_find_pin_by_eint_num(pctl, d->hwirq);
  656. if (!pin) {
  657. dev_err(pctl->dev, "Can not find pin\n");
  658. return -EINVAL;
  659. }
  660. ret = gpiochip_lock_as_irq(pctl->chip, pin->pin.number);
  661. if (ret) {
  662. dev_err(pctl->dev, "unable to lock HW IRQ %lu for IRQ\n",
  663. irqd_to_hwirq(d));
  664. return ret;
  665. }
  666. /* set mux to INT mode */
  667. mtk_pmx_set_mode(pctl->pctl_dev, pin->pin.number, pin->eint.eintmux);
  668. return 0;
  669. }
  670. static void mtk_pinctrl_irq_release_resources(struct irq_data *d)
  671. {
  672. struct mtk_pinctrl *pctl = irq_data_get_irq_chip_data(d);
  673. const struct mtk_desc_pin *pin;
  674. pin = mtk_find_pin_by_eint_num(pctl, d->hwirq);
  675. if (!pin) {
  676. dev_err(pctl->dev, "Can not find pin\n");
  677. return;
  678. }
  679. gpiochip_unlock_as_irq(pctl->chip, pin->pin.number);
  680. }
  681. static void __iomem *mtk_eint_get_offset(struct mtk_pinctrl *pctl,
  682. unsigned int eint_num, unsigned int offset)
  683. {
  684. unsigned int eint_base = 0;
  685. void __iomem *reg;
  686. if (eint_num >= pctl->devdata->ap_num)
  687. eint_base = pctl->devdata->ap_num;
  688. reg = pctl->eint_reg_base + offset + ((eint_num - eint_base) / 32) * 4;
  689. return reg;
  690. }
  691. /*
  692. * mtk_can_en_debounce: Check the EINT number is able to enable debounce or not
  693. * @eint_num: the EINT number to setmtk_pinctrl
  694. */
  695. static unsigned int mtk_eint_can_en_debounce(struct mtk_pinctrl *pctl,
  696. unsigned int eint_num)
  697. {
  698. unsigned int sens;
  699. unsigned int bit = BIT(eint_num % 32);
  700. const struct mtk_eint_offsets *eint_offsets =
  701. &pctl->devdata->eint_offsets;
  702. void __iomem *reg = mtk_eint_get_offset(pctl, eint_num,
  703. eint_offsets->sens);
  704. if (readl(reg) & bit)
  705. sens = MT_LEVEL_SENSITIVE;
  706. else
  707. sens = MT_EDGE_SENSITIVE;
  708. if ((eint_num < pctl->devdata->db_cnt) && (sens != MT_EDGE_SENSITIVE))
  709. return 1;
  710. else
  711. return 0;
  712. }
  713. /*
  714. * mtk_eint_get_mask: To get the eint mask
  715. * @eint_num: the EINT number to get
  716. */
  717. static unsigned int mtk_eint_get_mask(struct mtk_pinctrl *pctl,
  718. unsigned int eint_num)
  719. {
  720. unsigned int bit = BIT(eint_num % 32);
  721. const struct mtk_eint_offsets *eint_offsets =
  722. &pctl->devdata->eint_offsets;
  723. void __iomem *reg = mtk_eint_get_offset(pctl, eint_num,
  724. eint_offsets->mask);
  725. return !!(readl(reg) & bit);
  726. }
  727. static int mtk_eint_flip_edge(struct mtk_pinctrl *pctl, int hwirq)
  728. {
  729. int start_level, curr_level;
  730. unsigned int reg_offset;
  731. const struct mtk_eint_offsets *eint_offsets = &(pctl->devdata->eint_offsets);
  732. u32 mask = BIT(hwirq & 0x1f);
  733. u32 port = (hwirq >> 5) & eint_offsets->port_mask;
  734. void __iomem *reg = pctl->eint_reg_base + (port << 2);
  735. const struct mtk_desc_pin *pin;
  736. pin = mtk_find_pin_by_eint_num(pctl, hwirq);
  737. curr_level = mtk_gpio_get(pctl->chip, pin->pin.number);
  738. do {
  739. start_level = curr_level;
  740. if (start_level)
  741. reg_offset = eint_offsets->pol_clr;
  742. else
  743. reg_offset = eint_offsets->pol_set;
  744. writel(mask, reg + reg_offset);
  745. curr_level = mtk_gpio_get(pctl->chip, pin->pin.number);
  746. } while (start_level != curr_level);
  747. return start_level;
  748. }
  749. static void mtk_eint_mask(struct irq_data *d)
  750. {
  751. struct mtk_pinctrl *pctl = irq_data_get_irq_chip_data(d);
  752. const struct mtk_eint_offsets *eint_offsets =
  753. &pctl->devdata->eint_offsets;
  754. u32 mask = BIT(d->hwirq & 0x1f);
  755. void __iomem *reg = mtk_eint_get_offset(pctl, d->hwirq,
  756. eint_offsets->mask_set);
  757. writel(mask, reg);
  758. }
  759. static void mtk_eint_unmask(struct irq_data *d)
  760. {
  761. struct mtk_pinctrl *pctl = irq_data_get_irq_chip_data(d);
  762. const struct mtk_eint_offsets *eint_offsets =
  763. &pctl->devdata->eint_offsets;
  764. u32 mask = BIT(d->hwirq & 0x1f);
  765. void __iomem *reg = mtk_eint_get_offset(pctl, d->hwirq,
  766. eint_offsets->mask_clr);
  767. writel(mask, reg);
  768. if (pctl->eint_dual_edges[d->hwirq])
  769. mtk_eint_flip_edge(pctl, d->hwirq);
  770. }
  771. static int mtk_gpio_set_debounce(struct gpio_chip *chip, unsigned offset,
  772. unsigned debounce)
  773. {
  774. struct mtk_pinctrl *pctl = dev_get_drvdata(chip->dev);
  775. int eint_num, virq, eint_offset;
  776. unsigned int set_offset, bit, clr_bit, clr_offset, rst, i, unmask, dbnc;
  777. static const unsigned int debounce_time[] = {500, 1000, 16000, 32000, 64000,
  778. 128000, 256000};
  779. const struct mtk_desc_pin *pin;
  780. struct irq_data *d;
  781. pin = pctl->devdata->pins + offset;
  782. if (pin->eint.eintnum == NO_EINT_SUPPORT)
  783. return -EINVAL;
  784. eint_num = pin->eint.eintnum;
  785. virq = irq_find_mapping(pctl->domain, eint_num);
  786. eint_offset = (eint_num % 4) * 8;
  787. d = irq_get_irq_data(virq);
  788. set_offset = (eint_num / 4) * 4 + pctl->devdata->eint_offsets.dbnc_set;
  789. clr_offset = (eint_num / 4) * 4 + pctl->devdata->eint_offsets.dbnc_clr;
  790. if (!mtk_eint_can_en_debounce(pctl, eint_num))
  791. return -ENOSYS;
  792. dbnc = ARRAY_SIZE(debounce_time);
  793. for (i = 0; i < ARRAY_SIZE(debounce_time); i++) {
  794. if (debounce <= debounce_time[i]) {
  795. dbnc = i;
  796. break;
  797. }
  798. }
  799. if (!mtk_eint_get_mask(pctl, eint_num)) {
  800. mtk_eint_mask(d);
  801. unmask = 1;
  802. } else {
  803. unmask = 0;
  804. }
  805. clr_bit = 0xff << eint_offset;
  806. writel(clr_bit, pctl->eint_reg_base + clr_offset);
  807. bit = ((dbnc << EINT_DBNC_SET_DBNC_BITS) | EINT_DBNC_SET_EN) <<
  808. eint_offset;
  809. rst = EINT_DBNC_RST_BIT << eint_offset;
  810. writel(rst | bit, pctl->eint_reg_base + set_offset);
  811. /* Delay a while (more than 2T) to wait for hw debounce counter reset
  812. work correctly */
  813. udelay(1);
  814. if (unmask == 1)
  815. mtk_eint_unmask(d);
  816. return 0;
  817. }
  818. static struct gpio_chip mtk_gpio_chip = {
  819. .owner = THIS_MODULE,
  820. .request = gpiochip_generic_request,
  821. .free = gpiochip_generic_free,
  822. .get_direction = mtk_gpio_get_direction,
  823. .direction_input = mtk_gpio_direction_input,
  824. .direction_output = mtk_gpio_direction_output,
  825. .get = mtk_gpio_get,
  826. .set = mtk_gpio_set,
  827. .to_irq = mtk_gpio_to_irq,
  828. .set_debounce = mtk_gpio_set_debounce,
  829. .of_gpio_n_cells = 2,
  830. };
  831. static int mtk_eint_set_type(struct irq_data *d,
  832. unsigned int type)
  833. {
  834. struct mtk_pinctrl *pctl = irq_data_get_irq_chip_data(d);
  835. const struct mtk_eint_offsets *eint_offsets =
  836. &pctl->devdata->eint_offsets;
  837. u32 mask = BIT(d->hwirq & 0x1f);
  838. void __iomem *reg;
  839. if (((type & IRQ_TYPE_EDGE_BOTH) && (type & IRQ_TYPE_LEVEL_MASK)) ||
  840. ((type & IRQ_TYPE_LEVEL_MASK) == IRQ_TYPE_LEVEL_MASK)) {
  841. dev_err(pctl->dev, "Can't configure IRQ%d (EINT%lu) for type 0x%X\n",
  842. d->irq, d->hwirq, type);
  843. return -EINVAL;
  844. }
  845. if ((type & IRQ_TYPE_EDGE_BOTH) == IRQ_TYPE_EDGE_BOTH)
  846. pctl->eint_dual_edges[d->hwirq] = 1;
  847. else
  848. pctl->eint_dual_edges[d->hwirq] = 0;
  849. if (type & (IRQ_TYPE_LEVEL_LOW | IRQ_TYPE_EDGE_FALLING)) {
  850. reg = mtk_eint_get_offset(pctl, d->hwirq,
  851. eint_offsets->pol_clr);
  852. writel(mask, reg);
  853. } else {
  854. reg = mtk_eint_get_offset(pctl, d->hwirq,
  855. eint_offsets->pol_set);
  856. writel(mask, reg);
  857. }
  858. if (type & (IRQ_TYPE_EDGE_RISING | IRQ_TYPE_EDGE_FALLING)) {
  859. reg = mtk_eint_get_offset(pctl, d->hwirq,
  860. eint_offsets->sens_clr);
  861. writel(mask, reg);
  862. } else {
  863. reg = mtk_eint_get_offset(pctl, d->hwirq,
  864. eint_offsets->sens_set);
  865. writel(mask, reg);
  866. }
  867. if (pctl->eint_dual_edges[d->hwirq])
  868. mtk_eint_flip_edge(pctl, d->hwirq);
  869. return 0;
  870. }
  871. static int mtk_eint_irq_set_wake(struct irq_data *d, unsigned int on)
  872. {
  873. struct mtk_pinctrl *pctl = irq_data_get_irq_chip_data(d);
  874. int shift = d->hwirq & 0x1f;
  875. int reg = d->hwirq >> 5;
  876. if (on)
  877. pctl->wake_mask[reg] |= BIT(shift);
  878. else
  879. pctl->wake_mask[reg] &= ~BIT(shift);
  880. return 0;
  881. }
  882. static void mtk_eint_chip_write_mask(const struct mtk_eint_offsets *chip,
  883. void __iomem *eint_reg_base, u32 *buf)
  884. {
  885. int port;
  886. void __iomem *reg;
  887. for (port = 0; port < chip->ports; port++) {
  888. reg = eint_reg_base + (port << 2);
  889. writel_relaxed(~buf[port], reg + chip->mask_set);
  890. writel_relaxed(buf[port], reg + chip->mask_clr);
  891. }
  892. }
  893. static void mtk_eint_chip_read_mask(const struct mtk_eint_offsets *chip,
  894. void __iomem *eint_reg_base, u32 *buf)
  895. {
  896. int port;
  897. void __iomem *reg;
  898. for (port = 0; port < chip->ports; port++) {
  899. reg = eint_reg_base + chip->mask + (port << 2);
  900. buf[port] = ~readl_relaxed(reg);
  901. /* Mask is 0 when irq is enabled, and 1 when disabled. */
  902. }
  903. }
  904. static int mtk_eint_suspend(struct device *device)
  905. {
  906. void __iomem *reg;
  907. struct mtk_pinctrl *pctl = dev_get_drvdata(device);
  908. const struct mtk_eint_offsets *eint_offsets =
  909. &pctl->devdata->eint_offsets;
  910. reg = pctl->eint_reg_base;
  911. mtk_eint_chip_read_mask(eint_offsets, reg, pctl->cur_mask);
  912. mtk_eint_chip_write_mask(eint_offsets, reg, pctl->wake_mask);
  913. return 0;
  914. }
  915. static int mtk_eint_resume(struct device *device)
  916. {
  917. struct mtk_pinctrl *pctl = dev_get_drvdata(device);
  918. const struct mtk_eint_offsets *eint_offsets =
  919. &pctl->devdata->eint_offsets;
  920. mtk_eint_chip_write_mask(eint_offsets,
  921. pctl->eint_reg_base, pctl->cur_mask);
  922. return 0;
  923. }
  924. const struct dev_pm_ops mtk_eint_pm_ops = {
  925. .suspend = mtk_eint_suspend,
  926. .resume = mtk_eint_resume,
  927. };
  928. static void mtk_eint_ack(struct irq_data *d)
  929. {
  930. struct mtk_pinctrl *pctl = irq_data_get_irq_chip_data(d);
  931. const struct mtk_eint_offsets *eint_offsets =
  932. &pctl->devdata->eint_offsets;
  933. u32 mask = BIT(d->hwirq & 0x1f);
  934. void __iomem *reg = mtk_eint_get_offset(pctl, d->hwirq,
  935. eint_offsets->ack);
  936. writel(mask, reg);
  937. }
  938. static struct irq_chip mtk_pinctrl_irq_chip = {
  939. .name = "mt-eint",
  940. .irq_disable = mtk_eint_mask,
  941. .irq_mask = mtk_eint_mask,
  942. .irq_unmask = mtk_eint_unmask,
  943. .irq_ack = mtk_eint_ack,
  944. .irq_set_type = mtk_eint_set_type,
  945. .irq_set_wake = mtk_eint_irq_set_wake,
  946. .irq_request_resources = mtk_pinctrl_irq_request_resources,
  947. .irq_release_resources = mtk_pinctrl_irq_release_resources,
  948. };
  949. static unsigned int mtk_eint_init(struct mtk_pinctrl *pctl)
  950. {
  951. const struct mtk_eint_offsets *eint_offsets =
  952. &pctl->devdata->eint_offsets;
  953. void __iomem *reg = pctl->eint_reg_base + eint_offsets->dom_en;
  954. unsigned int i;
  955. for (i = 0; i < pctl->devdata->ap_num; i += 32) {
  956. writel(0xffffffff, reg);
  957. reg += 4;
  958. }
  959. return 0;
  960. }
  961. static inline void
  962. mtk_eint_debounce_process(struct mtk_pinctrl *pctl, int index)
  963. {
  964. unsigned int rst, ctrl_offset;
  965. unsigned int bit, dbnc;
  966. const struct mtk_eint_offsets *eint_offsets =
  967. &pctl->devdata->eint_offsets;
  968. ctrl_offset = (index / 4) * 4 + eint_offsets->dbnc_ctrl;
  969. dbnc = readl(pctl->eint_reg_base + ctrl_offset);
  970. bit = EINT_DBNC_SET_EN << ((index % 4) * 8);
  971. if ((bit & dbnc) > 0) {
  972. ctrl_offset = (index / 4) * 4 + eint_offsets->dbnc_set;
  973. rst = EINT_DBNC_RST_BIT << ((index % 4) * 8);
  974. writel(rst, pctl->eint_reg_base + ctrl_offset);
  975. }
  976. }
  977. static void mtk_eint_irq_handler(struct irq_desc *desc)
  978. {
  979. struct irq_chip *chip = irq_desc_get_chip(desc);
  980. struct mtk_pinctrl *pctl = irq_desc_get_handler_data(desc);
  981. unsigned int status, eint_num;
  982. int offset, index, virq;
  983. const struct mtk_eint_offsets *eint_offsets =
  984. &pctl->devdata->eint_offsets;
  985. void __iomem *reg = mtk_eint_get_offset(pctl, 0, eint_offsets->stat);
  986. int dual_edges, start_level, curr_level;
  987. const struct mtk_desc_pin *pin;
  988. chained_irq_enter(chip, desc);
  989. for (eint_num = 0;
  990. eint_num < pctl->devdata->ap_num;
  991. eint_num += 32, reg += 4) {
  992. status = readl(reg);
  993. while (status) {
  994. offset = __ffs(status);
  995. index = eint_num + offset;
  996. virq = irq_find_mapping(pctl->domain, index);
  997. status &= ~BIT(offset);
  998. dual_edges = pctl->eint_dual_edges[index];
  999. if (dual_edges) {
  1000. /* Clear soft-irq in case we raised it
  1001. last time */
  1002. writel(BIT(offset), reg - eint_offsets->stat +
  1003. eint_offsets->soft_clr);
  1004. pin = mtk_find_pin_by_eint_num(pctl, index);
  1005. start_level = mtk_gpio_get(pctl->chip,
  1006. pin->pin.number);
  1007. }
  1008. generic_handle_irq(virq);
  1009. if (dual_edges) {
  1010. curr_level = mtk_eint_flip_edge(pctl, index);
  1011. /* If level changed, we might lost one edge
  1012. interrupt, raised it through soft-irq */
  1013. if (start_level != curr_level)
  1014. writel(BIT(offset), reg -
  1015. eint_offsets->stat +
  1016. eint_offsets->soft_set);
  1017. }
  1018. if (index < pctl->devdata->db_cnt)
  1019. mtk_eint_debounce_process(pctl , index);
  1020. }
  1021. }
  1022. chained_irq_exit(chip, desc);
  1023. }
  1024. static int mtk_pctrl_build_state(struct platform_device *pdev)
  1025. {
  1026. struct mtk_pinctrl *pctl = platform_get_drvdata(pdev);
  1027. int i;
  1028. pctl->ngroups = pctl->devdata->npins;
  1029. /* Allocate groups */
  1030. pctl->groups = devm_kcalloc(&pdev->dev, pctl->ngroups,
  1031. sizeof(*pctl->groups), GFP_KERNEL);
  1032. if (!pctl->groups)
  1033. return -ENOMEM;
  1034. /* We assume that one pin is one group, use pin name as group name. */
  1035. pctl->grp_names = devm_kcalloc(&pdev->dev, pctl->ngroups,
  1036. sizeof(*pctl->grp_names), GFP_KERNEL);
  1037. if (!pctl->grp_names)
  1038. return -ENOMEM;
  1039. for (i = 0; i < pctl->devdata->npins; i++) {
  1040. const struct mtk_desc_pin *pin = pctl->devdata->pins + i;
  1041. struct mtk_pinctrl_group *group = pctl->groups + i;
  1042. group->name = pin->pin.name;
  1043. group->pin = pin->pin.number;
  1044. pctl->grp_names[i] = pin->pin.name;
  1045. }
  1046. return 0;
  1047. }
  1048. int mtk_pctrl_init(struct platform_device *pdev,
  1049. const struct mtk_pinctrl_devdata *data,
  1050. struct regmap *regmap)
  1051. {
  1052. struct pinctrl_pin_desc *pins;
  1053. struct mtk_pinctrl *pctl;
  1054. struct device_node *np = pdev->dev.of_node, *node;
  1055. struct property *prop;
  1056. struct resource *res;
  1057. int i, ret, irq, ports_buf;
  1058. pctl = devm_kzalloc(&pdev->dev, sizeof(*pctl), GFP_KERNEL);
  1059. if (!pctl)
  1060. return -ENOMEM;
  1061. platform_set_drvdata(pdev, pctl);
  1062. prop = of_find_property(np, "pins-are-numbered", NULL);
  1063. if (!prop) {
  1064. dev_err(&pdev->dev, "only support pins-are-numbered format\n");
  1065. return -EINVAL;
  1066. }
  1067. node = of_parse_phandle(np, "mediatek,pctl-regmap", 0);
  1068. if (node) {
  1069. pctl->regmap1 = syscon_node_to_regmap(node);
  1070. if (IS_ERR(pctl->regmap1))
  1071. return PTR_ERR(pctl->regmap1);
  1072. } else if (regmap) {
  1073. pctl->regmap1 = regmap;
  1074. } else {
  1075. dev_err(&pdev->dev, "Pinctrl node has not register regmap.\n");
  1076. return -EINVAL;
  1077. }
  1078. /* Only 8135 has two base addr, other SoCs have only one. */
  1079. node = of_parse_phandle(np, "mediatek,pctl-regmap", 1);
  1080. if (node) {
  1081. pctl->regmap2 = syscon_node_to_regmap(node);
  1082. if (IS_ERR(pctl->regmap2))
  1083. return PTR_ERR(pctl->regmap2);
  1084. }
  1085. pctl->devdata = data;
  1086. ret = mtk_pctrl_build_state(pdev);
  1087. if (ret) {
  1088. dev_err(&pdev->dev, "build state failed: %d\n", ret);
  1089. return -EINVAL;
  1090. }
  1091. pins = devm_kcalloc(&pdev->dev, pctl->devdata->npins, sizeof(*pins),
  1092. GFP_KERNEL);
  1093. if (!pins)
  1094. return -ENOMEM;
  1095. for (i = 0; i < pctl->devdata->npins; i++)
  1096. pins[i] = pctl->devdata->pins[i].pin;
  1097. pctl->pctl_desc.name = dev_name(&pdev->dev);
  1098. pctl->pctl_desc.owner = THIS_MODULE;
  1099. pctl->pctl_desc.pins = pins;
  1100. pctl->pctl_desc.npins = pctl->devdata->npins;
  1101. pctl->pctl_desc.confops = &mtk_pconf_ops;
  1102. pctl->pctl_desc.pctlops = &mtk_pctrl_ops;
  1103. pctl->pctl_desc.pmxops = &mtk_pmx_ops;
  1104. pctl->dev = &pdev->dev;
  1105. pctl->pctl_dev = pinctrl_register(&pctl->pctl_desc, &pdev->dev, pctl);
  1106. if (IS_ERR(pctl->pctl_dev)) {
  1107. dev_err(&pdev->dev, "couldn't register pinctrl driver\n");
  1108. return PTR_ERR(pctl->pctl_dev);
  1109. }
  1110. pctl->chip = devm_kzalloc(&pdev->dev, sizeof(*pctl->chip), GFP_KERNEL);
  1111. if (!pctl->chip) {
  1112. ret = -ENOMEM;
  1113. goto pctrl_error;
  1114. }
  1115. *pctl->chip = mtk_gpio_chip;
  1116. pctl->chip->ngpio = pctl->devdata->npins;
  1117. pctl->chip->label = dev_name(&pdev->dev);
  1118. pctl->chip->dev = &pdev->dev;
  1119. pctl->chip->base = -1;
  1120. ret = gpiochip_add(pctl->chip);
  1121. if (ret) {
  1122. ret = -EINVAL;
  1123. goto pctrl_error;
  1124. }
  1125. /* Register the GPIO to pin mappings. */
  1126. ret = gpiochip_add_pin_range(pctl->chip, dev_name(&pdev->dev),
  1127. 0, 0, pctl->devdata->npins);
  1128. if (ret) {
  1129. ret = -EINVAL;
  1130. goto chip_error;
  1131. }
  1132. if (!of_property_read_bool(np, "interrupt-controller"))
  1133. return 0;
  1134. /* Get EINT register base from dts. */
  1135. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  1136. if (!res) {
  1137. dev_err(&pdev->dev, "Unable to get Pinctrl resource\n");
  1138. ret = -EINVAL;
  1139. goto chip_error;
  1140. }
  1141. pctl->eint_reg_base = devm_ioremap_resource(&pdev->dev, res);
  1142. if (IS_ERR(pctl->eint_reg_base)) {
  1143. ret = -EINVAL;
  1144. goto chip_error;
  1145. }
  1146. ports_buf = pctl->devdata->eint_offsets.ports;
  1147. pctl->wake_mask = devm_kcalloc(&pdev->dev, ports_buf,
  1148. sizeof(*pctl->wake_mask), GFP_KERNEL);
  1149. if (!pctl->wake_mask) {
  1150. ret = -ENOMEM;
  1151. goto chip_error;
  1152. }
  1153. pctl->cur_mask = devm_kcalloc(&pdev->dev, ports_buf,
  1154. sizeof(*pctl->cur_mask), GFP_KERNEL);
  1155. if (!pctl->cur_mask) {
  1156. ret = -ENOMEM;
  1157. goto chip_error;
  1158. }
  1159. pctl->eint_dual_edges = devm_kcalloc(&pdev->dev, pctl->devdata->ap_num,
  1160. sizeof(int), GFP_KERNEL);
  1161. if (!pctl->eint_dual_edges) {
  1162. ret = -ENOMEM;
  1163. goto chip_error;
  1164. }
  1165. irq = irq_of_parse_and_map(np, 0);
  1166. if (!irq) {
  1167. dev_err(&pdev->dev, "couldn't parse and map irq\n");
  1168. ret = -EINVAL;
  1169. goto chip_error;
  1170. }
  1171. pctl->domain = irq_domain_add_linear(np,
  1172. pctl->devdata->ap_num, &irq_domain_simple_ops, NULL);
  1173. if (!pctl->domain) {
  1174. dev_err(&pdev->dev, "Couldn't register IRQ domain\n");
  1175. ret = -ENOMEM;
  1176. goto chip_error;
  1177. }
  1178. mtk_eint_init(pctl);
  1179. for (i = 0; i < pctl->devdata->ap_num; i++) {
  1180. int virq = irq_create_mapping(pctl->domain, i);
  1181. irq_set_chip_and_handler(virq, &mtk_pinctrl_irq_chip,
  1182. handle_level_irq);
  1183. irq_set_chip_data(virq, pctl);
  1184. }
  1185. irq_set_chained_handler_and_data(irq, mtk_eint_irq_handler, pctl);
  1186. return 0;
  1187. chip_error:
  1188. gpiochip_remove(pctl->chip);
  1189. pctrl_error:
  1190. pinctrl_unregister(pctl->pctl_dev);
  1191. return ret;
  1192. }
  1193. MODULE_LICENSE("GPL");
  1194. MODULE_DESCRIPTION("MediaTek Pinctrl Driver");
  1195. MODULE_AUTHOR("Hongzhou Yang <hongzhou.yang@mediatek.com>");