aic79xx_reg_print.c_shipped 19 KB

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  1. /*
  2. * DO NOT EDIT - This file is automatically generated
  3. * from the following source files:
  4. *
  5. * $Id: //depot/aic7xxx/aic7xxx/aic79xx.seq#120 $
  6. * $Id: //depot/aic7xxx/aic7xxx/aic79xx.reg#77 $
  7. */
  8. #include "aic79xx_osm.h"
  9. static const ahd_reg_parse_entry_t INTSTAT_parse_table[] = {
  10. { "SPLTINT", 0x01, 0x01 },
  11. { "CMDCMPLT", 0x02, 0x02 },
  12. { "SEQINT", 0x04, 0x04 },
  13. { "SCSIINT", 0x08, 0x08 },
  14. { "PCIINT", 0x10, 0x10 },
  15. { "SWTMINT", 0x20, 0x20 },
  16. { "BRKADRINT", 0x40, 0x40 },
  17. { "HWERRINT", 0x80, 0x80 },
  18. { "INT_PEND", 0xff, 0xff }
  19. };
  20. int
  21. ahd_intstat_print(u_int regvalue, u_int *cur_col, u_int wrap)
  22. {
  23. return (ahd_print_register(INTSTAT_parse_table, 9, "INTSTAT",
  24. 0x01, regvalue, cur_col, wrap));
  25. }
  26. static const ahd_reg_parse_entry_t HS_MAILBOX_parse_table[] = {
  27. { "ENINT_COALESCE", 0x40, 0x40 },
  28. { "HOST_TQINPOS", 0x80, 0x80 }
  29. };
  30. int
  31. ahd_hs_mailbox_print(u_int regvalue, u_int *cur_col, u_int wrap)
  32. {
  33. return (ahd_print_register(HS_MAILBOX_parse_table, 2, "HS_MAILBOX",
  34. 0x0b, regvalue, cur_col, wrap));
  35. }
  36. static const ahd_reg_parse_entry_t SEQINTSTAT_parse_table[] = {
  37. { "SEQ_SPLTINT", 0x01, 0x01 },
  38. { "SEQ_PCIINT", 0x02, 0x02 },
  39. { "SEQ_SCSIINT", 0x04, 0x04 },
  40. { "SEQ_SEQINT", 0x08, 0x08 },
  41. { "SEQ_SWTMRTO", 0x10, 0x10 }
  42. };
  43. int
  44. ahd_seqintstat_print(u_int regvalue, u_int *cur_col, u_int wrap)
  45. {
  46. return (ahd_print_register(SEQINTSTAT_parse_table, 5, "SEQINTSTAT",
  47. 0x0c, regvalue, cur_col, wrap));
  48. }
  49. static const ahd_reg_parse_entry_t INTCTL_parse_table[] = {
  50. { "SPLTINTEN", 0x01, 0x01 },
  51. { "SEQINTEN", 0x02, 0x02 },
  52. { "SCSIINTEN", 0x04, 0x04 },
  53. { "PCIINTEN", 0x08, 0x08 },
  54. { "AUTOCLRCMDINT", 0x10, 0x10 },
  55. { "SWTIMER_START", 0x20, 0x20 },
  56. { "SWTMINTEN", 0x40, 0x40 },
  57. { "SWTMINTMASK", 0x80, 0x80 }
  58. };
  59. int
  60. ahd_intctl_print(u_int regvalue, u_int *cur_col, u_int wrap)
  61. {
  62. return (ahd_print_register(INTCTL_parse_table, 8, "INTCTL",
  63. 0x18, regvalue, cur_col, wrap));
  64. }
  65. static const ahd_reg_parse_entry_t DFCNTRL_parse_table[] = {
  66. { "DIRECTIONEN", 0x01, 0x01 },
  67. { "FIFOFLUSH", 0x02, 0x02 },
  68. { "FIFOFLUSHACK", 0x02, 0x02 },
  69. { "DIRECTION", 0x04, 0x04 },
  70. { "DIRECTIONACK", 0x04, 0x04 },
  71. { "HDMAEN", 0x08, 0x08 },
  72. { "HDMAENACK", 0x08, 0x08 },
  73. { "SCSIEN", 0x20, 0x20 },
  74. { "SCSIENACK", 0x20, 0x20 },
  75. { "SCSIENWRDIS", 0x40, 0x40 },
  76. { "PRELOADEN", 0x80, 0x80 }
  77. };
  78. int
  79. ahd_dfcntrl_print(u_int regvalue, u_int *cur_col, u_int wrap)
  80. {
  81. return (ahd_print_register(DFCNTRL_parse_table, 11, "DFCNTRL",
  82. 0x19, regvalue, cur_col, wrap));
  83. }
  84. static const ahd_reg_parse_entry_t DFSTATUS_parse_table[] = {
  85. { "FIFOEMP", 0x01, 0x01 },
  86. { "FIFOFULL", 0x02, 0x02 },
  87. { "DFTHRESH", 0x04, 0x04 },
  88. { "HDONE", 0x08, 0x08 },
  89. { "MREQPEND", 0x10, 0x10 },
  90. { "PKT_PRELOAD_AVAIL", 0x40, 0x40 },
  91. { "PRELOAD_AVAIL", 0x80, 0x80 }
  92. };
  93. int
  94. ahd_dfstatus_print(u_int regvalue, u_int *cur_col, u_int wrap)
  95. {
  96. return (ahd_print_register(DFSTATUS_parse_table, 7, "DFSTATUS",
  97. 0x1a, regvalue, cur_col, wrap));
  98. }
  99. static const ahd_reg_parse_entry_t SG_CACHE_SHADOW_parse_table[] = {
  100. { "LAST_SEG_DONE", 0x01, 0x01 },
  101. { "LAST_SEG", 0x02, 0x02 },
  102. { "ODD_SEG", 0x04, 0x04 },
  103. { "SG_ADDR_MASK", 0xf8, 0xf8 }
  104. };
  105. int
  106. ahd_sg_cache_shadow_print(u_int regvalue, u_int *cur_col, u_int wrap)
  107. {
  108. return (ahd_print_register(SG_CACHE_SHADOW_parse_table, 4, "SG_CACHE_SHADOW",
  109. 0x1b, regvalue, cur_col, wrap));
  110. }
  111. static const ahd_reg_parse_entry_t SCSISEQ0_parse_table[] = {
  112. { "SCSIRSTO", 0x01, 0x01 },
  113. { "FORCEBUSFREE", 0x10, 0x10 },
  114. { "ENARBO", 0x20, 0x20 },
  115. { "ENSELO", 0x40, 0x40 },
  116. { "TEMODEO", 0x80, 0x80 }
  117. };
  118. int
  119. ahd_scsiseq0_print(u_int regvalue, u_int *cur_col, u_int wrap)
  120. {
  121. return (ahd_print_register(SCSISEQ0_parse_table, 5, "SCSISEQ0",
  122. 0x3a, regvalue, cur_col, wrap));
  123. }
  124. static const ahd_reg_parse_entry_t SCSISEQ1_parse_table[] = {
  125. { "ALTSTIM", 0x01, 0x01 },
  126. { "ENAUTOATNP", 0x02, 0x02 },
  127. { "MANUALP", 0x0c, 0x0c },
  128. { "ENRSELI", 0x10, 0x10 },
  129. { "ENSELI", 0x20, 0x20 },
  130. { "MANUALCTL", 0x40, 0x40 }
  131. };
  132. int
  133. ahd_scsiseq1_print(u_int regvalue, u_int *cur_col, u_int wrap)
  134. {
  135. return (ahd_print_register(SCSISEQ1_parse_table, 6, "SCSISEQ1",
  136. 0x3b, regvalue, cur_col, wrap));
  137. }
  138. static const ahd_reg_parse_entry_t DFFSTAT_parse_table[] = {
  139. { "CURRFIFO_0", 0x00, 0x03 },
  140. { "CURRFIFO_1", 0x01, 0x03 },
  141. { "CURRFIFO_NONE", 0x03, 0x03 },
  142. { "FIFO0FREE", 0x10, 0x10 },
  143. { "FIFO1FREE", 0x20, 0x20 },
  144. { "CURRFIFO", 0x03, 0x03 }
  145. };
  146. int
  147. ahd_dffstat_print(u_int regvalue, u_int *cur_col, u_int wrap)
  148. {
  149. return (ahd_print_register(DFFSTAT_parse_table, 6, "DFFSTAT",
  150. 0x3f, regvalue, cur_col, wrap));
  151. }
  152. static const ahd_reg_parse_entry_t SCSISIGI_parse_table[] = {
  153. { "P_DATAOUT", 0x00, 0xe0 },
  154. { "P_DATAOUT_DT", 0x20, 0xe0 },
  155. { "P_DATAIN", 0x40, 0xe0 },
  156. { "P_DATAIN_DT", 0x60, 0xe0 },
  157. { "P_COMMAND", 0x80, 0xe0 },
  158. { "P_MESGOUT", 0xa0, 0xe0 },
  159. { "P_STATUS", 0xc0, 0xe0 },
  160. { "P_MESGIN", 0xe0, 0xe0 },
  161. { "ACKI", 0x01, 0x01 },
  162. { "REQI", 0x02, 0x02 },
  163. { "BSYI", 0x04, 0x04 },
  164. { "SELI", 0x08, 0x08 },
  165. { "ATNI", 0x10, 0x10 },
  166. { "MSGI", 0x20, 0x20 },
  167. { "IOI", 0x40, 0x40 },
  168. { "CDI", 0x80, 0x80 },
  169. { "PHASE_MASK", 0xe0, 0xe0 }
  170. };
  171. int
  172. ahd_scsisigi_print(u_int regvalue, u_int *cur_col, u_int wrap)
  173. {
  174. return (ahd_print_register(SCSISIGI_parse_table, 17, "SCSISIGI",
  175. 0x41, regvalue, cur_col, wrap));
  176. }
  177. static const ahd_reg_parse_entry_t SCSIPHASE_parse_table[] = {
  178. { "DATA_OUT_PHASE", 0x01, 0x03 },
  179. { "DATA_IN_PHASE", 0x02, 0x03 },
  180. { "DATA_PHASE_MASK", 0x03, 0x03 },
  181. { "MSG_OUT_PHASE", 0x04, 0x04 },
  182. { "MSG_IN_PHASE", 0x08, 0x08 },
  183. { "COMMAND_PHASE", 0x10, 0x10 },
  184. { "STATUS_PHASE", 0x20, 0x20 }
  185. };
  186. int
  187. ahd_scsiphase_print(u_int regvalue, u_int *cur_col, u_int wrap)
  188. {
  189. return (ahd_print_register(SCSIPHASE_parse_table, 7, "SCSIPHASE",
  190. 0x42, regvalue, cur_col, wrap));
  191. }
  192. int
  193. ahd_scsibus_print(u_int regvalue, u_int *cur_col, u_int wrap)
  194. {
  195. return (ahd_print_register(NULL, 0, "SCSIBUS",
  196. 0x46, regvalue, cur_col, wrap));
  197. }
  198. static const ahd_reg_parse_entry_t SELID_parse_table[] = {
  199. { "ONEBIT", 0x08, 0x08 },
  200. { "SELID_MASK", 0xf0, 0xf0 }
  201. };
  202. int
  203. ahd_selid_print(u_int regvalue, u_int *cur_col, u_int wrap)
  204. {
  205. return (ahd_print_register(SELID_parse_table, 2, "SELID",
  206. 0x49, regvalue, cur_col, wrap));
  207. }
  208. static const ahd_reg_parse_entry_t SSTAT0_parse_table[] = {
  209. { "ARBDO", 0x01, 0x01 },
  210. { "SPIORDY", 0x02, 0x02 },
  211. { "OVERRUN", 0x04, 0x04 },
  212. { "IOERR", 0x08, 0x08 },
  213. { "SELINGO", 0x10, 0x10 },
  214. { "SELDI", 0x20, 0x20 },
  215. { "SELDO", 0x40, 0x40 },
  216. { "TARGET", 0x80, 0x80 }
  217. };
  218. int
  219. ahd_sstat0_print(u_int regvalue, u_int *cur_col, u_int wrap)
  220. {
  221. return (ahd_print_register(SSTAT0_parse_table, 8, "SSTAT0",
  222. 0x4b, regvalue, cur_col, wrap));
  223. }
  224. static const ahd_reg_parse_entry_t SIMODE0_parse_table[] = {
  225. { "ENARBDO", 0x01, 0x01 },
  226. { "ENSPIORDY", 0x02, 0x02 },
  227. { "ENOVERRUN", 0x04, 0x04 },
  228. { "ENIOERR", 0x08, 0x08 },
  229. { "ENSELINGO", 0x10, 0x10 },
  230. { "ENSELDI", 0x20, 0x20 },
  231. { "ENSELDO", 0x40, 0x40 }
  232. };
  233. int
  234. ahd_simode0_print(u_int regvalue, u_int *cur_col, u_int wrap)
  235. {
  236. return (ahd_print_register(SIMODE0_parse_table, 7, "SIMODE0",
  237. 0x4b, regvalue, cur_col, wrap));
  238. }
  239. static const ahd_reg_parse_entry_t SSTAT1_parse_table[] = {
  240. { "REQINIT", 0x01, 0x01 },
  241. { "STRB2FAST", 0x02, 0x02 },
  242. { "SCSIPERR", 0x04, 0x04 },
  243. { "BUSFREE", 0x08, 0x08 },
  244. { "PHASEMIS", 0x10, 0x10 },
  245. { "SCSIRSTI", 0x20, 0x20 },
  246. { "ATNTARG", 0x40, 0x40 },
  247. { "SELTO", 0x80, 0x80 }
  248. };
  249. int
  250. ahd_sstat1_print(u_int regvalue, u_int *cur_col, u_int wrap)
  251. {
  252. return (ahd_print_register(SSTAT1_parse_table, 8, "SSTAT1",
  253. 0x4c, regvalue, cur_col, wrap));
  254. }
  255. static const ahd_reg_parse_entry_t SSTAT2_parse_table[] = {
  256. { "BUSFREE_LQO", 0x40, 0xc0 },
  257. { "BUSFREE_DFF0", 0x80, 0xc0 },
  258. { "BUSFREE_DFF1", 0xc0, 0xc0 },
  259. { "DMADONE", 0x01, 0x01 },
  260. { "SDONE", 0x02, 0x02 },
  261. { "WIDE_RES", 0x04, 0x04 },
  262. { "BSYX", 0x08, 0x08 },
  263. { "EXP_ACTIVE", 0x10, 0x10 },
  264. { "NONPACKREQ", 0x20, 0x20 },
  265. { "BUSFREETIME", 0xc0, 0xc0 }
  266. };
  267. int
  268. ahd_sstat2_print(u_int regvalue, u_int *cur_col, u_int wrap)
  269. {
  270. return (ahd_print_register(SSTAT2_parse_table, 10, "SSTAT2",
  271. 0x4d, regvalue, cur_col, wrap));
  272. }
  273. static const ahd_reg_parse_entry_t PERRDIAG_parse_table[] = {
  274. { "DTERR", 0x01, 0x01 },
  275. { "DGFORMERR", 0x02, 0x02 },
  276. { "CRCERR", 0x04, 0x04 },
  277. { "AIPERR", 0x08, 0x08 },
  278. { "PARITYERR", 0x10, 0x10 },
  279. { "PREVPHASE", 0x20, 0x20 },
  280. { "HIPERR", 0x40, 0x40 },
  281. { "HIZERO", 0x80, 0x80 }
  282. };
  283. int
  284. ahd_perrdiag_print(u_int regvalue, u_int *cur_col, u_int wrap)
  285. {
  286. return (ahd_print_register(PERRDIAG_parse_table, 8, "PERRDIAG",
  287. 0x4e, regvalue, cur_col, wrap));
  288. }
  289. int
  290. ahd_soffcnt_print(u_int regvalue, u_int *cur_col, u_int wrap)
  291. {
  292. return (ahd_print_register(NULL, 0, "SOFFCNT",
  293. 0x4f, regvalue, cur_col, wrap));
  294. }
  295. static const ahd_reg_parse_entry_t LQISTAT0_parse_table[] = {
  296. { "LQIATNCMD", 0x01, 0x01 },
  297. { "LQIATNLQ", 0x02, 0x02 },
  298. { "LQIBADLQT", 0x04, 0x04 },
  299. { "LQICRCT2", 0x08, 0x08 },
  300. { "LQICRCT1", 0x10, 0x10 },
  301. { "LQIATNQAS", 0x20, 0x20 }
  302. };
  303. int
  304. ahd_lqistat0_print(u_int regvalue, u_int *cur_col, u_int wrap)
  305. {
  306. return (ahd_print_register(LQISTAT0_parse_table, 6, "LQISTAT0",
  307. 0x50, regvalue, cur_col, wrap));
  308. }
  309. static const ahd_reg_parse_entry_t LQISTAT1_parse_table[] = {
  310. { "LQIOVERI_NLQ", 0x01, 0x01 },
  311. { "LQIOVERI_LQ", 0x02, 0x02 },
  312. { "LQIBADLQI", 0x04, 0x04 },
  313. { "LQICRCI_NLQ", 0x08, 0x08 },
  314. { "LQICRCI_LQ", 0x10, 0x10 },
  315. { "LQIABORT", 0x20, 0x20 },
  316. { "LQIPHASE_NLQ", 0x40, 0x40 },
  317. { "LQIPHASE_LQ", 0x80, 0x80 }
  318. };
  319. int
  320. ahd_lqistat1_print(u_int regvalue, u_int *cur_col, u_int wrap)
  321. {
  322. return (ahd_print_register(LQISTAT1_parse_table, 8, "LQISTAT1",
  323. 0x51, regvalue, cur_col, wrap));
  324. }
  325. static const ahd_reg_parse_entry_t LQISTAT2_parse_table[] = {
  326. { "LQIGSAVAIL", 0x01, 0x01 },
  327. { "LQISTOPCMD", 0x02, 0x02 },
  328. { "LQISTOPLQ", 0x04, 0x04 },
  329. { "LQISTOPPKT", 0x08, 0x08 },
  330. { "LQIWAITFIFO", 0x10, 0x10 },
  331. { "LQIWORKONLQ", 0x20, 0x20 },
  332. { "LQIPHASE_OUTPKT", 0x40, 0x40 },
  333. { "PACKETIZED", 0x80, 0x80 }
  334. };
  335. int
  336. ahd_lqistat2_print(u_int regvalue, u_int *cur_col, u_int wrap)
  337. {
  338. return (ahd_print_register(LQISTAT2_parse_table, 8, "LQISTAT2",
  339. 0x52, regvalue, cur_col, wrap));
  340. }
  341. static const ahd_reg_parse_entry_t SSTAT3_parse_table[] = {
  342. { "OSRAMPERR", 0x01, 0x01 },
  343. { "NTRAMPERR", 0x02, 0x02 }
  344. };
  345. int
  346. ahd_sstat3_print(u_int regvalue, u_int *cur_col, u_int wrap)
  347. {
  348. return (ahd_print_register(SSTAT3_parse_table, 2, "SSTAT3",
  349. 0x53, regvalue, cur_col, wrap));
  350. }
  351. static const ahd_reg_parse_entry_t LQOSTAT0_parse_table[] = {
  352. { "LQOTCRC", 0x01, 0x01 },
  353. { "LQOATNPKT", 0x02, 0x02 },
  354. { "LQOATNLQ", 0x04, 0x04 },
  355. { "LQOSTOPT2", 0x08, 0x08 },
  356. { "LQOTARGSCBPERR", 0x10, 0x10 }
  357. };
  358. int
  359. ahd_lqostat0_print(u_int regvalue, u_int *cur_col, u_int wrap)
  360. {
  361. return (ahd_print_register(LQOSTAT0_parse_table, 5, "LQOSTAT0",
  362. 0x54, regvalue, cur_col, wrap));
  363. }
  364. static const ahd_reg_parse_entry_t LQOSTAT1_parse_table[] = {
  365. { "LQOPHACHGINPKT", 0x01, 0x01 },
  366. { "LQOBUSFREE", 0x02, 0x02 },
  367. { "LQOBADQAS", 0x04, 0x04 },
  368. { "LQOSTOPI2", 0x08, 0x08 },
  369. { "LQOINITSCBPERR", 0x10, 0x10 }
  370. };
  371. int
  372. ahd_lqostat1_print(u_int regvalue, u_int *cur_col, u_int wrap)
  373. {
  374. return (ahd_print_register(LQOSTAT1_parse_table, 5, "LQOSTAT1",
  375. 0x55, regvalue, cur_col, wrap));
  376. }
  377. static const ahd_reg_parse_entry_t LQOSTAT2_parse_table[] = {
  378. { "LQOSTOP0", 0x01, 0x01 },
  379. { "LQOPHACHGOUTPKT", 0x02, 0x02 },
  380. { "LQOWAITFIFO", 0x10, 0x10 },
  381. { "LQOPKT", 0xe0, 0xe0 }
  382. };
  383. int
  384. ahd_lqostat2_print(u_int regvalue, u_int *cur_col, u_int wrap)
  385. {
  386. return (ahd_print_register(LQOSTAT2_parse_table, 4, "LQOSTAT2",
  387. 0x56, regvalue, cur_col, wrap));
  388. }
  389. static const ahd_reg_parse_entry_t SIMODE1_parse_table[] = {
  390. { "ENREQINIT", 0x01, 0x01 },
  391. { "ENSTRB2FAST", 0x02, 0x02 },
  392. { "ENSCSIPERR", 0x04, 0x04 },
  393. { "ENBUSFREE", 0x08, 0x08 },
  394. { "ENPHASEMIS", 0x10, 0x10 },
  395. { "ENSCSIRST", 0x20, 0x20 },
  396. { "ENATNTARG", 0x40, 0x40 },
  397. { "ENSELTIMO", 0x80, 0x80 }
  398. };
  399. int
  400. ahd_simode1_print(u_int regvalue, u_int *cur_col, u_int wrap)
  401. {
  402. return (ahd_print_register(SIMODE1_parse_table, 8, "SIMODE1",
  403. 0x57, regvalue, cur_col, wrap));
  404. }
  405. static const ahd_reg_parse_entry_t DFFSXFRCTL_parse_table[] = {
  406. { "RSTCHN", 0x01, 0x01 },
  407. { "CLRCHN", 0x02, 0x02 },
  408. { "CLRSHCNT", 0x04, 0x04 },
  409. { "DFFBITBUCKET", 0x08, 0x08 }
  410. };
  411. int
  412. ahd_dffsxfrctl_print(u_int regvalue, u_int *cur_col, u_int wrap)
  413. {
  414. return (ahd_print_register(DFFSXFRCTL_parse_table, 4, "DFFSXFRCTL",
  415. 0x5a, regvalue, cur_col, wrap));
  416. }
  417. static const ahd_reg_parse_entry_t SEQINTSRC_parse_table[] = {
  418. { "CFG4TCMD", 0x01, 0x01 },
  419. { "CFG4ICMD", 0x02, 0x02 },
  420. { "CFG4TSTAT", 0x04, 0x04 },
  421. { "CFG4ISTAT", 0x08, 0x08 },
  422. { "CFG4DATA", 0x10, 0x10 },
  423. { "SAVEPTRS", 0x20, 0x20 },
  424. { "CTXTDONE", 0x40, 0x40 }
  425. };
  426. int
  427. ahd_seqintsrc_print(u_int regvalue, u_int *cur_col, u_int wrap)
  428. {
  429. return (ahd_print_register(SEQINTSRC_parse_table, 7, "SEQINTSRC",
  430. 0x5b, regvalue, cur_col, wrap));
  431. }
  432. static const ahd_reg_parse_entry_t SEQIMODE_parse_table[] = {
  433. { "ENCFG4TCMD", 0x01, 0x01 },
  434. { "ENCFG4ICMD", 0x02, 0x02 },
  435. { "ENCFG4TSTAT", 0x04, 0x04 },
  436. { "ENCFG4ISTAT", 0x08, 0x08 },
  437. { "ENCFG4DATA", 0x10, 0x10 },
  438. { "ENSAVEPTRS", 0x20, 0x20 },
  439. { "ENCTXTDONE", 0x40, 0x40 }
  440. };
  441. int
  442. ahd_seqimode_print(u_int regvalue, u_int *cur_col, u_int wrap)
  443. {
  444. return (ahd_print_register(SEQIMODE_parse_table, 7, "SEQIMODE",
  445. 0x5c, regvalue, cur_col, wrap));
  446. }
  447. static const ahd_reg_parse_entry_t MDFFSTAT_parse_table[] = {
  448. { "FIFOFREE", 0x01, 0x01 },
  449. { "DATAINFIFO", 0x02, 0x02 },
  450. { "DLZERO", 0x04, 0x04 },
  451. { "SHVALID", 0x08, 0x08 },
  452. { "LASTSDONE", 0x10, 0x10 },
  453. { "SHCNTMINUS1", 0x20, 0x20 },
  454. { "SHCNTNEGATIVE", 0x40, 0x40 }
  455. };
  456. int
  457. ahd_mdffstat_print(u_int regvalue, u_int *cur_col, u_int wrap)
  458. {
  459. return (ahd_print_register(MDFFSTAT_parse_table, 7, "MDFFSTAT",
  460. 0x5d, regvalue, cur_col, wrap));
  461. }
  462. int
  463. ahd_seloid_print(u_int regvalue, u_int *cur_col, u_int wrap)
  464. {
  465. return (ahd_print_register(NULL, 0, "SELOID",
  466. 0x6b, regvalue, cur_col, wrap));
  467. }
  468. static const ahd_reg_parse_entry_t SG_STATE_parse_table[] = {
  469. { "SEGS_AVAIL", 0x01, 0x01 },
  470. { "LOADING_NEEDED", 0x02, 0x02 },
  471. { "FETCH_INPROG", 0x04, 0x04 }
  472. };
  473. int
  474. ahd_sg_state_print(u_int regvalue, u_int *cur_col, u_int wrap)
  475. {
  476. return (ahd_print_register(SG_STATE_parse_table, 3, "SG_STATE",
  477. 0xa6, regvalue, cur_col, wrap));
  478. }
  479. static const ahd_reg_parse_entry_t CCSCBCTL_parse_table[] = {
  480. { "CCSCBRESET", 0x01, 0x01 },
  481. { "CCSCBDIR", 0x04, 0x04 },
  482. { "CCSCBEN", 0x08, 0x08 },
  483. { "CCARREN", 0x10, 0x10 },
  484. { "ARRDONE", 0x40, 0x40 },
  485. { "CCSCBDONE", 0x80, 0x80 }
  486. };
  487. int
  488. ahd_ccscbctl_print(u_int regvalue, u_int *cur_col, u_int wrap)
  489. {
  490. return (ahd_print_register(CCSCBCTL_parse_table, 6, "CCSCBCTL",
  491. 0xad, regvalue, cur_col, wrap));
  492. }
  493. static const ahd_reg_parse_entry_t CCSGCTL_parse_table[] = {
  494. { "CCSGRESET", 0x01, 0x01 },
  495. { "SG_FETCH_REQ", 0x02, 0x02 },
  496. { "CCSGENACK", 0x08, 0x08 },
  497. { "SG_CACHE_AVAIL", 0x10, 0x10 },
  498. { "CCSGDONE", 0x80, 0x80 },
  499. { "CCSGEN", 0x0c, 0x0c }
  500. };
  501. int
  502. ahd_ccsgctl_print(u_int regvalue, u_int *cur_col, u_int wrap)
  503. {
  504. return (ahd_print_register(CCSGCTL_parse_table, 6, "CCSGCTL",
  505. 0xad, regvalue, cur_col, wrap));
  506. }
  507. static const ahd_reg_parse_entry_t SEQCTL0_parse_table[] = {
  508. { "LOADRAM", 0x01, 0x01 },
  509. { "SEQRESET", 0x02, 0x02 },
  510. { "STEP", 0x04, 0x04 },
  511. { "BRKADRINTEN", 0x08, 0x08 },
  512. { "FASTMODE", 0x10, 0x10 },
  513. { "FAILDIS", 0x20, 0x20 },
  514. { "PAUSEDIS", 0x40, 0x40 },
  515. { "PERRORDIS", 0x80, 0x80 }
  516. };
  517. int
  518. ahd_seqctl0_print(u_int regvalue, u_int *cur_col, u_int wrap)
  519. {
  520. return (ahd_print_register(SEQCTL0_parse_table, 8, "SEQCTL0",
  521. 0xd6, regvalue, cur_col, wrap));
  522. }
  523. static const ahd_reg_parse_entry_t SEQINTCTL_parse_table[] = {
  524. { "IRET", 0x01, 0x01 },
  525. { "INTMASK1", 0x02, 0x02 },
  526. { "INTMASK2", 0x04, 0x04 },
  527. { "SCS_SEQ_INT1M0", 0x08, 0x08 },
  528. { "SCS_SEQ_INT1M1", 0x10, 0x10 },
  529. { "INT1_CONTEXT", 0x20, 0x20 },
  530. { "INTVEC1DSL", 0x80, 0x80 }
  531. };
  532. int
  533. ahd_seqintctl_print(u_int regvalue, u_int *cur_col, u_int wrap)
  534. {
  535. return (ahd_print_register(SEQINTCTL_parse_table, 7, "SEQINTCTL",
  536. 0xd9, regvalue, cur_col, wrap));
  537. }
  538. int
  539. ahd_sram_base_print(u_int regvalue, u_int *cur_col, u_int wrap)
  540. {
  541. return (ahd_print_register(NULL, 0, "SRAM_BASE",
  542. 0x100, regvalue, cur_col, wrap));
  543. }
  544. int
  545. ahd_qfreeze_count_print(u_int regvalue, u_int *cur_col, u_int wrap)
  546. {
  547. return (ahd_print_register(NULL, 0, "QFREEZE_COUNT",
  548. 0x132, regvalue, cur_col, wrap));
  549. }
  550. int
  551. ahd_kernel_qfreeze_count_print(u_int regvalue, u_int *cur_col, u_int wrap)
  552. {
  553. return (ahd_print_register(NULL, 0, "KERNEL_QFREEZE_COUNT",
  554. 0x134, regvalue, cur_col, wrap));
  555. }
  556. int
  557. ahd_saved_mode_print(u_int regvalue, u_int *cur_col, u_int wrap)
  558. {
  559. return (ahd_print_register(NULL, 0, "SAVED_MODE",
  560. 0x136, regvalue, cur_col, wrap));
  561. }
  562. static const ahd_reg_parse_entry_t SEQ_FLAGS_parse_table[] = {
  563. { "NO_DISCONNECT", 0x01, 0x01 },
  564. { "SPHASE_PENDING", 0x02, 0x02 },
  565. { "DPHASE_PENDING", 0x04, 0x04 },
  566. { "CMDPHASE_PENDING", 0x08, 0x08 },
  567. { "TARG_CMD_PENDING", 0x10, 0x10 },
  568. { "DPHASE", 0x20, 0x20 },
  569. { "NO_CDB_SENT", 0x40, 0x40 },
  570. { "TARGET_CMD_IS_TAGGED",0x40, 0x40 },
  571. { "NOT_IDENTIFIED", 0x80, 0x80 }
  572. };
  573. int
  574. ahd_seq_flags_print(u_int regvalue, u_int *cur_col, u_int wrap)
  575. {
  576. return (ahd_print_register(SEQ_FLAGS_parse_table, 9, "SEQ_FLAGS",
  577. 0x139, regvalue, cur_col, wrap));
  578. }
  579. static const ahd_reg_parse_entry_t LASTPHASE_parse_table[] = {
  580. { "P_DATAOUT", 0x00, 0xe0 },
  581. { "P_DATAOUT_DT", 0x20, 0xe0 },
  582. { "P_DATAIN", 0x40, 0xe0 },
  583. { "P_DATAIN_DT", 0x60, 0xe0 },
  584. { "P_COMMAND", 0x80, 0xe0 },
  585. { "P_MESGOUT", 0xa0, 0xe0 },
  586. { "P_STATUS", 0xc0, 0xe0 },
  587. { "P_MESGIN", 0xe0, 0xe0 },
  588. { "P_BUSFREE", 0x01, 0x01 },
  589. { "MSGI", 0x20, 0x20 },
  590. { "IOI", 0x40, 0x40 },
  591. { "CDI", 0x80, 0x80 },
  592. { "PHASE_MASK", 0xe0, 0xe0 }
  593. };
  594. int
  595. ahd_lastphase_print(u_int regvalue, u_int *cur_col, u_int wrap)
  596. {
  597. return (ahd_print_register(LASTPHASE_parse_table, 13, "LASTPHASE",
  598. 0x13c, regvalue, cur_col, wrap));
  599. }
  600. static const ahd_reg_parse_entry_t SEQ_FLAGS2_parse_table[] = {
  601. { "PENDING_MK_MESSAGE", 0x01, 0x01 },
  602. { "TARGET_MSG_PENDING", 0x02, 0x02 },
  603. { "SELECTOUT_QFROZEN", 0x04, 0x04 }
  604. };
  605. int
  606. ahd_seq_flags2_print(u_int regvalue, u_int *cur_col, u_int wrap)
  607. {
  608. return (ahd_print_register(SEQ_FLAGS2_parse_table, 3, "SEQ_FLAGS2",
  609. 0x14d, regvalue, cur_col, wrap));
  610. }
  611. int
  612. ahd_mk_message_scb_print(u_int regvalue, u_int *cur_col, u_int wrap)
  613. {
  614. return (ahd_print_register(NULL, 0, "MK_MESSAGE_SCB",
  615. 0x160, regvalue, cur_col, wrap));
  616. }
  617. int
  618. ahd_mk_message_scsiid_print(u_int regvalue, u_int *cur_col, u_int wrap)
  619. {
  620. return (ahd_print_register(NULL, 0, "MK_MESSAGE_SCSIID",
  621. 0x162, regvalue, cur_col, wrap));
  622. }
  623. int
  624. ahd_scb_base_print(u_int regvalue, u_int *cur_col, u_int wrap)
  625. {
  626. return (ahd_print_register(NULL, 0, "SCB_BASE",
  627. 0x180, regvalue, cur_col, wrap));
  628. }
  629. static const ahd_reg_parse_entry_t SCB_CONTROL_parse_table[] = {
  630. { "SCB_TAG_TYPE", 0x03, 0x03 },
  631. { "DISCONNECTED", 0x04, 0x04 },
  632. { "STATUS_RCVD", 0x08, 0x08 },
  633. { "MK_MESSAGE", 0x10, 0x10 },
  634. { "TAG_ENB", 0x20, 0x20 },
  635. { "DISCENB", 0x40, 0x40 },
  636. { "TARGET_SCB", 0x80, 0x80 }
  637. };
  638. int
  639. ahd_scb_control_print(u_int regvalue, u_int *cur_col, u_int wrap)
  640. {
  641. return (ahd_print_register(SCB_CONTROL_parse_table, 7, "SCB_CONTROL",
  642. 0x192, regvalue, cur_col, wrap));
  643. }
  644. static const ahd_reg_parse_entry_t SCB_SCSIID_parse_table[] = {
  645. { "OID", 0x0f, 0x0f },
  646. { "TID", 0xf0, 0xf0 }
  647. };
  648. int
  649. ahd_scb_scsiid_print(u_int regvalue, u_int *cur_col, u_int wrap)
  650. {
  651. return (ahd_print_register(SCB_SCSIID_parse_table, 2, "SCB_SCSIID",
  652. 0x193, regvalue, cur_col, wrap));
  653. }