aic94xx_hwi.c 38 KB

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  1. /*
  2. * Aic94xx SAS/SATA driver hardware interface.
  3. *
  4. * Copyright (C) 2005 Adaptec, Inc. All rights reserved.
  5. * Copyright (C) 2005 Luben Tuikov <luben_tuikov@adaptec.com>
  6. *
  7. * This file is licensed under GPLv2.
  8. *
  9. * This file is part of the aic94xx driver.
  10. *
  11. * The aic94xx driver is free software; you can redistribute it and/or
  12. * modify it under the terms of the GNU General Public License as
  13. * published by the Free Software Foundation; version 2 of the
  14. * License.
  15. *
  16. * The aic94xx driver is distributed in the hope that it will be useful,
  17. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
  19. * General Public License for more details.
  20. *
  21. * You should have received a copy of the GNU General Public License
  22. * along with the aic94xx driver; if not, write to the Free Software
  23. * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
  24. *
  25. */
  26. #include <linux/pci.h>
  27. #include <linux/slab.h>
  28. #include <linux/delay.h>
  29. #include <linux/module.h>
  30. #include <linux/firmware.h>
  31. #include "aic94xx.h"
  32. #include "aic94xx_reg.h"
  33. #include "aic94xx_hwi.h"
  34. #include "aic94xx_seq.h"
  35. #include "aic94xx_dump.h"
  36. u32 MBAR0_SWB_SIZE;
  37. /* ---------- Initialization ---------- */
  38. static int asd_get_user_sas_addr(struct asd_ha_struct *asd_ha)
  39. {
  40. /* adapter came with a sas address */
  41. if (asd_ha->hw_prof.sas_addr[0])
  42. return 0;
  43. return sas_request_addr(asd_ha->sas_ha.core.shost,
  44. asd_ha->hw_prof.sas_addr);
  45. }
  46. static void asd_propagate_sas_addr(struct asd_ha_struct *asd_ha)
  47. {
  48. int i;
  49. for (i = 0; i < ASD_MAX_PHYS; i++) {
  50. if (asd_ha->hw_prof.phy_desc[i].sas_addr[0] == 0)
  51. continue;
  52. /* Set a phy's address only if it has none.
  53. */
  54. ASD_DPRINTK("setting phy%d addr to %llx\n", i,
  55. SAS_ADDR(asd_ha->hw_prof.sas_addr));
  56. memcpy(asd_ha->hw_prof.phy_desc[i].sas_addr,
  57. asd_ha->hw_prof.sas_addr, SAS_ADDR_SIZE);
  58. }
  59. }
  60. /* ---------- PHY initialization ---------- */
  61. static void asd_init_phy_identify(struct asd_phy *phy)
  62. {
  63. phy->identify_frame = phy->id_frm_tok->vaddr;
  64. memset(phy->identify_frame, 0, sizeof(*phy->identify_frame));
  65. phy->identify_frame->dev_type = SAS_END_DEVICE;
  66. if (phy->sas_phy.role & PHY_ROLE_INITIATOR)
  67. phy->identify_frame->initiator_bits = phy->sas_phy.iproto;
  68. if (phy->sas_phy.role & PHY_ROLE_TARGET)
  69. phy->identify_frame->target_bits = phy->sas_phy.tproto;
  70. memcpy(phy->identify_frame->sas_addr, phy->phy_desc->sas_addr,
  71. SAS_ADDR_SIZE);
  72. phy->identify_frame->phy_id = phy->sas_phy.id;
  73. }
  74. static int asd_init_phy(struct asd_phy *phy)
  75. {
  76. struct asd_ha_struct *asd_ha = phy->sas_phy.ha->lldd_ha;
  77. struct asd_sas_phy *sas_phy = &phy->sas_phy;
  78. sas_phy->enabled = 1;
  79. sas_phy->class = SAS;
  80. sas_phy->iproto = SAS_PROTOCOL_ALL;
  81. sas_phy->tproto = 0;
  82. sas_phy->type = PHY_TYPE_PHYSICAL;
  83. sas_phy->role = PHY_ROLE_INITIATOR;
  84. sas_phy->oob_mode = OOB_NOT_CONNECTED;
  85. sas_phy->linkrate = SAS_LINK_RATE_UNKNOWN;
  86. phy->id_frm_tok = asd_alloc_coherent(asd_ha,
  87. sizeof(*phy->identify_frame),
  88. GFP_KERNEL);
  89. if (!phy->id_frm_tok) {
  90. asd_printk("no mem for IDENTIFY for phy%d\n", sas_phy->id);
  91. return -ENOMEM;
  92. } else
  93. asd_init_phy_identify(phy);
  94. memset(phy->frame_rcvd, 0, sizeof(phy->frame_rcvd));
  95. return 0;
  96. }
  97. static void asd_init_ports(struct asd_ha_struct *asd_ha)
  98. {
  99. int i;
  100. spin_lock_init(&asd_ha->asd_ports_lock);
  101. for (i = 0; i < ASD_MAX_PHYS; i++) {
  102. struct asd_port *asd_port = &asd_ha->asd_ports[i];
  103. memset(asd_port->sas_addr, 0, SAS_ADDR_SIZE);
  104. memset(asd_port->attached_sas_addr, 0, SAS_ADDR_SIZE);
  105. asd_port->phy_mask = 0;
  106. asd_port->num_phys = 0;
  107. }
  108. }
  109. static int asd_init_phys(struct asd_ha_struct *asd_ha)
  110. {
  111. u8 i;
  112. u8 phy_mask = asd_ha->hw_prof.enabled_phys;
  113. for (i = 0; i < ASD_MAX_PHYS; i++) {
  114. struct asd_phy *phy = &asd_ha->phys[i];
  115. phy->phy_desc = &asd_ha->hw_prof.phy_desc[i];
  116. phy->asd_port = NULL;
  117. phy->sas_phy.enabled = 0;
  118. phy->sas_phy.id = i;
  119. phy->sas_phy.sas_addr = &phy->phy_desc->sas_addr[0];
  120. phy->sas_phy.frame_rcvd = &phy->frame_rcvd[0];
  121. phy->sas_phy.ha = &asd_ha->sas_ha;
  122. phy->sas_phy.lldd_phy = phy;
  123. }
  124. /* Now enable and initialize only the enabled phys. */
  125. for_each_phy(phy_mask, phy_mask, i) {
  126. int err = asd_init_phy(&asd_ha->phys[i]);
  127. if (err)
  128. return err;
  129. }
  130. return 0;
  131. }
  132. /* ---------- Sliding windows ---------- */
  133. static int asd_init_sw(struct asd_ha_struct *asd_ha)
  134. {
  135. struct pci_dev *pcidev = asd_ha->pcidev;
  136. int err;
  137. u32 v;
  138. /* Unlock MBARs */
  139. err = pci_read_config_dword(pcidev, PCI_CONF_MBAR_KEY, &v);
  140. if (err) {
  141. asd_printk("couldn't access conf. space of %s\n",
  142. pci_name(pcidev));
  143. goto Err;
  144. }
  145. if (v)
  146. err = pci_write_config_dword(pcidev, PCI_CONF_MBAR_KEY, v);
  147. if (err) {
  148. asd_printk("couldn't write to MBAR_KEY of %s\n",
  149. pci_name(pcidev));
  150. goto Err;
  151. }
  152. /* Set sliding windows A, B and C to point to proper internal
  153. * memory regions.
  154. */
  155. pci_write_config_dword(pcidev, PCI_CONF_MBAR0_SWA, REG_BASE_ADDR);
  156. pci_write_config_dword(pcidev, PCI_CONF_MBAR0_SWB,
  157. REG_BASE_ADDR_CSEQCIO);
  158. pci_write_config_dword(pcidev, PCI_CONF_MBAR0_SWC, REG_BASE_ADDR_EXSI);
  159. asd_ha->io_handle[0].swa_base = REG_BASE_ADDR;
  160. asd_ha->io_handle[0].swb_base = REG_BASE_ADDR_CSEQCIO;
  161. asd_ha->io_handle[0].swc_base = REG_BASE_ADDR_EXSI;
  162. MBAR0_SWB_SIZE = asd_ha->io_handle[0].len - 0x80;
  163. if (!asd_ha->iospace) {
  164. /* MBAR1 will point to OCM (On Chip Memory) */
  165. pci_write_config_dword(pcidev, PCI_CONF_MBAR1, OCM_BASE_ADDR);
  166. asd_ha->io_handle[1].swa_base = OCM_BASE_ADDR;
  167. }
  168. spin_lock_init(&asd_ha->iolock);
  169. Err:
  170. return err;
  171. }
  172. /* ---------- SCB initialization ---------- */
  173. /**
  174. * asd_init_scbs - manually allocate the first SCB.
  175. * @asd_ha: pointer to host adapter structure
  176. *
  177. * This allocates the very first SCB which would be sent to the
  178. * sequencer for execution. Its bus address is written to
  179. * CSEQ_Q_NEW_POINTER, mode page 2, mode 8. Since the bus address of
  180. * the _next_ scb to be DMA-ed to the host adapter is read from the last
  181. * SCB DMA-ed to the host adapter, we have to always stay one step
  182. * ahead of the sequencer and keep one SCB already allocated.
  183. */
  184. static int asd_init_scbs(struct asd_ha_struct *asd_ha)
  185. {
  186. struct asd_seq_data *seq = &asd_ha->seq;
  187. int bitmap_bytes;
  188. /* allocate the index array and bitmap */
  189. asd_ha->seq.tc_index_bitmap_bits = asd_ha->hw_prof.max_scbs;
  190. asd_ha->seq.tc_index_array = kzalloc(asd_ha->seq.tc_index_bitmap_bits*
  191. sizeof(void *), GFP_KERNEL);
  192. if (!asd_ha->seq.tc_index_array)
  193. return -ENOMEM;
  194. bitmap_bytes = (asd_ha->seq.tc_index_bitmap_bits+7)/8;
  195. bitmap_bytes = BITS_TO_LONGS(bitmap_bytes*8)*sizeof(unsigned long);
  196. asd_ha->seq.tc_index_bitmap = kzalloc(bitmap_bytes, GFP_KERNEL);
  197. if (!asd_ha->seq.tc_index_bitmap)
  198. return -ENOMEM;
  199. spin_lock_init(&seq->tc_index_lock);
  200. seq->next_scb.size = sizeof(struct scb);
  201. seq->next_scb.vaddr = dma_pool_alloc(asd_ha->scb_pool, GFP_KERNEL,
  202. &seq->next_scb.dma_handle);
  203. if (!seq->next_scb.vaddr) {
  204. kfree(asd_ha->seq.tc_index_bitmap);
  205. kfree(asd_ha->seq.tc_index_array);
  206. asd_ha->seq.tc_index_bitmap = NULL;
  207. asd_ha->seq.tc_index_array = NULL;
  208. return -ENOMEM;
  209. }
  210. seq->pending = 0;
  211. spin_lock_init(&seq->pend_q_lock);
  212. INIT_LIST_HEAD(&seq->pend_q);
  213. return 0;
  214. }
  215. static void asd_get_max_scb_ddb(struct asd_ha_struct *asd_ha)
  216. {
  217. asd_ha->hw_prof.max_scbs = asd_get_cmdctx_size(asd_ha)/ASD_SCB_SIZE;
  218. asd_ha->hw_prof.max_ddbs = asd_get_devctx_size(asd_ha)/ASD_DDB_SIZE;
  219. ASD_DPRINTK("max_scbs:%d, max_ddbs:%d\n",
  220. asd_ha->hw_prof.max_scbs,
  221. asd_ha->hw_prof.max_ddbs);
  222. }
  223. /* ---------- Done List initialization ---------- */
  224. static void asd_dl_tasklet_handler(unsigned long);
  225. static int asd_init_dl(struct asd_ha_struct *asd_ha)
  226. {
  227. asd_ha->seq.actual_dl
  228. = asd_alloc_coherent(asd_ha,
  229. ASD_DL_SIZE * sizeof(struct done_list_struct),
  230. GFP_KERNEL);
  231. if (!asd_ha->seq.actual_dl)
  232. return -ENOMEM;
  233. asd_ha->seq.dl = asd_ha->seq.actual_dl->vaddr;
  234. asd_ha->seq.dl_toggle = ASD_DEF_DL_TOGGLE;
  235. asd_ha->seq.dl_next = 0;
  236. tasklet_init(&asd_ha->seq.dl_tasklet, asd_dl_tasklet_handler,
  237. (unsigned long) asd_ha);
  238. return 0;
  239. }
  240. /* ---------- EDB and ESCB init ---------- */
  241. static int asd_alloc_edbs(struct asd_ha_struct *asd_ha, gfp_t gfp_flags)
  242. {
  243. struct asd_seq_data *seq = &asd_ha->seq;
  244. int i;
  245. seq->edb_arr = kmalloc(seq->num_edbs*sizeof(*seq->edb_arr), gfp_flags);
  246. if (!seq->edb_arr)
  247. return -ENOMEM;
  248. for (i = 0; i < seq->num_edbs; i++) {
  249. seq->edb_arr[i] = asd_alloc_coherent(asd_ha, ASD_EDB_SIZE,
  250. gfp_flags);
  251. if (!seq->edb_arr[i])
  252. goto Err_unroll;
  253. memset(seq->edb_arr[i]->vaddr, 0, ASD_EDB_SIZE);
  254. }
  255. ASD_DPRINTK("num_edbs:%d\n", seq->num_edbs);
  256. return 0;
  257. Err_unroll:
  258. for (i-- ; i >= 0; i--)
  259. asd_free_coherent(asd_ha, seq->edb_arr[i]);
  260. kfree(seq->edb_arr);
  261. seq->edb_arr = NULL;
  262. return -ENOMEM;
  263. }
  264. static int asd_alloc_escbs(struct asd_ha_struct *asd_ha,
  265. gfp_t gfp_flags)
  266. {
  267. struct asd_seq_data *seq = &asd_ha->seq;
  268. struct asd_ascb *escb;
  269. int i, escbs;
  270. seq->escb_arr = kmalloc(seq->num_escbs*sizeof(*seq->escb_arr),
  271. gfp_flags);
  272. if (!seq->escb_arr)
  273. return -ENOMEM;
  274. escbs = seq->num_escbs;
  275. escb = asd_ascb_alloc_list(asd_ha, &escbs, gfp_flags);
  276. if (!escb) {
  277. asd_printk("couldn't allocate list of escbs\n");
  278. goto Err;
  279. }
  280. seq->num_escbs -= escbs; /* subtract what was not allocated */
  281. ASD_DPRINTK("num_escbs:%d\n", seq->num_escbs);
  282. for (i = 0; i < seq->num_escbs; i++, escb = list_entry(escb->list.next,
  283. struct asd_ascb,
  284. list)) {
  285. seq->escb_arr[i] = escb;
  286. escb->scb->header.opcode = EMPTY_SCB;
  287. }
  288. return 0;
  289. Err:
  290. kfree(seq->escb_arr);
  291. seq->escb_arr = NULL;
  292. return -ENOMEM;
  293. }
  294. static void asd_assign_edbs2escbs(struct asd_ha_struct *asd_ha)
  295. {
  296. struct asd_seq_data *seq = &asd_ha->seq;
  297. int i, k, z = 0;
  298. for (i = 0; i < seq->num_escbs; i++) {
  299. struct asd_ascb *ascb = seq->escb_arr[i];
  300. struct empty_scb *escb = &ascb->scb->escb;
  301. ascb->edb_index = z;
  302. escb->num_valid = ASD_EDBS_PER_SCB;
  303. for (k = 0; k < ASD_EDBS_PER_SCB; k++) {
  304. struct sg_el *eb = &escb->eb[k];
  305. struct asd_dma_tok *edb = seq->edb_arr[z++];
  306. memset(eb, 0, sizeof(*eb));
  307. eb->bus_addr = cpu_to_le64(((u64) edb->dma_handle));
  308. eb->size = cpu_to_le32(((u32) edb->size));
  309. }
  310. }
  311. }
  312. /**
  313. * asd_init_escbs -- allocate and initialize empty scbs
  314. * @asd_ha: pointer to host adapter structure
  315. *
  316. * An empty SCB has sg_elements of ASD_EDBS_PER_SCB (7) buffers.
  317. * They transport sense data, etc.
  318. */
  319. static int asd_init_escbs(struct asd_ha_struct *asd_ha)
  320. {
  321. struct asd_seq_data *seq = &asd_ha->seq;
  322. int err = 0;
  323. /* Allocate two empty data buffers (edb) per sequencer. */
  324. int edbs = 2*(1+asd_ha->hw_prof.num_phys);
  325. seq->num_escbs = (edbs+ASD_EDBS_PER_SCB-1)/ASD_EDBS_PER_SCB;
  326. seq->num_edbs = seq->num_escbs * ASD_EDBS_PER_SCB;
  327. err = asd_alloc_edbs(asd_ha, GFP_KERNEL);
  328. if (err) {
  329. asd_printk("couldn't allocate edbs\n");
  330. return err;
  331. }
  332. err = asd_alloc_escbs(asd_ha, GFP_KERNEL);
  333. if (err) {
  334. asd_printk("couldn't allocate escbs\n");
  335. return err;
  336. }
  337. asd_assign_edbs2escbs(asd_ha);
  338. /* In order to insure that normal SCBs do not overfill sequencer
  339. * memory and leave no space for escbs (halting condition),
  340. * we increment pending here by the number of escbs. However,
  341. * escbs are never pending.
  342. */
  343. seq->pending = seq->num_escbs;
  344. seq->can_queue = 1 + (asd_ha->hw_prof.max_scbs - seq->pending)/2;
  345. return 0;
  346. }
  347. /* ---------- HW initialization ---------- */
  348. /**
  349. * asd_chip_hardrst -- hard reset the chip
  350. * @asd_ha: pointer to host adapter structure
  351. *
  352. * This takes 16 cycles and is synchronous to CFCLK, which runs
  353. * at 200 MHz, so this should take at most 80 nanoseconds.
  354. */
  355. int asd_chip_hardrst(struct asd_ha_struct *asd_ha)
  356. {
  357. int i;
  358. int count = 100;
  359. u32 reg;
  360. for (i = 0 ; i < 4 ; i++) {
  361. asd_write_reg_dword(asd_ha, COMBIST, HARDRST);
  362. }
  363. do {
  364. udelay(1);
  365. reg = asd_read_reg_dword(asd_ha, CHIMINT);
  366. if (reg & HARDRSTDET) {
  367. asd_write_reg_dword(asd_ha, CHIMINT,
  368. HARDRSTDET|PORRSTDET);
  369. return 0;
  370. }
  371. } while (--count > 0);
  372. return -ENODEV;
  373. }
  374. /**
  375. * asd_init_chip -- initialize the chip
  376. * @asd_ha: pointer to host adapter structure
  377. *
  378. * Hard resets the chip, disables HA interrupts, downloads the sequnecer
  379. * microcode and starts the sequencers. The caller has to explicitly
  380. * enable HA interrupts with asd_enable_ints(asd_ha).
  381. */
  382. static int asd_init_chip(struct asd_ha_struct *asd_ha)
  383. {
  384. int err;
  385. err = asd_chip_hardrst(asd_ha);
  386. if (err) {
  387. asd_printk("couldn't hard reset %s\n",
  388. pci_name(asd_ha->pcidev));
  389. goto out;
  390. }
  391. asd_disable_ints(asd_ha);
  392. err = asd_init_seqs(asd_ha);
  393. if (err) {
  394. asd_printk("couldn't init seqs for %s\n",
  395. pci_name(asd_ha->pcidev));
  396. goto out;
  397. }
  398. err = asd_start_seqs(asd_ha);
  399. if (err) {
  400. asd_printk("coudln't start seqs for %s\n",
  401. pci_name(asd_ha->pcidev));
  402. goto out;
  403. }
  404. out:
  405. return err;
  406. }
  407. #define MAX_DEVS ((OCM_MAX_SIZE) / (ASD_DDB_SIZE))
  408. static int max_devs = 0;
  409. module_param_named(max_devs, max_devs, int, S_IRUGO);
  410. MODULE_PARM_DESC(max_devs, "\n"
  411. "\tMaximum number of SAS devices to support (not LUs).\n"
  412. "\tDefault: 2176, Maximum: 65663.\n");
  413. static int max_cmnds = 0;
  414. module_param_named(max_cmnds, max_cmnds, int, S_IRUGO);
  415. MODULE_PARM_DESC(max_cmnds, "\n"
  416. "\tMaximum number of commands queuable.\n"
  417. "\tDefault: 512, Maximum: 66047.\n");
  418. static void asd_extend_devctx_ocm(struct asd_ha_struct *asd_ha)
  419. {
  420. unsigned long dma_addr = OCM_BASE_ADDR;
  421. u32 d;
  422. dma_addr -= asd_ha->hw_prof.max_ddbs * ASD_DDB_SIZE;
  423. asd_write_reg_addr(asd_ha, DEVCTXBASE, (dma_addr_t) dma_addr);
  424. d = asd_read_reg_dword(asd_ha, CTXDOMAIN);
  425. d |= 4;
  426. asd_write_reg_dword(asd_ha, CTXDOMAIN, d);
  427. asd_ha->hw_prof.max_ddbs += MAX_DEVS;
  428. }
  429. static int asd_extend_devctx(struct asd_ha_struct *asd_ha)
  430. {
  431. dma_addr_t dma_handle;
  432. unsigned long dma_addr;
  433. u32 d;
  434. int size;
  435. asd_extend_devctx_ocm(asd_ha);
  436. asd_ha->hw_prof.ddb_ext = NULL;
  437. if (max_devs <= asd_ha->hw_prof.max_ddbs || max_devs > 0xFFFF) {
  438. max_devs = asd_ha->hw_prof.max_ddbs;
  439. return 0;
  440. }
  441. size = (max_devs - asd_ha->hw_prof.max_ddbs + 1) * ASD_DDB_SIZE;
  442. asd_ha->hw_prof.ddb_ext = asd_alloc_coherent(asd_ha, size, GFP_KERNEL);
  443. if (!asd_ha->hw_prof.ddb_ext) {
  444. asd_printk("couldn't allocate memory for %d devices\n",
  445. max_devs);
  446. max_devs = asd_ha->hw_prof.max_ddbs;
  447. return -ENOMEM;
  448. }
  449. dma_handle = asd_ha->hw_prof.ddb_ext->dma_handle;
  450. dma_addr = ALIGN((unsigned long) dma_handle, ASD_DDB_SIZE);
  451. dma_addr -= asd_ha->hw_prof.max_ddbs * ASD_DDB_SIZE;
  452. dma_handle = (dma_addr_t) dma_addr;
  453. asd_write_reg_addr(asd_ha, DEVCTXBASE, dma_handle);
  454. d = asd_read_reg_dword(asd_ha, CTXDOMAIN);
  455. d &= ~4;
  456. asd_write_reg_dword(asd_ha, CTXDOMAIN, d);
  457. asd_ha->hw_prof.max_ddbs = max_devs;
  458. return 0;
  459. }
  460. static int asd_extend_cmdctx(struct asd_ha_struct *asd_ha)
  461. {
  462. dma_addr_t dma_handle;
  463. unsigned long dma_addr;
  464. u32 d;
  465. int size;
  466. asd_ha->hw_prof.scb_ext = NULL;
  467. if (max_cmnds <= asd_ha->hw_prof.max_scbs || max_cmnds > 0xFFFF) {
  468. max_cmnds = asd_ha->hw_prof.max_scbs;
  469. return 0;
  470. }
  471. size = (max_cmnds - asd_ha->hw_prof.max_scbs + 1) * ASD_SCB_SIZE;
  472. asd_ha->hw_prof.scb_ext = asd_alloc_coherent(asd_ha, size, GFP_KERNEL);
  473. if (!asd_ha->hw_prof.scb_ext) {
  474. asd_printk("couldn't allocate memory for %d commands\n",
  475. max_cmnds);
  476. max_cmnds = asd_ha->hw_prof.max_scbs;
  477. return -ENOMEM;
  478. }
  479. dma_handle = asd_ha->hw_prof.scb_ext->dma_handle;
  480. dma_addr = ALIGN((unsigned long) dma_handle, ASD_SCB_SIZE);
  481. dma_addr -= asd_ha->hw_prof.max_scbs * ASD_SCB_SIZE;
  482. dma_handle = (dma_addr_t) dma_addr;
  483. asd_write_reg_addr(asd_ha, CMDCTXBASE, dma_handle);
  484. d = asd_read_reg_dword(asd_ha, CTXDOMAIN);
  485. d &= ~1;
  486. asd_write_reg_dword(asd_ha, CTXDOMAIN, d);
  487. asd_ha->hw_prof.max_scbs = max_cmnds;
  488. return 0;
  489. }
  490. /**
  491. * asd_init_ctxmem -- initialize context memory
  492. * asd_ha: pointer to host adapter structure
  493. *
  494. * This function sets the maximum number of SCBs and
  495. * DDBs which can be used by the sequencer. This is normally
  496. * 512 and 128 respectively. If support for more SCBs or more DDBs
  497. * is required then CMDCTXBASE, DEVCTXBASE and CTXDOMAIN are
  498. * initialized here to extend context memory to point to host memory,
  499. * thus allowing unlimited support for SCBs and DDBs -- only limited
  500. * by host memory.
  501. */
  502. static int asd_init_ctxmem(struct asd_ha_struct *asd_ha)
  503. {
  504. int bitmap_bytes;
  505. asd_get_max_scb_ddb(asd_ha);
  506. asd_extend_devctx(asd_ha);
  507. asd_extend_cmdctx(asd_ha);
  508. /* The kernel wants bitmaps to be unsigned long sized. */
  509. bitmap_bytes = (asd_ha->hw_prof.max_ddbs+7)/8;
  510. bitmap_bytes = BITS_TO_LONGS(bitmap_bytes*8)*sizeof(unsigned long);
  511. asd_ha->hw_prof.ddb_bitmap = kzalloc(bitmap_bytes, GFP_KERNEL);
  512. if (!asd_ha->hw_prof.ddb_bitmap)
  513. return -ENOMEM;
  514. spin_lock_init(&asd_ha->hw_prof.ddb_lock);
  515. return 0;
  516. }
  517. int asd_init_hw(struct asd_ha_struct *asd_ha)
  518. {
  519. int err;
  520. u32 v;
  521. err = asd_init_sw(asd_ha);
  522. if (err)
  523. return err;
  524. err = pci_read_config_dword(asd_ha->pcidev, PCIC_HSTPCIX_CNTRL, &v);
  525. if (err) {
  526. asd_printk("couldn't read PCIC_HSTPCIX_CNTRL of %s\n",
  527. pci_name(asd_ha->pcidev));
  528. return err;
  529. }
  530. pci_write_config_dword(asd_ha->pcidev, PCIC_HSTPCIX_CNTRL,
  531. v | SC_TMR_DIS);
  532. if (err) {
  533. asd_printk("couldn't disable split completion timer of %s\n",
  534. pci_name(asd_ha->pcidev));
  535. return err;
  536. }
  537. err = asd_read_ocm(asd_ha);
  538. if (err) {
  539. asd_printk("couldn't read ocm(%d)\n", err);
  540. /* While suspicios, it is not an error that we
  541. * couldn't read the OCM. */
  542. }
  543. err = asd_read_flash(asd_ha);
  544. if (err) {
  545. asd_printk("couldn't read flash(%d)\n", err);
  546. /* While suspicios, it is not an error that we
  547. * couldn't read FLASH memory.
  548. */
  549. }
  550. asd_init_ctxmem(asd_ha);
  551. if (asd_get_user_sas_addr(asd_ha)) {
  552. asd_printk("No SAS Address provided for %s\n",
  553. pci_name(asd_ha->pcidev));
  554. err = -ENODEV;
  555. goto Out;
  556. }
  557. asd_propagate_sas_addr(asd_ha);
  558. err = asd_init_phys(asd_ha);
  559. if (err) {
  560. asd_printk("couldn't initialize phys for %s\n",
  561. pci_name(asd_ha->pcidev));
  562. goto Out;
  563. }
  564. asd_init_ports(asd_ha);
  565. err = asd_init_scbs(asd_ha);
  566. if (err) {
  567. asd_printk("couldn't initialize scbs for %s\n",
  568. pci_name(asd_ha->pcidev));
  569. goto Out;
  570. }
  571. err = asd_init_dl(asd_ha);
  572. if (err) {
  573. asd_printk("couldn't initialize the done list:%d\n",
  574. err);
  575. goto Out;
  576. }
  577. err = asd_init_escbs(asd_ha);
  578. if (err) {
  579. asd_printk("couldn't initialize escbs\n");
  580. goto Out;
  581. }
  582. err = asd_init_chip(asd_ha);
  583. if (err) {
  584. asd_printk("couldn't init the chip\n");
  585. goto Out;
  586. }
  587. Out:
  588. return err;
  589. }
  590. /* ---------- Chip reset ---------- */
  591. /**
  592. * asd_chip_reset -- reset the host adapter, etc
  593. * @asd_ha: pointer to host adapter structure of interest
  594. *
  595. * Called from the ISR. Hard reset the chip. Let everything
  596. * timeout. This should be no different than hot-unplugging the
  597. * host adapter. Once everything times out we'll init the chip with
  598. * a call to asd_init_chip() and enable interrupts with asd_enable_ints().
  599. * XXX finish.
  600. */
  601. static void asd_chip_reset(struct asd_ha_struct *asd_ha)
  602. {
  603. struct sas_ha_struct *sas_ha = &asd_ha->sas_ha;
  604. ASD_DPRINTK("chip reset for %s\n", pci_name(asd_ha->pcidev));
  605. asd_chip_hardrst(asd_ha);
  606. sas_ha->notify_ha_event(sas_ha, HAE_RESET);
  607. }
  608. /* ---------- Done List Routines ---------- */
  609. static void asd_dl_tasklet_handler(unsigned long data)
  610. {
  611. struct asd_ha_struct *asd_ha = (struct asd_ha_struct *) data;
  612. struct asd_seq_data *seq = &asd_ha->seq;
  613. unsigned long flags;
  614. while (1) {
  615. struct done_list_struct *dl = &seq->dl[seq->dl_next];
  616. struct asd_ascb *ascb;
  617. if ((dl->toggle & DL_TOGGLE_MASK) != seq->dl_toggle)
  618. break;
  619. /* find the aSCB */
  620. spin_lock_irqsave(&seq->tc_index_lock, flags);
  621. ascb = asd_tc_index_find(seq, (int)le16_to_cpu(dl->index));
  622. spin_unlock_irqrestore(&seq->tc_index_lock, flags);
  623. if (unlikely(!ascb)) {
  624. ASD_DPRINTK("BUG:sequencer:dl:no ascb?!\n");
  625. goto next_1;
  626. } else if (ascb->scb->header.opcode == EMPTY_SCB) {
  627. goto out;
  628. } else if (!ascb->uldd_timer && !del_timer(&ascb->timer)) {
  629. goto next_1;
  630. }
  631. spin_lock_irqsave(&seq->pend_q_lock, flags);
  632. list_del_init(&ascb->list);
  633. seq->pending--;
  634. spin_unlock_irqrestore(&seq->pend_q_lock, flags);
  635. out:
  636. ascb->tasklet_complete(ascb, dl);
  637. next_1:
  638. seq->dl_next = (seq->dl_next + 1) & (ASD_DL_SIZE-1);
  639. if (!seq->dl_next)
  640. seq->dl_toggle ^= DL_TOGGLE_MASK;
  641. }
  642. }
  643. /* ---------- Interrupt Service Routines ---------- */
  644. /**
  645. * asd_process_donelist_isr -- schedule processing of done list entries
  646. * @asd_ha: pointer to host adapter structure
  647. */
  648. static void asd_process_donelist_isr(struct asd_ha_struct *asd_ha)
  649. {
  650. tasklet_schedule(&asd_ha->seq.dl_tasklet);
  651. }
  652. /**
  653. * asd_com_sas_isr -- process device communication interrupt (COMINT)
  654. * @asd_ha: pointer to host adapter structure
  655. */
  656. static void asd_com_sas_isr(struct asd_ha_struct *asd_ha)
  657. {
  658. u32 comstat = asd_read_reg_dword(asd_ha, COMSTAT);
  659. /* clear COMSTAT int */
  660. asd_write_reg_dword(asd_ha, COMSTAT, 0xFFFFFFFF);
  661. if (comstat & CSBUFPERR) {
  662. asd_printk("%s: command/status buffer dma parity error\n",
  663. pci_name(asd_ha->pcidev));
  664. } else if (comstat & CSERR) {
  665. int i;
  666. u32 dmaerr = asd_read_reg_dword(asd_ha, DMAERR);
  667. dmaerr &= 0xFF;
  668. asd_printk("%s: command/status dma error, DMAERR: 0x%02x, "
  669. "CSDMAADR: 0x%04x, CSDMAADR+4: 0x%04x\n",
  670. pci_name(asd_ha->pcidev),
  671. dmaerr,
  672. asd_read_reg_dword(asd_ha, CSDMAADR),
  673. asd_read_reg_dword(asd_ha, CSDMAADR+4));
  674. asd_printk("CSBUFFER:\n");
  675. for (i = 0; i < 8; i++) {
  676. asd_printk("%08x %08x %08x %08x\n",
  677. asd_read_reg_dword(asd_ha, CSBUFFER),
  678. asd_read_reg_dword(asd_ha, CSBUFFER+4),
  679. asd_read_reg_dword(asd_ha, CSBUFFER+8),
  680. asd_read_reg_dword(asd_ha, CSBUFFER+12));
  681. }
  682. asd_dump_seq_state(asd_ha, 0);
  683. } else if (comstat & OVLYERR) {
  684. u32 dmaerr = asd_read_reg_dword(asd_ha, DMAERR);
  685. dmaerr = (dmaerr >> 8) & 0xFF;
  686. asd_printk("%s: overlay dma error:0x%x\n",
  687. pci_name(asd_ha->pcidev),
  688. dmaerr);
  689. }
  690. asd_chip_reset(asd_ha);
  691. }
  692. static void asd_arp2_err(struct asd_ha_struct *asd_ha, u32 dchstatus)
  693. {
  694. static const char *halt_code[256] = {
  695. "UNEXPECTED_INTERRUPT0",
  696. "UNEXPECTED_INTERRUPT1",
  697. "UNEXPECTED_INTERRUPT2",
  698. "UNEXPECTED_INTERRUPT3",
  699. "UNEXPECTED_INTERRUPT4",
  700. "UNEXPECTED_INTERRUPT5",
  701. "UNEXPECTED_INTERRUPT6",
  702. "UNEXPECTED_INTERRUPT7",
  703. "UNEXPECTED_INTERRUPT8",
  704. "UNEXPECTED_INTERRUPT9",
  705. "UNEXPECTED_INTERRUPT10",
  706. [11 ... 19] = "unknown[11,19]",
  707. "NO_FREE_SCB_AVAILABLE",
  708. "INVALID_SCB_OPCODE",
  709. "INVALID_MBX_OPCODE",
  710. "INVALID_ATA_STATE",
  711. "ATA_QUEUE_FULL",
  712. "ATA_TAG_TABLE_FAULT",
  713. "ATA_TAG_MASK_FAULT",
  714. "BAD_LINK_QUEUE_STATE",
  715. "DMA2CHIM_QUEUE_ERROR",
  716. "EMPTY_SCB_LIST_FULL",
  717. "unknown[30]",
  718. "IN_USE_SCB_ON_FREE_LIST",
  719. "BAD_OPEN_WAIT_STATE",
  720. "INVALID_STP_AFFILIATION",
  721. "unknown[34]",
  722. "EXEC_QUEUE_ERROR",
  723. "TOO_MANY_EMPTIES_NEEDED",
  724. "EMPTY_REQ_QUEUE_ERROR",
  725. "Q_MONIRTT_MGMT_ERROR",
  726. "TARGET_MODE_FLOW_ERROR",
  727. "DEVICE_QUEUE_NOT_FOUND",
  728. "START_IRTT_TIMER_ERROR",
  729. "ABORT_TASK_ILLEGAL_REQ",
  730. [43 ... 255] = "unknown[43,255]"
  731. };
  732. if (dchstatus & CSEQINT) {
  733. u32 arp2int = asd_read_reg_dword(asd_ha, CARP2INT);
  734. if (arp2int & (ARP2WAITTO|ARP2ILLOPC|ARP2PERR|ARP2CIOPERR)) {
  735. asd_printk("%s: CSEQ arp2int:0x%x\n",
  736. pci_name(asd_ha->pcidev),
  737. arp2int);
  738. } else if (arp2int & ARP2HALTC)
  739. asd_printk("%s: CSEQ halted: %s\n",
  740. pci_name(asd_ha->pcidev),
  741. halt_code[(arp2int>>16)&0xFF]);
  742. else
  743. asd_printk("%s: CARP2INT:0x%x\n",
  744. pci_name(asd_ha->pcidev),
  745. arp2int);
  746. }
  747. if (dchstatus & LSEQINT_MASK) {
  748. int lseq;
  749. u8 lseq_mask = dchstatus & LSEQINT_MASK;
  750. for_each_sequencer(lseq_mask, lseq_mask, lseq) {
  751. u32 arp2int = asd_read_reg_dword(asd_ha,
  752. LmARP2INT(lseq));
  753. if (arp2int & (ARP2WAITTO | ARP2ILLOPC | ARP2PERR
  754. | ARP2CIOPERR)) {
  755. asd_printk("%s: LSEQ%d arp2int:0x%x\n",
  756. pci_name(asd_ha->pcidev),
  757. lseq, arp2int);
  758. /* XXX we should only do lseq reset */
  759. } else if (arp2int & ARP2HALTC)
  760. asd_printk("%s: LSEQ%d halted: %s\n",
  761. pci_name(asd_ha->pcidev),
  762. lseq,halt_code[(arp2int>>16)&0xFF]);
  763. else
  764. asd_printk("%s: LSEQ%d ARP2INT:0x%x\n",
  765. pci_name(asd_ha->pcidev), lseq,
  766. arp2int);
  767. }
  768. }
  769. asd_chip_reset(asd_ha);
  770. }
  771. /**
  772. * asd_dch_sas_isr -- process device channel interrupt (DEVINT)
  773. * @asd_ha: pointer to host adapter structure
  774. */
  775. static void asd_dch_sas_isr(struct asd_ha_struct *asd_ha)
  776. {
  777. u32 dchstatus = asd_read_reg_dword(asd_ha, DCHSTATUS);
  778. if (dchstatus & CFIFTOERR) {
  779. asd_printk("%s: CFIFTOERR\n", pci_name(asd_ha->pcidev));
  780. asd_chip_reset(asd_ha);
  781. } else
  782. asd_arp2_err(asd_ha, dchstatus);
  783. }
  784. /**
  785. * ads_rbi_exsi_isr -- process external system interface interrupt (INITERR)
  786. * @asd_ha: pointer to host adapter structure
  787. */
  788. static void asd_rbi_exsi_isr(struct asd_ha_struct *asd_ha)
  789. {
  790. u32 stat0r = asd_read_reg_dword(asd_ha, ASISTAT0R);
  791. if (!(stat0r & ASIERR)) {
  792. asd_printk("hmm, EXSI interrupted but no error?\n");
  793. return;
  794. }
  795. if (stat0r & ASIFMTERR) {
  796. asd_printk("ASI SEEPROM format error for %s\n",
  797. pci_name(asd_ha->pcidev));
  798. } else if (stat0r & ASISEECHKERR) {
  799. u32 stat1r = asd_read_reg_dword(asd_ha, ASISTAT1R);
  800. asd_printk("ASI SEEPROM checksum 0x%x error for %s\n",
  801. stat1r & CHECKSUM_MASK,
  802. pci_name(asd_ha->pcidev));
  803. } else {
  804. u32 statr = asd_read_reg_dword(asd_ha, ASIERRSTATR);
  805. if (!(statr & CPI2ASIMSTERR_MASK)) {
  806. ASD_DPRINTK("hmm, ASIERR?\n");
  807. return;
  808. } else {
  809. u32 addr = asd_read_reg_dword(asd_ha, ASIERRADDR);
  810. u32 data = asd_read_reg_dword(asd_ha, ASIERRDATAR);
  811. asd_printk("%s: CPI2 xfer err: addr: 0x%x, wdata: 0x%x, "
  812. "count: 0x%x, byteen: 0x%x, targerr: 0x%x "
  813. "master id: 0x%x, master err: 0x%x\n",
  814. pci_name(asd_ha->pcidev),
  815. addr, data,
  816. (statr & CPI2ASIBYTECNT_MASK) >> 16,
  817. (statr & CPI2ASIBYTEEN_MASK) >> 12,
  818. (statr & CPI2ASITARGERR_MASK) >> 8,
  819. (statr & CPI2ASITARGMID_MASK) >> 4,
  820. (statr & CPI2ASIMSTERR_MASK));
  821. }
  822. }
  823. asd_chip_reset(asd_ha);
  824. }
  825. /**
  826. * asd_hst_pcix_isr -- process host interface interrupts
  827. * @asd_ha: pointer to host adapter structure
  828. *
  829. * Asserted on PCIX errors: target abort, etc.
  830. */
  831. static void asd_hst_pcix_isr(struct asd_ha_struct *asd_ha)
  832. {
  833. u16 status;
  834. u32 pcix_status;
  835. u32 ecc_status;
  836. pci_read_config_word(asd_ha->pcidev, PCI_STATUS, &status);
  837. pci_read_config_dword(asd_ha->pcidev, PCIX_STATUS, &pcix_status);
  838. pci_read_config_dword(asd_ha->pcidev, ECC_CTRL_STAT, &ecc_status);
  839. if (status & PCI_STATUS_DETECTED_PARITY)
  840. asd_printk("parity error for %s\n", pci_name(asd_ha->pcidev));
  841. else if (status & PCI_STATUS_REC_MASTER_ABORT)
  842. asd_printk("master abort for %s\n", pci_name(asd_ha->pcidev));
  843. else if (status & PCI_STATUS_REC_TARGET_ABORT)
  844. asd_printk("target abort for %s\n", pci_name(asd_ha->pcidev));
  845. else if (status & PCI_STATUS_PARITY)
  846. asd_printk("data parity for %s\n", pci_name(asd_ha->pcidev));
  847. else if (pcix_status & RCV_SCE) {
  848. asd_printk("received split completion error for %s\n",
  849. pci_name(asd_ha->pcidev));
  850. pci_write_config_dword(asd_ha->pcidev,PCIX_STATUS,pcix_status);
  851. /* XXX: Abort task? */
  852. return;
  853. } else if (pcix_status & UNEXP_SC) {
  854. asd_printk("unexpected split completion for %s\n",
  855. pci_name(asd_ha->pcidev));
  856. pci_write_config_dword(asd_ha->pcidev,PCIX_STATUS,pcix_status);
  857. /* ignore */
  858. return;
  859. } else if (pcix_status & SC_DISCARD)
  860. asd_printk("split completion discarded for %s\n",
  861. pci_name(asd_ha->pcidev));
  862. else if (ecc_status & UNCOR_ECCERR)
  863. asd_printk("uncorrectable ECC error for %s\n",
  864. pci_name(asd_ha->pcidev));
  865. asd_chip_reset(asd_ha);
  866. }
  867. /**
  868. * asd_hw_isr -- host adapter interrupt service routine
  869. * @irq: ignored
  870. * @dev_id: pointer to host adapter structure
  871. *
  872. * The ISR processes done list entries and level 3 error handling.
  873. */
  874. irqreturn_t asd_hw_isr(int irq, void *dev_id)
  875. {
  876. struct asd_ha_struct *asd_ha = dev_id;
  877. u32 chimint = asd_read_reg_dword(asd_ha, CHIMINT);
  878. if (!chimint)
  879. return IRQ_NONE;
  880. asd_write_reg_dword(asd_ha, CHIMINT, chimint);
  881. (void) asd_read_reg_dword(asd_ha, CHIMINT);
  882. if (chimint & DLAVAIL)
  883. asd_process_donelist_isr(asd_ha);
  884. if (chimint & COMINT)
  885. asd_com_sas_isr(asd_ha);
  886. if (chimint & DEVINT)
  887. asd_dch_sas_isr(asd_ha);
  888. if (chimint & INITERR)
  889. asd_rbi_exsi_isr(asd_ha);
  890. if (chimint & HOSTERR)
  891. asd_hst_pcix_isr(asd_ha);
  892. return IRQ_HANDLED;
  893. }
  894. /* ---------- SCB handling ---------- */
  895. static struct asd_ascb *asd_ascb_alloc(struct asd_ha_struct *asd_ha,
  896. gfp_t gfp_flags)
  897. {
  898. extern struct kmem_cache *asd_ascb_cache;
  899. struct asd_seq_data *seq = &asd_ha->seq;
  900. struct asd_ascb *ascb;
  901. unsigned long flags;
  902. ascb = kmem_cache_zalloc(asd_ascb_cache, gfp_flags);
  903. if (ascb) {
  904. ascb->dma_scb.size = sizeof(struct scb);
  905. ascb->dma_scb.vaddr = dma_pool_alloc(asd_ha->scb_pool,
  906. gfp_flags,
  907. &ascb->dma_scb.dma_handle);
  908. if (!ascb->dma_scb.vaddr) {
  909. kmem_cache_free(asd_ascb_cache, ascb);
  910. return NULL;
  911. }
  912. memset(ascb->dma_scb.vaddr, 0, sizeof(struct scb));
  913. asd_init_ascb(asd_ha, ascb);
  914. spin_lock_irqsave(&seq->tc_index_lock, flags);
  915. ascb->tc_index = asd_tc_index_get(seq, ascb);
  916. spin_unlock_irqrestore(&seq->tc_index_lock, flags);
  917. if (ascb->tc_index == -1)
  918. goto undo;
  919. ascb->scb->header.index = cpu_to_le16((u16)ascb->tc_index);
  920. }
  921. return ascb;
  922. undo:
  923. dma_pool_free(asd_ha->scb_pool, ascb->dma_scb.vaddr,
  924. ascb->dma_scb.dma_handle);
  925. kmem_cache_free(asd_ascb_cache, ascb);
  926. ASD_DPRINTK("no index for ascb\n");
  927. return NULL;
  928. }
  929. /**
  930. * asd_ascb_alloc_list -- allocate a list of aSCBs
  931. * @asd_ha: pointer to host adapter structure
  932. * @num: pointer to integer number of aSCBs
  933. * @gfp_flags: GFP_ flags.
  934. *
  935. * This is the only function which is used to allocate aSCBs.
  936. * It can allocate one or many. If more than one, then they form
  937. * a linked list in two ways: by their list field of the ascb struct
  938. * and by the next_scb field of the scb_header.
  939. *
  940. * Returns NULL if no memory was available, else pointer to a list
  941. * of ascbs. When this function returns, @num would be the number
  942. * of SCBs which were not able to be allocated, 0 if all requested
  943. * were able to be allocated.
  944. */
  945. struct asd_ascb *asd_ascb_alloc_list(struct asd_ha_struct
  946. *asd_ha, int *num,
  947. gfp_t gfp_flags)
  948. {
  949. struct asd_ascb *first = NULL;
  950. for ( ; *num > 0; --*num) {
  951. struct asd_ascb *ascb = asd_ascb_alloc(asd_ha, gfp_flags);
  952. if (!ascb)
  953. break;
  954. else if (!first)
  955. first = ascb;
  956. else {
  957. struct asd_ascb *last = list_entry(first->list.prev,
  958. struct asd_ascb,
  959. list);
  960. list_add_tail(&ascb->list, &first->list);
  961. last->scb->header.next_scb =
  962. cpu_to_le64(((u64)ascb->dma_scb.dma_handle));
  963. }
  964. }
  965. return first;
  966. }
  967. /**
  968. * asd_swap_head_scb -- swap the head scb
  969. * @asd_ha: pointer to host adapter structure
  970. * @ascb: pointer to the head of an ascb list
  971. *
  972. * The sequencer knows the DMA address of the next SCB to be DMAed to
  973. * the host adapter, from initialization or from the last list DMAed.
  974. * seq->next_scb keeps the address of this SCB. The sequencer will
  975. * DMA to the host adapter this list of SCBs. But the head (first
  976. * element) of this list is not known to the sequencer. Here we swap
  977. * the head of the list with the known SCB (memcpy()).
  978. * Only one memcpy() is required per list so it is in our interest
  979. * to keep the list of SCB as long as possible so that the ratio
  980. * of number of memcpy calls to the number of SCB DMA-ed is as small
  981. * as possible.
  982. *
  983. * LOCKING: called with the pending list lock held.
  984. */
  985. static void asd_swap_head_scb(struct asd_ha_struct *asd_ha,
  986. struct asd_ascb *ascb)
  987. {
  988. struct asd_seq_data *seq = &asd_ha->seq;
  989. struct asd_ascb *last = list_entry(ascb->list.prev,
  990. struct asd_ascb,
  991. list);
  992. struct asd_dma_tok t = ascb->dma_scb;
  993. memcpy(seq->next_scb.vaddr, ascb->scb, sizeof(*ascb->scb));
  994. ascb->dma_scb = seq->next_scb;
  995. ascb->scb = ascb->dma_scb.vaddr;
  996. seq->next_scb = t;
  997. last->scb->header.next_scb =
  998. cpu_to_le64(((u64)seq->next_scb.dma_handle));
  999. }
  1000. /**
  1001. * asd_start_timers -- (add and) start timers of SCBs
  1002. * @list: pointer to struct list_head of the scbs
  1003. * @to: timeout in jiffies
  1004. *
  1005. * If an SCB in the @list has no timer function, assign the default
  1006. * one, then start the timer of the SCB. This function is
  1007. * intended to be called from asd_post_ascb_list(), just prior to
  1008. * posting the SCBs to the sequencer.
  1009. */
  1010. static void asd_start_scb_timers(struct list_head *list)
  1011. {
  1012. struct asd_ascb *ascb;
  1013. list_for_each_entry(ascb, list, list) {
  1014. if (!ascb->uldd_timer) {
  1015. ascb->timer.data = (unsigned long) ascb;
  1016. ascb->timer.function = asd_ascb_timedout;
  1017. ascb->timer.expires = jiffies + AIC94XX_SCB_TIMEOUT;
  1018. add_timer(&ascb->timer);
  1019. }
  1020. }
  1021. }
  1022. /**
  1023. * asd_post_ascb_list -- post a list of 1 or more aSCBs to the host adapter
  1024. * @asd_ha: pointer to a host adapter structure
  1025. * @ascb: pointer to the first aSCB in the list
  1026. * @num: number of aSCBs in the list (to be posted)
  1027. *
  1028. * See queueing comment in asd_post_escb_list().
  1029. *
  1030. * Additional note on queuing: In order to minimize the ratio of memcpy()
  1031. * to the number of ascbs sent, we try to batch-send as many ascbs as possible
  1032. * in one go.
  1033. * Two cases are possible:
  1034. * A) can_queue >= num,
  1035. * B) can_queue < num.
  1036. * Case A: we can send the whole batch at once. Increment "pending"
  1037. * in the beginning of this function, when it is checked, in order to
  1038. * eliminate races when this function is called by multiple processes.
  1039. * Case B: should never happen.
  1040. */
  1041. int asd_post_ascb_list(struct asd_ha_struct *asd_ha, struct asd_ascb *ascb,
  1042. int num)
  1043. {
  1044. unsigned long flags;
  1045. LIST_HEAD(list);
  1046. int can_queue;
  1047. spin_lock_irqsave(&asd_ha->seq.pend_q_lock, flags);
  1048. can_queue = asd_ha->hw_prof.max_scbs - asd_ha->seq.pending;
  1049. if (can_queue >= num)
  1050. asd_ha->seq.pending += num;
  1051. else
  1052. can_queue = 0;
  1053. if (!can_queue) {
  1054. spin_unlock_irqrestore(&asd_ha->seq.pend_q_lock, flags);
  1055. asd_printk("%s: scb queue full\n", pci_name(asd_ha->pcidev));
  1056. return -SAS_QUEUE_FULL;
  1057. }
  1058. asd_swap_head_scb(asd_ha, ascb);
  1059. __list_add(&list, ascb->list.prev, &ascb->list);
  1060. asd_start_scb_timers(&list);
  1061. asd_ha->seq.scbpro += num;
  1062. list_splice_init(&list, asd_ha->seq.pend_q.prev);
  1063. asd_write_reg_dword(asd_ha, SCBPRO, (u32)asd_ha->seq.scbpro);
  1064. spin_unlock_irqrestore(&asd_ha->seq.pend_q_lock, flags);
  1065. return 0;
  1066. }
  1067. /**
  1068. * asd_post_escb_list -- post a list of 1 or more empty scb
  1069. * @asd_ha: pointer to a host adapter structure
  1070. * @ascb: pointer to the first empty SCB in the list
  1071. * @num: number of aSCBs in the list (to be posted)
  1072. *
  1073. * This is essentially the same as asd_post_ascb_list, but we do not
  1074. * increment pending, add those to the pending list or get indexes.
  1075. * See asd_init_escbs() and asd_init_post_escbs().
  1076. *
  1077. * Since sending a list of ascbs is a superset of sending a single
  1078. * ascb, this function exists to generalize this. More specifically,
  1079. * when sending a list of those, we want to do only a _single_
  1080. * memcpy() at swap head, as opposed to for each ascb sent (in the
  1081. * case of sending them one by one). That is, we want to minimize the
  1082. * ratio of memcpy() operations to the number of ascbs sent. The same
  1083. * logic applies to asd_post_ascb_list().
  1084. */
  1085. int asd_post_escb_list(struct asd_ha_struct *asd_ha, struct asd_ascb *ascb,
  1086. int num)
  1087. {
  1088. unsigned long flags;
  1089. spin_lock_irqsave(&asd_ha->seq.pend_q_lock, flags);
  1090. asd_swap_head_scb(asd_ha, ascb);
  1091. asd_ha->seq.scbpro += num;
  1092. asd_write_reg_dword(asd_ha, SCBPRO, (u32)asd_ha->seq.scbpro);
  1093. spin_unlock_irqrestore(&asd_ha->seq.pend_q_lock, flags);
  1094. return 0;
  1095. }
  1096. /* ---------- LED ---------- */
  1097. /**
  1098. * asd_turn_led -- turn on/off an LED
  1099. * @asd_ha: pointer to host adapter structure
  1100. * @phy_id: the PHY id whose LED we want to manupulate
  1101. * @op: 1 to turn on, 0 to turn off
  1102. */
  1103. void asd_turn_led(struct asd_ha_struct *asd_ha, int phy_id, int op)
  1104. {
  1105. if (phy_id < ASD_MAX_PHYS) {
  1106. u32 v = asd_read_reg_dword(asd_ha, LmCONTROL(phy_id));
  1107. if (op)
  1108. v |= LEDPOL;
  1109. else
  1110. v &= ~LEDPOL;
  1111. asd_write_reg_dword(asd_ha, LmCONTROL(phy_id), v);
  1112. }
  1113. }
  1114. /**
  1115. * asd_control_led -- enable/disable an LED on the board
  1116. * @asd_ha: pointer to host adapter structure
  1117. * @phy_id: integer, the phy id
  1118. * @op: integer, 1 to enable, 0 to disable the LED
  1119. *
  1120. * First we output enable the LED, then we set the source
  1121. * to be an external module.
  1122. */
  1123. void asd_control_led(struct asd_ha_struct *asd_ha, int phy_id, int op)
  1124. {
  1125. if (phy_id < ASD_MAX_PHYS) {
  1126. u32 v;
  1127. v = asd_read_reg_dword(asd_ha, GPIOOER);
  1128. if (op)
  1129. v |= (1 << phy_id);
  1130. else
  1131. v &= ~(1 << phy_id);
  1132. asd_write_reg_dword(asd_ha, GPIOOER, v);
  1133. v = asd_read_reg_dword(asd_ha, GPIOCNFGR);
  1134. if (op)
  1135. v |= (1 << phy_id);
  1136. else
  1137. v &= ~(1 << phy_id);
  1138. asd_write_reg_dword(asd_ha, GPIOCNFGR, v);
  1139. }
  1140. }
  1141. /* ---------- PHY enable ---------- */
  1142. static int asd_enable_phy(struct asd_ha_struct *asd_ha, int phy_id)
  1143. {
  1144. struct asd_phy *phy = &asd_ha->phys[phy_id];
  1145. asd_write_reg_byte(asd_ha, LmSEQ_OOB_REG(phy_id, INT_ENABLE_2), 0);
  1146. asd_write_reg_byte(asd_ha, LmSEQ_OOB_REG(phy_id, HOT_PLUG_DELAY),
  1147. HOTPLUG_DELAY_TIMEOUT);
  1148. /* Get defaults from manuf. sector */
  1149. /* XXX we need defaults for those in case MS is broken. */
  1150. asd_write_reg_byte(asd_ha, LmSEQ_OOB_REG(phy_id, PHY_CONTROL_0),
  1151. phy->phy_desc->phy_control_0);
  1152. asd_write_reg_byte(asd_ha, LmSEQ_OOB_REG(phy_id, PHY_CONTROL_1),
  1153. phy->phy_desc->phy_control_1);
  1154. asd_write_reg_byte(asd_ha, LmSEQ_OOB_REG(phy_id, PHY_CONTROL_2),
  1155. phy->phy_desc->phy_control_2);
  1156. asd_write_reg_byte(asd_ha, LmSEQ_OOB_REG(phy_id, PHY_CONTROL_3),
  1157. phy->phy_desc->phy_control_3);
  1158. asd_write_reg_dword(asd_ha, LmSEQ_TEN_MS_COMINIT_TIMEOUT(phy_id),
  1159. ASD_COMINIT_TIMEOUT);
  1160. asd_write_reg_addr(asd_ha, LmSEQ_TX_ID_ADDR_FRAME(phy_id),
  1161. phy->id_frm_tok->dma_handle);
  1162. asd_control_led(asd_ha, phy_id, 1);
  1163. return 0;
  1164. }
  1165. int asd_enable_phys(struct asd_ha_struct *asd_ha, const u8 phy_mask)
  1166. {
  1167. u8 phy_m;
  1168. u8 i;
  1169. int num = 0, k;
  1170. struct asd_ascb *ascb;
  1171. struct asd_ascb *ascb_list;
  1172. if (!phy_mask) {
  1173. asd_printk("%s called with phy_mask of 0!?\n", __func__);
  1174. return 0;
  1175. }
  1176. for_each_phy(phy_mask, phy_m, i) {
  1177. num++;
  1178. asd_enable_phy(asd_ha, i);
  1179. }
  1180. k = num;
  1181. ascb_list = asd_ascb_alloc_list(asd_ha, &k, GFP_KERNEL);
  1182. if (!ascb_list) {
  1183. asd_printk("no memory for control phy ascb list\n");
  1184. return -ENOMEM;
  1185. }
  1186. num -= k;
  1187. ascb = ascb_list;
  1188. for_each_phy(phy_mask, phy_m, i) {
  1189. asd_build_control_phy(ascb, i, ENABLE_PHY);
  1190. ascb = list_entry(ascb->list.next, struct asd_ascb, list);
  1191. }
  1192. ASD_DPRINTK("posting %d control phy scbs\n", num);
  1193. k = asd_post_ascb_list(asd_ha, ascb_list, num);
  1194. if (k)
  1195. asd_ascb_free_list(ascb_list);
  1196. return k;
  1197. }