bfa_hw_cb.c 4.6 KB

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  1. /*
  2. * Copyright (c) 2005-2010 Brocade Communications Systems, Inc.
  3. * All rights reserved
  4. * www.brocade.com
  5. *
  6. * Linux driver for Brocade Fibre Channel Host Bus Adapter.
  7. *
  8. * This program is free software; you can redistribute it and/or modify it
  9. * under the terms of the GNU General Public License (GPL) Version 2 as
  10. * published by the Free Software Foundation
  11. *
  12. * This program is distributed in the hope that it will be useful, but
  13. * WITHOUT ANY WARRANTY; without even the implied warranty of
  14. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
  15. * General Public License for more details.
  16. */
  17. #include "bfad_drv.h"
  18. #include "bfa_modules.h"
  19. #include "bfi_reg.h"
  20. void
  21. bfa_hwcb_reginit(struct bfa_s *bfa)
  22. {
  23. struct bfa_iocfc_regs_s *bfa_regs = &bfa->iocfc.bfa_regs;
  24. void __iomem *kva = bfa_ioc_bar0(&bfa->ioc);
  25. int fn = bfa_ioc_pcifn(&bfa->ioc);
  26. if (fn == 0) {
  27. bfa_regs->intr_status = (kva + HOSTFN0_INT_STATUS);
  28. bfa_regs->intr_mask = (kva + HOSTFN0_INT_MSK);
  29. } else {
  30. bfa_regs->intr_status = (kva + HOSTFN1_INT_STATUS);
  31. bfa_regs->intr_mask = (kva + HOSTFN1_INT_MSK);
  32. }
  33. }
  34. static void
  35. bfa_hwcb_reqq_ack_msix(struct bfa_s *bfa, int reqq)
  36. {
  37. writel(__HFN_INT_CPE_Q0 << CPE_Q_NUM(bfa_ioc_pcifn(&bfa->ioc), reqq),
  38. bfa->iocfc.bfa_regs.intr_status);
  39. }
  40. /*
  41. * Actions to respond RME Interrupt for Crossbow ASIC:
  42. * - Write 1 to Interrupt Status register
  43. * INTX - done in bfa_intx()
  44. * MSIX - done in bfa_hwcb_rspq_ack_msix()
  45. * - Update CI (only if new CI)
  46. */
  47. static void
  48. bfa_hwcb_rspq_ack_msix(struct bfa_s *bfa, int rspq, u32 ci)
  49. {
  50. writel(__HFN_INT_RME_Q0 << RME_Q_NUM(bfa_ioc_pcifn(&bfa->ioc), rspq),
  51. bfa->iocfc.bfa_regs.intr_status);
  52. if (bfa_rspq_ci(bfa, rspq) == ci)
  53. return;
  54. bfa_rspq_ci(bfa, rspq) = ci;
  55. writel(ci, bfa->iocfc.bfa_regs.rme_q_ci[rspq]);
  56. mmiowb();
  57. }
  58. void
  59. bfa_hwcb_rspq_ack(struct bfa_s *bfa, int rspq, u32 ci)
  60. {
  61. if (bfa_rspq_ci(bfa, rspq) == ci)
  62. return;
  63. bfa_rspq_ci(bfa, rspq) = ci;
  64. writel(ci, bfa->iocfc.bfa_regs.rme_q_ci[rspq]);
  65. mmiowb();
  66. }
  67. void
  68. bfa_hwcb_msix_getvecs(struct bfa_s *bfa, u32 *msix_vecs_bmap,
  69. u32 *num_vecs, u32 *max_vec_bit)
  70. {
  71. #define __HFN_NUMINTS 13
  72. if (bfa_ioc_pcifn(&bfa->ioc) == 0) {
  73. *msix_vecs_bmap = (__HFN_INT_CPE_Q0 | __HFN_INT_CPE_Q1 |
  74. __HFN_INT_CPE_Q2 | __HFN_INT_CPE_Q3 |
  75. __HFN_INT_RME_Q0 | __HFN_INT_RME_Q1 |
  76. __HFN_INT_RME_Q2 | __HFN_INT_RME_Q3 |
  77. __HFN_INT_MBOX_LPU0);
  78. *max_vec_bit = __HFN_INT_MBOX_LPU0;
  79. } else {
  80. *msix_vecs_bmap = (__HFN_INT_CPE_Q4 | __HFN_INT_CPE_Q5 |
  81. __HFN_INT_CPE_Q6 | __HFN_INT_CPE_Q7 |
  82. __HFN_INT_RME_Q4 | __HFN_INT_RME_Q5 |
  83. __HFN_INT_RME_Q6 | __HFN_INT_RME_Q7 |
  84. __HFN_INT_MBOX_LPU1);
  85. *max_vec_bit = __HFN_INT_MBOX_LPU1;
  86. }
  87. *msix_vecs_bmap |= (__HFN_INT_ERR_EMC | __HFN_INT_ERR_LPU0 |
  88. __HFN_INT_ERR_LPU1 | __HFN_INT_ERR_PSS);
  89. *num_vecs = __HFN_NUMINTS;
  90. }
  91. /*
  92. * Dummy interrupt handler for handling spurious interrupts.
  93. */
  94. static void
  95. bfa_hwcb_msix_dummy(struct bfa_s *bfa, int vec)
  96. {
  97. }
  98. /*
  99. * No special setup required for crossbow -- vector assignments are implicit.
  100. */
  101. void
  102. bfa_hwcb_msix_init(struct bfa_s *bfa, int nvecs)
  103. {
  104. WARN_ON((nvecs != 1) && (nvecs != __HFN_NUMINTS));
  105. bfa->msix.nvecs = nvecs;
  106. bfa_hwcb_msix_uninstall(bfa);
  107. }
  108. void
  109. bfa_hwcb_msix_ctrl_install(struct bfa_s *bfa)
  110. {
  111. int i;
  112. if (bfa->msix.nvecs == 0)
  113. return;
  114. if (bfa->msix.nvecs == 1) {
  115. for (i = BFI_MSIX_CPE_QMIN_CB; i < BFI_MSIX_CB_MAX; i++)
  116. bfa->msix.handler[i] = bfa_msix_all;
  117. return;
  118. }
  119. for (i = BFI_MSIX_RME_QMAX_CB+1; i < BFI_MSIX_CB_MAX; i++)
  120. bfa->msix.handler[i] = bfa_msix_lpu_err;
  121. }
  122. void
  123. bfa_hwcb_msix_queue_install(struct bfa_s *bfa)
  124. {
  125. int i;
  126. if (bfa->msix.nvecs == 0)
  127. return;
  128. if (bfa->msix.nvecs == 1) {
  129. for (i = BFI_MSIX_CPE_QMIN_CB; i <= BFI_MSIX_RME_QMAX_CB; i++)
  130. bfa->msix.handler[i] = bfa_msix_all;
  131. return;
  132. }
  133. for (i = BFI_MSIX_CPE_QMIN_CB; i <= BFI_MSIX_CPE_QMAX_CB; i++)
  134. bfa->msix.handler[i] = bfa_msix_reqq;
  135. for (i = BFI_MSIX_RME_QMIN_CB; i <= BFI_MSIX_RME_QMAX_CB; i++)
  136. bfa->msix.handler[i] = bfa_msix_rspq;
  137. }
  138. void
  139. bfa_hwcb_msix_uninstall(struct bfa_s *bfa)
  140. {
  141. int i;
  142. for (i = 0; i < BFI_MSIX_CB_MAX; i++)
  143. bfa->msix.handler[i] = bfa_hwcb_msix_dummy;
  144. }
  145. /*
  146. * No special enable/disable -- vector assignments are implicit.
  147. */
  148. void
  149. bfa_hwcb_isr_mode_set(struct bfa_s *bfa, bfa_boolean_t msix)
  150. {
  151. if (msix) {
  152. bfa->iocfc.hwif.hw_reqq_ack = bfa_hwcb_reqq_ack_msix;
  153. bfa->iocfc.hwif.hw_rspq_ack = bfa_hwcb_rspq_ack_msix;
  154. } else {
  155. bfa->iocfc.hwif.hw_reqq_ack = NULL;
  156. bfa->iocfc.hwif.hw_rspq_ack = bfa_hwcb_rspq_ack;
  157. }
  158. }
  159. void
  160. bfa_hwcb_msix_get_rme_range(struct bfa_s *bfa, u32 *start, u32 *end)
  161. {
  162. *start = BFI_MSIX_RME_QMIN_CB;
  163. *end = BFI_MSIX_RME_QMAX_CB;
  164. }