bfa_ioc_cb.c 12 KB

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  1. /*
  2. * Copyright (c) 2005-2010 Brocade Communications Systems, Inc.
  3. * All rights reserved
  4. * www.brocade.com
  5. *
  6. * Linux driver for Brocade Fibre Channel Host Bus Adapter.
  7. *
  8. * This program is free software; you can redistribute it and/or modify it
  9. * under the terms of the GNU General Public License (GPL) Version 2 as
  10. * published by the Free Software Foundation
  11. *
  12. * This program is distributed in the hope that it will be useful, but
  13. * WITHOUT ANY WARRANTY; without even the implied warranty of
  14. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
  15. * General Public License for more details.
  16. */
  17. #include "bfad_drv.h"
  18. #include "bfa_ioc.h"
  19. #include "bfi_reg.h"
  20. #include "bfa_defs.h"
  21. BFA_TRC_FILE(CNA, IOC_CB);
  22. #define bfa_ioc_cb_join_pos(__ioc) ((u32) (1 << BFA_IOC_CB_JOIN_SH))
  23. /*
  24. * forward declarations
  25. */
  26. static bfa_boolean_t bfa_ioc_cb_firmware_lock(struct bfa_ioc_s *ioc);
  27. static void bfa_ioc_cb_firmware_unlock(struct bfa_ioc_s *ioc);
  28. static void bfa_ioc_cb_reg_init(struct bfa_ioc_s *ioc);
  29. static void bfa_ioc_cb_map_port(struct bfa_ioc_s *ioc);
  30. static void bfa_ioc_cb_isr_mode_set(struct bfa_ioc_s *ioc, bfa_boolean_t msix);
  31. static void bfa_ioc_cb_notify_fail(struct bfa_ioc_s *ioc);
  32. static void bfa_ioc_cb_ownership_reset(struct bfa_ioc_s *ioc);
  33. static bfa_boolean_t bfa_ioc_cb_sync_start(struct bfa_ioc_s *ioc);
  34. static void bfa_ioc_cb_sync_join(struct bfa_ioc_s *ioc);
  35. static void bfa_ioc_cb_sync_leave(struct bfa_ioc_s *ioc);
  36. static void bfa_ioc_cb_sync_ack(struct bfa_ioc_s *ioc);
  37. static bfa_boolean_t bfa_ioc_cb_sync_complete(struct bfa_ioc_s *ioc);
  38. static void bfa_ioc_cb_set_cur_ioc_fwstate(
  39. struct bfa_ioc_s *ioc, enum bfi_ioc_state fwstate);
  40. static enum bfi_ioc_state bfa_ioc_cb_get_cur_ioc_fwstate(struct bfa_ioc_s *ioc);
  41. static void bfa_ioc_cb_set_alt_ioc_fwstate(
  42. struct bfa_ioc_s *ioc, enum bfi_ioc_state fwstate);
  43. static enum bfi_ioc_state bfa_ioc_cb_get_alt_ioc_fwstate(struct bfa_ioc_s *ioc);
  44. static struct bfa_ioc_hwif_s hwif_cb;
  45. /*
  46. * Called from bfa_ioc_attach() to map asic specific calls.
  47. */
  48. void
  49. bfa_ioc_set_cb_hwif(struct bfa_ioc_s *ioc)
  50. {
  51. hwif_cb.ioc_pll_init = bfa_ioc_cb_pll_init;
  52. hwif_cb.ioc_firmware_lock = bfa_ioc_cb_firmware_lock;
  53. hwif_cb.ioc_firmware_unlock = bfa_ioc_cb_firmware_unlock;
  54. hwif_cb.ioc_reg_init = bfa_ioc_cb_reg_init;
  55. hwif_cb.ioc_map_port = bfa_ioc_cb_map_port;
  56. hwif_cb.ioc_isr_mode_set = bfa_ioc_cb_isr_mode_set;
  57. hwif_cb.ioc_notify_fail = bfa_ioc_cb_notify_fail;
  58. hwif_cb.ioc_ownership_reset = bfa_ioc_cb_ownership_reset;
  59. hwif_cb.ioc_sync_start = bfa_ioc_cb_sync_start;
  60. hwif_cb.ioc_sync_join = bfa_ioc_cb_sync_join;
  61. hwif_cb.ioc_sync_leave = bfa_ioc_cb_sync_leave;
  62. hwif_cb.ioc_sync_ack = bfa_ioc_cb_sync_ack;
  63. hwif_cb.ioc_sync_complete = bfa_ioc_cb_sync_complete;
  64. hwif_cb.ioc_set_fwstate = bfa_ioc_cb_set_cur_ioc_fwstate;
  65. hwif_cb.ioc_get_fwstate = bfa_ioc_cb_get_cur_ioc_fwstate;
  66. hwif_cb.ioc_set_alt_fwstate = bfa_ioc_cb_set_alt_ioc_fwstate;
  67. hwif_cb.ioc_get_alt_fwstate = bfa_ioc_cb_get_alt_ioc_fwstate;
  68. ioc->ioc_hwif = &hwif_cb;
  69. }
  70. /*
  71. * Return true if firmware of current driver matches the running firmware.
  72. */
  73. static bfa_boolean_t
  74. bfa_ioc_cb_firmware_lock(struct bfa_ioc_s *ioc)
  75. {
  76. enum bfi_ioc_state alt_fwstate, cur_fwstate;
  77. struct bfi_ioc_image_hdr_s fwhdr;
  78. cur_fwstate = bfa_ioc_cb_get_cur_ioc_fwstate(ioc);
  79. bfa_trc(ioc, cur_fwstate);
  80. alt_fwstate = bfa_ioc_cb_get_alt_ioc_fwstate(ioc);
  81. bfa_trc(ioc, alt_fwstate);
  82. /*
  83. * Uninit implies this is the only driver as of now.
  84. */
  85. if (cur_fwstate == BFI_IOC_UNINIT)
  86. return BFA_TRUE;
  87. /*
  88. * Check if another driver with a different firmware is active
  89. */
  90. bfa_ioc_fwver_get(ioc, &fwhdr);
  91. if (!bfa_ioc_fwver_cmp(ioc, &fwhdr) &&
  92. alt_fwstate != BFI_IOC_DISABLED) {
  93. bfa_trc(ioc, alt_fwstate);
  94. return BFA_FALSE;
  95. }
  96. return BFA_TRUE;
  97. }
  98. static void
  99. bfa_ioc_cb_firmware_unlock(struct bfa_ioc_s *ioc)
  100. {
  101. }
  102. /*
  103. * Notify other functions on HB failure.
  104. */
  105. static void
  106. bfa_ioc_cb_notify_fail(struct bfa_ioc_s *ioc)
  107. {
  108. writel(~0U, ioc->ioc_regs.err_set);
  109. readl(ioc->ioc_regs.err_set);
  110. }
  111. /*
  112. * Host to LPU mailbox message addresses
  113. */
  114. static struct { u32 hfn_mbox, lpu_mbox, hfn_pgn; } iocreg_fnreg[] = {
  115. { HOSTFN0_LPU_MBOX0_0, LPU_HOSTFN0_MBOX0_0, HOST_PAGE_NUM_FN0 },
  116. { HOSTFN1_LPU_MBOX0_8, LPU_HOSTFN1_MBOX0_8, HOST_PAGE_NUM_FN1 }
  117. };
  118. /*
  119. * Host <-> LPU mailbox command/status registers
  120. */
  121. static struct { u32 hfn, lpu; } iocreg_mbcmd[] = {
  122. { HOSTFN0_LPU0_CMD_STAT, LPU0_HOSTFN0_CMD_STAT },
  123. { HOSTFN1_LPU1_CMD_STAT, LPU1_HOSTFN1_CMD_STAT }
  124. };
  125. static void
  126. bfa_ioc_cb_reg_init(struct bfa_ioc_s *ioc)
  127. {
  128. void __iomem *rb;
  129. int pcifn = bfa_ioc_pcifn(ioc);
  130. rb = bfa_ioc_bar0(ioc);
  131. ioc->ioc_regs.hfn_mbox = rb + iocreg_fnreg[pcifn].hfn_mbox;
  132. ioc->ioc_regs.lpu_mbox = rb + iocreg_fnreg[pcifn].lpu_mbox;
  133. ioc->ioc_regs.host_page_num_fn = rb + iocreg_fnreg[pcifn].hfn_pgn;
  134. if (ioc->port_id == 0) {
  135. ioc->ioc_regs.heartbeat = rb + BFA_IOC0_HBEAT_REG;
  136. ioc->ioc_regs.ioc_fwstate = rb + BFA_IOC0_STATE_REG;
  137. ioc->ioc_regs.alt_ioc_fwstate = rb + BFA_IOC1_STATE_REG;
  138. } else {
  139. ioc->ioc_regs.heartbeat = (rb + BFA_IOC1_HBEAT_REG);
  140. ioc->ioc_regs.ioc_fwstate = (rb + BFA_IOC1_STATE_REG);
  141. ioc->ioc_regs.alt_ioc_fwstate = (rb + BFA_IOC0_STATE_REG);
  142. }
  143. /*
  144. * Host <-> LPU mailbox command/status registers
  145. */
  146. ioc->ioc_regs.hfn_mbox_cmd = rb + iocreg_mbcmd[pcifn].hfn;
  147. ioc->ioc_regs.lpu_mbox_cmd = rb + iocreg_mbcmd[pcifn].lpu;
  148. /*
  149. * PSS control registers
  150. */
  151. ioc->ioc_regs.pss_ctl_reg = (rb + PSS_CTL_REG);
  152. ioc->ioc_regs.pss_err_status_reg = (rb + PSS_ERR_STATUS_REG);
  153. ioc->ioc_regs.app_pll_fast_ctl_reg = (rb + APP_PLL_LCLK_CTL_REG);
  154. ioc->ioc_regs.app_pll_slow_ctl_reg = (rb + APP_PLL_SCLK_CTL_REG);
  155. /*
  156. * IOC semaphore registers and serialization
  157. */
  158. ioc->ioc_regs.ioc_sem_reg = (rb + HOST_SEM0_REG);
  159. ioc->ioc_regs.ioc_init_sem_reg = (rb + HOST_SEM2_REG);
  160. /*
  161. * sram memory access
  162. */
  163. ioc->ioc_regs.smem_page_start = (rb + PSS_SMEM_PAGE_START);
  164. ioc->ioc_regs.smem_pg0 = BFI_IOC_SMEM_PG0_CB;
  165. /*
  166. * err set reg : for notification of hb failure
  167. */
  168. ioc->ioc_regs.err_set = (rb + ERR_SET_REG);
  169. }
  170. /*
  171. * Initialize IOC to port mapping.
  172. */
  173. static void
  174. bfa_ioc_cb_map_port(struct bfa_ioc_s *ioc)
  175. {
  176. /*
  177. * For crossbow, port id is same as pci function.
  178. */
  179. ioc->port_id = bfa_ioc_pcifn(ioc);
  180. bfa_trc(ioc, ioc->port_id);
  181. }
  182. /*
  183. * Set interrupt mode for a function: INTX or MSIX
  184. */
  185. static void
  186. bfa_ioc_cb_isr_mode_set(struct bfa_ioc_s *ioc, bfa_boolean_t msix)
  187. {
  188. }
  189. /*
  190. * Synchronized IOC failure processing routines
  191. */
  192. static bfa_boolean_t
  193. bfa_ioc_cb_sync_start(struct bfa_ioc_s *ioc)
  194. {
  195. u32 ioc_fwstate = readl(ioc->ioc_regs.ioc_fwstate);
  196. /**
  197. * Driver load time. If the join bit is set,
  198. * it is due to an unclean exit by the driver for this
  199. * PCI fn in the previous incarnation. Whoever comes here first
  200. * should clean it up, no matter which PCI fn.
  201. */
  202. if (ioc_fwstate & BFA_IOC_CB_JOIN_MASK) {
  203. writel(BFI_IOC_UNINIT, ioc->ioc_regs.ioc_fwstate);
  204. writel(BFI_IOC_UNINIT, ioc->ioc_regs.alt_ioc_fwstate);
  205. return BFA_TRUE;
  206. }
  207. return bfa_ioc_cb_sync_complete(ioc);
  208. }
  209. /*
  210. * Cleanup hw semaphore and usecnt registers
  211. */
  212. static void
  213. bfa_ioc_cb_ownership_reset(struct bfa_ioc_s *ioc)
  214. {
  215. /*
  216. * Read the hw sem reg to make sure that it is locked
  217. * before we clear it. If it is not locked, writing 1
  218. * will lock it instead of clearing it.
  219. */
  220. readl(ioc->ioc_regs.ioc_sem_reg);
  221. writel(1, ioc->ioc_regs.ioc_sem_reg);
  222. }
  223. /*
  224. * Synchronized IOC failure processing routines
  225. */
  226. static void
  227. bfa_ioc_cb_sync_join(struct bfa_ioc_s *ioc)
  228. {
  229. u32 r32 = readl(ioc->ioc_regs.ioc_fwstate);
  230. u32 join_pos = bfa_ioc_cb_join_pos(ioc);
  231. writel((r32 | join_pos), ioc->ioc_regs.ioc_fwstate);
  232. }
  233. static void
  234. bfa_ioc_cb_sync_leave(struct bfa_ioc_s *ioc)
  235. {
  236. u32 r32 = readl(ioc->ioc_regs.ioc_fwstate);
  237. u32 join_pos = bfa_ioc_cb_join_pos(ioc);
  238. writel((r32 & ~join_pos), ioc->ioc_regs.ioc_fwstate);
  239. }
  240. static void
  241. bfa_ioc_cb_set_cur_ioc_fwstate(struct bfa_ioc_s *ioc,
  242. enum bfi_ioc_state fwstate)
  243. {
  244. u32 r32 = readl(ioc->ioc_regs.ioc_fwstate);
  245. writel((fwstate | (r32 & BFA_IOC_CB_JOIN_MASK)),
  246. ioc->ioc_regs.ioc_fwstate);
  247. }
  248. static enum bfi_ioc_state
  249. bfa_ioc_cb_get_cur_ioc_fwstate(struct bfa_ioc_s *ioc)
  250. {
  251. return (enum bfi_ioc_state)(readl(ioc->ioc_regs.ioc_fwstate) &
  252. BFA_IOC_CB_FWSTATE_MASK);
  253. }
  254. static void
  255. bfa_ioc_cb_set_alt_ioc_fwstate(struct bfa_ioc_s *ioc,
  256. enum bfi_ioc_state fwstate)
  257. {
  258. u32 r32 = readl(ioc->ioc_regs.alt_ioc_fwstate);
  259. writel((fwstate | (r32 & BFA_IOC_CB_JOIN_MASK)),
  260. ioc->ioc_regs.alt_ioc_fwstate);
  261. }
  262. static enum bfi_ioc_state
  263. bfa_ioc_cb_get_alt_ioc_fwstate(struct bfa_ioc_s *ioc)
  264. {
  265. return (enum bfi_ioc_state)(readl(ioc->ioc_regs.alt_ioc_fwstate) &
  266. BFA_IOC_CB_FWSTATE_MASK);
  267. }
  268. static void
  269. bfa_ioc_cb_sync_ack(struct bfa_ioc_s *ioc)
  270. {
  271. bfa_ioc_cb_set_cur_ioc_fwstate(ioc, BFI_IOC_FAIL);
  272. }
  273. static bfa_boolean_t
  274. bfa_ioc_cb_sync_complete(struct bfa_ioc_s *ioc)
  275. {
  276. u32 fwstate, alt_fwstate;
  277. fwstate = bfa_ioc_cb_get_cur_ioc_fwstate(ioc);
  278. /*
  279. * At this point, this IOC is hoding the hw sem in the
  280. * start path (fwcheck) OR in the disable/enable path
  281. * OR to check if the other IOC has acknowledged failure.
  282. *
  283. * So, this IOC can be in UNINIT, INITING, DISABLED, FAIL
  284. * or in MEMTEST states. In a normal scenario, this IOC
  285. * can not be in OP state when this function is called.
  286. *
  287. * However, this IOC could still be in OP state when
  288. * the OS driver is starting up, if the OptROM code has
  289. * left it in that state.
  290. *
  291. * If we had marked this IOC's fwstate as BFI_IOC_FAIL
  292. * in the failure case and now, if the fwstate is not
  293. * BFI_IOC_FAIL it implies that the other PCI fn have
  294. * reinitialized the ASIC or this IOC got disabled, so
  295. * return TRUE.
  296. */
  297. if (fwstate == BFI_IOC_UNINIT ||
  298. fwstate == BFI_IOC_INITING ||
  299. fwstate == BFI_IOC_DISABLED ||
  300. fwstate == BFI_IOC_MEMTEST ||
  301. fwstate == BFI_IOC_OP)
  302. return BFA_TRUE;
  303. else {
  304. alt_fwstate = bfa_ioc_cb_get_alt_ioc_fwstate(ioc);
  305. if (alt_fwstate == BFI_IOC_FAIL ||
  306. alt_fwstate == BFI_IOC_DISABLED ||
  307. alt_fwstate == BFI_IOC_UNINIT ||
  308. alt_fwstate == BFI_IOC_INITING ||
  309. alt_fwstate == BFI_IOC_MEMTEST)
  310. return BFA_TRUE;
  311. else
  312. return BFA_FALSE;
  313. }
  314. }
  315. bfa_status_t
  316. bfa_ioc_cb_pll_init(void __iomem *rb, enum bfi_asic_mode fcmode)
  317. {
  318. u32 pll_sclk, pll_fclk, join_bits;
  319. pll_sclk = __APP_PLL_SCLK_ENABLE | __APP_PLL_SCLK_LRESETN |
  320. __APP_PLL_SCLK_P0_1(3U) |
  321. __APP_PLL_SCLK_JITLMT0_1(3U) |
  322. __APP_PLL_SCLK_CNTLMT0_1(3U);
  323. pll_fclk = __APP_PLL_LCLK_ENABLE | __APP_PLL_LCLK_LRESETN |
  324. __APP_PLL_LCLK_RSEL200500 | __APP_PLL_LCLK_P0_1(3U) |
  325. __APP_PLL_LCLK_JITLMT0_1(3U) |
  326. __APP_PLL_LCLK_CNTLMT0_1(3U);
  327. join_bits = readl(rb + BFA_IOC0_STATE_REG) &
  328. BFA_IOC_CB_JOIN_MASK;
  329. writel((BFI_IOC_UNINIT | join_bits), (rb + BFA_IOC0_STATE_REG));
  330. join_bits = readl(rb + BFA_IOC1_STATE_REG) &
  331. BFA_IOC_CB_JOIN_MASK;
  332. writel((BFI_IOC_UNINIT | join_bits), (rb + BFA_IOC1_STATE_REG));
  333. writel(0xffffffffU, (rb + HOSTFN0_INT_MSK));
  334. writel(0xffffffffU, (rb + HOSTFN1_INT_MSK));
  335. writel(0xffffffffU, (rb + HOSTFN0_INT_STATUS));
  336. writel(0xffffffffU, (rb + HOSTFN1_INT_STATUS));
  337. writel(0xffffffffU, (rb + HOSTFN0_INT_MSK));
  338. writel(0xffffffffU, (rb + HOSTFN1_INT_MSK));
  339. writel(__APP_PLL_SCLK_LOGIC_SOFT_RESET, rb + APP_PLL_SCLK_CTL_REG);
  340. writel(__APP_PLL_SCLK_BYPASS | __APP_PLL_SCLK_LOGIC_SOFT_RESET,
  341. rb + APP_PLL_SCLK_CTL_REG);
  342. writel(__APP_PLL_LCLK_LOGIC_SOFT_RESET, rb + APP_PLL_LCLK_CTL_REG);
  343. writel(__APP_PLL_LCLK_BYPASS | __APP_PLL_LCLK_LOGIC_SOFT_RESET,
  344. rb + APP_PLL_LCLK_CTL_REG);
  345. udelay(2);
  346. writel(__APP_PLL_SCLK_LOGIC_SOFT_RESET, rb + APP_PLL_SCLK_CTL_REG);
  347. writel(__APP_PLL_LCLK_LOGIC_SOFT_RESET, rb + APP_PLL_LCLK_CTL_REG);
  348. writel(pll_sclk | __APP_PLL_SCLK_LOGIC_SOFT_RESET,
  349. rb + APP_PLL_SCLK_CTL_REG);
  350. writel(pll_fclk | __APP_PLL_LCLK_LOGIC_SOFT_RESET,
  351. rb + APP_PLL_LCLK_CTL_REG);
  352. udelay(2000);
  353. writel(0xffffffffU, (rb + HOSTFN0_INT_STATUS));
  354. writel(0xffffffffU, (rb + HOSTFN1_INT_STATUS));
  355. writel(pll_sclk, (rb + APP_PLL_SCLK_CTL_REG));
  356. writel(pll_fclk, (rb + APP_PLL_LCLK_CTL_REG));
  357. return BFA_STATUS_OK;
  358. }