hpsa.c 273 KB

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  1. /*
  2. * Disk Array driver for HP Smart Array SAS controllers
  3. * Copyright 2014-2015 PMC-Sierra, Inc.
  4. * Copyright 2000,2009-2015 Hewlett-Packard Development Company, L.P.
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License as published by
  8. * the Free Software Foundation; version 2 of the License.
  9. *
  10. * This program is distributed in the hope that it will be useful,
  11. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  12. * MERCHANTABILITY OR FITNESS FOR A PARTICULAR PURPOSE, GOOD TITLE or
  13. * NON INFRINGEMENT. See the GNU General Public License for more details.
  14. *
  15. * Questions/Comments/Bugfixes to storagedev@pmcs.com
  16. *
  17. */
  18. #include <linux/module.h>
  19. #include <linux/interrupt.h>
  20. #include <linux/types.h>
  21. #include <linux/pci.h>
  22. #include <linux/pci-aspm.h>
  23. #include <linux/kernel.h>
  24. #include <linux/slab.h>
  25. #include <linux/delay.h>
  26. #include <linux/fs.h>
  27. #include <linux/timer.h>
  28. #include <linux/init.h>
  29. #include <linux/spinlock.h>
  30. #include <linux/compat.h>
  31. #include <linux/blktrace_api.h>
  32. #include <linux/uaccess.h>
  33. #include <linux/io.h>
  34. #include <linux/dma-mapping.h>
  35. #include <linux/completion.h>
  36. #include <linux/moduleparam.h>
  37. #include <scsi/scsi.h>
  38. #include <scsi/scsi_cmnd.h>
  39. #include <scsi/scsi_device.h>
  40. #include <scsi/scsi_host.h>
  41. #include <scsi/scsi_tcq.h>
  42. #include <scsi/scsi_eh.h>
  43. #include <scsi/scsi_transport_sas.h>
  44. #include <scsi/scsi_dbg.h>
  45. #include <linux/cciss_ioctl.h>
  46. #include <linux/string.h>
  47. #include <linux/bitmap.h>
  48. #include <linux/atomic.h>
  49. #include <linux/jiffies.h>
  50. #include <linux/percpu-defs.h>
  51. #include <linux/percpu.h>
  52. #include <asm/unaligned.h>
  53. #include <asm/div64.h>
  54. #include "hpsa_cmd.h"
  55. #include "hpsa.h"
  56. /*
  57. * HPSA_DRIVER_VERSION must be 3 byte values (0-255) separated by '.'
  58. * with an optional trailing '-' followed by a byte value (0-255).
  59. */
  60. #define HPSA_DRIVER_VERSION "3.4.14-0"
  61. #define DRIVER_NAME "HP HPSA Driver (v " HPSA_DRIVER_VERSION ")"
  62. #define HPSA "hpsa"
  63. /* How long to wait for CISS doorbell communication */
  64. #define CLEAR_EVENT_WAIT_INTERVAL 20 /* ms for each msleep() call */
  65. #define MODE_CHANGE_WAIT_INTERVAL 10 /* ms for each msleep() call */
  66. #define MAX_CLEAR_EVENT_WAIT 30000 /* times 20 ms = 600 s */
  67. #define MAX_MODE_CHANGE_WAIT 2000 /* times 10 ms = 20 s */
  68. #define MAX_IOCTL_CONFIG_WAIT 1000
  69. /*define how many times we will try a command because of bus resets */
  70. #define MAX_CMD_RETRIES 3
  71. /* Embedded module documentation macros - see modules.h */
  72. MODULE_AUTHOR("Hewlett-Packard Company");
  73. MODULE_DESCRIPTION("Driver for HP Smart Array Controller version " \
  74. HPSA_DRIVER_VERSION);
  75. MODULE_SUPPORTED_DEVICE("HP Smart Array Controllers");
  76. MODULE_VERSION(HPSA_DRIVER_VERSION);
  77. MODULE_LICENSE("GPL");
  78. static int hpsa_allow_any;
  79. module_param(hpsa_allow_any, int, S_IRUGO|S_IWUSR);
  80. MODULE_PARM_DESC(hpsa_allow_any,
  81. "Allow hpsa driver to access unknown HP Smart Array hardware");
  82. static int hpsa_simple_mode;
  83. module_param(hpsa_simple_mode, int, S_IRUGO|S_IWUSR);
  84. MODULE_PARM_DESC(hpsa_simple_mode,
  85. "Use 'simple mode' rather than 'performant mode'");
  86. /* define the PCI info for the cards we can control */
  87. static const struct pci_device_id hpsa_pci_device_id[] = {
  88. {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3241},
  89. {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3243},
  90. {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3245},
  91. {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3247},
  92. {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3249},
  93. {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x324A},
  94. {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x324B},
  95. {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSE, 0x103C, 0x3233},
  96. {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3350},
  97. {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3351},
  98. {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3352},
  99. {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3353},
  100. {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3354},
  101. {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3355},
  102. {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSF, 0x103C, 0x3356},
  103. {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1921},
  104. {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1922},
  105. {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1923},
  106. {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1924},
  107. {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1926},
  108. {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1928},
  109. {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSH, 0x103C, 0x1929},
  110. {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21BD},
  111. {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21BE},
  112. {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21BF},
  113. {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C0},
  114. {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C1},
  115. {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C2},
  116. {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C3},
  117. {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C4},
  118. {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C5},
  119. {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C6},
  120. {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C7},
  121. {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C8},
  122. {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21C9},
  123. {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21CA},
  124. {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21CB},
  125. {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21CC},
  126. {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21CD},
  127. {PCI_VENDOR_ID_HP, PCI_DEVICE_ID_HP_CISSI, 0x103C, 0x21CE},
  128. {PCI_VENDOR_ID_ADAPTEC2, 0x0290, 0x9005, 0x0580},
  129. {PCI_VENDOR_ID_ADAPTEC2, 0x0290, 0x9005, 0x0581},
  130. {PCI_VENDOR_ID_ADAPTEC2, 0x0290, 0x9005, 0x0582},
  131. {PCI_VENDOR_ID_ADAPTEC2, 0x0290, 0x9005, 0x0583},
  132. {PCI_VENDOR_ID_ADAPTEC2, 0x0290, 0x9005, 0x0584},
  133. {PCI_VENDOR_ID_ADAPTEC2, 0x0290, 0x9005, 0x0585},
  134. {PCI_VENDOR_ID_HP_3PAR, 0x0075, 0x1590, 0x0076},
  135. {PCI_VENDOR_ID_HP_3PAR, 0x0075, 0x1590, 0x0087},
  136. {PCI_VENDOR_ID_HP_3PAR, 0x0075, 0x1590, 0x007D},
  137. {PCI_VENDOR_ID_HP_3PAR, 0x0075, 0x1590, 0x0088},
  138. {PCI_VENDOR_ID_HP, 0x333f, 0x103c, 0x333f},
  139. {PCI_VENDOR_ID_HP, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID,
  140. PCI_CLASS_STORAGE_RAID << 8, 0xffff << 8, 0},
  141. {0,}
  142. };
  143. MODULE_DEVICE_TABLE(pci, hpsa_pci_device_id);
  144. /* board_id = Subsystem Device ID & Vendor ID
  145. * product = Marketing Name for the board
  146. * access = Address of the struct of function pointers
  147. */
  148. static struct board_type products[] = {
  149. {0x3241103C, "Smart Array P212", &SA5_access},
  150. {0x3243103C, "Smart Array P410", &SA5_access},
  151. {0x3245103C, "Smart Array P410i", &SA5_access},
  152. {0x3247103C, "Smart Array P411", &SA5_access},
  153. {0x3249103C, "Smart Array P812", &SA5_access},
  154. {0x324A103C, "Smart Array P712m", &SA5_access},
  155. {0x324B103C, "Smart Array P711m", &SA5_access},
  156. {0x3233103C, "HP StorageWorks 1210m", &SA5_access}, /* alias of 333f */
  157. {0x3350103C, "Smart Array P222", &SA5_access},
  158. {0x3351103C, "Smart Array P420", &SA5_access},
  159. {0x3352103C, "Smart Array P421", &SA5_access},
  160. {0x3353103C, "Smart Array P822", &SA5_access},
  161. {0x3354103C, "Smart Array P420i", &SA5_access},
  162. {0x3355103C, "Smart Array P220i", &SA5_access},
  163. {0x3356103C, "Smart Array P721m", &SA5_access},
  164. {0x1921103C, "Smart Array P830i", &SA5_access},
  165. {0x1922103C, "Smart Array P430", &SA5_access},
  166. {0x1923103C, "Smart Array P431", &SA5_access},
  167. {0x1924103C, "Smart Array P830", &SA5_access},
  168. {0x1926103C, "Smart Array P731m", &SA5_access},
  169. {0x1928103C, "Smart Array P230i", &SA5_access},
  170. {0x1929103C, "Smart Array P530", &SA5_access},
  171. {0x21BD103C, "Smart Array P244br", &SA5_access},
  172. {0x21BE103C, "Smart Array P741m", &SA5_access},
  173. {0x21BF103C, "Smart HBA H240ar", &SA5_access},
  174. {0x21C0103C, "Smart Array P440ar", &SA5_access},
  175. {0x21C1103C, "Smart Array P840ar", &SA5_access},
  176. {0x21C2103C, "Smart Array P440", &SA5_access},
  177. {0x21C3103C, "Smart Array P441", &SA5_access},
  178. {0x21C4103C, "Smart Array", &SA5_access},
  179. {0x21C5103C, "Smart Array P841", &SA5_access},
  180. {0x21C6103C, "Smart HBA H244br", &SA5_access},
  181. {0x21C7103C, "Smart HBA H240", &SA5_access},
  182. {0x21C8103C, "Smart HBA H241", &SA5_access},
  183. {0x21C9103C, "Smart Array", &SA5_access},
  184. {0x21CA103C, "Smart Array P246br", &SA5_access},
  185. {0x21CB103C, "Smart Array P840", &SA5_access},
  186. {0x21CC103C, "Smart Array", &SA5_access},
  187. {0x21CD103C, "Smart Array", &SA5_access},
  188. {0x21CE103C, "Smart HBA", &SA5_access},
  189. {0x05809005, "SmartHBA-SA", &SA5_access},
  190. {0x05819005, "SmartHBA-SA 8i", &SA5_access},
  191. {0x05829005, "SmartHBA-SA 8i8e", &SA5_access},
  192. {0x05839005, "SmartHBA-SA 8e", &SA5_access},
  193. {0x05849005, "SmartHBA-SA 16i", &SA5_access},
  194. {0x05859005, "SmartHBA-SA 4i4e", &SA5_access},
  195. {0x00761590, "HP Storage P1224 Array Controller", &SA5_access},
  196. {0x00871590, "HP Storage P1224e Array Controller", &SA5_access},
  197. {0x007D1590, "HP Storage P1228 Array Controller", &SA5_access},
  198. {0x00881590, "HP Storage P1228e Array Controller", &SA5_access},
  199. {0x333f103c, "HP StorageWorks 1210m Array Controller", &SA5_access},
  200. {0xFFFF103C, "Unknown Smart Array", &SA5_access},
  201. };
  202. static struct scsi_transport_template *hpsa_sas_transport_template;
  203. static int hpsa_add_sas_host(struct ctlr_info *h);
  204. static void hpsa_delete_sas_host(struct ctlr_info *h);
  205. static int hpsa_add_sas_device(struct hpsa_sas_node *hpsa_sas_node,
  206. struct hpsa_scsi_dev_t *device);
  207. static void hpsa_remove_sas_device(struct hpsa_scsi_dev_t *device);
  208. static struct hpsa_scsi_dev_t
  209. *hpsa_find_device_by_sas_rphy(struct ctlr_info *h,
  210. struct sas_rphy *rphy);
  211. #define SCSI_CMD_BUSY ((struct scsi_cmnd *)&hpsa_cmd_busy)
  212. static const struct scsi_cmnd hpsa_cmd_busy;
  213. #define SCSI_CMD_IDLE ((struct scsi_cmnd *)&hpsa_cmd_idle)
  214. static const struct scsi_cmnd hpsa_cmd_idle;
  215. static int number_of_controllers;
  216. static irqreturn_t do_hpsa_intr_intx(int irq, void *dev_id);
  217. static irqreturn_t do_hpsa_intr_msi(int irq, void *dev_id);
  218. static int hpsa_ioctl(struct scsi_device *dev, int cmd, void __user *arg);
  219. #ifdef CONFIG_COMPAT
  220. static int hpsa_compat_ioctl(struct scsi_device *dev, int cmd,
  221. void __user *arg);
  222. #endif
  223. static void cmd_free(struct ctlr_info *h, struct CommandList *c);
  224. static struct CommandList *cmd_alloc(struct ctlr_info *h);
  225. static void cmd_tagged_free(struct ctlr_info *h, struct CommandList *c);
  226. static struct CommandList *cmd_tagged_alloc(struct ctlr_info *h,
  227. struct scsi_cmnd *scmd);
  228. static int fill_cmd(struct CommandList *c, u8 cmd, struct ctlr_info *h,
  229. void *buff, size_t size, u16 page_code, unsigned char *scsi3addr,
  230. int cmd_type);
  231. static void hpsa_free_cmd_pool(struct ctlr_info *h);
  232. #define VPD_PAGE (1 << 8)
  233. #define HPSA_SIMPLE_ERROR_BITS 0x03
  234. static int hpsa_scsi_queue_command(struct Scsi_Host *h, struct scsi_cmnd *cmd);
  235. static void hpsa_scan_start(struct Scsi_Host *);
  236. static int hpsa_scan_finished(struct Scsi_Host *sh,
  237. unsigned long elapsed_time);
  238. static int hpsa_change_queue_depth(struct scsi_device *sdev, int qdepth);
  239. static int hpsa_eh_device_reset_handler(struct scsi_cmnd *scsicmd);
  240. static int hpsa_eh_abort_handler(struct scsi_cmnd *scsicmd);
  241. static int hpsa_slave_alloc(struct scsi_device *sdev);
  242. static int hpsa_slave_configure(struct scsi_device *sdev);
  243. static void hpsa_slave_destroy(struct scsi_device *sdev);
  244. static void hpsa_update_scsi_devices(struct ctlr_info *h);
  245. static int check_for_unit_attention(struct ctlr_info *h,
  246. struct CommandList *c);
  247. static void check_ioctl_unit_attention(struct ctlr_info *h,
  248. struct CommandList *c);
  249. /* performant mode helper functions */
  250. static void calc_bucket_map(int *bucket, int num_buckets,
  251. int nsgs, int min_blocks, u32 *bucket_map);
  252. static void hpsa_free_performant_mode(struct ctlr_info *h);
  253. static int hpsa_put_ctlr_into_performant_mode(struct ctlr_info *h);
  254. static inline u32 next_command(struct ctlr_info *h, u8 q);
  255. static int hpsa_find_cfg_addrs(struct pci_dev *pdev, void __iomem *vaddr,
  256. u32 *cfg_base_addr, u64 *cfg_base_addr_index,
  257. u64 *cfg_offset);
  258. static int hpsa_pci_find_memory_BAR(struct pci_dev *pdev,
  259. unsigned long *memory_bar);
  260. static int hpsa_lookup_board_id(struct pci_dev *pdev, u32 *board_id);
  261. static int hpsa_wait_for_board_state(struct pci_dev *pdev, void __iomem *vaddr,
  262. int wait_for_ready);
  263. static inline void finish_cmd(struct CommandList *c);
  264. static int hpsa_wait_for_mode_change_ack(struct ctlr_info *h);
  265. #define BOARD_NOT_READY 0
  266. #define BOARD_READY 1
  267. static void hpsa_drain_accel_commands(struct ctlr_info *h);
  268. static void hpsa_flush_cache(struct ctlr_info *h);
  269. static int hpsa_scsi_ioaccel_queue_command(struct ctlr_info *h,
  270. struct CommandList *c, u32 ioaccel_handle, u8 *cdb, int cdb_len,
  271. u8 *scsi3addr, struct hpsa_scsi_dev_t *phys_disk);
  272. static void hpsa_command_resubmit_worker(struct work_struct *work);
  273. static u32 lockup_detected(struct ctlr_info *h);
  274. static int detect_controller_lockup(struct ctlr_info *h);
  275. static void hpsa_disable_rld_caching(struct ctlr_info *h);
  276. static inline int hpsa_scsi_do_report_phys_luns(struct ctlr_info *h,
  277. struct ReportExtendedLUNdata *buf, int bufsize);
  278. static int hpsa_luns_changed(struct ctlr_info *h);
  279. static inline struct ctlr_info *sdev_to_hba(struct scsi_device *sdev)
  280. {
  281. unsigned long *priv = shost_priv(sdev->host);
  282. return (struct ctlr_info *) *priv;
  283. }
  284. static inline struct ctlr_info *shost_to_hba(struct Scsi_Host *sh)
  285. {
  286. unsigned long *priv = shost_priv(sh);
  287. return (struct ctlr_info *) *priv;
  288. }
  289. static inline bool hpsa_is_cmd_idle(struct CommandList *c)
  290. {
  291. return c->scsi_cmd == SCSI_CMD_IDLE;
  292. }
  293. static inline bool hpsa_is_pending_event(struct CommandList *c)
  294. {
  295. return c->abort_pending || c->reset_pending;
  296. }
  297. /* extract sense key, asc, and ascq from sense data. -1 means invalid. */
  298. static void decode_sense_data(const u8 *sense_data, int sense_data_len,
  299. u8 *sense_key, u8 *asc, u8 *ascq)
  300. {
  301. struct scsi_sense_hdr sshdr;
  302. bool rc;
  303. *sense_key = -1;
  304. *asc = -1;
  305. *ascq = -1;
  306. if (sense_data_len < 1)
  307. return;
  308. rc = scsi_normalize_sense(sense_data, sense_data_len, &sshdr);
  309. if (rc) {
  310. *sense_key = sshdr.sense_key;
  311. *asc = sshdr.asc;
  312. *ascq = sshdr.ascq;
  313. }
  314. }
  315. static int check_for_unit_attention(struct ctlr_info *h,
  316. struct CommandList *c)
  317. {
  318. u8 sense_key, asc, ascq;
  319. int sense_len;
  320. if (c->err_info->SenseLen > sizeof(c->err_info->SenseInfo))
  321. sense_len = sizeof(c->err_info->SenseInfo);
  322. else
  323. sense_len = c->err_info->SenseLen;
  324. decode_sense_data(c->err_info->SenseInfo, sense_len,
  325. &sense_key, &asc, &ascq);
  326. if (sense_key != UNIT_ATTENTION || asc == 0xff)
  327. return 0;
  328. switch (asc) {
  329. case STATE_CHANGED:
  330. dev_warn(&h->pdev->dev,
  331. "%s: a state change detected, command retried\n",
  332. h->devname);
  333. break;
  334. case LUN_FAILED:
  335. dev_warn(&h->pdev->dev,
  336. "%s: LUN failure detected\n", h->devname);
  337. break;
  338. case REPORT_LUNS_CHANGED:
  339. dev_warn(&h->pdev->dev,
  340. "%s: report LUN data changed\n", h->devname);
  341. /*
  342. * Note: this REPORT_LUNS_CHANGED condition only occurs on the external
  343. * target (array) devices.
  344. */
  345. break;
  346. case POWER_OR_RESET:
  347. dev_warn(&h->pdev->dev,
  348. "%s: a power on or device reset detected\n",
  349. h->devname);
  350. break;
  351. case UNIT_ATTENTION_CLEARED:
  352. dev_warn(&h->pdev->dev,
  353. "%s: unit attention cleared by another initiator\n",
  354. h->devname);
  355. break;
  356. default:
  357. dev_warn(&h->pdev->dev,
  358. "%s: unknown unit attention detected\n",
  359. h->devname);
  360. break;
  361. }
  362. return 1;
  363. }
  364. static int check_for_busy(struct ctlr_info *h, struct CommandList *c)
  365. {
  366. if (c->err_info->CommandStatus != CMD_TARGET_STATUS ||
  367. (c->err_info->ScsiStatus != SAM_STAT_BUSY &&
  368. c->err_info->ScsiStatus != SAM_STAT_TASK_SET_FULL))
  369. return 0;
  370. dev_warn(&h->pdev->dev, HPSA "device busy");
  371. return 1;
  372. }
  373. static u32 lockup_detected(struct ctlr_info *h);
  374. static ssize_t host_show_lockup_detected(struct device *dev,
  375. struct device_attribute *attr, char *buf)
  376. {
  377. int ld;
  378. struct ctlr_info *h;
  379. struct Scsi_Host *shost = class_to_shost(dev);
  380. h = shost_to_hba(shost);
  381. ld = lockup_detected(h);
  382. return sprintf(buf, "ld=%d\n", ld);
  383. }
  384. static ssize_t host_store_hp_ssd_smart_path_status(struct device *dev,
  385. struct device_attribute *attr,
  386. const char *buf, size_t count)
  387. {
  388. int status, len;
  389. struct ctlr_info *h;
  390. struct Scsi_Host *shost = class_to_shost(dev);
  391. char tmpbuf[10];
  392. if (!capable(CAP_SYS_ADMIN) || !capable(CAP_SYS_RAWIO))
  393. return -EACCES;
  394. len = count > sizeof(tmpbuf) - 1 ? sizeof(tmpbuf) - 1 : count;
  395. strncpy(tmpbuf, buf, len);
  396. tmpbuf[len] = '\0';
  397. if (sscanf(tmpbuf, "%d", &status) != 1)
  398. return -EINVAL;
  399. h = shost_to_hba(shost);
  400. h->acciopath_status = !!status;
  401. dev_warn(&h->pdev->dev,
  402. "hpsa: HP SSD Smart Path %s via sysfs update.\n",
  403. h->acciopath_status ? "enabled" : "disabled");
  404. return count;
  405. }
  406. static ssize_t host_store_raid_offload_debug(struct device *dev,
  407. struct device_attribute *attr,
  408. const char *buf, size_t count)
  409. {
  410. int debug_level, len;
  411. struct ctlr_info *h;
  412. struct Scsi_Host *shost = class_to_shost(dev);
  413. char tmpbuf[10];
  414. if (!capable(CAP_SYS_ADMIN) || !capable(CAP_SYS_RAWIO))
  415. return -EACCES;
  416. len = count > sizeof(tmpbuf) - 1 ? sizeof(tmpbuf) - 1 : count;
  417. strncpy(tmpbuf, buf, len);
  418. tmpbuf[len] = '\0';
  419. if (sscanf(tmpbuf, "%d", &debug_level) != 1)
  420. return -EINVAL;
  421. if (debug_level < 0)
  422. debug_level = 0;
  423. h = shost_to_hba(shost);
  424. h->raid_offload_debug = debug_level;
  425. dev_warn(&h->pdev->dev, "hpsa: Set raid_offload_debug level = %d\n",
  426. h->raid_offload_debug);
  427. return count;
  428. }
  429. static ssize_t host_store_rescan(struct device *dev,
  430. struct device_attribute *attr,
  431. const char *buf, size_t count)
  432. {
  433. struct ctlr_info *h;
  434. struct Scsi_Host *shost = class_to_shost(dev);
  435. h = shost_to_hba(shost);
  436. hpsa_scan_start(h->scsi_host);
  437. return count;
  438. }
  439. static ssize_t host_show_firmware_revision(struct device *dev,
  440. struct device_attribute *attr, char *buf)
  441. {
  442. struct ctlr_info *h;
  443. struct Scsi_Host *shost = class_to_shost(dev);
  444. unsigned char *fwrev;
  445. h = shost_to_hba(shost);
  446. if (!h->hba_inquiry_data)
  447. return 0;
  448. fwrev = &h->hba_inquiry_data[32];
  449. return snprintf(buf, 20, "%c%c%c%c\n",
  450. fwrev[0], fwrev[1], fwrev[2], fwrev[3]);
  451. }
  452. static ssize_t host_show_commands_outstanding(struct device *dev,
  453. struct device_attribute *attr, char *buf)
  454. {
  455. struct Scsi_Host *shost = class_to_shost(dev);
  456. struct ctlr_info *h = shost_to_hba(shost);
  457. return snprintf(buf, 20, "%d\n",
  458. atomic_read(&h->commands_outstanding));
  459. }
  460. static ssize_t host_show_transport_mode(struct device *dev,
  461. struct device_attribute *attr, char *buf)
  462. {
  463. struct ctlr_info *h;
  464. struct Scsi_Host *shost = class_to_shost(dev);
  465. h = shost_to_hba(shost);
  466. return snprintf(buf, 20, "%s\n",
  467. h->transMethod & CFGTBL_Trans_Performant ?
  468. "performant" : "simple");
  469. }
  470. static ssize_t host_show_hp_ssd_smart_path_status(struct device *dev,
  471. struct device_attribute *attr, char *buf)
  472. {
  473. struct ctlr_info *h;
  474. struct Scsi_Host *shost = class_to_shost(dev);
  475. h = shost_to_hba(shost);
  476. return snprintf(buf, 30, "HP SSD Smart Path %s\n",
  477. (h->acciopath_status == 1) ? "enabled" : "disabled");
  478. }
  479. /* List of controllers which cannot be hard reset on kexec with reset_devices */
  480. static u32 unresettable_controller[] = {
  481. 0x324a103C, /* Smart Array P712m */
  482. 0x324b103C, /* Smart Array P711m */
  483. 0x3223103C, /* Smart Array P800 */
  484. 0x3234103C, /* Smart Array P400 */
  485. 0x3235103C, /* Smart Array P400i */
  486. 0x3211103C, /* Smart Array E200i */
  487. 0x3212103C, /* Smart Array E200 */
  488. 0x3213103C, /* Smart Array E200i */
  489. 0x3214103C, /* Smart Array E200i */
  490. 0x3215103C, /* Smart Array E200i */
  491. 0x3237103C, /* Smart Array E500 */
  492. 0x323D103C, /* Smart Array P700m */
  493. 0x40800E11, /* Smart Array 5i */
  494. 0x409C0E11, /* Smart Array 6400 */
  495. 0x409D0E11, /* Smart Array 6400 EM */
  496. 0x40700E11, /* Smart Array 5300 */
  497. 0x40820E11, /* Smart Array 532 */
  498. 0x40830E11, /* Smart Array 5312 */
  499. 0x409A0E11, /* Smart Array 641 */
  500. 0x409B0E11, /* Smart Array 642 */
  501. 0x40910E11, /* Smart Array 6i */
  502. };
  503. /* List of controllers which cannot even be soft reset */
  504. static u32 soft_unresettable_controller[] = {
  505. 0x40800E11, /* Smart Array 5i */
  506. 0x40700E11, /* Smart Array 5300 */
  507. 0x40820E11, /* Smart Array 532 */
  508. 0x40830E11, /* Smart Array 5312 */
  509. 0x409A0E11, /* Smart Array 641 */
  510. 0x409B0E11, /* Smart Array 642 */
  511. 0x40910E11, /* Smart Array 6i */
  512. /* Exclude 640x boards. These are two pci devices in one slot
  513. * which share a battery backed cache module. One controls the
  514. * cache, the other accesses the cache through the one that controls
  515. * it. If we reset the one controlling the cache, the other will
  516. * likely not be happy. Just forbid resetting this conjoined mess.
  517. * The 640x isn't really supported by hpsa anyway.
  518. */
  519. 0x409C0E11, /* Smart Array 6400 */
  520. 0x409D0E11, /* Smart Array 6400 EM */
  521. };
  522. static u32 needs_abort_tags_swizzled[] = {
  523. 0x323D103C, /* Smart Array P700m */
  524. 0x324a103C, /* Smart Array P712m */
  525. 0x324b103C, /* SmartArray P711m */
  526. };
  527. static int board_id_in_array(u32 a[], int nelems, u32 board_id)
  528. {
  529. int i;
  530. for (i = 0; i < nelems; i++)
  531. if (a[i] == board_id)
  532. return 1;
  533. return 0;
  534. }
  535. static int ctlr_is_hard_resettable(u32 board_id)
  536. {
  537. return !board_id_in_array(unresettable_controller,
  538. ARRAY_SIZE(unresettable_controller), board_id);
  539. }
  540. static int ctlr_is_soft_resettable(u32 board_id)
  541. {
  542. return !board_id_in_array(soft_unresettable_controller,
  543. ARRAY_SIZE(soft_unresettable_controller), board_id);
  544. }
  545. static int ctlr_is_resettable(u32 board_id)
  546. {
  547. return ctlr_is_hard_resettable(board_id) ||
  548. ctlr_is_soft_resettable(board_id);
  549. }
  550. static int ctlr_needs_abort_tags_swizzled(u32 board_id)
  551. {
  552. return board_id_in_array(needs_abort_tags_swizzled,
  553. ARRAY_SIZE(needs_abort_tags_swizzled), board_id);
  554. }
  555. static ssize_t host_show_resettable(struct device *dev,
  556. struct device_attribute *attr, char *buf)
  557. {
  558. struct ctlr_info *h;
  559. struct Scsi_Host *shost = class_to_shost(dev);
  560. h = shost_to_hba(shost);
  561. return snprintf(buf, 20, "%d\n", ctlr_is_resettable(h->board_id));
  562. }
  563. static inline int is_logical_dev_addr_mode(unsigned char scsi3addr[])
  564. {
  565. return (scsi3addr[3] & 0xC0) == 0x40;
  566. }
  567. static const char * const raid_label[] = { "0", "4", "1(+0)", "5", "5+1", "6",
  568. "1(+0)ADM", "UNKNOWN", "PHYS DRV"
  569. };
  570. #define HPSA_RAID_0 0
  571. #define HPSA_RAID_4 1
  572. #define HPSA_RAID_1 2 /* also used for RAID 10 */
  573. #define HPSA_RAID_5 3 /* also used for RAID 50 */
  574. #define HPSA_RAID_51 4
  575. #define HPSA_RAID_6 5 /* also used for RAID 60 */
  576. #define HPSA_RAID_ADM 6 /* also used for RAID 1+0 ADM */
  577. #define RAID_UNKNOWN (ARRAY_SIZE(raid_label) - 2)
  578. #define PHYSICAL_DRIVE (ARRAY_SIZE(raid_label) - 1)
  579. static inline bool is_logical_device(struct hpsa_scsi_dev_t *device)
  580. {
  581. return !device->physical_device;
  582. }
  583. static ssize_t raid_level_show(struct device *dev,
  584. struct device_attribute *attr, char *buf)
  585. {
  586. ssize_t l = 0;
  587. unsigned char rlevel;
  588. struct ctlr_info *h;
  589. struct scsi_device *sdev;
  590. struct hpsa_scsi_dev_t *hdev;
  591. unsigned long flags;
  592. sdev = to_scsi_device(dev);
  593. h = sdev_to_hba(sdev);
  594. spin_lock_irqsave(&h->lock, flags);
  595. hdev = sdev->hostdata;
  596. if (!hdev) {
  597. spin_unlock_irqrestore(&h->lock, flags);
  598. return -ENODEV;
  599. }
  600. /* Is this even a logical drive? */
  601. if (!is_logical_device(hdev)) {
  602. spin_unlock_irqrestore(&h->lock, flags);
  603. l = snprintf(buf, PAGE_SIZE, "N/A\n");
  604. return l;
  605. }
  606. rlevel = hdev->raid_level;
  607. spin_unlock_irqrestore(&h->lock, flags);
  608. if (rlevel > RAID_UNKNOWN)
  609. rlevel = RAID_UNKNOWN;
  610. l = snprintf(buf, PAGE_SIZE, "RAID %s\n", raid_label[rlevel]);
  611. return l;
  612. }
  613. static ssize_t lunid_show(struct device *dev,
  614. struct device_attribute *attr, char *buf)
  615. {
  616. struct ctlr_info *h;
  617. struct scsi_device *sdev;
  618. struct hpsa_scsi_dev_t *hdev;
  619. unsigned long flags;
  620. unsigned char lunid[8];
  621. sdev = to_scsi_device(dev);
  622. h = sdev_to_hba(sdev);
  623. spin_lock_irqsave(&h->lock, flags);
  624. hdev = sdev->hostdata;
  625. if (!hdev) {
  626. spin_unlock_irqrestore(&h->lock, flags);
  627. return -ENODEV;
  628. }
  629. memcpy(lunid, hdev->scsi3addr, sizeof(lunid));
  630. spin_unlock_irqrestore(&h->lock, flags);
  631. return snprintf(buf, 20, "0x%02x%02x%02x%02x%02x%02x%02x%02x\n",
  632. lunid[0], lunid[1], lunid[2], lunid[3],
  633. lunid[4], lunid[5], lunid[6], lunid[7]);
  634. }
  635. static ssize_t unique_id_show(struct device *dev,
  636. struct device_attribute *attr, char *buf)
  637. {
  638. struct ctlr_info *h;
  639. struct scsi_device *sdev;
  640. struct hpsa_scsi_dev_t *hdev;
  641. unsigned long flags;
  642. unsigned char sn[16];
  643. sdev = to_scsi_device(dev);
  644. h = sdev_to_hba(sdev);
  645. spin_lock_irqsave(&h->lock, flags);
  646. hdev = sdev->hostdata;
  647. if (!hdev) {
  648. spin_unlock_irqrestore(&h->lock, flags);
  649. return -ENODEV;
  650. }
  651. memcpy(sn, hdev->device_id, sizeof(sn));
  652. spin_unlock_irqrestore(&h->lock, flags);
  653. return snprintf(buf, 16 * 2 + 2,
  654. "%02X%02X%02X%02X%02X%02X%02X%02X"
  655. "%02X%02X%02X%02X%02X%02X%02X%02X\n",
  656. sn[0], sn[1], sn[2], sn[3],
  657. sn[4], sn[5], sn[6], sn[7],
  658. sn[8], sn[9], sn[10], sn[11],
  659. sn[12], sn[13], sn[14], sn[15]);
  660. }
  661. static ssize_t host_show_hp_ssd_smart_path_enabled(struct device *dev,
  662. struct device_attribute *attr, char *buf)
  663. {
  664. struct ctlr_info *h;
  665. struct scsi_device *sdev;
  666. struct hpsa_scsi_dev_t *hdev;
  667. unsigned long flags;
  668. int offload_enabled;
  669. sdev = to_scsi_device(dev);
  670. h = sdev_to_hba(sdev);
  671. spin_lock_irqsave(&h->lock, flags);
  672. hdev = sdev->hostdata;
  673. if (!hdev) {
  674. spin_unlock_irqrestore(&h->lock, flags);
  675. return -ENODEV;
  676. }
  677. offload_enabled = hdev->offload_enabled;
  678. spin_unlock_irqrestore(&h->lock, flags);
  679. return snprintf(buf, 20, "%d\n", offload_enabled);
  680. }
  681. #define MAX_PATHS 8
  682. static ssize_t path_info_show(struct device *dev,
  683. struct device_attribute *attr, char *buf)
  684. {
  685. struct ctlr_info *h;
  686. struct scsi_device *sdev;
  687. struct hpsa_scsi_dev_t *hdev;
  688. unsigned long flags;
  689. int i;
  690. int output_len = 0;
  691. u8 box;
  692. u8 bay;
  693. u8 path_map_index = 0;
  694. char *active;
  695. unsigned char phys_connector[2];
  696. sdev = to_scsi_device(dev);
  697. h = sdev_to_hba(sdev);
  698. spin_lock_irqsave(&h->devlock, flags);
  699. hdev = sdev->hostdata;
  700. if (!hdev) {
  701. spin_unlock_irqrestore(&h->devlock, flags);
  702. return -ENODEV;
  703. }
  704. bay = hdev->bay;
  705. for (i = 0; i < MAX_PATHS; i++) {
  706. path_map_index = 1<<i;
  707. if (i == hdev->active_path_index)
  708. active = "Active";
  709. else if (hdev->path_map & path_map_index)
  710. active = "Inactive";
  711. else
  712. continue;
  713. output_len += scnprintf(buf + output_len,
  714. PAGE_SIZE - output_len,
  715. "[%d:%d:%d:%d] %20.20s ",
  716. h->scsi_host->host_no,
  717. hdev->bus, hdev->target, hdev->lun,
  718. scsi_device_type(hdev->devtype));
  719. if (hdev->external ||
  720. hdev->devtype == TYPE_RAID ||
  721. is_logical_device(hdev)) {
  722. output_len += snprintf(buf + output_len,
  723. PAGE_SIZE - output_len,
  724. "%s\n", active);
  725. continue;
  726. }
  727. box = hdev->box[i];
  728. memcpy(&phys_connector, &hdev->phys_connector[i],
  729. sizeof(phys_connector));
  730. if (phys_connector[0] < '0')
  731. phys_connector[0] = '0';
  732. if (phys_connector[1] < '0')
  733. phys_connector[1] = '0';
  734. if (hdev->phys_connector[i] > 0)
  735. output_len += snprintf(buf + output_len,
  736. PAGE_SIZE - output_len,
  737. "PORT: %.2s ",
  738. phys_connector);
  739. if (hdev->devtype == TYPE_DISK && hdev->expose_device) {
  740. if (box == 0 || box == 0xFF) {
  741. output_len += snprintf(buf + output_len,
  742. PAGE_SIZE - output_len,
  743. "BAY: %hhu %s\n",
  744. bay, active);
  745. } else {
  746. output_len += snprintf(buf + output_len,
  747. PAGE_SIZE - output_len,
  748. "BOX: %hhu BAY: %hhu %s\n",
  749. box, bay, active);
  750. }
  751. } else if (box != 0 && box != 0xFF) {
  752. output_len += snprintf(buf + output_len,
  753. PAGE_SIZE - output_len, "BOX: %hhu %s\n",
  754. box, active);
  755. } else
  756. output_len += snprintf(buf + output_len,
  757. PAGE_SIZE - output_len, "%s\n", active);
  758. }
  759. spin_unlock_irqrestore(&h->devlock, flags);
  760. return output_len;
  761. }
  762. static DEVICE_ATTR(raid_level, S_IRUGO, raid_level_show, NULL);
  763. static DEVICE_ATTR(lunid, S_IRUGO, lunid_show, NULL);
  764. static DEVICE_ATTR(unique_id, S_IRUGO, unique_id_show, NULL);
  765. static DEVICE_ATTR(rescan, S_IWUSR, NULL, host_store_rescan);
  766. static DEVICE_ATTR(hp_ssd_smart_path_enabled, S_IRUGO,
  767. host_show_hp_ssd_smart_path_enabled, NULL);
  768. static DEVICE_ATTR(path_info, S_IRUGO, path_info_show, NULL);
  769. static DEVICE_ATTR(hp_ssd_smart_path_status, S_IWUSR|S_IRUGO|S_IROTH,
  770. host_show_hp_ssd_smart_path_status,
  771. host_store_hp_ssd_smart_path_status);
  772. static DEVICE_ATTR(raid_offload_debug, S_IWUSR, NULL,
  773. host_store_raid_offload_debug);
  774. static DEVICE_ATTR(firmware_revision, S_IRUGO,
  775. host_show_firmware_revision, NULL);
  776. static DEVICE_ATTR(commands_outstanding, S_IRUGO,
  777. host_show_commands_outstanding, NULL);
  778. static DEVICE_ATTR(transport_mode, S_IRUGO,
  779. host_show_transport_mode, NULL);
  780. static DEVICE_ATTR(resettable, S_IRUGO,
  781. host_show_resettable, NULL);
  782. static DEVICE_ATTR(lockup_detected, S_IRUGO,
  783. host_show_lockup_detected, NULL);
  784. static struct device_attribute *hpsa_sdev_attrs[] = {
  785. &dev_attr_raid_level,
  786. &dev_attr_lunid,
  787. &dev_attr_unique_id,
  788. &dev_attr_hp_ssd_smart_path_enabled,
  789. &dev_attr_path_info,
  790. NULL,
  791. };
  792. static struct device_attribute *hpsa_shost_attrs[] = {
  793. &dev_attr_rescan,
  794. &dev_attr_firmware_revision,
  795. &dev_attr_commands_outstanding,
  796. &dev_attr_transport_mode,
  797. &dev_attr_resettable,
  798. &dev_attr_hp_ssd_smart_path_status,
  799. &dev_attr_raid_offload_debug,
  800. &dev_attr_lockup_detected,
  801. NULL,
  802. };
  803. #define HPSA_NRESERVED_CMDS (HPSA_CMDS_RESERVED_FOR_ABORTS + \
  804. HPSA_CMDS_RESERVED_FOR_DRIVER + HPSA_MAX_CONCURRENT_PASSTHRUS)
  805. static struct scsi_host_template hpsa_driver_template = {
  806. .module = THIS_MODULE,
  807. .name = HPSA,
  808. .proc_name = HPSA,
  809. .queuecommand = hpsa_scsi_queue_command,
  810. .scan_start = hpsa_scan_start,
  811. .scan_finished = hpsa_scan_finished,
  812. .change_queue_depth = hpsa_change_queue_depth,
  813. .this_id = -1,
  814. .use_clustering = ENABLE_CLUSTERING,
  815. .eh_abort_handler = hpsa_eh_abort_handler,
  816. .eh_device_reset_handler = hpsa_eh_device_reset_handler,
  817. .ioctl = hpsa_ioctl,
  818. .slave_alloc = hpsa_slave_alloc,
  819. .slave_configure = hpsa_slave_configure,
  820. .slave_destroy = hpsa_slave_destroy,
  821. #ifdef CONFIG_COMPAT
  822. .compat_ioctl = hpsa_compat_ioctl,
  823. #endif
  824. .sdev_attrs = hpsa_sdev_attrs,
  825. .shost_attrs = hpsa_shost_attrs,
  826. .max_sectors = 8192,
  827. .no_write_same = 1,
  828. };
  829. static inline u32 next_command(struct ctlr_info *h, u8 q)
  830. {
  831. u32 a;
  832. struct reply_queue_buffer *rq = &h->reply_queue[q];
  833. if (h->transMethod & CFGTBL_Trans_io_accel1)
  834. return h->access.command_completed(h, q);
  835. if (unlikely(!(h->transMethod & CFGTBL_Trans_Performant)))
  836. return h->access.command_completed(h, q);
  837. if ((rq->head[rq->current_entry] & 1) == rq->wraparound) {
  838. a = rq->head[rq->current_entry];
  839. rq->current_entry++;
  840. atomic_dec(&h->commands_outstanding);
  841. } else {
  842. a = FIFO_EMPTY;
  843. }
  844. /* Check for wraparound */
  845. if (rq->current_entry == h->max_commands) {
  846. rq->current_entry = 0;
  847. rq->wraparound ^= 1;
  848. }
  849. return a;
  850. }
  851. /*
  852. * There are some special bits in the bus address of the
  853. * command that we have to set for the controller to know
  854. * how to process the command:
  855. *
  856. * Normal performant mode:
  857. * bit 0: 1 means performant mode, 0 means simple mode.
  858. * bits 1-3 = block fetch table entry
  859. * bits 4-6 = command type (== 0)
  860. *
  861. * ioaccel1 mode:
  862. * bit 0 = "performant mode" bit.
  863. * bits 1-3 = block fetch table entry
  864. * bits 4-6 = command type (== 110)
  865. * (command type is needed because ioaccel1 mode
  866. * commands are submitted through the same register as normal
  867. * mode commands, so this is how the controller knows whether
  868. * the command is normal mode or ioaccel1 mode.)
  869. *
  870. * ioaccel2 mode:
  871. * bit 0 = "performant mode" bit.
  872. * bits 1-4 = block fetch table entry (note extra bit)
  873. * bits 4-6 = not needed, because ioaccel2 mode has
  874. * a separate special register for submitting commands.
  875. */
  876. /*
  877. * set_performant_mode: Modify the tag for cciss performant
  878. * set bit 0 for pull model, bits 3-1 for block fetch
  879. * register number
  880. */
  881. #define DEFAULT_REPLY_QUEUE (-1)
  882. static void set_performant_mode(struct ctlr_info *h, struct CommandList *c,
  883. int reply_queue)
  884. {
  885. if (likely(h->transMethod & CFGTBL_Trans_Performant)) {
  886. c->busaddr |= 1 | (h->blockFetchTable[c->Header.SGList] << 1);
  887. if (unlikely(!h->msix_vector))
  888. return;
  889. if (likely(reply_queue == DEFAULT_REPLY_QUEUE))
  890. c->Header.ReplyQueue =
  891. raw_smp_processor_id() % h->nreply_queues;
  892. else
  893. c->Header.ReplyQueue = reply_queue % h->nreply_queues;
  894. }
  895. }
  896. static void set_ioaccel1_performant_mode(struct ctlr_info *h,
  897. struct CommandList *c,
  898. int reply_queue)
  899. {
  900. struct io_accel1_cmd *cp = &h->ioaccel_cmd_pool[c->cmdindex];
  901. /*
  902. * Tell the controller to post the reply to the queue for this
  903. * processor. This seems to give the best I/O throughput.
  904. */
  905. if (likely(reply_queue == DEFAULT_REPLY_QUEUE))
  906. cp->ReplyQueue = smp_processor_id() % h->nreply_queues;
  907. else
  908. cp->ReplyQueue = reply_queue % h->nreply_queues;
  909. /*
  910. * Set the bits in the address sent down to include:
  911. * - performant mode bit (bit 0)
  912. * - pull count (bits 1-3)
  913. * - command type (bits 4-6)
  914. */
  915. c->busaddr |= 1 | (h->ioaccel1_blockFetchTable[c->Header.SGList] << 1) |
  916. IOACCEL1_BUSADDR_CMDTYPE;
  917. }
  918. static void set_ioaccel2_tmf_performant_mode(struct ctlr_info *h,
  919. struct CommandList *c,
  920. int reply_queue)
  921. {
  922. struct hpsa_tmf_struct *cp = (struct hpsa_tmf_struct *)
  923. &h->ioaccel2_cmd_pool[c->cmdindex];
  924. /* Tell the controller to post the reply to the queue for this
  925. * processor. This seems to give the best I/O throughput.
  926. */
  927. if (likely(reply_queue == DEFAULT_REPLY_QUEUE))
  928. cp->reply_queue = smp_processor_id() % h->nreply_queues;
  929. else
  930. cp->reply_queue = reply_queue % h->nreply_queues;
  931. /* Set the bits in the address sent down to include:
  932. * - performant mode bit not used in ioaccel mode 2
  933. * - pull count (bits 0-3)
  934. * - command type isn't needed for ioaccel2
  935. */
  936. c->busaddr |= h->ioaccel2_blockFetchTable[0];
  937. }
  938. static void set_ioaccel2_performant_mode(struct ctlr_info *h,
  939. struct CommandList *c,
  940. int reply_queue)
  941. {
  942. struct io_accel2_cmd *cp = &h->ioaccel2_cmd_pool[c->cmdindex];
  943. /*
  944. * Tell the controller to post the reply to the queue for this
  945. * processor. This seems to give the best I/O throughput.
  946. */
  947. if (likely(reply_queue == DEFAULT_REPLY_QUEUE))
  948. cp->reply_queue = smp_processor_id() % h->nreply_queues;
  949. else
  950. cp->reply_queue = reply_queue % h->nreply_queues;
  951. /*
  952. * Set the bits in the address sent down to include:
  953. * - performant mode bit not used in ioaccel mode 2
  954. * - pull count (bits 0-3)
  955. * - command type isn't needed for ioaccel2
  956. */
  957. c->busaddr |= (h->ioaccel2_blockFetchTable[cp->sg_count]);
  958. }
  959. static int is_firmware_flash_cmd(u8 *cdb)
  960. {
  961. return cdb[0] == BMIC_WRITE && cdb[6] == BMIC_FLASH_FIRMWARE;
  962. }
  963. /*
  964. * During firmware flash, the heartbeat register may not update as frequently
  965. * as it should. So we dial down lockup detection during firmware flash. and
  966. * dial it back up when firmware flash completes.
  967. */
  968. #define HEARTBEAT_SAMPLE_INTERVAL_DURING_FLASH (240 * HZ)
  969. #define HEARTBEAT_SAMPLE_INTERVAL (30 * HZ)
  970. static void dial_down_lockup_detection_during_fw_flash(struct ctlr_info *h,
  971. struct CommandList *c)
  972. {
  973. if (!is_firmware_flash_cmd(c->Request.CDB))
  974. return;
  975. atomic_inc(&h->firmware_flash_in_progress);
  976. h->heartbeat_sample_interval = HEARTBEAT_SAMPLE_INTERVAL_DURING_FLASH;
  977. }
  978. static void dial_up_lockup_detection_on_fw_flash_complete(struct ctlr_info *h,
  979. struct CommandList *c)
  980. {
  981. if (is_firmware_flash_cmd(c->Request.CDB) &&
  982. atomic_dec_and_test(&h->firmware_flash_in_progress))
  983. h->heartbeat_sample_interval = HEARTBEAT_SAMPLE_INTERVAL;
  984. }
  985. static void __enqueue_cmd_and_start_io(struct ctlr_info *h,
  986. struct CommandList *c, int reply_queue)
  987. {
  988. dial_down_lockup_detection_during_fw_flash(h, c);
  989. atomic_inc(&h->commands_outstanding);
  990. switch (c->cmd_type) {
  991. case CMD_IOACCEL1:
  992. set_ioaccel1_performant_mode(h, c, reply_queue);
  993. writel(c->busaddr, h->vaddr + SA5_REQUEST_PORT_OFFSET);
  994. break;
  995. case CMD_IOACCEL2:
  996. set_ioaccel2_performant_mode(h, c, reply_queue);
  997. writel(c->busaddr, h->vaddr + IOACCEL2_INBOUND_POSTQ_32);
  998. break;
  999. case IOACCEL2_TMF:
  1000. set_ioaccel2_tmf_performant_mode(h, c, reply_queue);
  1001. writel(c->busaddr, h->vaddr + IOACCEL2_INBOUND_POSTQ_32);
  1002. break;
  1003. default:
  1004. set_performant_mode(h, c, reply_queue);
  1005. h->access.submit_command(h, c);
  1006. }
  1007. }
  1008. static void enqueue_cmd_and_start_io(struct ctlr_info *h, struct CommandList *c)
  1009. {
  1010. if (unlikely(hpsa_is_pending_event(c)))
  1011. return finish_cmd(c);
  1012. __enqueue_cmd_and_start_io(h, c, DEFAULT_REPLY_QUEUE);
  1013. }
  1014. static inline int is_hba_lunid(unsigned char scsi3addr[])
  1015. {
  1016. return memcmp(scsi3addr, RAID_CTLR_LUNID, 8) == 0;
  1017. }
  1018. static inline int is_scsi_rev_5(struct ctlr_info *h)
  1019. {
  1020. if (!h->hba_inquiry_data)
  1021. return 0;
  1022. if ((h->hba_inquiry_data[2] & 0x07) == 5)
  1023. return 1;
  1024. return 0;
  1025. }
  1026. static int hpsa_find_target_lun(struct ctlr_info *h,
  1027. unsigned char scsi3addr[], int bus, int *target, int *lun)
  1028. {
  1029. /* finds an unused bus, target, lun for a new physical device
  1030. * assumes h->devlock is held
  1031. */
  1032. int i, found = 0;
  1033. DECLARE_BITMAP(lun_taken, HPSA_MAX_DEVICES);
  1034. bitmap_zero(lun_taken, HPSA_MAX_DEVICES);
  1035. for (i = 0; i < h->ndevices; i++) {
  1036. if (h->dev[i]->bus == bus && h->dev[i]->target != -1)
  1037. __set_bit(h->dev[i]->target, lun_taken);
  1038. }
  1039. i = find_first_zero_bit(lun_taken, HPSA_MAX_DEVICES);
  1040. if (i < HPSA_MAX_DEVICES) {
  1041. /* *bus = 1; */
  1042. *target = i;
  1043. *lun = 0;
  1044. found = 1;
  1045. }
  1046. return !found;
  1047. }
  1048. static void hpsa_show_dev_msg(const char *level, struct ctlr_info *h,
  1049. struct hpsa_scsi_dev_t *dev, char *description)
  1050. {
  1051. #define LABEL_SIZE 25
  1052. char label[LABEL_SIZE];
  1053. if (h == NULL || h->pdev == NULL || h->scsi_host == NULL)
  1054. return;
  1055. switch (dev->devtype) {
  1056. case TYPE_RAID:
  1057. snprintf(label, LABEL_SIZE, "controller");
  1058. break;
  1059. case TYPE_ENCLOSURE:
  1060. snprintf(label, LABEL_SIZE, "enclosure");
  1061. break;
  1062. case TYPE_DISK:
  1063. if (dev->external)
  1064. snprintf(label, LABEL_SIZE, "external");
  1065. else if (!is_logical_dev_addr_mode(dev->scsi3addr))
  1066. snprintf(label, LABEL_SIZE, "%s",
  1067. raid_label[PHYSICAL_DRIVE]);
  1068. else
  1069. snprintf(label, LABEL_SIZE, "RAID-%s",
  1070. dev->raid_level > RAID_UNKNOWN ? "?" :
  1071. raid_label[dev->raid_level]);
  1072. break;
  1073. case TYPE_ROM:
  1074. snprintf(label, LABEL_SIZE, "rom");
  1075. break;
  1076. case TYPE_TAPE:
  1077. snprintf(label, LABEL_SIZE, "tape");
  1078. break;
  1079. case TYPE_MEDIUM_CHANGER:
  1080. snprintf(label, LABEL_SIZE, "changer");
  1081. break;
  1082. default:
  1083. snprintf(label, LABEL_SIZE, "UNKNOWN");
  1084. break;
  1085. }
  1086. dev_printk(level, &h->pdev->dev,
  1087. "scsi %d:%d:%d:%d: %s %s %.8s %.16s %s SSDSmartPathCap%c En%c Exp=%d\n",
  1088. h->scsi_host->host_no, dev->bus, dev->target, dev->lun,
  1089. description,
  1090. scsi_device_type(dev->devtype),
  1091. dev->vendor,
  1092. dev->model,
  1093. label,
  1094. dev->offload_config ? '+' : '-',
  1095. dev->offload_enabled ? '+' : '-',
  1096. dev->expose_device);
  1097. }
  1098. /* Add an entry into h->dev[] array. */
  1099. static int hpsa_scsi_add_entry(struct ctlr_info *h,
  1100. struct hpsa_scsi_dev_t *device,
  1101. struct hpsa_scsi_dev_t *added[], int *nadded)
  1102. {
  1103. /* assumes h->devlock is held */
  1104. int n = h->ndevices;
  1105. int i;
  1106. unsigned char addr1[8], addr2[8];
  1107. struct hpsa_scsi_dev_t *sd;
  1108. if (n >= HPSA_MAX_DEVICES) {
  1109. dev_err(&h->pdev->dev, "too many devices, some will be "
  1110. "inaccessible.\n");
  1111. return -1;
  1112. }
  1113. /* physical devices do not have lun or target assigned until now. */
  1114. if (device->lun != -1)
  1115. /* Logical device, lun is already assigned. */
  1116. goto lun_assigned;
  1117. /* If this device a non-zero lun of a multi-lun device
  1118. * byte 4 of the 8-byte LUN addr will contain the logical
  1119. * unit no, zero otherwise.
  1120. */
  1121. if (device->scsi3addr[4] == 0) {
  1122. /* This is not a non-zero lun of a multi-lun device */
  1123. if (hpsa_find_target_lun(h, device->scsi3addr,
  1124. device->bus, &device->target, &device->lun) != 0)
  1125. return -1;
  1126. goto lun_assigned;
  1127. }
  1128. /* This is a non-zero lun of a multi-lun device.
  1129. * Search through our list and find the device which
  1130. * has the same 8 byte LUN address, excepting byte 4 and 5.
  1131. * Assign the same bus and target for this new LUN.
  1132. * Use the logical unit number from the firmware.
  1133. */
  1134. memcpy(addr1, device->scsi3addr, 8);
  1135. addr1[4] = 0;
  1136. addr1[5] = 0;
  1137. for (i = 0; i < n; i++) {
  1138. sd = h->dev[i];
  1139. memcpy(addr2, sd->scsi3addr, 8);
  1140. addr2[4] = 0;
  1141. addr2[5] = 0;
  1142. /* differ only in byte 4 and 5? */
  1143. if (memcmp(addr1, addr2, 8) == 0) {
  1144. device->bus = sd->bus;
  1145. device->target = sd->target;
  1146. device->lun = device->scsi3addr[4];
  1147. break;
  1148. }
  1149. }
  1150. if (device->lun == -1) {
  1151. dev_warn(&h->pdev->dev, "physical device with no LUN=0,"
  1152. " suspect firmware bug or unsupported hardware "
  1153. "configuration.\n");
  1154. return -1;
  1155. }
  1156. lun_assigned:
  1157. h->dev[n] = device;
  1158. h->ndevices++;
  1159. added[*nadded] = device;
  1160. (*nadded)++;
  1161. hpsa_show_dev_msg(KERN_INFO, h, device,
  1162. device->expose_device ? "added" : "masked");
  1163. device->offload_to_be_enabled = device->offload_enabled;
  1164. device->offload_enabled = 0;
  1165. return 0;
  1166. }
  1167. /* Update an entry in h->dev[] array. */
  1168. static void hpsa_scsi_update_entry(struct ctlr_info *h,
  1169. int entry, struct hpsa_scsi_dev_t *new_entry)
  1170. {
  1171. int offload_enabled;
  1172. /* assumes h->devlock is held */
  1173. BUG_ON(entry < 0 || entry >= HPSA_MAX_DEVICES);
  1174. /* Raid level changed. */
  1175. h->dev[entry]->raid_level = new_entry->raid_level;
  1176. /* Raid offload parameters changed. Careful about the ordering. */
  1177. if (new_entry->offload_config && new_entry->offload_enabled) {
  1178. /*
  1179. * if drive is newly offload_enabled, we want to copy the
  1180. * raid map data first. If previously offload_enabled and
  1181. * offload_config were set, raid map data had better be
  1182. * the same as it was before. if raid map data is changed
  1183. * then it had better be the case that
  1184. * h->dev[entry]->offload_enabled is currently 0.
  1185. */
  1186. h->dev[entry]->raid_map = new_entry->raid_map;
  1187. h->dev[entry]->ioaccel_handle = new_entry->ioaccel_handle;
  1188. }
  1189. if (new_entry->hba_ioaccel_enabled) {
  1190. h->dev[entry]->ioaccel_handle = new_entry->ioaccel_handle;
  1191. wmb(); /* set ioaccel_handle *before* hba_ioaccel_enabled */
  1192. }
  1193. h->dev[entry]->hba_ioaccel_enabled = new_entry->hba_ioaccel_enabled;
  1194. h->dev[entry]->offload_config = new_entry->offload_config;
  1195. h->dev[entry]->offload_to_mirror = new_entry->offload_to_mirror;
  1196. h->dev[entry]->queue_depth = new_entry->queue_depth;
  1197. /*
  1198. * We can turn off ioaccel offload now, but need to delay turning
  1199. * it on until we can update h->dev[entry]->phys_disk[], but we
  1200. * can't do that until all the devices are updated.
  1201. */
  1202. h->dev[entry]->offload_to_be_enabled = new_entry->offload_enabled;
  1203. if (!new_entry->offload_enabled)
  1204. h->dev[entry]->offload_enabled = 0;
  1205. offload_enabled = h->dev[entry]->offload_enabled;
  1206. h->dev[entry]->offload_enabled = h->dev[entry]->offload_to_be_enabled;
  1207. hpsa_show_dev_msg(KERN_INFO, h, h->dev[entry], "updated");
  1208. h->dev[entry]->offload_enabled = offload_enabled;
  1209. }
  1210. /* Replace an entry from h->dev[] array. */
  1211. static void hpsa_scsi_replace_entry(struct ctlr_info *h,
  1212. int entry, struct hpsa_scsi_dev_t *new_entry,
  1213. struct hpsa_scsi_dev_t *added[], int *nadded,
  1214. struct hpsa_scsi_dev_t *removed[], int *nremoved)
  1215. {
  1216. /* assumes h->devlock is held */
  1217. BUG_ON(entry < 0 || entry >= HPSA_MAX_DEVICES);
  1218. removed[*nremoved] = h->dev[entry];
  1219. (*nremoved)++;
  1220. /*
  1221. * New physical devices won't have target/lun assigned yet
  1222. * so we need to preserve the values in the slot we are replacing.
  1223. */
  1224. if (new_entry->target == -1) {
  1225. new_entry->target = h->dev[entry]->target;
  1226. new_entry->lun = h->dev[entry]->lun;
  1227. }
  1228. h->dev[entry] = new_entry;
  1229. added[*nadded] = new_entry;
  1230. (*nadded)++;
  1231. hpsa_show_dev_msg(KERN_INFO, h, new_entry, "replaced");
  1232. new_entry->offload_to_be_enabled = new_entry->offload_enabled;
  1233. new_entry->offload_enabled = 0;
  1234. }
  1235. /* Remove an entry from h->dev[] array. */
  1236. static void hpsa_scsi_remove_entry(struct ctlr_info *h, int entry,
  1237. struct hpsa_scsi_dev_t *removed[], int *nremoved)
  1238. {
  1239. /* assumes h->devlock is held */
  1240. int i;
  1241. struct hpsa_scsi_dev_t *sd;
  1242. BUG_ON(entry < 0 || entry >= HPSA_MAX_DEVICES);
  1243. sd = h->dev[entry];
  1244. removed[*nremoved] = h->dev[entry];
  1245. (*nremoved)++;
  1246. for (i = entry; i < h->ndevices-1; i++)
  1247. h->dev[i] = h->dev[i+1];
  1248. h->ndevices--;
  1249. hpsa_show_dev_msg(KERN_INFO, h, sd, "removed");
  1250. }
  1251. #define SCSI3ADDR_EQ(a, b) ( \
  1252. (a)[7] == (b)[7] && \
  1253. (a)[6] == (b)[6] && \
  1254. (a)[5] == (b)[5] && \
  1255. (a)[4] == (b)[4] && \
  1256. (a)[3] == (b)[3] && \
  1257. (a)[2] == (b)[2] && \
  1258. (a)[1] == (b)[1] && \
  1259. (a)[0] == (b)[0])
  1260. static void fixup_botched_add(struct ctlr_info *h,
  1261. struct hpsa_scsi_dev_t *added)
  1262. {
  1263. /* called when scsi_add_device fails in order to re-adjust
  1264. * h->dev[] to match the mid layer's view.
  1265. */
  1266. unsigned long flags;
  1267. int i, j;
  1268. spin_lock_irqsave(&h->lock, flags);
  1269. for (i = 0; i < h->ndevices; i++) {
  1270. if (h->dev[i] == added) {
  1271. for (j = i; j < h->ndevices-1; j++)
  1272. h->dev[j] = h->dev[j+1];
  1273. h->ndevices--;
  1274. break;
  1275. }
  1276. }
  1277. spin_unlock_irqrestore(&h->lock, flags);
  1278. kfree(added);
  1279. }
  1280. static inline int device_is_the_same(struct hpsa_scsi_dev_t *dev1,
  1281. struct hpsa_scsi_dev_t *dev2)
  1282. {
  1283. /* we compare everything except lun and target as these
  1284. * are not yet assigned. Compare parts likely
  1285. * to differ first
  1286. */
  1287. if (memcmp(dev1->scsi3addr, dev2->scsi3addr,
  1288. sizeof(dev1->scsi3addr)) != 0)
  1289. return 0;
  1290. if (memcmp(dev1->device_id, dev2->device_id,
  1291. sizeof(dev1->device_id)) != 0)
  1292. return 0;
  1293. if (memcmp(dev1->model, dev2->model, sizeof(dev1->model)) != 0)
  1294. return 0;
  1295. if (memcmp(dev1->vendor, dev2->vendor, sizeof(dev1->vendor)) != 0)
  1296. return 0;
  1297. if (dev1->devtype != dev2->devtype)
  1298. return 0;
  1299. if (dev1->bus != dev2->bus)
  1300. return 0;
  1301. return 1;
  1302. }
  1303. static inline int device_updated(struct hpsa_scsi_dev_t *dev1,
  1304. struct hpsa_scsi_dev_t *dev2)
  1305. {
  1306. /* Device attributes that can change, but don't mean
  1307. * that the device is a different device, nor that the OS
  1308. * needs to be told anything about the change.
  1309. */
  1310. if (dev1->raid_level != dev2->raid_level)
  1311. return 1;
  1312. if (dev1->offload_config != dev2->offload_config)
  1313. return 1;
  1314. if (dev1->offload_enabled != dev2->offload_enabled)
  1315. return 1;
  1316. if (!is_logical_dev_addr_mode(dev1->scsi3addr))
  1317. if (dev1->queue_depth != dev2->queue_depth)
  1318. return 1;
  1319. return 0;
  1320. }
  1321. /* Find needle in haystack. If exact match found, return DEVICE_SAME,
  1322. * and return needle location in *index. If scsi3addr matches, but not
  1323. * vendor, model, serial num, etc. return DEVICE_CHANGED, and return needle
  1324. * location in *index.
  1325. * In the case of a minor device attribute change, such as RAID level, just
  1326. * return DEVICE_UPDATED, along with the updated device's location in index.
  1327. * If needle not found, return DEVICE_NOT_FOUND.
  1328. */
  1329. static int hpsa_scsi_find_entry(struct hpsa_scsi_dev_t *needle,
  1330. struct hpsa_scsi_dev_t *haystack[], int haystack_size,
  1331. int *index)
  1332. {
  1333. int i;
  1334. #define DEVICE_NOT_FOUND 0
  1335. #define DEVICE_CHANGED 1
  1336. #define DEVICE_SAME 2
  1337. #define DEVICE_UPDATED 3
  1338. if (needle == NULL)
  1339. return DEVICE_NOT_FOUND;
  1340. for (i = 0; i < haystack_size; i++) {
  1341. if (haystack[i] == NULL) /* previously removed. */
  1342. continue;
  1343. if (SCSI3ADDR_EQ(needle->scsi3addr, haystack[i]->scsi3addr)) {
  1344. *index = i;
  1345. if (device_is_the_same(needle, haystack[i])) {
  1346. if (device_updated(needle, haystack[i]))
  1347. return DEVICE_UPDATED;
  1348. return DEVICE_SAME;
  1349. } else {
  1350. /* Keep offline devices offline */
  1351. if (needle->volume_offline)
  1352. return DEVICE_NOT_FOUND;
  1353. return DEVICE_CHANGED;
  1354. }
  1355. }
  1356. }
  1357. *index = -1;
  1358. return DEVICE_NOT_FOUND;
  1359. }
  1360. static void hpsa_monitor_offline_device(struct ctlr_info *h,
  1361. unsigned char scsi3addr[])
  1362. {
  1363. struct offline_device_entry *device;
  1364. unsigned long flags;
  1365. /* Check to see if device is already on the list */
  1366. spin_lock_irqsave(&h->offline_device_lock, flags);
  1367. list_for_each_entry(device, &h->offline_device_list, offline_list) {
  1368. if (memcmp(device->scsi3addr, scsi3addr,
  1369. sizeof(device->scsi3addr)) == 0) {
  1370. spin_unlock_irqrestore(&h->offline_device_lock, flags);
  1371. return;
  1372. }
  1373. }
  1374. spin_unlock_irqrestore(&h->offline_device_lock, flags);
  1375. /* Device is not on the list, add it. */
  1376. device = kmalloc(sizeof(*device), GFP_KERNEL);
  1377. if (!device) {
  1378. dev_warn(&h->pdev->dev, "out of memory in %s\n", __func__);
  1379. return;
  1380. }
  1381. memcpy(device->scsi3addr, scsi3addr, sizeof(device->scsi3addr));
  1382. spin_lock_irqsave(&h->offline_device_lock, flags);
  1383. list_add_tail(&device->offline_list, &h->offline_device_list);
  1384. spin_unlock_irqrestore(&h->offline_device_lock, flags);
  1385. }
  1386. /* Print a message explaining various offline volume states */
  1387. static void hpsa_show_volume_status(struct ctlr_info *h,
  1388. struct hpsa_scsi_dev_t *sd)
  1389. {
  1390. if (sd->volume_offline == HPSA_VPD_LV_STATUS_UNSUPPORTED)
  1391. dev_info(&h->pdev->dev,
  1392. "C%d:B%d:T%d:L%d Volume status is not available through vital product data pages.\n",
  1393. h->scsi_host->host_no,
  1394. sd->bus, sd->target, sd->lun);
  1395. switch (sd->volume_offline) {
  1396. case HPSA_LV_OK:
  1397. break;
  1398. case HPSA_LV_UNDERGOING_ERASE:
  1399. dev_info(&h->pdev->dev,
  1400. "C%d:B%d:T%d:L%d Volume is undergoing background erase process.\n",
  1401. h->scsi_host->host_no,
  1402. sd->bus, sd->target, sd->lun);
  1403. break;
  1404. case HPSA_LV_NOT_AVAILABLE:
  1405. dev_info(&h->pdev->dev,
  1406. "C%d:B%d:T%d:L%d Volume is waiting for transforming volume.\n",
  1407. h->scsi_host->host_no,
  1408. sd->bus, sd->target, sd->lun);
  1409. break;
  1410. case HPSA_LV_UNDERGOING_RPI:
  1411. dev_info(&h->pdev->dev,
  1412. "C%d:B%d:T%d:L%d Volume is undergoing rapid parity init.\n",
  1413. h->scsi_host->host_no,
  1414. sd->bus, sd->target, sd->lun);
  1415. break;
  1416. case HPSA_LV_PENDING_RPI:
  1417. dev_info(&h->pdev->dev,
  1418. "C%d:B%d:T%d:L%d Volume is queued for rapid parity initialization process.\n",
  1419. h->scsi_host->host_no,
  1420. sd->bus, sd->target, sd->lun);
  1421. break;
  1422. case HPSA_LV_ENCRYPTED_NO_KEY:
  1423. dev_info(&h->pdev->dev,
  1424. "C%d:B%d:T%d:L%d Volume is encrypted and cannot be accessed because key is not present.\n",
  1425. h->scsi_host->host_no,
  1426. sd->bus, sd->target, sd->lun);
  1427. break;
  1428. case HPSA_LV_PLAINTEXT_IN_ENCRYPT_ONLY_CONTROLLER:
  1429. dev_info(&h->pdev->dev,
  1430. "C%d:B%d:T%d:L%d Volume is not encrypted and cannot be accessed because controller is in encryption-only mode.\n",
  1431. h->scsi_host->host_no,
  1432. sd->bus, sd->target, sd->lun);
  1433. break;
  1434. case HPSA_LV_UNDERGOING_ENCRYPTION:
  1435. dev_info(&h->pdev->dev,
  1436. "C%d:B%d:T%d:L%d Volume is undergoing encryption process.\n",
  1437. h->scsi_host->host_no,
  1438. sd->bus, sd->target, sd->lun);
  1439. break;
  1440. case HPSA_LV_UNDERGOING_ENCRYPTION_REKEYING:
  1441. dev_info(&h->pdev->dev,
  1442. "C%d:B%d:T%d:L%d Volume is undergoing encryption re-keying process.\n",
  1443. h->scsi_host->host_no,
  1444. sd->bus, sd->target, sd->lun);
  1445. break;
  1446. case HPSA_LV_ENCRYPTED_IN_NON_ENCRYPTED_CONTROLLER:
  1447. dev_info(&h->pdev->dev,
  1448. "C%d:B%d:T%d:L%d Volume is encrypted and cannot be accessed because controller does not have encryption enabled.\n",
  1449. h->scsi_host->host_no,
  1450. sd->bus, sd->target, sd->lun);
  1451. break;
  1452. case HPSA_LV_PENDING_ENCRYPTION:
  1453. dev_info(&h->pdev->dev,
  1454. "C%d:B%d:T%d:L%d Volume is pending migration to encrypted state, but process has not started.\n",
  1455. h->scsi_host->host_no,
  1456. sd->bus, sd->target, sd->lun);
  1457. break;
  1458. case HPSA_LV_PENDING_ENCRYPTION_REKEYING:
  1459. dev_info(&h->pdev->dev,
  1460. "C%d:B%d:T%d:L%d Volume is encrypted and is pending encryption rekeying.\n",
  1461. h->scsi_host->host_no,
  1462. sd->bus, sd->target, sd->lun);
  1463. break;
  1464. }
  1465. }
  1466. /*
  1467. * Figure the list of physical drive pointers for a logical drive with
  1468. * raid offload configured.
  1469. */
  1470. static void hpsa_figure_phys_disk_ptrs(struct ctlr_info *h,
  1471. struct hpsa_scsi_dev_t *dev[], int ndevices,
  1472. struct hpsa_scsi_dev_t *logical_drive)
  1473. {
  1474. struct raid_map_data *map = &logical_drive->raid_map;
  1475. struct raid_map_disk_data *dd = &map->data[0];
  1476. int i, j;
  1477. int total_disks_per_row = le16_to_cpu(map->data_disks_per_row) +
  1478. le16_to_cpu(map->metadata_disks_per_row);
  1479. int nraid_map_entries = le16_to_cpu(map->row_cnt) *
  1480. le16_to_cpu(map->layout_map_count) *
  1481. total_disks_per_row;
  1482. int nphys_disk = le16_to_cpu(map->layout_map_count) *
  1483. total_disks_per_row;
  1484. int qdepth;
  1485. if (nraid_map_entries > RAID_MAP_MAX_ENTRIES)
  1486. nraid_map_entries = RAID_MAP_MAX_ENTRIES;
  1487. logical_drive->nphysical_disks = nraid_map_entries;
  1488. qdepth = 0;
  1489. for (i = 0; i < nraid_map_entries; i++) {
  1490. logical_drive->phys_disk[i] = NULL;
  1491. if (!logical_drive->offload_config)
  1492. continue;
  1493. for (j = 0; j < ndevices; j++) {
  1494. if (dev[j] == NULL)
  1495. continue;
  1496. if (dev[j]->devtype != TYPE_DISK)
  1497. continue;
  1498. if (is_logical_device(dev[j]))
  1499. continue;
  1500. if (dev[j]->ioaccel_handle != dd[i].ioaccel_handle)
  1501. continue;
  1502. logical_drive->phys_disk[i] = dev[j];
  1503. if (i < nphys_disk)
  1504. qdepth = min(h->nr_cmds, qdepth +
  1505. logical_drive->phys_disk[i]->queue_depth);
  1506. break;
  1507. }
  1508. /*
  1509. * This can happen if a physical drive is removed and
  1510. * the logical drive is degraded. In that case, the RAID
  1511. * map data will refer to a physical disk which isn't actually
  1512. * present. And in that case offload_enabled should already
  1513. * be 0, but we'll turn it off here just in case
  1514. */
  1515. if (!logical_drive->phys_disk[i]) {
  1516. logical_drive->offload_enabled = 0;
  1517. logical_drive->offload_to_be_enabled = 0;
  1518. logical_drive->queue_depth = 8;
  1519. }
  1520. }
  1521. if (nraid_map_entries)
  1522. /*
  1523. * This is correct for reads, too high for full stripe writes,
  1524. * way too high for partial stripe writes
  1525. */
  1526. logical_drive->queue_depth = qdepth;
  1527. else
  1528. logical_drive->queue_depth = h->nr_cmds;
  1529. }
  1530. static void hpsa_update_log_drive_phys_drive_ptrs(struct ctlr_info *h,
  1531. struct hpsa_scsi_dev_t *dev[], int ndevices)
  1532. {
  1533. int i;
  1534. for (i = 0; i < ndevices; i++) {
  1535. if (dev[i] == NULL)
  1536. continue;
  1537. if (dev[i]->devtype != TYPE_DISK)
  1538. continue;
  1539. if (!is_logical_device(dev[i]))
  1540. continue;
  1541. /*
  1542. * If offload is currently enabled, the RAID map and
  1543. * phys_disk[] assignment *better* not be changing
  1544. * and since it isn't changing, we do not need to
  1545. * update it.
  1546. */
  1547. if (dev[i]->offload_enabled)
  1548. continue;
  1549. hpsa_figure_phys_disk_ptrs(h, dev, ndevices, dev[i]);
  1550. }
  1551. }
  1552. static int hpsa_add_device(struct ctlr_info *h, struct hpsa_scsi_dev_t *device)
  1553. {
  1554. int rc = 0;
  1555. if (!h->scsi_host)
  1556. return 1;
  1557. if (is_logical_device(device)) /* RAID */
  1558. rc = scsi_add_device(h->scsi_host, device->bus,
  1559. device->target, device->lun);
  1560. else /* HBA */
  1561. rc = hpsa_add_sas_device(h->sas_host, device);
  1562. return rc;
  1563. }
  1564. static void hpsa_remove_device(struct ctlr_info *h,
  1565. struct hpsa_scsi_dev_t *device)
  1566. {
  1567. struct scsi_device *sdev = NULL;
  1568. if (!h->scsi_host)
  1569. return;
  1570. if (is_logical_device(device)) { /* RAID */
  1571. sdev = scsi_device_lookup(h->scsi_host, device->bus,
  1572. device->target, device->lun);
  1573. if (sdev) {
  1574. scsi_remove_device(sdev);
  1575. scsi_device_put(sdev);
  1576. } else {
  1577. /*
  1578. * We don't expect to get here. Future commands
  1579. * to this device will get a selection timeout as
  1580. * if the device were gone.
  1581. */
  1582. hpsa_show_dev_msg(KERN_WARNING, h, device,
  1583. "didn't find device for removal.");
  1584. }
  1585. } else /* HBA */
  1586. hpsa_remove_sas_device(device);
  1587. }
  1588. static void adjust_hpsa_scsi_table(struct ctlr_info *h,
  1589. struct hpsa_scsi_dev_t *sd[], int nsds)
  1590. {
  1591. /* sd contains scsi3 addresses and devtypes, and inquiry
  1592. * data. This function takes what's in sd to be the current
  1593. * reality and updates h->dev[] to reflect that reality.
  1594. */
  1595. int i, entry, device_change, changes = 0;
  1596. struct hpsa_scsi_dev_t *csd;
  1597. unsigned long flags;
  1598. struct hpsa_scsi_dev_t **added, **removed;
  1599. int nadded, nremoved;
  1600. /*
  1601. * A reset can cause a device status to change
  1602. * re-schedule the scan to see what happened.
  1603. */
  1604. if (h->reset_in_progress) {
  1605. h->drv_req_rescan = 1;
  1606. return;
  1607. }
  1608. added = kzalloc(sizeof(*added) * HPSA_MAX_DEVICES, GFP_KERNEL);
  1609. removed = kzalloc(sizeof(*removed) * HPSA_MAX_DEVICES, GFP_KERNEL);
  1610. if (!added || !removed) {
  1611. dev_warn(&h->pdev->dev, "out of memory in "
  1612. "adjust_hpsa_scsi_table\n");
  1613. goto free_and_out;
  1614. }
  1615. spin_lock_irqsave(&h->devlock, flags);
  1616. /* find any devices in h->dev[] that are not in
  1617. * sd[] and remove them from h->dev[], and for any
  1618. * devices which have changed, remove the old device
  1619. * info and add the new device info.
  1620. * If minor device attributes change, just update
  1621. * the existing device structure.
  1622. */
  1623. i = 0;
  1624. nremoved = 0;
  1625. nadded = 0;
  1626. while (i < h->ndevices) {
  1627. csd = h->dev[i];
  1628. device_change = hpsa_scsi_find_entry(csd, sd, nsds, &entry);
  1629. if (device_change == DEVICE_NOT_FOUND) {
  1630. changes++;
  1631. hpsa_scsi_remove_entry(h, i, removed, &nremoved);
  1632. continue; /* remove ^^^, hence i not incremented */
  1633. } else if (device_change == DEVICE_CHANGED) {
  1634. changes++;
  1635. hpsa_scsi_replace_entry(h, i, sd[entry],
  1636. added, &nadded, removed, &nremoved);
  1637. /* Set it to NULL to prevent it from being freed
  1638. * at the bottom of hpsa_update_scsi_devices()
  1639. */
  1640. sd[entry] = NULL;
  1641. } else if (device_change == DEVICE_UPDATED) {
  1642. hpsa_scsi_update_entry(h, i, sd[entry]);
  1643. }
  1644. i++;
  1645. }
  1646. /* Now, make sure every device listed in sd[] is also
  1647. * listed in h->dev[], adding them if they aren't found
  1648. */
  1649. for (i = 0; i < nsds; i++) {
  1650. if (!sd[i]) /* if already added above. */
  1651. continue;
  1652. /* Don't add devices which are NOT READY, FORMAT IN PROGRESS
  1653. * as the SCSI mid-layer does not handle such devices well.
  1654. * It relentlessly loops sending TUR at 3Hz, then READ(10)
  1655. * at 160Hz, and prevents the system from coming up.
  1656. */
  1657. if (sd[i]->volume_offline) {
  1658. hpsa_show_volume_status(h, sd[i]);
  1659. hpsa_show_dev_msg(KERN_INFO, h, sd[i], "offline");
  1660. continue;
  1661. }
  1662. device_change = hpsa_scsi_find_entry(sd[i], h->dev,
  1663. h->ndevices, &entry);
  1664. if (device_change == DEVICE_NOT_FOUND) {
  1665. changes++;
  1666. if (hpsa_scsi_add_entry(h, sd[i], added, &nadded) != 0)
  1667. break;
  1668. sd[i] = NULL; /* prevent from being freed later. */
  1669. } else if (device_change == DEVICE_CHANGED) {
  1670. /* should never happen... */
  1671. changes++;
  1672. dev_warn(&h->pdev->dev,
  1673. "device unexpectedly changed.\n");
  1674. /* but if it does happen, we just ignore that device */
  1675. }
  1676. }
  1677. hpsa_update_log_drive_phys_drive_ptrs(h, h->dev, h->ndevices);
  1678. /* Now that h->dev[]->phys_disk[] is coherent, we can enable
  1679. * any logical drives that need it enabled.
  1680. */
  1681. for (i = 0; i < h->ndevices; i++) {
  1682. if (h->dev[i] == NULL)
  1683. continue;
  1684. h->dev[i]->offload_enabled = h->dev[i]->offload_to_be_enabled;
  1685. }
  1686. spin_unlock_irqrestore(&h->devlock, flags);
  1687. /* Monitor devices which are in one of several NOT READY states to be
  1688. * brought online later. This must be done without holding h->devlock,
  1689. * so don't touch h->dev[]
  1690. */
  1691. for (i = 0; i < nsds; i++) {
  1692. if (!sd[i]) /* if already added above. */
  1693. continue;
  1694. if (sd[i]->volume_offline)
  1695. hpsa_monitor_offline_device(h, sd[i]->scsi3addr);
  1696. }
  1697. /* Don't notify scsi mid layer of any changes the first time through
  1698. * (or if there are no changes) scsi_scan_host will do it later the
  1699. * first time through.
  1700. */
  1701. if (!changes)
  1702. goto free_and_out;
  1703. /* Notify scsi mid layer of any removed devices */
  1704. for (i = 0; i < nremoved; i++) {
  1705. if (removed[i] == NULL)
  1706. continue;
  1707. if (removed[i]->expose_device)
  1708. hpsa_remove_device(h, removed[i]);
  1709. kfree(removed[i]);
  1710. removed[i] = NULL;
  1711. }
  1712. /* Notify scsi mid layer of any added devices */
  1713. for (i = 0; i < nadded; i++) {
  1714. int rc = 0;
  1715. if (added[i] == NULL)
  1716. continue;
  1717. if (!(added[i]->expose_device))
  1718. continue;
  1719. rc = hpsa_add_device(h, added[i]);
  1720. if (!rc)
  1721. continue;
  1722. dev_warn(&h->pdev->dev,
  1723. "addition failed %d, device not added.", rc);
  1724. /* now we have to remove it from h->dev,
  1725. * since it didn't get added to scsi mid layer
  1726. */
  1727. fixup_botched_add(h, added[i]);
  1728. h->drv_req_rescan = 1;
  1729. }
  1730. free_and_out:
  1731. kfree(added);
  1732. kfree(removed);
  1733. }
  1734. /*
  1735. * Lookup bus/target/lun and return corresponding struct hpsa_scsi_dev_t *
  1736. * Assume's h->devlock is held.
  1737. */
  1738. static struct hpsa_scsi_dev_t *lookup_hpsa_scsi_dev(struct ctlr_info *h,
  1739. int bus, int target, int lun)
  1740. {
  1741. int i;
  1742. struct hpsa_scsi_dev_t *sd;
  1743. for (i = 0; i < h->ndevices; i++) {
  1744. sd = h->dev[i];
  1745. if (sd->bus == bus && sd->target == target && sd->lun == lun)
  1746. return sd;
  1747. }
  1748. return NULL;
  1749. }
  1750. static int hpsa_slave_alloc(struct scsi_device *sdev)
  1751. {
  1752. struct hpsa_scsi_dev_t *sd;
  1753. unsigned long flags;
  1754. struct ctlr_info *h;
  1755. h = sdev_to_hba(sdev);
  1756. spin_lock_irqsave(&h->devlock, flags);
  1757. if (sdev_channel(sdev) == HPSA_PHYSICAL_DEVICE_BUS) {
  1758. struct scsi_target *starget;
  1759. struct sas_rphy *rphy;
  1760. starget = scsi_target(sdev);
  1761. rphy = target_to_rphy(starget);
  1762. sd = hpsa_find_device_by_sas_rphy(h, rphy);
  1763. if (sd) {
  1764. sd->target = sdev_id(sdev);
  1765. sd->lun = sdev->lun;
  1766. }
  1767. } else
  1768. sd = lookup_hpsa_scsi_dev(h, sdev_channel(sdev),
  1769. sdev_id(sdev), sdev->lun);
  1770. if (sd && sd->expose_device) {
  1771. atomic_set(&sd->ioaccel_cmds_out, 0);
  1772. sdev->hostdata = sd;
  1773. } else
  1774. sdev->hostdata = NULL;
  1775. spin_unlock_irqrestore(&h->devlock, flags);
  1776. return 0;
  1777. }
  1778. /* configure scsi device based on internal per-device structure */
  1779. static int hpsa_slave_configure(struct scsi_device *sdev)
  1780. {
  1781. struct hpsa_scsi_dev_t *sd;
  1782. int queue_depth;
  1783. sd = sdev->hostdata;
  1784. sdev->no_uld_attach = !sd || !sd->expose_device;
  1785. if (sd)
  1786. queue_depth = sd->queue_depth != 0 ?
  1787. sd->queue_depth : sdev->host->can_queue;
  1788. else
  1789. queue_depth = sdev->host->can_queue;
  1790. scsi_change_queue_depth(sdev, queue_depth);
  1791. return 0;
  1792. }
  1793. static void hpsa_slave_destroy(struct scsi_device *sdev)
  1794. {
  1795. /* nothing to do. */
  1796. }
  1797. static void hpsa_free_ioaccel2_sg_chain_blocks(struct ctlr_info *h)
  1798. {
  1799. int i;
  1800. if (!h->ioaccel2_cmd_sg_list)
  1801. return;
  1802. for (i = 0; i < h->nr_cmds; i++) {
  1803. kfree(h->ioaccel2_cmd_sg_list[i]);
  1804. h->ioaccel2_cmd_sg_list[i] = NULL;
  1805. }
  1806. kfree(h->ioaccel2_cmd_sg_list);
  1807. h->ioaccel2_cmd_sg_list = NULL;
  1808. }
  1809. static int hpsa_allocate_ioaccel2_sg_chain_blocks(struct ctlr_info *h)
  1810. {
  1811. int i;
  1812. if (h->chainsize <= 0)
  1813. return 0;
  1814. h->ioaccel2_cmd_sg_list =
  1815. kzalloc(sizeof(*h->ioaccel2_cmd_sg_list) * h->nr_cmds,
  1816. GFP_KERNEL);
  1817. if (!h->ioaccel2_cmd_sg_list)
  1818. return -ENOMEM;
  1819. for (i = 0; i < h->nr_cmds; i++) {
  1820. h->ioaccel2_cmd_sg_list[i] =
  1821. kmalloc(sizeof(*h->ioaccel2_cmd_sg_list[i]) *
  1822. h->maxsgentries, GFP_KERNEL);
  1823. if (!h->ioaccel2_cmd_sg_list[i])
  1824. goto clean;
  1825. }
  1826. return 0;
  1827. clean:
  1828. hpsa_free_ioaccel2_sg_chain_blocks(h);
  1829. return -ENOMEM;
  1830. }
  1831. static void hpsa_free_sg_chain_blocks(struct ctlr_info *h)
  1832. {
  1833. int i;
  1834. if (!h->cmd_sg_list)
  1835. return;
  1836. for (i = 0; i < h->nr_cmds; i++) {
  1837. kfree(h->cmd_sg_list[i]);
  1838. h->cmd_sg_list[i] = NULL;
  1839. }
  1840. kfree(h->cmd_sg_list);
  1841. h->cmd_sg_list = NULL;
  1842. }
  1843. static int hpsa_alloc_sg_chain_blocks(struct ctlr_info *h)
  1844. {
  1845. int i;
  1846. if (h->chainsize <= 0)
  1847. return 0;
  1848. h->cmd_sg_list = kzalloc(sizeof(*h->cmd_sg_list) * h->nr_cmds,
  1849. GFP_KERNEL);
  1850. if (!h->cmd_sg_list) {
  1851. dev_err(&h->pdev->dev, "Failed to allocate SG list\n");
  1852. return -ENOMEM;
  1853. }
  1854. for (i = 0; i < h->nr_cmds; i++) {
  1855. h->cmd_sg_list[i] = kmalloc(sizeof(*h->cmd_sg_list[i]) *
  1856. h->chainsize, GFP_KERNEL);
  1857. if (!h->cmd_sg_list[i]) {
  1858. dev_err(&h->pdev->dev, "Failed to allocate cmd SG\n");
  1859. goto clean;
  1860. }
  1861. }
  1862. return 0;
  1863. clean:
  1864. hpsa_free_sg_chain_blocks(h);
  1865. return -ENOMEM;
  1866. }
  1867. static int hpsa_map_ioaccel2_sg_chain_block(struct ctlr_info *h,
  1868. struct io_accel2_cmd *cp, struct CommandList *c)
  1869. {
  1870. struct ioaccel2_sg_element *chain_block;
  1871. u64 temp64;
  1872. u32 chain_size;
  1873. chain_block = h->ioaccel2_cmd_sg_list[c->cmdindex];
  1874. chain_size = le32_to_cpu(cp->sg[0].length);
  1875. temp64 = pci_map_single(h->pdev, chain_block, chain_size,
  1876. PCI_DMA_TODEVICE);
  1877. if (dma_mapping_error(&h->pdev->dev, temp64)) {
  1878. /* prevent subsequent unmapping */
  1879. cp->sg->address = 0;
  1880. return -1;
  1881. }
  1882. cp->sg->address = cpu_to_le64(temp64);
  1883. return 0;
  1884. }
  1885. static void hpsa_unmap_ioaccel2_sg_chain_block(struct ctlr_info *h,
  1886. struct io_accel2_cmd *cp)
  1887. {
  1888. struct ioaccel2_sg_element *chain_sg;
  1889. u64 temp64;
  1890. u32 chain_size;
  1891. chain_sg = cp->sg;
  1892. temp64 = le64_to_cpu(chain_sg->address);
  1893. chain_size = le32_to_cpu(cp->sg[0].length);
  1894. pci_unmap_single(h->pdev, temp64, chain_size, PCI_DMA_TODEVICE);
  1895. }
  1896. static int hpsa_map_sg_chain_block(struct ctlr_info *h,
  1897. struct CommandList *c)
  1898. {
  1899. struct SGDescriptor *chain_sg, *chain_block;
  1900. u64 temp64;
  1901. u32 chain_len;
  1902. chain_sg = &c->SG[h->max_cmd_sg_entries - 1];
  1903. chain_block = h->cmd_sg_list[c->cmdindex];
  1904. chain_sg->Ext = cpu_to_le32(HPSA_SG_CHAIN);
  1905. chain_len = sizeof(*chain_sg) *
  1906. (le16_to_cpu(c->Header.SGTotal) - h->max_cmd_sg_entries);
  1907. chain_sg->Len = cpu_to_le32(chain_len);
  1908. temp64 = pci_map_single(h->pdev, chain_block, chain_len,
  1909. PCI_DMA_TODEVICE);
  1910. if (dma_mapping_error(&h->pdev->dev, temp64)) {
  1911. /* prevent subsequent unmapping */
  1912. chain_sg->Addr = cpu_to_le64(0);
  1913. return -1;
  1914. }
  1915. chain_sg->Addr = cpu_to_le64(temp64);
  1916. return 0;
  1917. }
  1918. static void hpsa_unmap_sg_chain_block(struct ctlr_info *h,
  1919. struct CommandList *c)
  1920. {
  1921. struct SGDescriptor *chain_sg;
  1922. if (le16_to_cpu(c->Header.SGTotal) <= h->max_cmd_sg_entries)
  1923. return;
  1924. chain_sg = &c->SG[h->max_cmd_sg_entries - 1];
  1925. pci_unmap_single(h->pdev, le64_to_cpu(chain_sg->Addr),
  1926. le32_to_cpu(chain_sg->Len), PCI_DMA_TODEVICE);
  1927. }
  1928. /* Decode the various types of errors on ioaccel2 path.
  1929. * Return 1 for any error that should generate a RAID path retry.
  1930. * Return 0 for errors that don't require a RAID path retry.
  1931. */
  1932. static int handle_ioaccel_mode2_error(struct ctlr_info *h,
  1933. struct CommandList *c,
  1934. struct scsi_cmnd *cmd,
  1935. struct io_accel2_cmd *c2)
  1936. {
  1937. int data_len;
  1938. int retry = 0;
  1939. u32 ioaccel2_resid = 0;
  1940. switch (c2->error_data.serv_response) {
  1941. case IOACCEL2_SERV_RESPONSE_COMPLETE:
  1942. switch (c2->error_data.status) {
  1943. case IOACCEL2_STATUS_SR_TASK_COMP_GOOD:
  1944. break;
  1945. case IOACCEL2_STATUS_SR_TASK_COMP_CHK_COND:
  1946. cmd->result |= SAM_STAT_CHECK_CONDITION;
  1947. if (c2->error_data.data_present !=
  1948. IOACCEL2_SENSE_DATA_PRESENT) {
  1949. memset(cmd->sense_buffer, 0,
  1950. SCSI_SENSE_BUFFERSIZE);
  1951. break;
  1952. }
  1953. /* copy the sense data */
  1954. data_len = c2->error_data.sense_data_len;
  1955. if (data_len > SCSI_SENSE_BUFFERSIZE)
  1956. data_len = SCSI_SENSE_BUFFERSIZE;
  1957. if (data_len > sizeof(c2->error_data.sense_data_buff))
  1958. data_len =
  1959. sizeof(c2->error_data.sense_data_buff);
  1960. memcpy(cmd->sense_buffer,
  1961. c2->error_data.sense_data_buff, data_len);
  1962. retry = 1;
  1963. break;
  1964. case IOACCEL2_STATUS_SR_TASK_COMP_BUSY:
  1965. retry = 1;
  1966. break;
  1967. case IOACCEL2_STATUS_SR_TASK_COMP_RES_CON:
  1968. retry = 1;
  1969. break;
  1970. case IOACCEL2_STATUS_SR_TASK_COMP_SET_FULL:
  1971. retry = 1;
  1972. break;
  1973. case IOACCEL2_STATUS_SR_TASK_COMP_ABORTED:
  1974. retry = 1;
  1975. break;
  1976. default:
  1977. retry = 1;
  1978. break;
  1979. }
  1980. break;
  1981. case IOACCEL2_SERV_RESPONSE_FAILURE:
  1982. switch (c2->error_data.status) {
  1983. case IOACCEL2_STATUS_SR_IO_ERROR:
  1984. case IOACCEL2_STATUS_SR_IO_ABORTED:
  1985. case IOACCEL2_STATUS_SR_OVERRUN:
  1986. retry = 1;
  1987. break;
  1988. case IOACCEL2_STATUS_SR_UNDERRUN:
  1989. cmd->result = (DID_OK << 16); /* host byte */
  1990. cmd->result |= (COMMAND_COMPLETE << 8); /* msg byte */
  1991. ioaccel2_resid = get_unaligned_le32(
  1992. &c2->error_data.resid_cnt[0]);
  1993. scsi_set_resid(cmd, ioaccel2_resid);
  1994. break;
  1995. case IOACCEL2_STATUS_SR_NO_PATH_TO_DEVICE:
  1996. case IOACCEL2_STATUS_SR_INVALID_DEVICE:
  1997. case IOACCEL2_STATUS_SR_IOACCEL_DISABLED:
  1998. /* We will get an event from ctlr to trigger rescan */
  1999. retry = 1;
  2000. break;
  2001. default:
  2002. retry = 1;
  2003. }
  2004. break;
  2005. case IOACCEL2_SERV_RESPONSE_TMF_COMPLETE:
  2006. break;
  2007. case IOACCEL2_SERV_RESPONSE_TMF_SUCCESS:
  2008. break;
  2009. case IOACCEL2_SERV_RESPONSE_TMF_REJECTED:
  2010. retry = 1;
  2011. break;
  2012. case IOACCEL2_SERV_RESPONSE_TMF_WRONG_LUN:
  2013. break;
  2014. default:
  2015. retry = 1;
  2016. break;
  2017. }
  2018. return retry; /* retry on raid path? */
  2019. }
  2020. static void hpsa_cmd_resolve_events(struct ctlr_info *h,
  2021. struct CommandList *c)
  2022. {
  2023. bool do_wake = false;
  2024. /*
  2025. * Prevent the following race in the abort handler:
  2026. *
  2027. * 1. LLD is requested to abort a SCSI command
  2028. * 2. The SCSI command completes
  2029. * 3. The struct CommandList associated with step 2 is made available
  2030. * 4. New I/O request to LLD to another LUN re-uses struct CommandList
  2031. * 5. Abort handler follows scsi_cmnd->host_scribble and
  2032. * finds struct CommandList and tries to aborts it
  2033. * Now we have aborted the wrong command.
  2034. *
  2035. * Reset c->scsi_cmd here so that the abort or reset handler will know
  2036. * this command has completed. Then, check to see if the handler is
  2037. * waiting for this command, and, if so, wake it.
  2038. */
  2039. c->scsi_cmd = SCSI_CMD_IDLE;
  2040. mb(); /* Declare command idle before checking for pending events. */
  2041. if (c->abort_pending) {
  2042. do_wake = true;
  2043. c->abort_pending = false;
  2044. }
  2045. if (c->reset_pending) {
  2046. unsigned long flags;
  2047. struct hpsa_scsi_dev_t *dev;
  2048. /*
  2049. * There appears to be a reset pending; lock the lock and
  2050. * reconfirm. If so, then decrement the count of outstanding
  2051. * commands and wake the reset command if this is the last one.
  2052. */
  2053. spin_lock_irqsave(&h->lock, flags);
  2054. dev = c->reset_pending; /* Re-fetch under the lock. */
  2055. if (dev && atomic_dec_and_test(&dev->reset_cmds_out))
  2056. do_wake = true;
  2057. c->reset_pending = NULL;
  2058. spin_unlock_irqrestore(&h->lock, flags);
  2059. }
  2060. if (do_wake)
  2061. wake_up_all(&h->event_sync_wait_queue);
  2062. }
  2063. static void hpsa_cmd_resolve_and_free(struct ctlr_info *h,
  2064. struct CommandList *c)
  2065. {
  2066. hpsa_cmd_resolve_events(h, c);
  2067. cmd_tagged_free(h, c);
  2068. }
  2069. static void hpsa_cmd_free_and_done(struct ctlr_info *h,
  2070. struct CommandList *c, struct scsi_cmnd *cmd)
  2071. {
  2072. hpsa_cmd_resolve_and_free(h, c);
  2073. cmd->scsi_done(cmd);
  2074. }
  2075. static void hpsa_retry_cmd(struct ctlr_info *h, struct CommandList *c)
  2076. {
  2077. INIT_WORK(&c->work, hpsa_command_resubmit_worker);
  2078. queue_work_on(raw_smp_processor_id(), h->resubmit_wq, &c->work);
  2079. }
  2080. static void hpsa_set_scsi_cmd_aborted(struct scsi_cmnd *cmd)
  2081. {
  2082. cmd->result = DID_ABORT << 16;
  2083. }
  2084. static void hpsa_cmd_abort_and_free(struct ctlr_info *h, struct CommandList *c,
  2085. struct scsi_cmnd *cmd)
  2086. {
  2087. hpsa_set_scsi_cmd_aborted(cmd);
  2088. dev_warn(&h->pdev->dev, "CDB %16phN was aborted with status 0x%x\n",
  2089. c->Request.CDB, c->err_info->ScsiStatus);
  2090. hpsa_cmd_resolve_and_free(h, c);
  2091. }
  2092. static void process_ioaccel2_completion(struct ctlr_info *h,
  2093. struct CommandList *c, struct scsi_cmnd *cmd,
  2094. struct hpsa_scsi_dev_t *dev)
  2095. {
  2096. struct io_accel2_cmd *c2 = &h->ioaccel2_cmd_pool[c->cmdindex];
  2097. /* check for good status */
  2098. if (likely(c2->error_data.serv_response == 0 &&
  2099. c2->error_data.status == 0))
  2100. return hpsa_cmd_free_and_done(h, c, cmd);
  2101. /*
  2102. * Any RAID offload error results in retry which will use
  2103. * the normal I/O path so the controller can handle whatever's
  2104. * wrong.
  2105. */
  2106. if (is_logical_device(dev) &&
  2107. c2->error_data.serv_response ==
  2108. IOACCEL2_SERV_RESPONSE_FAILURE) {
  2109. if (c2->error_data.status ==
  2110. IOACCEL2_STATUS_SR_IOACCEL_DISABLED)
  2111. dev->offload_enabled = 0;
  2112. return hpsa_retry_cmd(h, c);
  2113. }
  2114. if (handle_ioaccel_mode2_error(h, c, cmd, c2))
  2115. return hpsa_retry_cmd(h, c);
  2116. return hpsa_cmd_free_and_done(h, c, cmd);
  2117. }
  2118. /* Returns 0 on success, < 0 otherwise. */
  2119. static int hpsa_evaluate_tmf_status(struct ctlr_info *h,
  2120. struct CommandList *cp)
  2121. {
  2122. u8 tmf_status = cp->err_info->ScsiStatus;
  2123. switch (tmf_status) {
  2124. case CISS_TMF_COMPLETE:
  2125. /*
  2126. * CISS_TMF_COMPLETE never happens, instead,
  2127. * ei->CommandStatus == 0 for this case.
  2128. */
  2129. case CISS_TMF_SUCCESS:
  2130. return 0;
  2131. case CISS_TMF_INVALID_FRAME:
  2132. case CISS_TMF_NOT_SUPPORTED:
  2133. case CISS_TMF_FAILED:
  2134. case CISS_TMF_WRONG_LUN:
  2135. case CISS_TMF_OVERLAPPED_TAG:
  2136. break;
  2137. default:
  2138. dev_warn(&h->pdev->dev, "Unknown TMF status: 0x%02x\n",
  2139. tmf_status);
  2140. break;
  2141. }
  2142. return -tmf_status;
  2143. }
  2144. static void complete_scsi_command(struct CommandList *cp)
  2145. {
  2146. struct scsi_cmnd *cmd;
  2147. struct ctlr_info *h;
  2148. struct ErrorInfo *ei;
  2149. struct hpsa_scsi_dev_t *dev;
  2150. struct io_accel2_cmd *c2;
  2151. u8 sense_key;
  2152. u8 asc; /* additional sense code */
  2153. u8 ascq; /* additional sense code qualifier */
  2154. unsigned long sense_data_size;
  2155. ei = cp->err_info;
  2156. cmd = cp->scsi_cmd;
  2157. h = cp->h;
  2158. dev = cmd->device->hostdata;
  2159. c2 = &h->ioaccel2_cmd_pool[cp->cmdindex];
  2160. scsi_dma_unmap(cmd); /* undo the DMA mappings */
  2161. if ((cp->cmd_type == CMD_SCSI) &&
  2162. (le16_to_cpu(cp->Header.SGTotal) > h->max_cmd_sg_entries))
  2163. hpsa_unmap_sg_chain_block(h, cp);
  2164. if ((cp->cmd_type == CMD_IOACCEL2) &&
  2165. (c2->sg[0].chain_indicator == IOACCEL2_CHAIN))
  2166. hpsa_unmap_ioaccel2_sg_chain_block(h, c2);
  2167. cmd->result = (DID_OK << 16); /* host byte */
  2168. cmd->result |= (COMMAND_COMPLETE << 8); /* msg byte */
  2169. if (cp->cmd_type == CMD_IOACCEL2 || cp->cmd_type == CMD_IOACCEL1)
  2170. atomic_dec(&cp->phys_disk->ioaccel_cmds_out);
  2171. /*
  2172. * We check for lockup status here as it may be set for
  2173. * CMD_SCSI, CMD_IOACCEL1 and CMD_IOACCEL2 commands by
  2174. * fail_all_oustanding_cmds()
  2175. */
  2176. if (unlikely(ei->CommandStatus == CMD_CTLR_LOCKUP)) {
  2177. /* DID_NO_CONNECT will prevent a retry */
  2178. cmd->result = DID_NO_CONNECT << 16;
  2179. return hpsa_cmd_free_and_done(h, cp, cmd);
  2180. }
  2181. if ((unlikely(hpsa_is_pending_event(cp)))) {
  2182. if (cp->reset_pending)
  2183. return hpsa_cmd_resolve_and_free(h, cp);
  2184. if (cp->abort_pending)
  2185. return hpsa_cmd_abort_and_free(h, cp, cmd);
  2186. }
  2187. if (cp->cmd_type == CMD_IOACCEL2)
  2188. return process_ioaccel2_completion(h, cp, cmd, dev);
  2189. scsi_set_resid(cmd, ei->ResidualCnt);
  2190. if (ei->CommandStatus == 0)
  2191. return hpsa_cmd_free_and_done(h, cp, cmd);
  2192. /* For I/O accelerator commands, copy over some fields to the normal
  2193. * CISS header used below for error handling.
  2194. */
  2195. if (cp->cmd_type == CMD_IOACCEL1) {
  2196. struct io_accel1_cmd *c = &h->ioaccel_cmd_pool[cp->cmdindex];
  2197. cp->Header.SGList = scsi_sg_count(cmd);
  2198. cp->Header.SGTotal = cpu_to_le16(cp->Header.SGList);
  2199. cp->Request.CDBLen = le16_to_cpu(c->io_flags) &
  2200. IOACCEL1_IOFLAGS_CDBLEN_MASK;
  2201. cp->Header.tag = c->tag;
  2202. memcpy(cp->Header.LUN.LunAddrBytes, c->CISS_LUN, 8);
  2203. memcpy(cp->Request.CDB, c->CDB, cp->Request.CDBLen);
  2204. /* Any RAID offload error results in retry which will use
  2205. * the normal I/O path so the controller can handle whatever's
  2206. * wrong.
  2207. */
  2208. if (is_logical_device(dev)) {
  2209. if (ei->CommandStatus == CMD_IOACCEL_DISABLED)
  2210. dev->offload_enabled = 0;
  2211. return hpsa_retry_cmd(h, cp);
  2212. }
  2213. }
  2214. /* an error has occurred */
  2215. switch (ei->CommandStatus) {
  2216. case CMD_TARGET_STATUS:
  2217. cmd->result |= ei->ScsiStatus;
  2218. /* copy the sense data */
  2219. if (SCSI_SENSE_BUFFERSIZE < sizeof(ei->SenseInfo))
  2220. sense_data_size = SCSI_SENSE_BUFFERSIZE;
  2221. else
  2222. sense_data_size = sizeof(ei->SenseInfo);
  2223. if (ei->SenseLen < sense_data_size)
  2224. sense_data_size = ei->SenseLen;
  2225. memcpy(cmd->sense_buffer, ei->SenseInfo, sense_data_size);
  2226. if (ei->ScsiStatus)
  2227. decode_sense_data(ei->SenseInfo, sense_data_size,
  2228. &sense_key, &asc, &ascq);
  2229. if (ei->ScsiStatus == SAM_STAT_CHECK_CONDITION) {
  2230. if (sense_key == ABORTED_COMMAND) {
  2231. cmd->result |= DID_SOFT_ERROR << 16;
  2232. break;
  2233. }
  2234. break;
  2235. }
  2236. /* Problem was not a check condition
  2237. * Pass it up to the upper layers...
  2238. */
  2239. if (ei->ScsiStatus) {
  2240. dev_warn(&h->pdev->dev, "cp %p has status 0x%x "
  2241. "Sense: 0x%x, ASC: 0x%x, ASCQ: 0x%x, "
  2242. "Returning result: 0x%x\n",
  2243. cp, ei->ScsiStatus,
  2244. sense_key, asc, ascq,
  2245. cmd->result);
  2246. } else { /* scsi status is zero??? How??? */
  2247. dev_warn(&h->pdev->dev, "cp %p SCSI status was 0. "
  2248. "Returning no connection.\n", cp),
  2249. /* Ordinarily, this case should never happen,
  2250. * but there is a bug in some released firmware
  2251. * revisions that allows it to happen if, for
  2252. * example, a 4100 backplane loses power and
  2253. * the tape drive is in it. We assume that
  2254. * it's a fatal error of some kind because we
  2255. * can't show that it wasn't. We will make it
  2256. * look like selection timeout since that is
  2257. * the most common reason for this to occur,
  2258. * and it's severe enough.
  2259. */
  2260. cmd->result = DID_NO_CONNECT << 16;
  2261. }
  2262. break;
  2263. case CMD_DATA_UNDERRUN: /* let mid layer handle it. */
  2264. break;
  2265. case CMD_DATA_OVERRUN:
  2266. dev_warn(&h->pdev->dev,
  2267. "CDB %16phN data overrun\n", cp->Request.CDB);
  2268. break;
  2269. case CMD_INVALID: {
  2270. /* print_bytes(cp, sizeof(*cp), 1, 0);
  2271. print_cmd(cp); */
  2272. /* We get CMD_INVALID if you address a non-existent device
  2273. * instead of a selection timeout (no response). You will
  2274. * see this if you yank out a drive, then try to access it.
  2275. * This is kind of a shame because it means that any other
  2276. * CMD_INVALID (e.g. driver bug) will get interpreted as a
  2277. * missing target. */
  2278. cmd->result = DID_NO_CONNECT << 16;
  2279. }
  2280. break;
  2281. case CMD_PROTOCOL_ERR:
  2282. cmd->result = DID_ERROR << 16;
  2283. dev_warn(&h->pdev->dev, "CDB %16phN : protocol error\n",
  2284. cp->Request.CDB);
  2285. break;
  2286. case CMD_HARDWARE_ERR:
  2287. cmd->result = DID_ERROR << 16;
  2288. dev_warn(&h->pdev->dev, "CDB %16phN : hardware error\n",
  2289. cp->Request.CDB);
  2290. break;
  2291. case CMD_CONNECTION_LOST:
  2292. cmd->result = DID_ERROR << 16;
  2293. dev_warn(&h->pdev->dev, "CDB %16phN : connection lost\n",
  2294. cp->Request.CDB);
  2295. break;
  2296. case CMD_ABORTED:
  2297. /* Return now to avoid calling scsi_done(). */
  2298. return hpsa_cmd_abort_and_free(h, cp, cmd);
  2299. case CMD_ABORT_FAILED:
  2300. cmd->result = DID_ERROR << 16;
  2301. dev_warn(&h->pdev->dev, "CDB %16phN : abort failed\n",
  2302. cp->Request.CDB);
  2303. break;
  2304. case CMD_UNSOLICITED_ABORT:
  2305. cmd->result = DID_SOFT_ERROR << 16; /* retry the command */
  2306. dev_warn(&h->pdev->dev, "CDB %16phN : unsolicited abort\n",
  2307. cp->Request.CDB);
  2308. break;
  2309. case CMD_TIMEOUT:
  2310. cmd->result = DID_TIME_OUT << 16;
  2311. dev_warn(&h->pdev->dev, "CDB %16phN timed out\n",
  2312. cp->Request.CDB);
  2313. break;
  2314. case CMD_UNABORTABLE:
  2315. cmd->result = DID_ERROR << 16;
  2316. dev_warn(&h->pdev->dev, "Command unabortable\n");
  2317. break;
  2318. case CMD_TMF_STATUS:
  2319. if (hpsa_evaluate_tmf_status(h, cp)) /* TMF failed? */
  2320. cmd->result = DID_ERROR << 16;
  2321. break;
  2322. case CMD_IOACCEL_DISABLED:
  2323. /* This only handles the direct pass-through case since RAID
  2324. * offload is handled above. Just attempt a retry.
  2325. */
  2326. cmd->result = DID_SOFT_ERROR << 16;
  2327. dev_warn(&h->pdev->dev,
  2328. "cp %p had HP SSD Smart Path error\n", cp);
  2329. break;
  2330. default:
  2331. cmd->result = DID_ERROR << 16;
  2332. dev_warn(&h->pdev->dev, "cp %p returned unknown status %x\n",
  2333. cp, ei->CommandStatus);
  2334. }
  2335. return hpsa_cmd_free_and_done(h, cp, cmd);
  2336. }
  2337. static void hpsa_pci_unmap(struct pci_dev *pdev,
  2338. struct CommandList *c, int sg_used, int data_direction)
  2339. {
  2340. int i;
  2341. for (i = 0; i < sg_used; i++)
  2342. pci_unmap_single(pdev, (dma_addr_t) le64_to_cpu(c->SG[i].Addr),
  2343. le32_to_cpu(c->SG[i].Len),
  2344. data_direction);
  2345. }
  2346. static int hpsa_map_one(struct pci_dev *pdev,
  2347. struct CommandList *cp,
  2348. unsigned char *buf,
  2349. size_t buflen,
  2350. int data_direction)
  2351. {
  2352. u64 addr64;
  2353. if (buflen == 0 || data_direction == PCI_DMA_NONE) {
  2354. cp->Header.SGList = 0;
  2355. cp->Header.SGTotal = cpu_to_le16(0);
  2356. return 0;
  2357. }
  2358. addr64 = pci_map_single(pdev, buf, buflen, data_direction);
  2359. if (dma_mapping_error(&pdev->dev, addr64)) {
  2360. /* Prevent subsequent unmap of something never mapped */
  2361. cp->Header.SGList = 0;
  2362. cp->Header.SGTotal = cpu_to_le16(0);
  2363. return -1;
  2364. }
  2365. cp->SG[0].Addr = cpu_to_le64(addr64);
  2366. cp->SG[0].Len = cpu_to_le32(buflen);
  2367. cp->SG[0].Ext = cpu_to_le32(HPSA_SG_LAST); /* we are not chaining */
  2368. cp->Header.SGList = 1; /* no. SGs contig in this cmd */
  2369. cp->Header.SGTotal = cpu_to_le16(1); /* total sgs in cmd list */
  2370. return 0;
  2371. }
  2372. #define NO_TIMEOUT ((unsigned long) -1)
  2373. #define DEFAULT_TIMEOUT 30000 /* milliseconds */
  2374. static int hpsa_scsi_do_simple_cmd_core(struct ctlr_info *h,
  2375. struct CommandList *c, int reply_queue, unsigned long timeout_msecs)
  2376. {
  2377. DECLARE_COMPLETION_ONSTACK(wait);
  2378. c->waiting = &wait;
  2379. __enqueue_cmd_and_start_io(h, c, reply_queue);
  2380. if (timeout_msecs == NO_TIMEOUT) {
  2381. /* TODO: get rid of this no-timeout thing */
  2382. wait_for_completion_io(&wait);
  2383. return IO_OK;
  2384. }
  2385. if (!wait_for_completion_io_timeout(&wait,
  2386. msecs_to_jiffies(timeout_msecs))) {
  2387. dev_warn(&h->pdev->dev, "Command timed out.\n");
  2388. return -ETIMEDOUT;
  2389. }
  2390. return IO_OK;
  2391. }
  2392. static int hpsa_scsi_do_simple_cmd(struct ctlr_info *h, struct CommandList *c,
  2393. int reply_queue, unsigned long timeout_msecs)
  2394. {
  2395. if (unlikely(lockup_detected(h))) {
  2396. c->err_info->CommandStatus = CMD_CTLR_LOCKUP;
  2397. return IO_OK;
  2398. }
  2399. return hpsa_scsi_do_simple_cmd_core(h, c, reply_queue, timeout_msecs);
  2400. }
  2401. static u32 lockup_detected(struct ctlr_info *h)
  2402. {
  2403. int cpu;
  2404. u32 rc, *lockup_detected;
  2405. cpu = get_cpu();
  2406. lockup_detected = per_cpu_ptr(h->lockup_detected, cpu);
  2407. rc = *lockup_detected;
  2408. put_cpu();
  2409. return rc;
  2410. }
  2411. #define MAX_DRIVER_CMD_RETRIES 25
  2412. static int hpsa_scsi_do_simple_cmd_with_retry(struct ctlr_info *h,
  2413. struct CommandList *c, int data_direction, unsigned long timeout_msecs)
  2414. {
  2415. int backoff_time = 10, retry_count = 0;
  2416. int rc;
  2417. do {
  2418. memset(c->err_info, 0, sizeof(*c->err_info));
  2419. rc = hpsa_scsi_do_simple_cmd(h, c, DEFAULT_REPLY_QUEUE,
  2420. timeout_msecs);
  2421. if (rc)
  2422. break;
  2423. retry_count++;
  2424. if (retry_count > 3) {
  2425. msleep(backoff_time);
  2426. if (backoff_time < 1000)
  2427. backoff_time *= 2;
  2428. }
  2429. } while ((check_for_unit_attention(h, c) ||
  2430. check_for_busy(h, c)) &&
  2431. retry_count <= MAX_DRIVER_CMD_RETRIES);
  2432. hpsa_pci_unmap(h->pdev, c, 1, data_direction);
  2433. if (retry_count > MAX_DRIVER_CMD_RETRIES)
  2434. rc = -EIO;
  2435. return rc;
  2436. }
  2437. static void hpsa_print_cmd(struct ctlr_info *h, char *txt,
  2438. struct CommandList *c)
  2439. {
  2440. const u8 *cdb = c->Request.CDB;
  2441. const u8 *lun = c->Header.LUN.LunAddrBytes;
  2442. dev_warn(&h->pdev->dev, "%s: LUN:%02x%02x%02x%02x%02x%02x%02x%02x"
  2443. " CDB:%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x%02x\n",
  2444. txt, lun[0], lun[1], lun[2], lun[3],
  2445. lun[4], lun[5], lun[6], lun[7],
  2446. cdb[0], cdb[1], cdb[2], cdb[3],
  2447. cdb[4], cdb[5], cdb[6], cdb[7],
  2448. cdb[8], cdb[9], cdb[10], cdb[11],
  2449. cdb[12], cdb[13], cdb[14], cdb[15]);
  2450. }
  2451. static void hpsa_scsi_interpret_error(struct ctlr_info *h,
  2452. struct CommandList *cp)
  2453. {
  2454. const struct ErrorInfo *ei = cp->err_info;
  2455. struct device *d = &cp->h->pdev->dev;
  2456. u8 sense_key, asc, ascq;
  2457. int sense_len;
  2458. switch (ei->CommandStatus) {
  2459. case CMD_TARGET_STATUS:
  2460. if (ei->SenseLen > sizeof(ei->SenseInfo))
  2461. sense_len = sizeof(ei->SenseInfo);
  2462. else
  2463. sense_len = ei->SenseLen;
  2464. decode_sense_data(ei->SenseInfo, sense_len,
  2465. &sense_key, &asc, &ascq);
  2466. hpsa_print_cmd(h, "SCSI status", cp);
  2467. if (ei->ScsiStatus == SAM_STAT_CHECK_CONDITION)
  2468. dev_warn(d, "SCSI Status = 02, Sense key = 0x%02x, ASC = 0x%02x, ASCQ = 0x%02x\n",
  2469. sense_key, asc, ascq);
  2470. else
  2471. dev_warn(d, "SCSI Status = 0x%02x\n", ei->ScsiStatus);
  2472. if (ei->ScsiStatus == 0)
  2473. dev_warn(d, "SCSI status is abnormally zero. "
  2474. "(probably indicates selection timeout "
  2475. "reported incorrectly due to a known "
  2476. "firmware bug, circa July, 2001.)\n");
  2477. break;
  2478. case CMD_DATA_UNDERRUN: /* let mid layer handle it. */
  2479. break;
  2480. case CMD_DATA_OVERRUN:
  2481. hpsa_print_cmd(h, "overrun condition", cp);
  2482. break;
  2483. case CMD_INVALID: {
  2484. /* controller unfortunately reports SCSI passthru's
  2485. * to non-existent targets as invalid commands.
  2486. */
  2487. hpsa_print_cmd(h, "invalid command", cp);
  2488. dev_warn(d, "probably means device no longer present\n");
  2489. }
  2490. break;
  2491. case CMD_PROTOCOL_ERR:
  2492. hpsa_print_cmd(h, "protocol error", cp);
  2493. break;
  2494. case CMD_HARDWARE_ERR:
  2495. hpsa_print_cmd(h, "hardware error", cp);
  2496. break;
  2497. case CMD_CONNECTION_LOST:
  2498. hpsa_print_cmd(h, "connection lost", cp);
  2499. break;
  2500. case CMD_ABORTED:
  2501. hpsa_print_cmd(h, "aborted", cp);
  2502. break;
  2503. case CMD_ABORT_FAILED:
  2504. hpsa_print_cmd(h, "abort failed", cp);
  2505. break;
  2506. case CMD_UNSOLICITED_ABORT:
  2507. hpsa_print_cmd(h, "unsolicited abort", cp);
  2508. break;
  2509. case CMD_TIMEOUT:
  2510. hpsa_print_cmd(h, "timed out", cp);
  2511. break;
  2512. case CMD_UNABORTABLE:
  2513. hpsa_print_cmd(h, "unabortable", cp);
  2514. break;
  2515. case CMD_CTLR_LOCKUP:
  2516. hpsa_print_cmd(h, "controller lockup detected", cp);
  2517. break;
  2518. default:
  2519. hpsa_print_cmd(h, "unknown status", cp);
  2520. dev_warn(d, "Unknown command status %x\n",
  2521. ei->CommandStatus);
  2522. }
  2523. }
  2524. static int hpsa_scsi_do_inquiry(struct ctlr_info *h, unsigned char *scsi3addr,
  2525. u16 page, unsigned char *buf,
  2526. unsigned char bufsize)
  2527. {
  2528. int rc = IO_OK;
  2529. struct CommandList *c;
  2530. struct ErrorInfo *ei;
  2531. c = cmd_alloc(h);
  2532. if (fill_cmd(c, HPSA_INQUIRY, h, buf, bufsize,
  2533. page, scsi3addr, TYPE_CMD)) {
  2534. rc = -1;
  2535. goto out;
  2536. }
  2537. rc = hpsa_scsi_do_simple_cmd_with_retry(h, c,
  2538. PCI_DMA_FROMDEVICE, NO_TIMEOUT);
  2539. if (rc)
  2540. goto out;
  2541. ei = c->err_info;
  2542. if (ei->CommandStatus != 0 && ei->CommandStatus != CMD_DATA_UNDERRUN) {
  2543. hpsa_scsi_interpret_error(h, c);
  2544. rc = -1;
  2545. }
  2546. out:
  2547. cmd_free(h, c);
  2548. return rc;
  2549. }
  2550. static int hpsa_send_reset(struct ctlr_info *h, unsigned char *scsi3addr,
  2551. u8 reset_type, int reply_queue)
  2552. {
  2553. int rc = IO_OK;
  2554. struct CommandList *c;
  2555. struct ErrorInfo *ei;
  2556. c = cmd_alloc(h);
  2557. /* fill_cmd can't fail here, no data buffer to map. */
  2558. (void) fill_cmd(c, reset_type, h, NULL, 0, 0,
  2559. scsi3addr, TYPE_MSG);
  2560. rc = hpsa_scsi_do_simple_cmd(h, c, reply_queue, NO_TIMEOUT);
  2561. if (rc) {
  2562. dev_warn(&h->pdev->dev, "Failed to send reset command\n");
  2563. goto out;
  2564. }
  2565. /* no unmap needed here because no data xfer. */
  2566. ei = c->err_info;
  2567. if (ei->CommandStatus != 0) {
  2568. hpsa_scsi_interpret_error(h, c);
  2569. rc = -1;
  2570. }
  2571. out:
  2572. cmd_free(h, c);
  2573. return rc;
  2574. }
  2575. static bool hpsa_cmd_dev_match(struct ctlr_info *h, struct CommandList *c,
  2576. struct hpsa_scsi_dev_t *dev,
  2577. unsigned char *scsi3addr)
  2578. {
  2579. int i;
  2580. bool match = false;
  2581. struct io_accel2_cmd *c2 = &h->ioaccel2_cmd_pool[c->cmdindex];
  2582. struct hpsa_tmf_struct *ac = (struct hpsa_tmf_struct *) c2;
  2583. if (hpsa_is_cmd_idle(c))
  2584. return false;
  2585. switch (c->cmd_type) {
  2586. case CMD_SCSI:
  2587. case CMD_IOCTL_PEND:
  2588. match = !memcmp(scsi3addr, &c->Header.LUN.LunAddrBytes,
  2589. sizeof(c->Header.LUN.LunAddrBytes));
  2590. break;
  2591. case CMD_IOACCEL1:
  2592. case CMD_IOACCEL2:
  2593. if (c->phys_disk == dev) {
  2594. /* HBA mode match */
  2595. match = true;
  2596. } else {
  2597. /* Possible RAID mode -- check each phys dev. */
  2598. /* FIXME: Do we need to take out a lock here? If
  2599. * so, we could just call hpsa_get_pdisk_of_ioaccel2()
  2600. * instead. */
  2601. for (i = 0; i < dev->nphysical_disks && !match; i++) {
  2602. /* FIXME: an alternate test might be
  2603. *
  2604. * match = dev->phys_disk[i]->ioaccel_handle
  2605. * == c2->scsi_nexus; */
  2606. match = dev->phys_disk[i] == c->phys_disk;
  2607. }
  2608. }
  2609. break;
  2610. case IOACCEL2_TMF:
  2611. for (i = 0; i < dev->nphysical_disks && !match; i++) {
  2612. match = dev->phys_disk[i]->ioaccel_handle ==
  2613. le32_to_cpu(ac->it_nexus);
  2614. }
  2615. break;
  2616. case 0: /* The command is in the middle of being initialized. */
  2617. match = false;
  2618. break;
  2619. default:
  2620. dev_err(&h->pdev->dev, "unexpected cmd_type: %d\n",
  2621. c->cmd_type);
  2622. BUG();
  2623. }
  2624. return match;
  2625. }
  2626. static int hpsa_do_reset(struct ctlr_info *h, struct hpsa_scsi_dev_t *dev,
  2627. unsigned char *scsi3addr, u8 reset_type, int reply_queue)
  2628. {
  2629. int i;
  2630. int rc = 0;
  2631. /* We can really only handle one reset at a time */
  2632. if (mutex_lock_interruptible(&h->reset_mutex) == -EINTR) {
  2633. dev_warn(&h->pdev->dev, "concurrent reset wait interrupted.\n");
  2634. return -EINTR;
  2635. }
  2636. BUG_ON(atomic_read(&dev->reset_cmds_out) != 0);
  2637. for (i = 0; i < h->nr_cmds; i++) {
  2638. struct CommandList *c = h->cmd_pool + i;
  2639. int refcount = atomic_inc_return(&c->refcount);
  2640. if (refcount > 1 && hpsa_cmd_dev_match(h, c, dev, scsi3addr)) {
  2641. unsigned long flags;
  2642. /*
  2643. * Mark the target command as having a reset pending,
  2644. * then lock a lock so that the command cannot complete
  2645. * while we're considering it. If the command is not
  2646. * idle then count it; otherwise revoke the event.
  2647. */
  2648. c->reset_pending = dev;
  2649. spin_lock_irqsave(&h->lock, flags); /* Implied MB */
  2650. if (!hpsa_is_cmd_idle(c))
  2651. atomic_inc(&dev->reset_cmds_out);
  2652. else
  2653. c->reset_pending = NULL;
  2654. spin_unlock_irqrestore(&h->lock, flags);
  2655. }
  2656. cmd_free(h, c);
  2657. }
  2658. rc = hpsa_send_reset(h, scsi3addr, reset_type, reply_queue);
  2659. if (!rc)
  2660. wait_event(h->event_sync_wait_queue,
  2661. atomic_read(&dev->reset_cmds_out) == 0 ||
  2662. lockup_detected(h));
  2663. if (unlikely(lockup_detected(h))) {
  2664. dev_warn(&h->pdev->dev,
  2665. "Controller lockup detected during reset wait\n");
  2666. rc = -ENODEV;
  2667. }
  2668. if (unlikely(rc))
  2669. atomic_set(&dev->reset_cmds_out, 0);
  2670. mutex_unlock(&h->reset_mutex);
  2671. return rc;
  2672. }
  2673. static void hpsa_get_raid_level(struct ctlr_info *h,
  2674. unsigned char *scsi3addr, unsigned char *raid_level)
  2675. {
  2676. int rc;
  2677. unsigned char *buf;
  2678. *raid_level = RAID_UNKNOWN;
  2679. buf = kzalloc(64, GFP_KERNEL);
  2680. if (!buf)
  2681. return;
  2682. rc = hpsa_scsi_do_inquiry(h, scsi3addr, VPD_PAGE | 0xC1, buf, 64);
  2683. if (rc == 0)
  2684. *raid_level = buf[8];
  2685. if (*raid_level > RAID_UNKNOWN)
  2686. *raid_level = RAID_UNKNOWN;
  2687. kfree(buf);
  2688. return;
  2689. }
  2690. #define HPSA_MAP_DEBUG
  2691. #ifdef HPSA_MAP_DEBUG
  2692. static void hpsa_debug_map_buff(struct ctlr_info *h, int rc,
  2693. struct raid_map_data *map_buff)
  2694. {
  2695. struct raid_map_disk_data *dd = &map_buff->data[0];
  2696. int map, row, col;
  2697. u16 map_cnt, row_cnt, disks_per_row;
  2698. if (rc != 0)
  2699. return;
  2700. /* Show details only if debugging has been activated. */
  2701. if (h->raid_offload_debug < 2)
  2702. return;
  2703. dev_info(&h->pdev->dev, "structure_size = %u\n",
  2704. le32_to_cpu(map_buff->structure_size));
  2705. dev_info(&h->pdev->dev, "volume_blk_size = %u\n",
  2706. le32_to_cpu(map_buff->volume_blk_size));
  2707. dev_info(&h->pdev->dev, "volume_blk_cnt = 0x%llx\n",
  2708. le64_to_cpu(map_buff->volume_blk_cnt));
  2709. dev_info(&h->pdev->dev, "physicalBlockShift = %u\n",
  2710. map_buff->phys_blk_shift);
  2711. dev_info(&h->pdev->dev, "parity_rotation_shift = %u\n",
  2712. map_buff->parity_rotation_shift);
  2713. dev_info(&h->pdev->dev, "strip_size = %u\n",
  2714. le16_to_cpu(map_buff->strip_size));
  2715. dev_info(&h->pdev->dev, "disk_starting_blk = 0x%llx\n",
  2716. le64_to_cpu(map_buff->disk_starting_blk));
  2717. dev_info(&h->pdev->dev, "disk_blk_cnt = 0x%llx\n",
  2718. le64_to_cpu(map_buff->disk_blk_cnt));
  2719. dev_info(&h->pdev->dev, "data_disks_per_row = %u\n",
  2720. le16_to_cpu(map_buff->data_disks_per_row));
  2721. dev_info(&h->pdev->dev, "metadata_disks_per_row = %u\n",
  2722. le16_to_cpu(map_buff->metadata_disks_per_row));
  2723. dev_info(&h->pdev->dev, "row_cnt = %u\n",
  2724. le16_to_cpu(map_buff->row_cnt));
  2725. dev_info(&h->pdev->dev, "layout_map_count = %u\n",
  2726. le16_to_cpu(map_buff->layout_map_count));
  2727. dev_info(&h->pdev->dev, "flags = 0x%x\n",
  2728. le16_to_cpu(map_buff->flags));
  2729. dev_info(&h->pdev->dev, "encrypytion = %s\n",
  2730. le16_to_cpu(map_buff->flags) &
  2731. RAID_MAP_FLAG_ENCRYPT_ON ? "ON" : "OFF");
  2732. dev_info(&h->pdev->dev, "dekindex = %u\n",
  2733. le16_to_cpu(map_buff->dekindex));
  2734. map_cnt = le16_to_cpu(map_buff->layout_map_count);
  2735. for (map = 0; map < map_cnt; map++) {
  2736. dev_info(&h->pdev->dev, "Map%u:\n", map);
  2737. row_cnt = le16_to_cpu(map_buff->row_cnt);
  2738. for (row = 0; row < row_cnt; row++) {
  2739. dev_info(&h->pdev->dev, " Row%u:\n", row);
  2740. disks_per_row =
  2741. le16_to_cpu(map_buff->data_disks_per_row);
  2742. for (col = 0; col < disks_per_row; col++, dd++)
  2743. dev_info(&h->pdev->dev,
  2744. " D%02u: h=0x%04x xor=%u,%u\n",
  2745. col, dd->ioaccel_handle,
  2746. dd->xor_mult[0], dd->xor_mult[1]);
  2747. disks_per_row =
  2748. le16_to_cpu(map_buff->metadata_disks_per_row);
  2749. for (col = 0; col < disks_per_row; col++, dd++)
  2750. dev_info(&h->pdev->dev,
  2751. " M%02u: h=0x%04x xor=%u,%u\n",
  2752. col, dd->ioaccel_handle,
  2753. dd->xor_mult[0], dd->xor_mult[1]);
  2754. }
  2755. }
  2756. }
  2757. #else
  2758. static void hpsa_debug_map_buff(__attribute__((unused)) struct ctlr_info *h,
  2759. __attribute__((unused)) int rc,
  2760. __attribute__((unused)) struct raid_map_data *map_buff)
  2761. {
  2762. }
  2763. #endif
  2764. static int hpsa_get_raid_map(struct ctlr_info *h,
  2765. unsigned char *scsi3addr, struct hpsa_scsi_dev_t *this_device)
  2766. {
  2767. int rc = 0;
  2768. struct CommandList *c;
  2769. struct ErrorInfo *ei;
  2770. c = cmd_alloc(h);
  2771. if (fill_cmd(c, HPSA_GET_RAID_MAP, h, &this_device->raid_map,
  2772. sizeof(this_device->raid_map), 0,
  2773. scsi3addr, TYPE_CMD)) {
  2774. dev_warn(&h->pdev->dev, "hpsa_get_raid_map fill_cmd failed\n");
  2775. cmd_free(h, c);
  2776. return -1;
  2777. }
  2778. rc = hpsa_scsi_do_simple_cmd_with_retry(h, c,
  2779. PCI_DMA_FROMDEVICE, NO_TIMEOUT);
  2780. if (rc)
  2781. goto out;
  2782. ei = c->err_info;
  2783. if (ei->CommandStatus != 0 && ei->CommandStatus != CMD_DATA_UNDERRUN) {
  2784. hpsa_scsi_interpret_error(h, c);
  2785. rc = -1;
  2786. goto out;
  2787. }
  2788. cmd_free(h, c);
  2789. /* @todo in the future, dynamically allocate RAID map memory */
  2790. if (le32_to_cpu(this_device->raid_map.structure_size) >
  2791. sizeof(this_device->raid_map)) {
  2792. dev_warn(&h->pdev->dev, "RAID map size is too large!\n");
  2793. rc = -1;
  2794. }
  2795. hpsa_debug_map_buff(h, rc, &this_device->raid_map);
  2796. return rc;
  2797. out:
  2798. cmd_free(h, c);
  2799. return rc;
  2800. }
  2801. static int hpsa_bmic_sense_subsystem_information(struct ctlr_info *h,
  2802. unsigned char scsi3addr[], u16 bmic_device_index,
  2803. struct bmic_sense_subsystem_info *buf, size_t bufsize)
  2804. {
  2805. int rc = IO_OK;
  2806. struct CommandList *c;
  2807. struct ErrorInfo *ei;
  2808. c = cmd_alloc(h);
  2809. rc = fill_cmd(c, BMIC_SENSE_SUBSYSTEM_INFORMATION, h, buf, bufsize,
  2810. 0, RAID_CTLR_LUNID, TYPE_CMD);
  2811. if (rc)
  2812. goto out;
  2813. c->Request.CDB[2] = bmic_device_index & 0xff;
  2814. c->Request.CDB[9] = (bmic_device_index >> 8) & 0xff;
  2815. rc = hpsa_scsi_do_simple_cmd_with_retry(h, c,
  2816. PCI_DMA_FROMDEVICE, NO_TIMEOUT);
  2817. if (rc)
  2818. goto out;
  2819. ei = c->err_info;
  2820. if (ei->CommandStatus != 0 && ei->CommandStatus != CMD_DATA_UNDERRUN) {
  2821. hpsa_scsi_interpret_error(h, c);
  2822. rc = -1;
  2823. }
  2824. out:
  2825. cmd_free(h, c);
  2826. return rc;
  2827. }
  2828. static int hpsa_bmic_id_controller(struct ctlr_info *h,
  2829. struct bmic_identify_controller *buf, size_t bufsize)
  2830. {
  2831. int rc = IO_OK;
  2832. struct CommandList *c;
  2833. struct ErrorInfo *ei;
  2834. c = cmd_alloc(h);
  2835. rc = fill_cmd(c, BMIC_IDENTIFY_CONTROLLER, h, buf, bufsize,
  2836. 0, RAID_CTLR_LUNID, TYPE_CMD);
  2837. if (rc)
  2838. goto out;
  2839. rc = hpsa_scsi_do_simple_cmd_with_retry(h, c,
  2840. PCI_DMA_FROMDEVICE, NO_TIMEOUT);
  2841. if (rc)
  2842. goto out;
  2843. ei = c->err_info;
  2844. if (ei->CommandStatus != 0 && ei->CommandStatus != CMD_DATA_UNDERRUN) {
  2845. hpsa_scsi_interpret_error(h, c);
  2846. rc = -1;
  2847. }
  2848. out:
  2849. cmd_free(h, c);
  2850. return rc;
  2851. }
  2852. static int hpsa_bmic_id_physical_device(struct ctlr_info *h,
  2853. unsigned char scsi3addr[], u16 bmic_device_index,
  2854. struct bmic_identify_physical_device *buf, size_t bufsize)
  2855. {
  2856. int rc = IO_OK;
  2857. struct CommandList *c;
  2858. struct ErrorInfo *ei;
  2859. c = cmd_alloc(h);
  2860. rc = fill_cmd(c, BMIC_IDENTIFY_PHYSICAL_DEVICE, h, buf, bufsize,
  2861. 0, RAID_CTLR_LUNID, TYPE_CMD);
  2862. if (rc)
  2863. goto out;
  2864. c->Request.CDB[2] = bmic_device_index & 0xff;
  2865. c->Request.CDB[9] = (bmic_device_index >> 8) & 0xff;
  2866. hpsa_scsi_do_simple_cmd_with_retry(h, c, PCI_DMA_FROMDEVICE,
  2867. NO_TIMEOUT);
  2868. ei = c->err_info;
  2869. if (ei->CommandStatus != 0 && ei->CommandStatus != CMD_DATA_UNDERRUN) {
  2870. hpsa_scsi_interpret_error(h, c);
  2871. rc = -1;
  2872. }
  2873. out:
  2874. cmd_free(h, c);
  2875. return rc;
  2876. }
  2877. static u64 hpsa_get_sas_address_from_report_physical(struct ctlr_info *h,
  2878. unsigned char *scsi3addr)
  2879. {
  2880. struct ReportExtendedLUNdata *physdev;
  2881. u32 nphysicals;
  2882. u64 sa = 0;
  2883. int i;
  2884. physdev = kzalloc(sizeof(*physdev), GFP_KERNEL);
  2885. if (!physdev)
  2886. return 0;
  2887. if (hpsa_scsi_do_report_phys_luns(h, physdev, sizeof(*physdev))) {
  2888. dev_err(&h->pdev->dev, "report physical LUNs failed.\n");
  2889. kfree(physdev);
  2890. return 0;
  2891. }
  2892. nphysicals = get_unaligned_be32(physdev->LUNListLength) / 24;
  2893. for (i = 0; i < nphysicals; i++)
  2894. if (!memcmp(&physdev->LUN[i].lunid[0], scsi3addr, 8)) {
  2895. sa = get_unaligned_be64(&physdev->LUN[i].wwid[0]);
  2896. break;
  2897. }
  2898. kfree(physdev);
  2899. return sa;
  2900. }
  2901. static void hpsa_get_sas_address(struct ctlr_info *h, unsigned char *scsi3addr,
  2902. struct hpsa_scsi_dev_t *dev)
  2903. {
  2904. int rc;
  2905. u64 sa = 0;
  2906. if (is_hba_lunid(scsi3addr)) {
  2907. struct bmic_sense_subsystem_info *ssi;
  2908. ssi = kzalloc(sizeof(*ssi), GFP_KERNEL);
  2909. if (ssi == NULL) {
  2910. dev_warn(&h->pdev->dev,
  2911. "%s: out of memory\n", __func__);
  2912. return;
  2913. }
  2914. rc = hpsa_bmic_sense_subsystem_information(h,
  2915. scsi3addr, 0, ssi, sizeof(*ssi));
  2916. if (rc == 0) {
  2917. sa = get_unaligned_be64(ssi->primary_world_wide_id);
  2918. h->sas_address = sa;
  2919. }
  2920. kfree(ssi);
  2921. } else
  2922. sa = hpsa_get_sas_address_from_report_physical(h, scsi3addr);
  2923. dev->sas_address = sa;
  2924. }
  2925. /* Get a device id from inquiry page 0x83 */
  2926. static int hpsa_vpd_page_supported(struct ctlr_info *h,
  2927. unsigned char scsi3addr[], u8 page)
  2928. {
  2929. int rc;
  2930. int i;
  2931. int pages;
  2932. unsigned char *buf, bufsize;
  2933. buf = kzalloc(256, GFP_KERNEL);
  2934. if (!buf)
  2935. return 0;
  2936. /* Get the size of the page list first */
  2937. rc = hpsa_scsi_do_inquiry(h, scsi3addr,
  2938. VPD_PAGE | HPSA_VPD_SUPPORTED_PAGES,
  2939. buf, HPSA_VPD_HEADER_SZ);
  2940. if (rc != 0)
  2941. goto exit_unsupported;
  2942. pages = buf[3];
  2943. if ((pages + HPSA_VPD_HEADER_SZ) <= 255)
  2944. bufsize = pages + HPSA_VPD_HEADER_SZ;
  2945. else
  2946. bufsize = 255;
  2947. /* Get the whole VPD page list */
  2948. rc = hpsa_scsi_do_inquiry(h, scsi3addr,
  2949. VPD_PAGE | HPSA_VPD_SUPPORTED_PAGES,
  2950. buf, bufsize);
  2951. if (rc != 0)
  2952. goto exit_unsupported;
  2953. pages = buf[3];
  2954. for (i = 1; i <= pages; i++)
  2955. if (buf[3 + i] == page)
  2956. goto exit_supported;
  2957. exit_unsupported:
  2958. kfree(buf);
  2959. return 0;
  2960. exit_supported:
  2961. kfree(buf);
  2962. return 1;
  2963. }
  2964. static void hpsa_get_ioaccel_status(struct ctlr_info *h,
  2965. unsigned char *scsi3addr, struct hpsa_scsi_dev_t *this_device)
  2966. {
  2967. int rc;
  2968. unsigned char *buf;
  2969. u8 ioaccel_status;
  2970. this_device->offload_config = 0;
  2971. this_device->offload_enabled = 0;
  2972. this_device->offload_to_be_enabled = 0;
  2973. buf = kzalloc(64, GFP_KERNEL);
  2974. if (!buf)
  2975. return;
  2976. if (!hpsa_vpd_page_supported(h, scsi3addr, HPSA_VPD_LV_IOACCEL_STATUS))
  2977. goto out;
  2978. rc = hpsa_scsi_do_inquiry(h, scsi3addr,
  2979. VPD_PAGE | HPSA_VPD_LV_IOACCEL_STATUS, buf, 64);
  2980. if (rc != 0)
  2981. goto out;
  2982. #define IOACCEL_STATUS_BYTE 4
  2983. #define OFFLOAD_CONFIGURED_BIT 0x01
  2984. #define OFFLOAD_ENABLED_BIT 0x02
  2985. ioaccel_status = buf[IOACCEL_STATUS_BYTE];
  2986. this_device->offload_config =
  2987. !!(ioaccel_status & OFFLOAD_CONFIGURED_BIT);
  2988. if (this_device->offload_config) {
  2989. this_device->offload_enabled =
  2990. !!(ioaccel_status & OFFLOAD_ENABLED_BIT);
  2991. if (hpsa_get_raid_map(h, scsi3addr, this_device))
  2992. this_device->offload_enabled = 0;
  2993. }
  2994. this_device->offload_to_be_enabled = this_device->offload_enabled;
  2995. out:
  2996. kfree(buf);
  2997. return;
  2998. }
  2999. /* Get the device id from inquiry page 0x83 */
  3000. static int hpsa_get_device_id(struct ctlr_info *h, unsigned char *scsi3addr,
  3001. unsigned char *device_id, int index, int buflen)
  3002. {
  3003. int rc;
  3004. unsigned char *buf;
  3005. if (buflen > 16)
  3006. buflen = 16;
  3007. buf = kzalloc(64, GFP_KERNEL);
  3008. if (!buf)
  3009. return -ENOMEM;
  3010. rc = hpsa_scsi_do_inquiry(h, scsi3addr, VPD_PAGE | 0x83, buf, 64);
  3011. if (rc == 0)
  3012. memcpy(device_id, &buf[index], buflen);
  3013. kfree(buf);
  3014. return rc != 0;
  3015. }
  3016. static int hpsa_scsi_do_report_luns(struct ctlr_info *h, int logical,
  3017. void *buf, int bufsize,
  3018. int extended_response)
  3019. {
  3020. int rc = IO_OK;
  3021. struct CommandList *c;
  3022. unsigned char scsi3addr[8];
  3023. struct ErrorInfo *ei;
  3024. c = cmd_alloc(h);
  3025. /* address the controller */
  3026. memset(scsi3addr, 0, sizeof(scsi3addr));
  3027. if (fill_cmd(c, logical ? HPSA_REPORT_LOG : HPSA_REPORT_PHYS, h,
  3028. buf, bufsize, 0, scsi3addr, TYPE_CMD)) {
  3029. rc = -1;
  3030. goto out;
  3031. }
  3032. if (extended_response)
  3033. c->Request.CDB[1] = extended_response;
  3034. rc = hpsa_scsi_do_simple_cmd_with_retry(h, c,
  3035. PCI_DMA_FROMDEVICE, NO_TIMEOUT);
  3036. if (rc)
  3037. goto out;
  3038. ei = c->err_info;
  3039. if (ei->CommandStatus != 0 &&
  3040. ei->CommandStatus != CMD_DATA_UNDERRUN) {
  3041. hpsa_scsi_interpret_error(h, c);
  3042. rc = -1;
  3043. } else {
  3044. struct ReportLUNdata *rld = buf;
  3045. if (rld->extended_response_flag != extended_response) {
  3046. dev_err(&h->pdev->dev,
  3047. "report luns requested format %u, got %u\n",
  3048. extended_response,
  3049. rld->extended_response_flag);
  3050. rc = -1;
  3051. }
  3052. }
  3053. out:
  3054. cmd_free(h, c);
  3055. return rc;
  3056. }
  3057. static inline int hpsa_scsi_do_report_phys_luns(struct ctlr_info *h,
  3058. struct ReportExtendedLUNdata *buf, int bufsize)
  3059. {
  3060. return hpsa_scsi_do_report_luns(h, 0, buf, bufsize,
  3061. HPSA_REPORT_PHYS_EXTENDED);
  3062. }
  3063. static inline int hpsa_scsi_do_report_log_luns(struct ctlr_info *h,
  3064. struct ReportLUNdata *buf, int bufsize)
  3065. {
  3066. return hpsa_scsi_do_report_luns(h, 1, buf, bufsize, 0);
  3067. }
  3068. static inline void hpsa_set_bus_target_lun(struct hpsa_scsi_dev_t *device,
  3069. int bus, int target, int lun)
  3070. {
  3071. device->bus = bus;
  3072. device->target = target;
  3073. device->lun = lun;
  3074. }
  3075. /* Use VPD inquiry to get details of volume status */
  3076. static int hpsa_get_volume_status(struct ctlr_info *h,
  3077. unsigned char scsi3addr[])
  3078. {
  3079. int rc;
  3080. int status;
  3081. int size;
  3082. unsigned char *buf;
  3083. buf = kzalloc(64, GFP_KERNEL);
  3084. if (!buf)
  3085. return HPSA_VPD_LV_STATUS_UNSUPPORTED;
  3086. /* Does controller have VPD for logical volume status? */
  3087. if (!hpsa_vpd_page_supported(h, scsi3addr, HPSA_VPD_LV_STATUS))
  3088. goto exit_failed;
  3089. /* Get the size of the VPD return buffer */
  3090. rc = hpsa_scsi_do_inquiry(h, scsi3addr, VPD_PAGE | HPSA_VPD_LV_STATUS,
  3091. buf, HPSA_VPD_HEADER_SZ);
  3092. if (rc != 0)
  3093. goto exit_failed;
  3094. size = buf[3];
  3095. /* Now get the whole VPD buffer */
  3096. rc = hpsa_scsi_do_inquiry(h, scsi3addr, VPD_PAGE | HPSA_VPD_LV_STATUS,
  3097. buf, size + HPSA_VPD_HEADER_SZ);
  3098. if (rc != 0)
  3099. goto exit_failed;
  3100. status = buf[4]; /* status byte */
  3101. kfree(buf);
  3102. return status;
  3103. exit_failed:
  3104. kfree(buf);
  3105. return HPSA_VPD_LV_STATUS_UNSUPPORTED;
  3106. }
  3107. /* Determine offline status of a volume.
  3108. * Return either:
  3109. * 0 (not offline)
  3110. * 0xff (offline for unknown reasons)
  3111. * # (integer code indicating one of several NOT READY states
  3112. * describing why a volume is to be kept offline)
  3113. */
  3114. static unsigned char hpsa_volume_offline(struct ctlr_info *h,
  3115. unsigned char scsi3addr[])
  3116. {
  3117. struct CommandList *c;
  3118. unsigned char *sense;
  3119. u8 sense_key, asc, ascq;
  3120. int sense_len;
  3121. int rc, ldstat = 0;
  3122. u16 cmd_status;
  3123. u8 scsi_status;
  3124. #define ASC_LUN_NOT_READY 0x04
  3125. #define ASCQ_LUN_NOT_READY_FORMAT_IN_PROGRESS 0x04
  3126. #define ASCQ_LUN_NOT_READY_INITIALIZING_CMD_REQ 0x02
  3127. c = cmd_alloc(h);
  3128. (void) fill_cmd(c, TEST_UNIT_READY, h, NULL, 0, 0, scsi3addr, TYPE_CMD);
  3129. rc = hpsa_scsi_do_simple_cmd(h, c, DEFAULT_REPLY_QUEUE, NO_TIMEOUT);
  3130. if (rc) {
  3131. cmd_free(h, c);
  3132. return HPSA_VPD_LV_STATUS_UNSUPPORTED;
  3133. }
  3134. sense = c->err_info->SenseInfo;
  3135. if (c->err_info->SenseLen > sizeof(c->err_info->SenseInfo))
  3136. sense_len = sizeof(c->err_info->SenseInfo);
  3137. else
  3138. sense_len = c->err_info->SenseLen;
  3139. decode_sense_data(sense, sense_len, &sense_key, &asc, &ascq);
  3140. cmd_status = c->err_info->CommandStatus;
  3141. scsi_status = c->err_info->ScsiStatus;
  3142. cmd_free(h, c);
  3143. /* Determine the reason for not ready state */
  3144. ldstat = hpsa_get_volume_status(h, scsi3addr);
  3145. /* Keep volume offline in certain cases: */
  3146. switch (ldstat) {
  3147. case HPSA_LV_FAILED:
  3148. case HPSA_LV_UNDERGOING_ERASE:
  3149. case HPSA_LV_NOT_AVAILABLE:
  3150. case HPSA_LV_UNDERGOING_RPI:
  3151. case HPSA_LV_PENDING_RPI:
  3152. case HPSA_LV_ENCRYPTED_NO_KEY:
  3153. case HPSA_LV_PLAINTEXT_IN_ENCRYPT_ONLY_CONTROLLER:
  3154. case HPSA_LV_UNDERGOING_ENCRYPTION:
  3155. case HPSA_LV_UNDERGOING_ENCRYPTION_REKEYING:
  3156. case HPSA_LV_ENCRYPTED_IN_NON_ENCRYPTED_CONTROLLER:
  3157. return ldstat;
  3158. case HPSA_VPD_LV_STATUS_UNSUPPORTED:
  3159. /* If VPD status page isn't available,
  3160. * use ASC/ASCQ to determine state
  3161. */
  3162. if ((ascq == ASCQ_LUN_NOT_READY_FORMAT_IN_PROGRESS) ||
  3163. (ascq == ASCQ_LUN_NOT_READY_INITIALIZING_CMD_REQ))
  3164. return ldstat;
  3165. break;
  3166. default:
  3167. break;
  3168. }
  3169. return HPSA_LV_OK;
  3170. }
  3171. /*
  3172. * Find out if a logical device supports aborts by simply trying one.
  3173. * Smart Array may claim not to support aborts on logical drives, but
  3174. * if a MSA2000 * is connected, the drives on that will be presented
  3175. * by the Smart Array as logical drives, and aborts may be sent to
  3176. * those devices successfully. So the simplest way to find out is
  3177. * to simply try an abort and see how the device responds.
  3178. */
  3179. static int hpsa_device_supports_aborts(struct ctlr_info *h,
  3180. unsigned char *scsi3addr)
  3181. {
  3182. struct CommandList *c;
  3183. struct ErrorInfo *ei;
  3184. int rc = 0;
  3185. u64 tag = (u64) -1; /* bogus tag */
  3186. /* Assume that physical devices support aborts */
  3187. if (!is_logical_dev_addr_mode(scsi3addr))
  3188. return 1;
  3189. c = cmd_alloc(h);
  3190. (void) fill_cmd(c, HPSA_ABORT_MSG, h, &tag, 0, 0, scsi3addr, TYPE_MSG);
  3191. (void) hpsa_scsi_do_simple_cmd(h, c, DEFAULT_REPLY_QUEUE, NO_TIMEOUT);
  3192. /* no unmap needed here because no data xfer. */
  3193. ei = c->err_info;
  3194. switch (ei->CommandStatus) {
  3195. case CMD_INVALID:
  3196. rc = 0;
  3197. break;
  3198. case CMD_UNABORTABLE:
  3199. case CMD_ABORT_FAILED:
  3200. rc = 1;
  3201. break;
  3202. case CMD_TMF_STATUS:
  3203. rc = hpsa_evaluate_tmf_status(h, c);
  3204. break;
  3205. default:
  3206. rc = 0;
  3207. break;
  3208. }
  3209. cmd_free(h, c);
  3210. return rc;
  3211. }
  3212. static void sanitize_inquiry_string(unsigned char *s, int len)
  3213. {
  3214. bool terminated = false;
  3215. for (; len > 0; (--len, ++s)) {
  3216. if (*s == 0)
  3217. terminated = true;
  3218. if (terminated || *s < 0x20 || *s > 0x7e)
  3219. *s = ' ';
  3220. }
  3221. }
  3222. static int hpsa_update_device_info(struct ctlr_info *h,
  3223. unsigned char scsi3addr[], struct hpsa_scsi_dev_t *this_device,
  3224. unsigned char *is_OBDR_device)
  3225. {
  3226. #define OBDR_SIG_OFFSET 43
  3227. #define OBDR_TAPE_SIG "$DR-10"
  3228. #define OBDR_SIG_LEN (sizeof(OBDR_TAPE_SIG) - 1)
  3229. #define OBDR_TAPE_INQ_SIZE (OBDR_SIG_OFFSET + OBDR_SIG_LEN)
  3230. unsigned char *inq_buff;
  3231. unsigned char *obdr_sig;
  3232. int rc = 0;
  3233. inq_buff = kzalloc(OBDR_TAPE_INQ_SIZE, GFP_KERNEL);
  3234. if (!inq_buff) {
  3235. rc = -ENOMEM;
  3236. goto bail_out;
  3237. }
  3238. /* Do an inquiry to the device to see what it is. */
  3239. if (hpsa_scsi_do_inquiry(h, scsi3addr, 0, inq_buff,
  3240. (unsigned char) OBDR_TAPE_INQ_SIZE) != 0) {
  3241. dev_err(&h->pdev->dev,
  3242. "%s: inquiry failed, device will be skipped.\n",
  3243. __func__);
  3244. rc = HPSA_INQUIRY_FAILED;
  3245. goto bail_out;
  3246. }
  3247. sanitize_inquiry_string(&inq_buff[8], 8);
  3248. sanitize_inquiry_string(&inq_buff[16], 16);
  3249. this_device->devtype = (inq_buff[0] & 0x1f);
  3250. memcpy(this_device->scsi3addr, scsi3addr, 8);
  3251. memcpy(this_device->vendor, &inq_buff[8],
  3252. sizeof(this_device->vendor));
  3253. memcpy(this_device->model, &inq_buff[16],
  3254. sizeof(this_device->model));
  3255. memset(this_device->device_id, 0,
  3256. sizeof(this_device->device_id));
  3257. hpsa_get_device_id(h, scsi3addr, this_device->device_id, 8,
  3258. sizeof(this_device->device_id));
  3259. if (this_device->devtype == TYPE_DISK &&
  3260. is_logical_dev_addr_mode(scsi3addr)) {
  3261. unsigned char volume_offline;
  3262. hpsa_get_raid_level(h, scsi3addr, &this_device->raid_level);
  3263. if (h->fw_support & MISC_FW_RAID_OFFLOAD_BASIC)
  3264. hpsa_get_ioaccel_status(h, scsi3addr, this_device);
  3265. volume_offline = hpsa_volume_offline(h, scsi3addr);
  3266. this_device->volume_offline = volume_offline;
  3267. if (volume_offline == HPSA_LV_FAILED) {
  3268. rc = HPSA_LV_FAILED;
  3269. dev_err(&h->pdev->dev,
  3270. "%s: LV failed, device will be skipped.\n",
  3271. __func__);
  3272. goto bail_out;
  3273. }
  3274. } else {
  3275. this_device->raid_level = RAID_UNKNOWN;
  3276. this_device->offload_config = 0;
  3277. this_device->offload_enabled = 0;
  3278. this_device->offload_to_be_enabled = 0;
  3279. this_device->hba_ioaccel_enabled = 0;
  3280. this_device->volume_offline = 0;
  3281. this_device->queue_depth = h->nr_cmds;
  3282. }
  3283. if (is_OBDR_device) {
  3284. /* See if this is a One-Button-Disaster-Recovery device
  3285. * by looking for "$DR-10" at offset 43 in inquiry data.
  3286. */
  3287. obdr_sig = &inq_buff[OBDR_SIG_OFFSET];
  3288. *is_OBDR_device = (this_device->devtype == TYPE_ROM &&
  3289. strncmp(obdr_sig, OBDR_TAPE_SIG,
  3290. OBDR_SIG_LEN) == 0);
  3291. }
  3292. kfree(inq_buff);
  3293. return 0;
  3294. bail_out:
  3295. kfree(inq_buff);
  3296. return rc;
  3297. }
  3298. static void hpsa_update_device_supports_aborts(struct ctlr_info *h,
  3299. struct hpsa_scsi_dev_t *dev, u8 *scsi3addr)
  3300. {
  3301. unsigned long flags;
  3302. int rc, entry;
  3303. /*
  3304. * See if this device supports aborts. If we already know
  3305. * the device, we already know if it supports aborts, otherwise
  3306. * we have to find out if it supports aborts by trying one.
  3307. */
  3308. spin_lock_irqsave(&h->devlock, flags);
  3309. rc = hpsa_scsi_find_entry(dev, h->dev, h->ndevices, &entry);
  3310. if ((rc == DEVICE_SAME || rc == DEVICE_UPDATED) &&
  3311. entry >= 0 && entry < h->ndevices) {
  3312. dev->supports_aborts = h->dev[entry]->supports_aborts;
  3313. spin_unlock_irqrestore(&h->devlock, flags);
  3314. } else {
  3315. spin_unlock_irqrestore(&h->devlock, flags);
  3316. dev->supports_aborts =
  3317. hpsa_device_supports_aborts(h, scsi3addr);
  3318. if (dev->supports_aborts < 0)
  3319. dev->supports_aborts = 0;
  3320. }
  3321. }
  3322. /*
  3323. * Helper function to assign bus, target, lun mapping of devices.
  3324. * Logical drive target and lun are assigned at this time, but
  3325. * physical device lun and target assignment are deferred (assigned
  3326. * in hpsa_find_target_lun, called by hpsa_scsi_add_entry.)
  3327. */
  3328. static void figure_bus_target_lun(struct ctlr_info *h,
  3329. u8 *lunaddrbytes, struct hpsa_scsi_dev_t *device)
  3330. {
  3331. u32 lunid = get_unaligned_le32(lunaddrbytes);
  3332. if (!is_logical_dev_addr_mode(lunaddrbytes)) {
  3333. /* physical device, target and lun filled in later */
  3334. if (is_hba_lunid(lunaddrbytes))
  3335. hpsa_set_bus_target_lun(device,
  3336. HPSA_HBA_BUS, 0, lunid & 0x3fff);
  3337. else
  3338. /* defer target, lun assignment for physical devices */
  3339. hpsa_set_bus_target_lun(device,
  3340. HPSA_PHYSICAL_DEVICE_BUS, -1, -1);
  3341. return;
  3342. }
  3343. /* It's a logical device */
  3344. if (device->external) {
  3345. hpsa_set_bus_target_lun(device,
  3346. HPSA_EXTERNAL_RAID_VOLUME_BUS, (lunid >> 16) & 0x3fff,
  3347. lunid & 0x00ff);
  3348. return;
  3349. }
  3350. hpsa_set_bus_target_lun(device, HPSA_RAID_VOLUME_BUS,
  3351. 0, lunid & 0x3fff);
  3352. }
  3353. /*
  3354. * Get address of physical disk used for an ioaccel2 mode command:
  3355. * 1. Extract ioaccel2 handle from the command.
  3356. * 2. Find a matching ioaccel2 handle from list of physical disks.
  3357. * 3. Return:
  3358. * 1 and set scsi3addr to address of matching physical
  3359. * 0 if no matching physical disk was found.
  3360. */
  3361. static int hpsa_get_pdisk_of_ioaccel2(struct ctlr_info *h,
  3362. struct CommandList *ioaccel2_cmd_to_abort, unsigned char *scsi3addr)
  3363. {
  3364. struct io_accel2_cmd *c2 =
  3365. &h->ioaccel2_cmd_pool[ioaccel2_cmd_to_abort->cmdindex];
  3366. unsigned long flags;
  3367. int i;
  3368. spin_lock_irqsave(&h->devlock, flags);
  3369. for (i = 0; i < h->ndevices; i++)
  3370. if (h->dev[i]->ioaccel_handle == le32_to_cpu(c2->scsi_nexus)) {
  3371. memcpy(scsi3addr, h->dev[i]->scsi3addr,
  3372. sizeof(h->dev[i]->scsi3addr));
  3373. spin_unlock_irqrestore(&h->devlock, flags);
  3374. return 1;
  3375. }
  3376. spin_unlock_irqrestore(&h->devlock, flags);
  3377. return 0;
  3378. }
  3379. static int figure_external_status(struct ctlr_info *h, int raid_ctlr_position,
  3380. int i, int nphysicals, int nlocal_logicals)
  3381. {
  3382. /* In report logicals, local logicals are listed first,
  3383. * then any externals.
  3384. */
  3385. int logicals_start = nphysicals + (raid_ctlr_position == 0);
  3386. if (i == raid_ctlr_position)
  3387. return 0;
  3388. if (i < logicals_start)
  3389. return 0;
  3390. /* i is in logicals range, but still within local logicals */
  3391. if ((i - nphysicals - (raid_ctlr_position == 0)) < nlocal_logicals)
  3392. return 0;
  3393. return 1; /* it's an external lun */
  3394. }
  3395. /*
  3396. * Do CISS_REPORT_PHYS and CISS_REPORT_LOG. Data is returned in physdev,
  3397. * logdev. The number of luns in physdev and logdev are returned in
  3398. * *nphysicals and *nlogicals, respectively.
  3399. * Returns 0 on success, -1 otherwise.
  3400. */
  3401. static int hpsa_gather_lun_info(struct ctlr_info *h,
  3402. struct ReportExtendedLUNdata *physdev, u32 *nphysicals,
  3403. struct ReportLUNdata *logdev, u32 *nlogicals)
  3404. {
  3405. if (hpsa_scsi_do_report_phys_luns(h, physdev, sizeof(*physdev))) {
  3406. dev_err(&h->pdev->dev, "report physical LUNs failed.\n");
  3407. return -1;
  3408. }
  3409. *nphysicals = be32_to_cpu(*((__be32 *)physdev->LUNListLength)) / 24;
  3410. if (*nphysicals > HPSA_MAX_PHYS_LUN) {
  3411. dev_warn(&h->pdev->dev, "maximum physical LUNs (%d) exceeded. %d LUNs ignored.\n",
  3412. HPSA_MAX_PHYS_LUN, *nphysicals - HPSA_MAX_PHYS_LUN);
  3413. *nphysicals = HPSA_MAX_PHYS_LUN;
  3414. }
  3415. if (hpsa_scsi_do_report_log_luns(h, logdev, sizeof(*logdev))) {
  3416. dev_err(&h->pdev->dev, "report logical LUNs failed.\n");
  3417. return -1;
  3418. }
  3419. *nlogicals = be32_to_cpu(*((__be32 *) logdev->LUNListLength)) / 8;
  3420. /* Reject Logicals in excess of our max capability. */
  3421. if (*nlogicals > HPSA_MAX_LUN) {
  3422. dev_warn(&h->pdev->dev,
  3423. "maximum logical LUNs (%d) exceeded. "
  3424. "%d LUNs ignored.\n", HPSA_MAX_LUN,
  3425. *nlogicals - HPSA_MAX_LUN);
  3426. *nlogicals = HPSA_MAX_LUN;
  3427. }
  3428. if (*nlogicals + *nphysicals > HPSA_MAX_PHYS_LUN) {
  3429. dev_warn(&h->pdev->dev,
  3430. "maximum logical + physical LUNs (%d) exceeded. "
  3431. "%d LUNs ignored.\n", HPSA_MAX_PHYS_LUN,
  3432. *nphysicals + *nlogicals - HPSA_MAX_PHYS_LUN);
  3433. *nlogicals = HPSA_MAX_PHYS_LUN - *nphysicals;
  3434. }
  3435. return 0;
  3436. }
  3437. static u8 *figure_lunaddrbytes(struct ctlr_info *h, int raid_ctlr_position,
  3438. int i, int nphysicals, int nlogicals,
  3439. struct ReportExtendedLUNdata *physdev_list,
  3440. struct ReportLUNdata *logdev_list)
  3441. {
  3442. /* Helper function, figure out where the LUN ID info is coming from
  3443. * given index i, lists of physical and logical devices, where in
  3444. * the list the raid controller is supposed to appear (first or last)
  3445. */
  3446. int logicals_start = nphysicals + (raid_ctlr_position == 0);
  3447. int last_device = nphysicals + nlogicals + (raid_ctlr_position == 0);
  3448. if (i == raid_ctlr_position)
  3449. return RAID_CTLR_LUNID;
  3450. if (i < logicals_start)
  3451. return &physdev_list->LUN[i -
  3452. (raid_ctlr_position == 0)].lunid[0];
  3453. if (i < last_device)
  3454. return &logdev_list->LUN[i - nphysicals -
  3455. (raid_ctlr_position == 0)][0];
  3456. BUG();
  3457. return NULL;
  3458. }
  3459. /* get physical drive ioaccel handle and queue depth */
  3460. static void hpsa_get_ioaccel_drive_info(struct ctlr_info *h,
  3461. struct hpsa_scsi_dev_t *dev,
  3462. struct ReportExtendedLUNdata *rlep, int rle_index,
  3463. struct bmic_identify_physical_device *id_phys)
  3464. {
  3465. int rc;
  3466. struct ext_report_lun_entry *rle = &rlep->LUN[rle_index];
  3467. dev->ioaccel_handle = rle->ioaccel_handle;
  3468. if ((rle->device_flags & 0x08) && dev->ioaccel_handle)
  3469. dev->hba_ioaccel_enabled = 1;
  3470. memset(id_phys, 0, sizeof(*id_phys));
  3471. rc = hpsa_bmic_id_physical_device(h, &rle->lunid[0],
  3472. GET_BMIC_DRIVE_NUMBER(&rle->lunid[0]), id_phys,
  3473. sizeof(*id_phys));
  3474. if (!rc)
  3475. /* Reserve space for FW operations */
  3476. #define DRIVE_CMDS_RESERVED_FOR_FW 2
  3477. #define DRIVE_QUEUE_DEPTH 7
  3478. dev->queue_depth =
  3479. le16_to_cpu(id_phys->current_queue_depth_limit) -
  3480. DRIVE_CMDS_RESERVED_FOR_FW;
  3481. else
  3482. dev->queue_depth = DRIVE_QUEUE_DEPTH; /* conservative */
  3483. }
  3484. static void hpsa_get_path_info(struct hpsa_scsi_dev_t *this_device,
  3485. struct ReportExtendedLUNdata *rlep, int rle_index,
  3486. struct bmic_identify_physical_device *id_phys)
  3487. {
  3488. struct ext_report_lun_entry *rle = &rlep->LUN[rle_index];
  3489. if ((rle->device_flags & 0x08) && this_device->ioaccel_handle)
  3490. this_device->hba_ioaccel_enabled = 1;
  3491. memcpy(&this_device->active_path_index,
  3492. &id_phys->active_path_number,
  3493. sizeof(this_device->active_path_index));
  3494. memcpy(&this_device->path_map,
  3495. &id_phys->redundant_path_present_map,
  3496. sizeof(this_device->path_map));
  3497. memcpy(&this_device->box,
  3498. &id_phys->alternate_paths_phys_box_on_port,
  3499. sizeof(this_device->box));
  3500. memcpy(&this_device->phys_connector,
  3501. &id_phys->alternate_paths_phys_connector,
  3502. sizeof(this_device->phys_connector));
  3503. memcpy(&this_device->bay,
  3504. &id_phys->phys_bay_in_box,
  3505. sizeof(this_device->bay));
  3506. }
  3507. /* get number of local logical disks. */
  3508. static int hpsa_set_local_logical_count(struct ctlr_info *h,
  3509. struct bmic_identify_controller *id_ctlr,
  3510. u32 *nlocals)
  3511. {
  3512. int rc;
  3513. if (!id_ctlr) {
  3514. dev_warn(&h->pdev->dev, "%s: id_ctlr buffer is NULL.\n",
  3515. __func__);
  3516. return -ENOMEM;
  3517. }
  3518. memset(id_ctlr, 0, sizeof(*id_ctlr));
  3519. rc = hpsa_bmic_id_controller(h, id_ctlr, sizeof(*id_ctlr));
  3520. if (!rc)
  3521. if (id_ctlr->configured_logical_drive_count < 256)
  3522. *nlocals = id_ctlr->configured_logical_drive_count;
  3523. else
  3524. *nlocals = le16_to_cpu(
  3525. id_ctlr->extended_logical_unit_count);
  3526. else
  3527. *nlocals = -1;
  3528. return rc;
  3529. }
  3530. static bool hpsa_is_disk_spare(struct ctlr_info *h, u8 *lunaddrbytes)
  3531. {
  3532. struct bmic_identify_physical_device *id_phys;
  3533. bool is_spare = false;
  3534. int rc;
  3535. id_phys = kzalloc(sizeof(*id_phys), GFP_KERNEL);
  3536. if (!id_phys)
  3537. return false;
  3538. rc = hpsa_bmic_id_physical_device(h,
  3539. lunaddrbytes,
  3540. GET_BMIC_DRIVE_NUMBER(lunaddrbytes),
  3541. id_phys, sizeof(*id_phys));
  3542. if (rc == 0)
  3543. is_spare = (id_phys->more_flags >> 6) & 0x01;
  3544. kfree(id_phys);
  3545. return is_spare;
  3546. }
  3547. #define RPL_DEV_FLAG_NON_DISK 0x1
  3548. #define RPL_DEV_FLAG_UNCONFIG_DISK_REPORTING_SUPPORTED 0x2
  3549. #define RPL_DEV_FLAG_UNCONFIG_DISK 0x4
  3550. #define BMIC_DEVICE_TYPE_ENCLOSURE 6
  3551. static bool hpsa_skip_device(struct ctlr_info *h, u8 *lunaddrbytes,
  3552. struct ext_report_lun_entry *rle)
  3553. {
  3554. u8 device_flags;
  3555. u8 device_type;
  3556. if (!MASKED_DEVICE(lunaddrbytes))
  3557. return false;
  3558. device_flags = rle->device_flags;
  3559. device_type = rle->device_type;
  3560. if (device_flags & RPL_DEV_FLAG_NON_DISK) {
  3561. if (device_type == BMIC_DEVICE_TYPE_ENCLOSURE)
  3562. return false;
  3563. return true;
  3564. }
  3565. if (!(device_flags & RPL_DEV_FLAG_UNCONFIG_DISK_REPORTING_SUPPORTED))
  3566. return false;
  3567. if (device_flags & RPL_DEV_FLAG_UNCONFIG_DISK)
  3568. return false;
  3569. /*
  3570. * Spares may be spun down, we do not want to
  3571. * do an Inquiry to a RAID set spare drive as
  3572. * that would have them spun up, that is a
  3573. * performance hit because I/O to the RAID device
  3574. * stops while the spin up occurs which can take
  3575. * over 50 seconds.
  3576. */
  3577. if (hpsa_is_disk_spare(h, lunaddrbytes))
  3578. return true;
  3579. return false;
  3580. }
  3581. static void hpsa_update_scsi_devices(struct ctlr_info *h)
  3582. {
  3583. /* the idea here is we could get notified
  3584. * that some devices have changed, so we do a report
  3585. * physical luns and report logical luns cmd, and adjust
  3586. * our list of devices accordingly.
  3587. *
  3588. * The scsi3addr's of devices won't change so long as the
  3589. * adapter is not reset. That means we can rescan and
  3590. * tell which devices we already know about, vs. new
  3591. * devices, vs. disappearing devices.
  3592. */
  3593. struct ReportExtendedLUNdata *physdev_list = NULL;
  3594. struct ReportLUNdata *logdev_list = NULL;
  3595. struct bmic_identify_physical_device *id_phys = NULL;
  3596. struct bmic_identify_controller *id_ctlr = NULL;
  3597. u32 nphysicals = 0;
  3598. u32 nlogicals = 0;
  3599. u32 nlocal_logicals = 0;
  3600. u32 ndev_allocated = 0;
  3601. struct hpsa_scsi_dev_t **currentsd, *this_device, *tmpdevice;
  3602. int ncurrent = 0;
  3603. int i, n_ext_target_devs, ndevs_to_allocate;
  3604. int raid_ctlr_position;
  3605. bool physical_device;
  3606. DECLARE_BITMAP(lunzerobits, MAX_EXT_TARGETS);
  3607. currentsd = kzalloc(sizeof(*currentsd) * HPSA_MAX_DEVICES, GFP_KERNEL);
  3608. physdev_list = kzalloc(sizeof(*physdev_list), GFP_KERNEL);
  3609. logdev_list = kzalloc(sizeof(*logdev_list), GFP_KERNEL);
  3610. tmpdevice = kzalloc(sizeof(*tmpdevice), GFP_KERNEL);
  3611. id_phys = kzalloc(sizeof(*id_phys), GFP_KERNEL);
  3612. id_ctlr = kzalloc(sizeof(*id_ctlr), GFP_KERNEL);
  3613. if (!currentsd || !physdev_list || !logdev_list ||
  3614. !tmpdevice || !id_phys || !id_ctlr) {
  3615. dev_err(&h->pdev->dev, "out of memory\n");
  3616. goto out;
  3617. }
  3618. memset(lunzerobits, 0, sizeof(lunzerobits));
  3619. h->drv_req_rescan = 0; /* cancel scheduled rescan - we're doing it. */
  3620. if (hpsa_gather_lun_info(h, physdev_list, &nphysicals,
  3621. logdev_list, &nlogicals)) {
  3622. h->drv_req_rescan = 1;
  3623. goto out;
  3624. }
  3625. /* Set number of local logicals (non PTRAID) */
  3626. if (hpsa_set_local_logical_count(h, id_ctlr, &nlocal_logicals)) {
  3627. dev_warn(&h->pdev->dev,
  3628. "%s: Can't determine number of local logical devices.\n",
  3629. __func__);
  3630. }
  3631. /* We might see up to the maximum number of logical and physical disks
  3632. * plus external target devices, and a device for the local RAID
  3633. * controller.
  3634. */
  3635. ndevs_to_allocate = nphysicals + nlogicals + MAX_EXT_TARGETS + 1;
  3636. /* Allocate the per device structures */
  3637. for (i = 0; i < ndevs_to_allocate; i++) {
  3638. if (i >= HPSA_MAX_DEVICES) {
  3639. dev_warn(&h->pdev->dev, "maximum devices (%d) exceeded."
  3640. " %d devices ignored.\n", HPSA_MAX_DEVICES,
  3641. ndevs_to_allocate - HPSA_MAX_DEVICES);
  3642. break;
  3643. }
  3644. currentsd[i] = kzalloc(sizeof(*currentsd[i]), GFP_KERNEL);
  3645. if (!currentsd[i]) {
  3646. dev_warn(&h->pdev->dev, "out of memory at %s:%d\n",
  3647. __FILE__, __LINE__);
  3648. h->drv_req_rescan = 1;
  3649. goto out;
  3650. }
  3651. ndev_allocated++;
  3652. }
  3653. if (is_scsi_rev_5(h))
  3654. raid_ctlr_position = 0;
  3655. else
  3656. raid_ctlr_position = nphysicals + nlogicals;
  3657. /* adjust our table of devices */
  3658. n_ext_target_devs = 0;
  3659. for (i = 0; i < nphysicals + nlogicals + 1; i++) {
  3660. u8 *lunaddrbytes, is_OBDR = 0;
  3661. int rc = 0;
  3662. int phys_dev_index = i - (raid_ctlr_position == 0);
  3663. bool skip_device = false;
  3664. physical_device = i < nphysicals + (raid_ctlr_position == 0);
  3665. /* Figure out where the LUN ID info is coming from */
  3666. lunaddrbytes = figure_lunaddrbytes(h, raid_ctlr_position,
  3667. i, nphysicals, nlogicals, physdev_list, logdev_list);
  3668. /*
  3669. * Skip over some devices such as a spare.
  3670. */
  3671. if (!tmpdevice->external && physical_device) {
  3672. skip_device = hpsa_skip_device(h, lunaddrbytes,
  3673. &physdev_list->LUN[phys_dev_index]);
  3674. if (skip_device)
  3675. continue;
  3676. }
  3677. /* Get device type, vendor, model, device id */
  3678. rc = hpsa_update_device_info(h, lunaddrbytes, tmpdevice,
  3679. &is_OBDR);
  3680. if (rc == -ENOMEM) {
  3681. dev_warn(&h->pdev->dev,
  3682. "Out of memory, rescan deferred.\n");
  3683. h->drv_req_rescan = 1;
  3684. goto out;
  3685. }
  3686. if (rc) {
  3687. h->drv_req_rescan = 1;
  3688. continue;
  3689. }
  3690. /* Determine if this is a lun from an external target array */
  3691. tmpdevice->external =
  3692. figure_external_status(h, raid_ctlr_position, i,
  3693. nphysicals, nlocal_logicals);
  3694. figure_bus_target_lun(h, lunaddrbytes, tmpdevice);
  3695. hpsa_update_device_supports_aborts(h, tmpdevice, lunaddrbytes);
  3696. this_device = currentsd[ncurrent];
  3697. /* Turn on discovery_polling if there are ext target devices.
  3698. * Event-based change notification is unreliable for those.
  3699. */
  3700. if (!h->discovery_polling) {
  3701. if (tmpdevice->external) {
  3702. h->discovery_polling = 1;
  3703. dev_info(&h->pdev->dev,
  3704. "External target, activate discovery polling.\n");
  3705. }
  3706. }
  3707. *this_device = *tmpdevice;
  3708. this_device->physical_device = physical_device;
  3709. /*
  3710. * Expose all devices except for physical devices that
  3711. * are masked.
  3712. */
  3713. if (MASKED_DEVICE(lunaddrbytes) && this_device->physical_device)
  3714. this_device->expose_device = 0;
  3715. else
  3716. this_device->expose_device = 1;
  3717. /*
  3718. * Get the SAS address for physical devices that are exposed.
  3719. */
  3720. if (this_device->physical_device && this_device->expose_device)
  3721. hpsa_get_sas_address(h, lunaddrbytes, this_device);
  3722. switch (this_device->devtype) {
  3723. case TYPE_ROM:
  3724. /* We don't *really* support actual CD-ROM devices,
  3725. * just "One Button Disaster Recovery" tape drive
  3726. * which temporarily pretends to be a CD-ROM drive.
  3727. * So we check that the device is really an OBDR tape
  3728. * device by checking for "$DR-10" in bytes 43-48 of
  3729. * the inquiry data.
  3730. */
  3731. if (is_OBDR)
  3732. ncurrent++;
  3733. break;
  3734. case TYPE_DISK:
  3735. if (this_device->physical_device) {
  3736. /* The disk is in HBA mode. */
  3737. /* Never use RAID mapper in HBA mode. */
  3738. this_device->offload_enabled = 0;
  3739. hpsa_get_ioaccel_drive_info(h, this_device,
  3740. physdev_list, phys_dev_index, id_phys);
  3741. hpsa_get_path_info(this_device,
  3742. physdev_list, phys_dev_index, id_phys);
  3743. }
  3744. ncurrent++;
  3745. break;
  3746. case TYPE_TAPE:
  3747. case TYPE_MEDIUM_CHANGER:
  3748. case TYPE_ENCLOSURE:
  3749. ncurrent++;
  3750. break;
  3751. case TYPE_RAID:
  3752. /* Only present the Smartarray HBA as a RAID controller.
  3753. * If it's a RAID controller other than the HBA itself
  3754. * (an external RAID controller, MSA500 or similar)
  3755. * don't present it.
  3756. */
  3757. if (!is_hba_lunid(lunaddrbytes))
  3758. break;
  3759. ncurrent++;
  3760. break;
  3761. default:
  3762. break;
  3763. }
  3764. if (ncurrent >= HPSA_MAX_DEVICES)
  3765. break;
  3766. }
  3767. if (h->sas_host == NULL) {
  3768. int rc = 0;
  3769. rc = hpsa_add_sas_host(h);
  3770. if (rc) {
  3771. dev_warn(&h->pdev->dev,
  3772. "Could not add sas host %d\n", rc);
  3773. goto out;
  3774. }
  3775. }
  3776. adjust_hpsa_scsi_table(h, currentsd, ncurrent);
  3777. out:
  3778. kfree(tmpdevice);
  3779. for (i = 0; i < ndev_allocated; i++)
  3780. kfree(currentsd[i]);
  3781. kfree(currentsd);
  3782. kfree(physdev_list);
  3783. kfree(logdev_list);
  3784. kfree(id_ctlr);
  3785. kfree(id_phys);
  3786. }
  3787. static void hpsa_set_sg_descriptor(struct SGDescriptor *desc,
  3788. struct scatterlist *sg)
  3789. {
  3790. u64 addr64 = (u64) sg_dma_address(sg);
  3791. unsigned int len = sg_dma_len(sg);
  3792. desc->Addr = cpu_to_le64(addr64);
  3793. desc->Len = cpu_to_le32(len);
  3794. desc->Ext = 0;
  3795. }
  3796. /*
  3797. * hpsa_scatter_gather takes a struct scsi_cmnd, (cmd), and does the pci
  3798. * dma mapping and fills in the scatter gather entries of the
  3799. * hpsa command, cp.
  3800. */
  3801. static int hpsa_scatter_gather(struct ctlr_info *h,
  3802. struct CommandList *cp,
  3803. struct scsi_cmnd *cmd)
  3804. {
  3805. struct scatterlist *sg;
  3806. int use_sg, i, sg_limit, chained, last_sg;
  3807. struct SGDescriptor *curr_sg;
  3808. BUG_ON(scsi_sg_count(cmd) > h->maxsgentries);
  3809. use_sg = scsi_dma_map(cmd);
  3810. if (use_sg < 0)
  3811. return use_sg;
  3812. if (!use_sg)
  3813. goto sglist_finished;
  3814. /*
  3815. * If the number of entries is greater than the max for a single list,
  3816. * then we have a chained list; we will set up all but one entry in the
  3817. * first list (the last entry is saved for link information);
  3818. * otherwise, we don't have a chained list and we'll set up at each of
  3819. * the entries in the one list.
  3820. */
  3821. curr_sg = cp->SG;
  3822. chained = use_sg > h->max_cmd_sg_entries;
  3823. sg_limit = chained ? h->max_cmd_sg_entries - 1 : use_sg;
  3824. last_sg = scsi_sg_count(cmd) - 1;
  3825. scsi_for_each_sg(cmd, sg, sg_limit, i) {
  3826. hpsa_set_sg_descriptor(curr_sg, sg);
  3827. curr_sg++;
  3828. }
  3829. if (chained) {
  3830. /*
  3831. * Continue with the chained list. Set curr_sg to the chained
  3832. * list. Modify the limit to the total count less the entries
  3833. * we've already set up. Resume the scan at the list entry
  3834. * where the previous loop left off.
  3835. */
  3836. curr_sg = h->cmd_sg_list[cp->cmdindex];
  3837. sg_limit = use_sg - sg_limit;
  3838. for_each_sg(sg, sg, sg_limit, i) {
  3839. hpsa_set_sg_descriptor(curr_sg, sg);
  3840. curr_sg++;
  3841. }
  3842. }
  3843. /* Back the pointer up to the last entry and mark it as "last". */
  3844. (curr_sg - 1)->Ext = cpu_to_le32(HPSA_SG_LAST);
  3845. if (use_sg + chained > h->maxSG)
  3846. h->maxSG = use_sg + chained;
  3847. if (chained) {
  3848. cp->Header.SGList = h->max_cmd_sg_entries;
  3849. cp->Header.SGTotal = cpu_to_le16(use_sg + 1);
  3850. if (hpsa_map_sg_chain_block(h, cp)) {
  3851. scsi_dma_unmap(cmd);
  3852. return -1;
  3853. }
  3854. return 0;
  3855. }
  3856. sglist_finished:
  3857. cp->Header.SGList = (u8) use_sg; /* no. SGs contig in this cmd */
  3858. cp->Header.SGTotal = cpu_to_le16(use_sg); /* total sgs in cmd list */
  3859. return 0;
  3860. }
  3861. #define IO_ACCEL_INELIGIBLE (1)
  3862. static int fixup_ioaccel_cdb(u8 *cdb, int *cdb_len)
  3863. {
  3864. int is_write = 0;
  3865. u32 block;
  3866. u32 block_cnt;
  3867. /* Perform some CDB fixups if needed using 10 byte reads/writes only */
  3868. switch (cdb[0]) {
  3869. case WRITE_6:
  3870. case WRITE_12:
  3871. is_write = 1;
  3872. case READ_6:
  3873. case READ_12:
  3874. if (*cdb_len == 6) {
  3875. block = get_unaligned_be16(&cdb[2]);
  3876. block_cnt = cdb[4];
  3877. if (block_cnt == 0)
  3878. block_cnt = 256;
  3879. } else {
  3880. BUG_ON(*cdb_len != 12);
  3881. block = get_unaligned_be32(&cdb[2]);
  3882. block_cnt = get_unaligned_be32(&cdb[6]);
  3883. }
  3884. if (block_cnt > 0xffff)
  3885. return IO_ACCEL_INELIGIBLE;
  3886. cdb[0] = is_write ? WRITE_10 : READ_10;
  3887. cdb[1] = 0;
  3888. cdb[2] = (u8) (block >> 24);
  3889. cdb[3] = (u8) (block >> 16);
  3890. cdb[4] = (u8) (block >> 8);
  3891. cdb[5] = (u8) (block);
  3892. cdb[6] = 0;
  3893. cdb[7] = (u8) (block_cnt >> 8);
  3894. cdb[8] = (u8) (block_cnt);
  3895. cdb[9] = 0;
  3896. *cdb_len = 10;
  3897. break;
  3898. }
  3899. return 0;
  3900. }
  3901. static int hpsa_scsi_ioaccel1_queue_command(struct ctlr_info *h,
  3902. struct CommandList *c, u32 ioaccel_handle, u8 *cdb, int cdb_len,
  3903. u8 *scsi3addr, struct hpsa_scsi_dev_t *phys_disk)
  3904. {
  3905. struct scsi_cmnd *cmd = c->scsi_cmd;
  3906. struct io_accel1_cmd *cp = &h->ioaccel_cmd_pool[c->cmdindex];
  3907. unsigned int len;
  3908. unsigned int total_len = 0;
  3909. struct scatterlist *sg;
  3910. u64 addr64;
  3911. int use_sg, i;
  3912. struct SGDescriptor *curr_sg;
  3913. u32 control = IOACCEL1_CONTROL_SIMPLEQUEUE;
  3914. /* TODO: implement chaining support */
  3915. if (scsi_sg_count(cmd) > h->ioaccel_maxsg) {
  3916. atomic_dec(&phys_disk->ioaccel_cmds_out);
  3917. return IO_ACCEL_INELIGIBLE;
  3918. }
  3919. BUG_ON(cmd->cmd_len > IOACCEL1_IOFLAGS_CDBLEN_MAX);
  3920. if (fixup_ioaccel_cdb(cdb, &cdb_len)) {
  3921. atomic_dec(&phys_disk->ioaccel_cmds_out);
  3922. return IO_ACCEL_INELIGIBLE;
  3923. }
  3924. c->cmd_type = CMD_IOACCEL1;
  3925. /* Adjust the DMA address to point to the accelerated command buffer */
  3926. c->busaddr = (u32) h->ioaccel_cmd_pool_dhandle +
  3927. (c->cmdindex * sizeof(*cp));
  3928. BUG_ON(c->busaddr & 0x0000007F);
  3929. use_sg = scsi_dma_map(cmd);
  3930. if (use_sg < 0) {
  3931. atomic_dec(&phys_disk->ioaccel_cmds_out);
  3932. return use_sg;
  3933. }
  3934. if (use_sg) {
  3935. curr_sg = cp->SG;
  3936. scsi_for_each_sg(cmd, sg, use_sg, i) {
  3937. addr64 = (u64) sg_dma_address(sg);
  3938. len = sg_dma_len(sg);
  3939. total_len += len;
  3940. curr_sg->Addr = cpu_to_le64(addr64);
  3941. curr_sg->Len = cpu_to_le32(len);
  3942. curr_sg->Ext = cpu_to_le32(0);
  3943. curr_sg++;
  3944. }
  3945. (--curr_sg)->Ext = cpu_to_le32(HPSA_SG_LAST);
  3946. switch (cmd->sc_data_direction) {
  3947. case DMA_TO_DEVICE:
  3948. control |= IOACCEL1_CONTROL_DATA_OUT;
  3949. break;
  3950. case DMA_FROM_DEVICE:
  3951. control |= IOACCEL1_CONTROL_DATA_IN;
  3952. break;
  3953. case DMA_NONE:
  3954. control |= IOACCEL1_CONTROL_NODATAXFER;
  3955. break;
  3956. default:
  3957. dev_err(&h->pdev->dev, "unknown data direction: %d\n",
  3958. cmd->sc_data_direction);
  3959. BUG();
  3960. break;
  3961. }
  3962. } else {
  3963. control |= IOACCEL1_CONTROL_NODATAXFER;
  3964. }
  3965. c->Header.SGList = use_sg;
  3966. /* Fill out the command structure to submit */
  3967. cp->dev_handle = cpu_to_le16(ioaccel_handle & 0xFFFF);
  3968. cp->transfer_len = cpu_to_le32(total_len);
  3969. cp->io_flags = cpu_to_le16(IOACCEL1_IOFLAGS_IO_REQ |
  3970. (cdb_len & IOACCEL1_IOFLAGS_CDBLEN_MASK));
  3971. cp->control = cpu_to_le32(control);
  3972. memcpy(cp->CDB, cdb, cdb_len);
  3973. memcpy(cp->CISS_LUN, scsi3addr, 8);
  3974. /* Tag was already set at init time. */
  3975. enqueue_cmd_and_start_io(h, c);
  3976. return 0;
  3977. }
  3978. /*
  3979. * Queue a command directly to a device behind the controller using the
  3980. * I/O accelerator path.
  3981. */
  3982. static int hpsa_scsi_ioaccel_direct_map(struct ctlr_info *h,
  3983. struct CommandList *c)
  3984. {
  3985. struct scsi_cmnd *cmd = c->scsi_cmd;
  3986. struct hpsa_scsi_dev_t *dev = cmd->device->hostdata;
  3987. c->phys_disk = dev;
  3988. return hpsa_scsi_ioaccel_queue_command(h, c, dev->ioaccel_handle,
  3989. cmd->cmnd, cmd->cmd_len, dev->scsi3addr, dev);
  3990. }
  3991. /*
  3992. * Set encryption parameters for the ioaccel2 request
  3993. */
  3994. static void set_encrypt_ioaccel2(struct ctlr_info *h,
  3995. struct CommandList *c, struct io_accel2_cmd *cp)
  3996. {
  3997. struct scsi_cmnd *cmd = c->scsi_cmd;
  3998. struct hpsa_scsi_dev_t *dev = cmd->device->hostdata;
  3999. struct raid_map_data *map = &dev->raid_map;
  4000. u64 first_block;
  4001. /* Are we doing encryption on this device */
  4002. if (!(le16_to_cpu(map->flags) & RAID_MAP_FLAG_ENCRYPT_ON))
  4003. return;
  4004. /* Set the data encryption key index. */
  4005. cp->dekindex = map->dekindex;
  4006. /* Set the encryption enable flag, encoded into direction field. */
  4007. cp->direction |= IOACCEL2_DIRECTION_ENCRYPT_MASK;
  4008. /* Set encryption tweak values based on logical block address
  4009. * If block size is 512, tweak value is LBA.
  4010. * For other block sizes, tweak is (LBA * block size)/ 512)
  4011. */
  4012. switch (cmd->cmnd[0]) {
  4013. /* Required? 6-byte cdbs eliminated by fixup_ioaccel_cdb */
  4014. case WRITE_6:
  4015. case READ_6:
  4016. first_block = get_unaligned_be16(&cmd->cmnd[2]);
  4017. break;
  4018. case WRITE_10:
  4019. case READ_10:
  4020. /* Required? 12-byte cdbs eliminated by fixup_ioaccel_cdb */
  4021. case WRITE_12:
  4022. case READ_12:
  4023. first_block = get_unaligned_be32(&cmd->cmnd[2]);
  4024. break;
  4025. case WRITE_16:
  4026. case READ_16:
  4027. first_block = get_unaligned_be64(&cmd->cmnd[2]);
  4028. break;
  4029. default:
  4030. dev_err(&h->pdev->dev,
  4031. "ERROR: %s: size (0x%x) not supported for encryption\n",
  4032. __func__, cmd->cmnd[0]);
  4033. BUG();
  4034. break;
  4035. }
  4036. if (le32_to_cpu(map->volume_blk_size) != 512)
  4037. first_block = first_block *
  4038. le32_to_cpu(map->volume_blk_size)/512;
  4039. cp->tweak_lower = cpu_to_le32(first_block);
  4040. cp->tweak_upper = cpu_to_le32(first_block >> 32);
  4041. }
  4042. static int hpsa_scsi_ioaccel2_queue_command(struct ctlr_info *h,
  4043. struct CommandList *c, u32 ioaccel_handle, u8 *cdb, int cdb_len,
  4044. u8 *scsi3addr, struct hpsa_scsi_dev_t *phys_disk)
  4045. {
  4046. struct scsi_cmnd *cmd = c->scsi_cmd;
  4047. struct io_accel2_cmd *cp = &h->ioaccel2_cmd_pool[c->cmdindex];
  4048. struct ioaccel2_sg_element *curr_sg;
  4049. int use_sg, i;
  4050. struct scatterlist *sg;
  4051. u64 addr64;
  4052. u32 len;
  4053. u32 total_len = 0;
  4054. BUG_ON(scsi_sg_count(cmd) > h->maxsgentries);
  4055. if (fixup_ioaccel_cdb(cdb, &cdb_len)) {
  4056. atomic_dec(&phys_disk->ioaccel_cmds_out);
  4057. return IO_ACCEL_INELIGIBLE;
  4058. }
  4059. c->cmd_type = CMD_IOACCEL2;
  4060. /* Adjust the DMA address to point to the accelerated command buffer */
  4061. c->busaddr = (u32) h->ioaccel2_cmd_pool_dhandle +
  4062. (c->cmdindex * sizeof(*cp));
  4063. BUG_ON(c->busaddr & 0x0000007F);
  4064. memset(cp, 0, sizeof(*cp));
  4065. cp->IU_type = IOACCEL2_IU_TYPE;
  4066. use_sg = scsi_dma_map(cmd);
  4067. if (use_sg < 0) {
  4068. atomic_dec(&phys_disk->ioaccel_cmds_out);
  4069. return use_sg;
  4070. }
  4071. if (use_sg) {
  4072. curr_sg = cp->sg;
  4073. if (use_sg > h->ioaccel_maxsg) {
  4074. addr64 = le64_to_cpu(
  4075. h->ioaccel2_cmd_sg_list[c->cmdindex]->address);
  4076. curr_sg->address = cpu_to_le64(addr64);
  4077. curr_sg->length = 0;
  4078. curr_sg->reserved[0] = 0;
  4079. curr_sg->reserved[1] = 0;
  4080. curr_sg->reserved[2] = 0;
  4081. curr_sg->chain_indicator = 0x80;
  4082. curr_sg = h->ioaccel2_cmd_sg_list[c->cmdindex];
  4083. }
  4084. scsi_for_each_sg(cmd, sg, use_sg, i) {
  4085. addr64 = (u64) sg_dma_address(sg);
  4086. len = sg_dma_len(sg);
  4087. total_len += len;
  4088. curr_sg->address = cpu_to_le64(addr64);
  4089. curr_sg->length = cpu_to_le32(len);
  4090. curr_sg->reserved[0] = 0;
  4091. curr_sg->reserved[1] = 0;
  4092. curr_sg->reserved[2] = 0;
  4093. curr_sg->chain_indicator = 0;
  4094. curr_sg++;
  4095. }
  4096. switch (cmd->sc_data_direction) {
  4097. case DMA_TO_DEVICE:
  4098. cp->direction &= ~IOACCEL2_DIRECTION_MASK;
  4099. cp->direction |= IOACCEL2_DIR_DATA_OUT;
  4100. break;
  4101. case DMA_FROM_DEVICE:
  4102. cp->direction &= ~IOACCEL2_DIRECTION_MASK;
  4103. cp->direction |= IOACCEL2_DIR_DATA_IN;
  4104. break;
  4105. case DMA_NONE:
  4106. cp->direction &= ~IOACCEL2_DIRECTION_MASK;
  4107. cp->direction |= IOACCEL2_DIR_NO_DATA;
  4108. break;
  4109. default:
  4110. dev_err(&h->pdev->dev, "unknown data direction: %d\n",
  4111. cmd->sc_data_direction);
  4112. BUG();
  4113. break;
  4114. }
  4115. } else {
  4116. cp->direction &= ~IOACCEL2_DIRECTION_MASK;
  4117. cp->direction |= IOACCEL2_DIR_NO_DATA;
  4118. }
  4119. /* Set encryption parameters, if necessary */
  4120. set_encrypt_ioaccel2(h, c, cp);
  4121. cp->scsi_nexus = cpu_to_le32(ioaccel_handle);
  4122. cp->Tag = cpu_to_le32(c->cmdindex << DIRECT_LOOKUP_SHIFT);
  4123. memcpy(cp->cdb, cdb, sizeof(cp->cdb));
  4124. cp->data_len = cpu_to_le32(total_len);
  4125. cp->err_ptr = cpu_to_le64(c->busaddr +
  4126. offsetof(struct io_accel2_cmd, error_data));
  4127. cp->err_len = cpu_to_le32(sizeof(cp->error_data));
  4128. /* fill in sg elements */
  4129. if (use_sg > h->ioaccel_maxsg) {
  4130. cp->sg_count = 1;
  4131. cp->sg[0].length = cpu_to_le32(use_sg * sizeof(cp->sg[0]));
  4132. if (hpsa_map_ioaccel2_sg_chain_block(h, cp, c)) {
  4133. atomic_dec(&phys_disk->ioaccel_cmds_out);
  4134. scsi_dma_unmap(cmd);
  4135. return -1;
  4136. }
  4137. } else
  4138. cp->sg_count = (u8) use_sg;
  4139. enqueue_cmd_and_start_io(h, c);
  4140. return 0;
  4141. }
  4142. /*
  4143. * Queue a command to the correct I/O accelerator path.
  4144. */
  4145. static int hpsa_scsi_ioaccel_queue_command(struct ctlr_info *h,
  4146. struct CommandList *c, u32 ioaccel_handle, u8 *cdb, int cdb_len,
  4147. u8 *scsi3addr, struct hpsa_scsi_dev_t *phys_disk)
  4148. {
  4149. /* Try to honor the device's queue depth */
  4150. if (atomic_inc_return(&phys_disk->ioaccel_cmds_out) >
  4151. phys_disk->queue_depth) {
  4152. atomic_dec(&phys_disk->ioaccel_cmds_out);
  4153. return IO_ACCEL_INELIGIBLE;
  4154. }
  4155. if (h->transMethod & CFGTBL_Trans_io_accel1)
  4156. return hpsa_scsi_ioaccel1_queue_command(h, c, ioaccel_handle,
  4157. cdb, cdb_len, scsi3addr,
  4158. phys_disk);
  4159. else
  4160. return hpsa_scsi_ioaccel2_queue_command(h, c, ioaccel_handle,
  4161. cdb, cdb_len, scsi3addr,
  4162. phys_disk);
  4163. }
  4164. static void raid_map_helper(struct raid_map_data *map,
  4165. int offload_to_mirror, u32 *map_index, u32 *current_group)
  4166. {
  4167. if (offload_to_mirror == 0) {
  4168. /* use physical disk in the first mirrored group. */
  4169. *map_index %= le16_to_cpu(map->data_disks_per_row);
  4170. return;
  4171. }
  4172. do {
  4173. /* determine mirror group that *map_index indicates */
  4174. *current_group = *map_index /
  4175. le16_to_cpu(map->data_disks_per_row);
  4176. if (offload_to_mirror == *current_group)
  4177. continue;
  4178. if (*current_group < le16_to_cpu(map->layout_map_count) - 1) {
  4179. /* select map index from next group */
  4180. *map_index += le16_to_cpu(map->data_disks_per_row);
  4181. (*current_group)++;
  4182. } else {
  4183. /* select map index from first group */
  4184. *map_index %= le16_to_cpu(map->data_disks_per_row);
  4185. *current_group = 0;
  4186. }
  4187. } while (offload_to_mirror != *current_group);
  4188. }
  4189. /*
  4190. * Attempt to perform offload RAID mapping for a logical volume I/O.
  4191. */
  4192. static int hpsa_scsi_ioaccel_raid_map(struct ctlr_info *h,
  4193. struct CommandList *c)
  4194. {
  4195. struct scsi_cmnd *cmd = c->scsi_cmd;
  4196. struct hpsa_scsi_dev_t *dev = cmd->device->hostdata;
  4197. struct raid_map_data *map = &dev->raid_map;
  4198. struct raid_map_disk_data *dd = &map->data[0];
  4199. int is_write = 0;
  4200. u32 map_index;
  4201. u64 first_block, last_block;
  4202. u32 block_cnt;
  4203. u32 blocks_per_row;
  4204. u64 first_row, last_row;
  4205. u32 first_row_offset, last_row_offset;
  4206. u32 first_column, last_column;
  4207. u64 r0_first_row, r0_last_row;
  4208. u32 r5or6_blocks_per_row;
  4209. u64 r5or6_first_row, r5or6_last_row;
  4210. u32 r5or6_first_row_offset, r5or6_last_row_offset;
  4211. u32 r5or6_first_column, r5or6_last_column;
  4212. u32 total_disks_per_row;
  4213. u32 stripesize;
  4214. u32 first_group, last_group, current_group;
  4215. u32 map_row;
  4216. u32 disk_handle;
  4217. u64 disk_block;
  4218. u32 disk_block_cnt;
  4219. u8 cdb[16];
  4220. u8 cdb_len;
  4221. u16 strip_size;
  4222. #if BITS_PER_LONG == 32
  4223. u64 tmpdiv;
  4224. #endif
  4225. int offload_to_mirror;
  4226. /* check for valid opcode, get LBA and block count */
  4227. switch (cmd->cmnd[0]) {
  4228. case WRITE_6:
  4229. is_write = 1;
  4230. case READ_6:
  4231. first_block = get_unaligned_be16(&cmd->cmnd[2]);
  4232. block_cnt = cmd->cmnd[4];
  4233. if (block_cnt == 0)
  4234. block_cnt = 256;
  4235. break;
  4236. case WRITE_10:
  4237. is_write = 1;
  4238. case READ_10:
  4239. first_block =
  4240. (((u64) cmd->cmnd[2]) << 24) |
  4241. (((u64) cmd->cmnd[3]) << 16) |
  4242. (((u64) cmd->cmnd[4]) << 8) |
  4243. cmd->cmnd[5];
  4244. block_cnt =
  4245. (((u32) cmd->cmnd[7]) << 8) |
  4246. cmd->cmnd[8];
  4247. break;
  4248. case WRITE_12:
  4249. is_write = 1;
  4250. case READ_12:
  4251. first_block =
  4252. (((u64) cmd->cmnd[2]) << 24) |
  4253. (((u64) cmd->cmnd[3]) << 16) |
  4254. (((u64) cmd->cmnd[4]) << 8) |
  4255. cmd->cmnd[5];
  4256. block_cnt =
  4257. (((u32) cmd->cmnd[6]) << 24) |
  4258. (((u32) cmd->cmnd[7]) << 16) |
  4259. (((u32) cmd->cmnd[8]) << 8) |
  4260. cmd->cmnd[9];
  4261. break;
  4262. case WRITE_16:
  4263. is_write = 1;
  4264. case READ_16:
  4265. first_block =
  4266. (((u64) cmd->cmnd[2]) << 56) |
  4267. (((u64) cmd->cmnd[3]) << 48) |
  4268. (((u64) cmd->cmnd[4]) << 40) |
  4269. (((u64) cmd->cmnd[5]) << 32) |
  4270. (((u64) cmd->cmnd[6]) << 24) |
  4271. (((u64) cmd->cmnd[7]) << 16) |
  4272. (((u64) cmd->cmnd[8]) << 8) |
  4273. cmd->cmnd[9];
  4274. block_cnt =
  4275. (((u32) cmd->cmnd[10]) << 24) |
  4276. (((u32) cmd->cmnd[11]) << 16) |
  4277. (((u32) cmd->cmnd[12]) << 8) |
  4278. cmd->cmnd[13];
  4279. break;
  4280. default:
  4281. return IO_ACCEL_INELIGIBLE; /* process via normal I/O path */
  4282. }
  4283. last_block = first_block + block_cnt - 1;
  4284. /* check for write to non-RAID-0 */
  4285. if (is_write && dev->raid_level != 0)
  4286. return IO_ACCEL_INELIGIBLE;
  4287. /* check for invalid block or wraparound */
  4288. if (last_block >= le64_to_cpu(map->volume_blk_cnt) ||
  4289. last_block < first_block)
  4290. return IO_ACCEL_INELIGIBLE;
  4291. /* calculate stripe information for the request */
  4292. blocks_per_row = le16_to_cpu(map->data_disks_per_row) *
  4293. le16_to_cpu(map->strip_size);
  4294. strip_size = le16_to_cpu(map->strip_size);
  4295. #if BITS_PER_LONG == 32
  4296. tmpdiv = first_block;
  4297. (void) do_div(tmpdiv, blocks_per_row);
  4298. first_row = tmpdiv;
  4299. tmpdiv = last_block;
  4300. (void) do_div(tmpdiv, blocks_per_row);
  4301. last_row = tmpdiv;
  4302. first_row_offset = (u32) (first_block - (first_row * blocks_per_row));
  4303. last_row_offset = (u32) (last_block - (last_row * blocks_per_row));
  4304. tmpdiv = first_row_offset;
  4305. (void) do_div(tmpdiv, strip_size);
  4306. first_column = tmpdiv;
  4307. tmpdiv = last_row_offset;
  4308. (void) do_div(tmpdiv, strip_size);
  4309. last_column = tmpdiv;
  4310. #else
  4311. first_row = first_block / blocks_per_row;
  4312. last_row = last_block / blocks_per_row;
  4313. first_row_offset = (u32) (first_block - (first_row * blocks_per_row));
  4314. last_row_offset = (u32) (last_block - (last_row * blocks_per_row));
  4315. first_column = first_row_offset / strip_size;
  4316. last_column = last_row_offset / strip_size;
  4317. #endif
  4318. /* if this isn't a single row/column then give to the controller */
  4319. if ((first_row != last_row) || (first_column != last_column))
  4320. return IO_ACCEL_INELIGIBLE;
  4321. /* proceeding with driver mapping */
  4322. total_disks_per_row = le16_to_cpu(map->data_disks_per_row) +
  4323. le16_to_cpu(map->metadata_disks_per_row);
  4324. map_row = ((u32)(first_row >> map->parity_rotation_shift)) %
  4325. le16_to_cpu(map->row_cnt);
  4326. map_index = (map_row * total_disks_per_row) + first_column;
  4327. switch (dev->raid_level) {
  4328. case HPSA_RAID_0:
  4329. break; /* nothing special to do */
  4330. case HPSA_RAID_1:
  4331. /* Handles load balance across RAID 1 members.
  4332. * (2-drive R1 and R10 with even # of drives.)
  4333. * Appropriate for SSDs, not optimal for HDDs
  4334. */
  4335. BUG_ON(le16_to_cpu(map->layout_map_count) != 2);
  4336. if (dev->offload_to_mirror)
  4337. map_index += le16_to_cpu(map->data_disks_per_row);
  4338. dev->offload_to_mirror = !dev->offload_to_mirror;
  4339. break;
  4340. case HPSA_RAID_ADM:
  4341. /* Handles N-way mirrors (R1-ADM)
  4342. * and R10 with # of drives divisible by 3.)
  4343. */
  4344. BUG_ON(le16_to_cpu(map->layout_map_count) != 3);
  4345. offload_to_mirror = dev->offload_to_mirror;
  4346. raid_map_helper(map, offload_to_mirror,
  4347. &map_index, &current_group);
  4348. /* set mirror group to use next time */
  4349. offload_to_mirror =
  4350. (offload_to_mirror >=
  4351. le16_to_cpu(map->layout_map_count) - 1)
  4352. ? 0 : offload_to_mirror + 1;
  4353. dev->offload_to_mirror = offload_to_mirror;
  4354. /* Avoid direct use of dev->offload_to_mirror within this
  4355. * function since multiple threads might simultaneously
  4356. * increment it beyond the range of dev->layout_map_count -1.
  4357. */
  4358. break;
  4359. case HPSA_RAID_5:
  4360. case HPSA_RAID_6:
  4361. if (le16_to_cpu(map->layout_map_count) <= 1)
  4362. break;
  4363. /* Verify first and last block are in same RAID group */
  4364. r5or6_blocks_per_row =
  4365. le16_to_cpu(map->strip_size) *
  4366. le16_to_cpu(map->data_disks_per_row);
  4367. BUG_ON(r5or6_blocks_per_row == 0);
  4368. stripesize = r5or6_blocks_per_row *
  4369. le16_to_cpu(map->layout_map_count);
  4370. #if BITS_PER_LONG == 32
  4371. tmpdiv = first_block;
  4372. first_group = do_div(tmpdiv, stripesize);
  4373. tmpdiv = first_group;
  4374. (void) do_div(tmpdiv, r5or6_blocks_per_row);
  4375. first_group = tmpdiv;
  4376. tmpdiv = last_block;
  4377. last_group = do_div(tmpdiv, stripesize);
  4378. tmpdiv = last_group;
  4379. (void) do_div(tmpdiv, r5or6_blocks_per_row);
  4380. last_group = tmpdiv;
  4381. #else
  4382. first_group = (first_block % stripesize) / r5or6_blocks_per_row;
  4383. last_group = (last_block % stripesize) / r5or6_blocks_per_row;
  4384. #endif
  4385. if (first_group != last_group)
  4386. return IO_ACCEL_INELIGIBLE;
  4387. /* Verify request is in a single row of RAID 5/6 */
  4388. #if BITS_PER_LONG == 32
  4389. tmpdiv = first_block;
  4390. (void) do_div(tmpdiv, stripesize);
  4391. first_row = r5or6_first_row = r0_first_row = tmpdiv;
  4392. tmpdiv = last_block;
  4393. (void) do_div(tmpdiv, stripesize);
  4394. r5or6_last_row = r0_last_row = tmpdiv;
  4395. #else
  4396. first_row = r5or6_first_row = r0_first_row =
  4397. first_block / stripesize;
  4398. r5or6_last_row = r0_last_row = last_block / stripesize;
  4399. #endif
  4400. if (r5or6_first_row != r5or6_last_row)
  4401. return IO_ACCEL_INELIGIBLE;
  4402. /* Verify request is in a single column */
  4403. #if BITS_PER_LONG == 32
  4404. tmpdiv = first_block;
  4405. first_row_offset = do_div(tmpdiv, stripesize);
  4406. tmpdiv = first_row_offset;
  4407. first_row_offset = (u32) do_div(tmpdiv, r5or6_blocks_per_row);
  4408. r5or6_first_row_offset = first_row_offset;
  4409. tmpdiv = last_block;
  4410. r5or6_last_row_offset = do_div(tmpdiv, stripesize);
  4411. tmpdiv = r5or6_last_row_offset;
  4412. r5or6_last_row_offset = do_div(tmpdiv, r5or6_blocks_per_row);
  4413. tmpdiv = r5or6_first_row_offset;
  4414. (void) do_div(tmpdiv, map->strip_size);
  4415. first_column = r5or6_first_column = tmpdiv;
  4416. tmpdiv = r5or6_last_row_offset;
  4417. (void) do_div(tmpdiv, map->strip_size);
  4418. r5or6_last_column = tmpdiv;
  4419. #else
  4420. first_row_offset = r5or6_first_row_offset =
  4421. (u32)((first_block % stripesize) %
  4422. r5or6_blocks_per_row);
  4423. r5or6_last_row_offset =
  4424. (u32)((last_block % stripesize) %
  4425. r5or6_blocks_per_row);
  4426. first_column = r5or6_first_column =
  4427. r5or6_first_row_offset / le16_to_cpu(map->strip_size);
  4428. r5or6_last_column =
  4429. r5or6_last_row_offset / le16_to_cpu(map->strip_size);
  4430. #endif
  4431. if (r5or6_first_column != r5or6_last_column)
  4432. return IO_ACCEL_INELIGIBLE;
  4433. /* Request is eligible */
  4434. map_row = ((u32)(first_row >> map->parity_rotation_shift)) %
  4435. le16_to_cpu(map->row_cnt);
  4436. map_index = (first_group *
  4437. (le16_to_cpu(map->row_cnt) * total_disks_per_row)) +
  4438. (map_row * total_disks_per_row) + first_column;
  4439. break;
  4440. default:
  4441. return IO_ACCEL_INELIGIBLE;
  4442. }
  4443. if (unlikely(map_index >= RAID_MAP_MAX_ENTRIES))
  4444. return IO_ACCEL_INELIGIBLE;
  4445. c->phys_disk = dev->phys_disk[map_index];
  4446. disk_handle = dd[map_index].ioaccel_handle;
  4447. disk_block = le64_to_cpu(map->disk_starting_blk) +
  4448. first_row * le16_to_cpu(map->strip_size) +
  4449. (first_row_offset - first_column *
  4450. le16_to_cpu(map->strip_size));
  4451. disk_block_cnt = block_cnt;
  4452. /* handle differing logical/physical block sizes */
  4453. if (map->phys_blk_shift) {
  4454. disk_block <<= map->phys_blk_shift;
  4455. disk_block_cnt <<= map->phys_blk_shift;
  4456. }
  4457. BUG_ON(disk_block_cnt > 0xffff);
  4458. /* build the new CDB for the physical disk I/O */
  4459. if (disk_block > 0xffffffff) {
  4460. cdb[0] = is_write ? WRITE_16 : READ_16;
  4461. cdb[1] = 0;
  4462. cdb[2] = (u8) (disk_block >> 56);
  4463. cdb[3] = (u8) (disk_block >> 48);
  4464. cdb[4] = (u8) (disk_block >> 40);
  4465. cdb[5] = (u8) (disk_block >> 32);
  4466. cdb[6] = (u8) (disk_block >> 24);
  4467. cdb[7] = (u8) (disk_block >> 16);
  4468. cdb[8] = (u8) (disk_block >> 8);
  4469. cdb[9] = (u8) (disk_block);
  4470. cdb[10] = (u8) (disk_block_cnt >> 24);
  4471. cdb[11] = (u8) (disk_block_cnt >> 16);
  4472. cdb[12] = (u8) (disk_block_cnt >> 8);
  4473. cdb[13] = (u8) (disk_block_cnt);
  4474. cdb[14] = 0;
  4475. cdb[15] = 0;
  4476. cdb_len = 16;
  4477. } else {
  4478. cdb[0] = is_write ? WRITE_10 : READ_10;
  4479. cdb[1] = 0;
  4480. cdb[2] = (u8) (disk_block >> 24);
  4481. cdb[3] = (u8) (disk_block >> 16);
  4482. cdb[4] = (u8) (disk_block >> 8);
  4483. cdb[5] = (u8) (disk_block);
  4484. cdb[6] = 0;
  4485. cdb[7] = (u8) (disk_block_cnt >> 8);
  4486. cdb[8] = (u8) (disk_block_cnt);
  4487. cdb[9] = 0;
  4488. cdb_len = 10;
  4489. }
  4490. return hpsa_scsi_ioaccel_queue_command(h, c, disk_handle, cdb, cdb_len,
  4491. dev->scsi3addr,
  4492. dev->phys_disk[map_index]);
  4493. }
  4494. /*
  4495. * Submit commands down the "normal" RAID stack path
  4496. * All callers to hpsa_ciss_submit must check lockup_detected
  4497. * beforehand, before (opt.) and after calling cmd_alloc
  4498. */
  4499. static int hpsa_ciss_submit(struct ctlr_info *h,
  4500. struct CommandList *c, struct scsi_cmnd *cmd,
  4501. unsigned char scsi3addr[])
  4502. {
  4503. cmd->host_scribble = (unsigned char *) c;
  4504. c->cmd_type = CMD_SCSI;
  4505. c->scsi_cmd = cmd;
  4506. c->Header.ReplyQueue = 0; /* unused in simple mode */
  4507. memcpy(&c->Header.LUN.LunAddrBytes[0], &scsi3addr[0], 8);
  4508. c->Header.tag = cpu_to_le64((c->cmdindex << DIRECT_LOOKUP_SHIFT));
  4509. /* Fill in the request block... */
  4510. c->Request.Timeout = 0;
  4511. BUG_ON(cmd->cmd_len > sizeof(c->Request.CDB));
  4512. c->Request.CDBLen = cmd->cmd_len;
  4513. memcpy(c->Request.CDB, cmd->cmnd, cmd->cmd_len);
  4514. switch (cmd->sc_data_direction) {
  4515. case DMA_TO_DEVICE:
  4516. c->Request.type_attr_dir =
  4517. TYPE_ATTR_DIR(TYPE_CMD, ATTR_SIMPLE, XFER_WRITE);
  4518. break;
  4519. case DMA_FROM_DEVICE:
  4520. c->Request.type_attr_dir =
  4521. TYPE_ATTR_DIR(TYPE_CMD, ATTR_SIMPLE, XFER_READ);
  4522. break;
  4523. case DMA_NONE:
  4524. c->Request.type_attr_dir =
  4525. TYPE_ATTR_DIR(TYPE_CMD, ATTR_SIMPLE, XFER_NONE);
  4526. break;
  4527. case DMA_BIDIRECTIONAL:
  4528. /* This can happen if a buggy application does a scsi passthru
  4529. * and sets both inlen and outlen to non-zero. ( see
  4530. * ../scsi/scsi_ioctl.c:scsi_ioctl_send_command() )
  4531. */
  4532. c->Request.type_attr_dir =
  4533. TYPE_ATTR_DIR(TYPE_CMD, ATTR_SIMPLE, XFER_RSVD);
  4534. /* This is technically wrong, and hpsa controllers should
  4535. * reject it with CMD_INVALID, which is the most correct
  4536. * response, but non-fibre backends appear to let it
  4537. * slide by, and give the same results as if this field
  4538. * were set correctly. Either way is acceptable for
  4539. * our purposes here.
  4540. */
  4541. break;
  4542. default:
  4543. dev_err(&h->pdev->dev, "unknown data direction: %d\n",
  4544. cmd->sc_data_direction);
  4545. BUG();
  4546. break;
  4547. }
  4548. if (hpsa_scatter_gather(h, c, cmd) < 0) { /* Fill SG list */
  4549. hpsa_cmd_resolve_and_free(h, c);
  4550. return SCSI_MLQUEUE_HOST_BUSY;
  4551. }
  4552. enqueue_cmd_and_start_io(h, c);
  4553. /* the cmd'll come back via intr handler in complete_scsi_command() */
  4554. return 0;
  4555. }
  4556. static void hpsa_cmd_init(struct ctlr_info *h, int index,
  4557. struct CommandList *c)
  4558. {
  4559. dma_addr_t cmd_dma_handle, err_dma_handle;
  4560. /* Zero out all of commandlist except the last field, refcount */
  4561. memset(c, 0, offsetof(struct CommandList, refcount));
  4562. c->Header.tag = cpu_to_le64((u64) (index << DIRECT_LOOKUP_SHIFT));
  4563. cmd_dma_handle = h->cmd_pool_dhandle + index * sizeof(*c);
  4564. c->err_info = h->errinfo_pool + index;
  4565. memset(c->err_info, 0, sizeof(*c->err_info));
  4566. err_dma_handle = h->errinfo_pool_dhandle
  4567. + index * sizeof(*c->err_info);
  4568. c->cmdindex = index;
  4569. c->busaddr = (u32) cmd_dma_handle;
  4570. c->ErrDesc.Addr = cpu_to_le64((u64) err_dma_handle);
  4571. c->ErrDesc.Len = cpu_to_le32((u32) sizeof(*c->err_info));
  4572. c->h = h;
  4573. c->scsi_cmd = SCSI_CMD_IDLE;
  4574. }
  4575. static void hpsa_preinitialize_commands(struct ctlr_info *h)
  4576. {
  4577. int i;
  4578. for (i = 0; i < h->nr_cmds; i++) {
  4579. struct CommandList *c = h->cmd_pool + i;
  4580. hpsa_cmd_init(h, i, c);
  4581. atomic_set(&c->refcount, 0);
  4582. }
  4583. }
  4584. static inline void hpsa_cmd_partial_init(struct ctlr_info *h, int index,
  4585. struct CommandList *c)
  4586. {
  4587. dma_addr_t cmd_dma_handle = h->cmd_pool_dhandle + index * sizeof(*c);
  4588. BUG_ON(c->cmdindex != index);
  4589. memset(c->Request.CDB, 0, sizeof(c->Request.CDB));
  4590. memset(c->err_info, 0, sizeof(*c->err_info));
  4591. c->busaddr = (u32) cmd_dma_handle;
  4592. }
  4593. static int hpsa_ioaccel_submit(struct ctlr_info *h,
  4594. struct CommandList *c, struct scsi_cmnd *cmd,
  4595. unsigned char *scsi3addr)
  4596. {
  4597. struct hpsa_scsi_dev_t *dev = cmd->device->hostdata;
  4598. int rc = IO_ACCEL_INELIGIBLE;
  4599. cmd->host_scribble = (unsigned char *) c;
  4600. if (dev->offload_enabled) {
  4601. hpsa_cmd_init(h, c->cmdindex, c);
  4602. c->cmd_type = CMD_SCSI;
  4603. c->scsi_cmd = cmd;
  4604. rc = hpsa_scsi_ioaccel_raid_map(h, c);
  4605. if (rc < 0) /* scsi_dma_map failed. */
  4606. rc = SCSI_MLQUEUE_HOST_BUSY;
  4607. } else if (dev->hba_ioaccel_enabled) {
  4608. hpsa_cmd_init(h, c->cmdindex, c);
  4609. c->cmd_type = CMD_SCSI;
  4610. c->scsi_cmd = cmd;
  4611. rc = hpsa_scsi_ioaccel_direct_map(h, c);
  4612. if (rc < 0) /* scsi_dma_map failed. */
  4613. rc = SCSI_MLQUEUE_HOST_BUSY;
  4614. }
  4615. return rc;
  4616. }
  4617. static void hpsa_command_resubmit_worker(struct work_struct *work)
  4618. {
  4619. struct scsi_cmnd *cmd;
  4620. struct hpsa_scsi_dev_t *dev;
  4621. struct CommandList *c = container_of(work, struct CommandList, work);
  4622. cmd = c->scsi_cmd;
  4623. dev = cmd->device->hostdata;
  4624. if (!dev) {
  4625. cmd->result = DID_NO_CONNECT << 16;
  4626. return hpsa_cmd_free_and_done(c->h, c, cmd);
  4627. }
  4628. if (c->reset_pending)
  4629. return hpsa_cmd_resolve_and_free(c->h, c);
  4630. if (c->abort_pending)
  4631. return hpsa_cmd_abort_and_free(c->h, c, cmd);
  4632. if (c->cmd_type == CMD_IOACCEL2) {
  4633. struct ctlr_info *h = c->h;
  4634. struct io_accel2_cmd *c2 = &h->ioaccel2_cmd_pool[c->cmdindex];
  4635. int rc;
  4636. if (c2->error_data.serv_response ==
  4637. IOACCEL2_STATUS_SR_TASK_COMP_SET_FULL) {
  4638. rc = hpsa_ioaccel_submit(h, c, cmd, dev->scsi3addr);
  4639. if (rc == 0)
  4640. return;
  4641. if (rc == SCSI_MLQUEUE_HOST_BUSY) {
  4642. /*
  4643. * If we get here, it means dma mapping failed.
  4644. * Try again via scsi mid layer, which will
  4645. * then get SCSI_MLQUEUE_HOST_BUSY.
  4646. */
  4647. cmd->result = DID_IMM_RETRY << 16;
  4648. return hpsa_cmd_free_and_done(h, c, cmd);
  4649. }
  4650. /* else, fall thru and resubmit down CISS path */
  4651. }
  4652. }
  4653. hpsa_cmd_partial_init(c->h, c->cmdindex, c);
  4654. if (hpsa_ciss_submit(c->h, c, cmd, dev->scsi3addr)) {
  4655. /*
  4656. * If we get here, it means dma mapping failed. Try
  4657. * again via scsi mid layer, which will then get
  4658. * SCSI_MLQUEUE_HOST_BUSY.
  4659. *
  4660. * hpsa_ciss_submit will have already freed c
  4661. * if it encountered a dma mapping failure.
  4662. */
  4663. cmd->result = DID_IMM_RETRY << 16;
  4664. cmd->scsi_done(cmd);
  4665. }
  4666. }
  4667. /* Running in struct Scsi_Host->host_lock less mode */
  4668. static int hpsa_scsi_queue_command(struct Scsi_Host *sh, struct scsi_cmnd *cmd)
  4669. {
  4670. struct ctlr_info *h;
  4671. struct hpsa_scsi_dev_t *dev;
  4672. unsigned char scsi3addr[8];
  4673. struct CommandList *c;
  4674. int rc = 0;
  4675. /* Get the ptr to our adapter structure out of cmd->host. */
  4676. h = sdev_to_hba(cmd->device);
  4677. BUG_ON(cmd->request->tag < 0);
  4678. dev = cmd->device->hostdata;
  4679. if (!dev) {
  4680. cmd->result = DID_NO_CONNECT << 16;
  4681. cmd->scsi_done(cmd);
  4682. return 0;
  4683. }
  4684. memcpy(scsi3addr, dev->scsi3addr, sizeof(scsi3addr));
  4685. if (unlikely(lockup_detected(h))) {
  4686. cmd->result = DID_NO_CONNECT << 16;
  4687. cmd->scsi_done(cmd);
  4688. return 0;
  4689. }
  4690. c = cmd_tagged_alloc(h, cmd);
  4691. /*
  4692. * Call alternate submit routine for I/O accelerated commands.
  4693. * Retries always go down the normal I/O path.
  4694. */
  4695. if (likely(cmd->retries == 0 &&
  4696. cmd->request->cmd_type == REQ_TYPE_FS &&
  4697. h->acciopath_status)) {
  4698. rc = hpsa_ioaccel_submit(h, c, cmd, scsi3addr);
  4699. if (rc == 0)
  4700. return 0;
  4701. if (rc == SCSI_MLQUEUE_HOST_BUSY) {
  4702. hpsa_cmd_resolve_and_free(h, c);
  4703. return SCSI_MLQUEUE_HOST_BUSY;
  4704. }
  4705. }
  4706. return hpsa_ciss_submit(h, c, cmd, scsi3addr);
  4707. }
  4708. static void hpsa_scan_complete(struct ctlr_info *h)
  4709. {
  4710. unsigned long flags;
  4711. spin_lock_irqsave(&h->scan_lock, flags);
  4712. h->scan_finished = 1;
  4713. wake_up(&h->scan_wait_queue);
  4714. spin_unlock_irqrestore(&h->scan_lock, flags);
  4715. }
  4716. static void hpsa_scan_start(struct Scsi_Host *sh)
  4717. {
  4718. struct ctlr_info *h = shost_to_hba(sh);
  4719. unsigned long flags;
  4720. /*
  4721. * Don't let rescans be initiated on a controller known to be locked
  4722. * up. If the controller locks up *during* a rescan, that thread is
  4723. * probably hosed, but at least we can prevent new rescan threads from
  4724. * piling up on a locked up controller.
  4725. */
  4726. if (unlikely(lockup_detected(h)))
  4727. return hpsa_scan_complete(h);
  4728. /*
  4729. * If a scan is already waiting to run, no need to add another
  4730. */
  4731. spin_lock_irqsave(&h->scan_lock, flags);
  4732. if (h->scan_waiting) {
  4733. spin_unlock_irqrestore(&h->scan_lock, flags);
  4734. return;
  4735. }
  4736. spin_unlock_irqrestore(&h->scan_lock, flags);
  4737. /* wait until any scan already in progress is finished. */
  4738. while (1) {
  4739. spin_lock_irqsave(&h->scan_lock, flags);
  4740. if (h->scan_finished)
  4741. break;
  4742. h->scan_waiting = 1;
  4743. spin_unlock_irqrestore(&h->scan_lock, flags);
  4744. wait_event(h->scan_wait_queue, h->scan_finished);
  4745. /* Note: We don't need to worry about a race between this
  4746. * thread and driver unload because the midlayer will
  4747. * have incremented the reference count, so unload won't
  4748. * happen if we're in here.
  4749. */
  4750. }
  4751. h->scan_finished = 0; /* mark scan as in progress */
  4752. h->scan_waiting = 0;
  4753. spin_unlock_irqrestore(&h->scan_lock, flags);
  4754. if (unlikely(lockup_detected(h)))
  4755. return hpsa_scan_complete(h);
  4756. hpsa_update_scsi_devices(h);
  4757. hpsa_scan_complete(h);
  4758. }
  4759. static int hpsa_change_queue_depth(struct scsi_device *sdev, int qdepth)
  4760. {
  4761. struct hpsa_scsi_dev_t *logical_drive = sdev->hostdata;
  4762. if (!logical_drive)
  4763. return -ENODEV;
  4764. if (qdepth < 1)
  4765. qdepth = 1;
  4766. else if (qdepth > logical_drive->queue_depth)
  4767. qdepth = logical_drive->queue_depth;
  4768. return scsi_change_queue_depth(sdev, qdepth);
  4769. }
  4770. static int hpsa_scan_finished(struct Scsi_Host *sh,
  4771. unsigned long elapsed_time)
  4772. {
  4773. struct ctlr_info *h = shost_to_hba(sh);
  4774. unsigned long flags;
  4775. int finished;
  4776. spin_lock_irqsave(&h->scan_lock, flags);
  4777. finished = h->scan_finished;
  4778. spin_unlock_irqrestore(&h->scan_lock, flags);
  4779. return finished;
  4780. }
  4781. static int hpsa_scsi_host_alloc(struct ctlr_info *h)
  4782. {
  4783. struct Scsi_Host *sh;
  4784. sh = scsi_host_alloc(&hpsa_driver_template, sizeof(h));
  4785. if (sh == NULL) {
  4786. dev_err(&h->pdev->dev, "scsi_host_alloc failed\n");
  4787. return -ENOMEM;
  4788. }
  4789. sh->io_port = 0;
  4790. sh->n_io_port = 0;
  4791. sh->this_id = -1;
  4792. sh->max_channel = 3;
  4793. sh->max_cmd_len = MAX_COMMAND_SIZE;
  4794. sh->max_lun = HPSA_MAX_LUN;
  4795. sh->max_id = HPSA_MAX_LUN;
  4796. sh->can_queue = h->nr_cmds - HPSA_NRESERVED_CMDS;
  4797. sh->cmd_per_lun = sh->can_queue;
  4798. sh->sg_tablesize = h->maxsgentries;
  4799. sh->transportt = hpsa_sas_transport_template;
  4800. sh->hostdata[0] = (unsigned long) h;
  4801. sh->irq = h->intr[h->intr_mode];
  4802. sh->unique_id = sh->irq;
  4803. h->scsi_host = sh;
  4804. return 0;
  4805. }
  4806. static int hpsa_scsi_add_host(struct ctlr_info *h)
  4807. {
  4808. int rv;
  4809. rv = scsi_add_host(h->scsi_host, &h->pdev->dev);
  4810. if (rv) {
  4811. dev_err(&h->pdev->dev, "scsi_add_host failed\n");
  4812. return rv;
  4813. }
  4814. scsi_scan_host(h->scsi_host);
  4815. return 0;
  4816. }
  4817. /*
  4818. * The block layer has already gone to the trouble of picking out a unique,
  4819. * small-integer tag for this request. We use an offset from that value as
  4820. * an index to select our command block. (The offset allows us to reserve the
  4821. * low-numbered entries for our own uses.)
  4822. */
  4823. static int hpsa_get_cmd_index(struct scsi_cmnd *scmd)
  4824. {
  4825. int idx = scmd->request->tag;
  4826. if (idx < 0)
  4827. return idx;
  4828. /* Offset to leave space for internal cmds. */
  4829. return idx += HPSA_NRESERVED_CMDS;
  4830. }
  4831. /*
  4832. * Send a TEST_UNIT_READY command to the specified LUN using the specified
  4833. * reply queue; returns zero if the unit is ready, and non-zero otherwise.
  4834. */
  4835. static int hpsa_send_test_unit_ready(struct ctlr_info *h,
  4836. struct CommandList *c, unsigned char lunaddr[],
  4837. int reply_queue)
  4838. {
  4839. int rc;
  4840. /* Send the Test Unit Ready, fill_cmd can't fail, no mapping */
  4841. (void) fill_cmd(c, TEST_UNIT_READY, h,
  4842. NULL, 0, 0, lunaddr, TYPE_CMD);
  4843. rc = hpsa_scsi_do_simple_cmd(h, c, reply_queue, NO_TIMEOUT);
  4844. if (rc)
  4845. return rc;
  4846. /* no unmap needed here because no data xfer. */
  4847. /* Check if the unit is already ready. */
  4848. if (c->err_info->CommandStatus == CMD_SUCCESS)
  4849. return 0;
  4850. /*
  4851. * The first command sent after reset will receive "unit attention" to
  4852. * indicate that the LUN has been reset...this is actually what we're
  4853. * looking for (but, success is good too).
  4854. */
  4855. if (c->err_info->CommandStatus == CMD_TARGET_STATUS &&
  4856. c->err_info->ScsiStatus == SAM_STAT_CHECK_CONDITION &&
  4857. (c->err_info->SenseInfo[2] == NO_SENSE ||
  4858. c->err_info->SenseInfo[2] == UNIT_ATTENTION))
  4859. return 0;
  4860. return 1;
  4861. }
  4862. /*
  4863. * Wait for a TEST_UNIT_READY command to complete, retrying as necessary;
  4864. * returns zero when the unit is ready, and non-zero when giving up.
  4865. */
  4866. static int hpsa_wait_for_test_unit_ready(struct ctlr_info *h,
  4867. struct CommandList *c,
  4868. unsigned char lunaddr[], int reply_queue)
  4869. {
  4870. int rc;
  4871. int count = 0;
  4872. int waittime = 1; /* seconds */
  4873. /* Send test unit ready until device ready, or give up. */
  4874. for (count = 0; count < HPSA_TUR_RETRY_LIMIT; count++) {
  4875. /*
  4876. * Wait for a bit. do this first, because if we send
  4877. * the TUR right away, the reset will just abort it.
  4878. */
  4879. msleep(1000 * waittime);
  4880. rc = hpsa_send_test_unit_ready(h, c, lunaddr, reply_queue);
  4881. if (!rc)
  4882. break;
  4883. /* Increase wait time with each try, up to a point. */
  4884. if (waittime < HPSA_MAX_WAIT_INTERVAL_SECS)
  4885. waittime *= 2;
  4886. dev_warn(&h->pdev->dev,
  4887. "waiting %d secs for device to become ready.\n",
  4888. waittime);
  4889. }
  4890. return rc;
  4891. }
  4892. static int wait_for_device_to_become_ready(struct ctlr_info *h,
  4893. unsigned char lunaddr[],
  4894. int reply_queue)
  4895. {
  4896. int first_queue;
  4897. int last_queue;
  4898. int rq;
  4899. int rc = 0;
  4900. struct CommandList *c;
  4901. c = cmd_alloc(h);
  4902. /*
  4903. * If no specific reply queue was requested, then send the TUR
  4904. * repeatedly, requesting a reply on each reply queue; otherwise execute
  4905. * the loop exactly once using only the specified queue.
  4906. */
  4907. if (reply_queue == DEFAULT_REPLY_QUEUE) {
  4908. first_queue = 0;
  4909. last_queue = h->nreply_queues - 1;
  4910. } else {
  4911. first_queue = reply_queue;
  4912. last_queue = reply_queue;
  4913. }
  4914. for (rq = first_queue; rq <= last_queue; rq++) {
  4915. rc = hpsa_wait_for_test_unit_ready(h, c, lunaddr, rq);
  4916. if (rc)
  4917. break;
  4918. }
  4919. if (rc)
  4920. dev_warn(&h->pdev->dev, "giving up on device.\n");
  4921. else
  4922. dev_warn(&h->pdev->dev, "device is ready.\n");
  4923. cmd_free(h, c);
  4924. return rc;
  4925. }
  4926. /* Need at least one of these error handlers to keep ../scsi/hosts.c from
  4927. * complaining. Doing a host- or bus-reset can't do anything good here.
  4928. */
  4929. static int hpsa_eh_device_reset_handler(struct scsi_cmnd *scsicmd)
  4930. {
  4931. int rc;
  4932. struct ctlr_info *h;
  4933. struct hpsa_scsi_dev_t *dev;
  4934. u8 reset_type;
  4935. char msg[48];
  4936. /* find the controller to which the command to be aborted was sent */
  4937. h = sdev_to_hba(scsicmd->device);
  4938. if (h == NULL) /* paranoia */
  4939. return FAILED;
  4940. if (lockup_detected(h))
  4941. return FAILED;
  4942. dev = scsicmd->device->hostdata;
  4943. if (!dev) {
  4944. dev_err(&h->pdev->dev, "%s: device lookup failed\n", __func__);
  4945. return FAILED;
  4946. }
  4947. /* if controller locked up, we can guarantee command won't complete */
  4948. if (lockup_detected(h)) {
  4949. snprintf(msg, sizeof(msg),
  4950. "cmd %d RESET FAILED, lockup detected",
  4951. hpsa_get_cmd_index(scsicmd));
  4952. hpsa_show_dev_msg(KERN_WARNING, h, dev, msg);
  4953. return FAILED;
  4954. }
  4955. /* this reset request might be the result of a lockup; check */
  4956. if (detect_controller_lockup(h)) {
  4957. snprintf(msg, sizeof(msg),
  4958. "cmd %d RESET FAILED, new lockup detected",
  4959. hpsa_get_cmd_index(scsicmd));
  4960. hpsa_show_dev_msg(KERN_WARNING, h, dev, msg);
  4961. return FAILED;
  4962. }
  4963. /* Do not attempt on controller */
  4964. if (is_hba_lunid(dev->scsi3addr))
  4965. return SUCCESS;
  4966. if (is_logical_dev_addr_mode(dev->scsi3addr))
  4967. reset_type = HPSA_DEVICE_RESET_MSG;
  4968. else
  4969. reset_type = HPSA_PHYS_TARGET_RESET;
  4970. sprintf(msg, "resetting %s",
  4971. reset_type == HPSA_DEVICE_RESET_MSG ? "logical " : "physical ");
  4972. hpsa_show_dev_msg(KERN_WARNING, h, dev, msg);
  4973. h->reset_in_progress = 1;
  4974. /* send a reset to the SCSI LUN which the command was sent to */
  4975. rc = hpsa_do_reset(h, dev, dev->scsi3addr, reset_type,
  4976. DEFAULT_REPLY_QUEUE);
  4977. sprintf(msg, "reset %s %s",
  4978. reset_type == HPSA_DEVICE_RESET_MSG ? "logical " : "physical ",
  4979. rc == 0 ? "completed successfully" : "failed");
  4980. hpsa_show_dev_msg(KERN_WARNING, h, dev, msg);
  4981. h->reset_in_progress = 0;
  4982. return rc == 0 ? SUCCESS : FAILED;
  4983. }
  4984. static void swizzle_abort_tag(u8 *tag)
  4985. {
  4986. u8 original_tag[8];
  4987. memcpy(original_tag, tag, 8);
  4988. tag[0] = original_tag[3];
  4989. tag[1] = original_tag[2];
  4990. tag[2] = original_tag[1];
  4991. tag[3] = original_tag[0];
  4992. tag[4] = original_tag[7];
  4993. tag[5] = original_tag[6];
  4994. tag[6] = original_tag[5];
  4995. tag[7] = original_tag[4];
  4996. }
  4997. static void hpsa_get_tag(struct ctlr_info *h,
  4998. struct CommandList *c, __le32 *taglower, __le32 *tagupper)
  4999. {
  5000. u64 tag;
  5001. if (c->cmd_type == CMD_IOACCEL1) {
  5002. struct io_accel1_cmd *cm1 = (struct io_accel1_cmd *)
  5003. &h->ioaccel_cmd_pool[c->cmdindex];
  5004. tag = le64_to_cpu(cm1->tag);
  5005. *tagupper = cpu_to_le32(tag >> 32);
  5006. *taglower = cpu_to_le32(tag);
  5007. return;
  5008. }
  5009. if (c->cmd_type == CMD_IOACCEL2) {
  5010. struct io_accel2_cmd *cm2 = (struct io_accel2_cmd *)
  5011. &h->ioaccel2_cmd_pool[c->cmdindex];
  5012. /* upper tag not used in ioaccel2 mode */
  5013. memset(tagupper, 0, sizeof(*tagupper));
  5014. *taglower = cm2->Tag;
  5015. return;
  5016. }
  5017. tag = le64_to_cpu(c->Header.tag);
  5018. *tagupper = cpu_to_le32(tag >> 32);
  5019. *taglower = cpu_to_le32(tag);
  5020. }
  5021. static int hpsa_send_abort(struct ctlr_info *h, unsigned char *scsi3addr,
  5022. struct CommandList *abort, int reply_queue)
  5023. {
  5024. int rc = IO_OK;
  5025. struct CommandList *c;
  5026. struct ErrorInfo *ei;
  5027. __le32 tagupper, taglower;
  5028. c = cmd_alloc(h);
  5029. /* fill_cmd can't fail here, no buffer to map */
  5030. (void) fill_cmd(c, HPSA_ABORT_MSG, h, &abort->Header.tag,
  5031. 0, 0, scsi3addr, TYPE_MSG);
  5032. if (h->needs_abort_tags_swizzled)
  5033. swizzle_abort_tag(&c->Request.CDB[4]);
  5034. (void) hpsa_scsi_do_simple_cmd(h, c, reply_queue, NO_TIMEOUT);
  5035. hpsa_get_tag(h, abort, &taglower, &tagupper);
  5036. dev_dbg(&h->pdev->dev, "%s: Tag:0x%08x:%08x: do_simple_cmd(abort) completed.\n",
  5037. __func__, tagupper, taglower);
  5038. /* no unmap needed here because no data xfer. */
  5039. ei = c->err_info;
  5040. switch (ei->CommandStatus) {
  5041. case CMD_SUCCESS:
  5042. break;
  5043. case CMD_TMF_STATUS:
  5044. rc = hpsa_evaluate_tmf_status(h, c);
  5045. break;
  5046. case CMD_UNABORTABLE: /* Very common, don't make noise. */
  5047. rc = -1;
  5048. break;
  5049. default:
  5050. dev_dbg(&h->pdev->dev, "%s: Tag:0x%08x:%08x: interpreting error.\n",
  5051. __func__, tagupper, taglower);
  5052. hpsa_scsi_interpret_error(h, c);
  5053. rc = -1;
  5054. break;
  5055. }
  5056. cmd_free(h, c);
  5057. dev_dbg(&h->pdev->dev, "%s: Tag:0x%08x:%08x: Finished.\n",
  5058. __func__, tagupper, taglower);
  5059. return rc;
  5060. }
  5061. static void setup_ioaccel2_abort_cmd(struct CommandList *c, struct ctlr_info *h,
  5062. struct CommandList *command_to_abort, int reply_queue)
  5063. {
  5064. struct io_accel2_cmd *c2 = &h->ioaccel2_cmd_pool[c->cmdindex];
  5065. struct hpsa_tmf_struct *ac = (struct hpsa_tmf_struct *) c2;
  5066. struct io_accel2_cmd *c2a =
  5067. &h->ioaccel2_cmd_pool[command_to_abort->cmdindex];
  5068. struct scsi_cmnd *scmd = command_to_abort->scsi_cmd;
  5069. struct hpsa_scsi_dev_t *dev = scmd->device->hostdata;
  5070. /*
  5071. * We're overlaying struct hpsa_tmf_struct on top of something which
  5072. * was allocated as a struct io_accel2_cmd, so we better be sure it
  5073. * actually fits, and doesn't overrun the error info space.
  5074. */
  5075. BUILD_BUG_ON(sizeof(struct hpsa_tmf_struct) >
  5076. sizeof(struct io_accel2_cmd));
  5077. BUG_ON(offsetof(struct io_accel2_cmd, error_data) <
  5078. offsetof(struct hpsa_tmf_struct, error_len) +
  5079. sizeof(ac->error_len));
  5080. c->cmd_type = IOACCEL2_TMF;
  5081. c->scsi_cmd = SCSI_CMD_BUSY;
  5082. /* Adjust the DMA address to point to the accelerated command buffer */
  5083. c->busaddr = (u32) h->ioaccel2_cmd_pool_dhandle +
  5084. (c->cmdindex * sizeof(struct io_accel2_cmd));
  5085. BUG_ON(c->busaddr & 0x0000007F);
  5086. memset(ac, 0, sizeof(*c2)); /* yes this is correct */
  5087. ac->iu_type = IOACCEL2_IU_TMF_TYPE;
  5088. ac->reply_queue = reply_queue;
  5089. ac->tmf = IOACCEL2_TMF_ABORT;
  5090. ac->it_nexus = cpu_to_le32(dev->ioaccel_handle);
  5091. memset(ac->lun_id, 0, sizeof(ac->lun_id));
  5092. ac->tag = cpu_to_le64(c->cmdindex << DIRECT_LOOKUP_SHIFT);
  5093. ac->abort_tag = cpu_to_le64(le32_to_cpu(c2a->Tag));
  5094. ac->error_ptr = cpu_to_le64(c->busaddr +
  5095. offsetof(struct io_accel2_cmd, error_data));
  5096. ac->error_len = cpu_to_le32(sizeof(c2->error_data));
  5097. }
  5098. /* ioaccel2 path firmware cannot handle abort task requests.
  5099. * Change abort requests to physical target reset, and send to the
  5100. * address of the physical disk used for the ioaccel 2 command.
  5101. * Return 0 on success (IO_OK)
  5102. * -1 on failure
  5103. */
  5104. static int hpsa_send_reset_as_abort_ioaccel2(struct ctlr_info *h,
  5105. unsigned char *scsi3addr, struct CommandList *abort, int reply_queue)
  5106. {
  5107. int rc = IO_OK;
  5108. struct scsi_cmnd *scmd; /* scsi command within request being aborted */
  5109. struct hpsa_scsi_dev_t *dev; /* device to which scsi cmd was sent */
  5110. unsigned char phys_scsi3addr[8]; /* addr of phys disk with volume */
  5111. unsigned char *psa = &phys_scsi3addr[0];
  5112. /* Get a pointer to the hpsa logical device. */
  5113. scmd = abort->scsi_cmd;
  5114. dev = (struct hpsa_scsi_dev_t *)(scmd->device->hostdata);
  5115. if (dev == NULL) {
  5116. dev_warn(&h->pdev->dev,
  5117. "Cannot abort: no device pointer for command.\n");
  5118. return -1; /* not abortable */
  5119. }
  5120. if (h->raid_offload_debug > 0)
  5121. dev_info(&h->pdev->dev,
  5122. "scsi %d:%d:%d:%d %s scsi3addr 0x%02x%02x%02x%02x%02x%02x%02x%02x\n",
  5123. h->scsi_host->host_no, dev->bus, dev->target, dev->lun,
  5124. "Reset as abort",
  5125. scsi3addr[0], scsi3addr[1], scsi3addr[2], scsi3addr[3],
  5126. scsi3addr[4], scsi3addr[5], scsi3addr[6], scsi3addr[7]);
  5127. if (!dev->offload_enabled) {
  5128. dev_warn(&h->pdev->dev,
  5129. "Can't abort: device is not operating in HP SSD Smart Path mode.\n");
  5130. return -1; /* not abortable */
  5131. }
  5132. /* Incoming scsi3addr is logical addr. We need physical disk addr. */
  5133. if (!hpsa_get_pdisk_of_ioaccel2(h, abort, psa)) {
  5134. dev_warn(&h->pdev->dev, "Can't abort: Failed lookup of physical address.\n");
  5135. return -1; /* not abortable */
  5136. }
  5137. /* send the reset */
  5138. if (h->raid_offload_debug > 0)
  5139. dev_info(&h->pdev->dev,
  5140. "Reset as abort: Resetting physical device at scsi3addr 0x%02x%02x%02x%02x%02x%02x%02x%02x\n",
  5141. psa[0], psa[1], psa[2], psa[3],
  5142. psa[4], psa[5], psa[6], psa[7]);
  5143. rc = hpsa_do_reset(h, dev, psa, HPSA_RESET_TYPE_TARGET, reply_queue);
  5144. if (rc != 0) {
  5145. dev_warn(&h->pdev->dev,
  5146. "Reset as abort: Failed on physical device at scsi3addr 0x%02x%02x%02x%02x%02x%02x%02x%02x\n",
  5147. psa[0], psa[1], psa[2], psa[3],
  5148. psa[4], psa[5], psa[6], psa[7]);
  5149. return rc; /* failed to reset */
  5150. }
  5151. /* wait for device to recover */
  5152. if (wait_for_device_to_become_ready(h, psa, reply_queue) != 0) {
  5153. dev_warn(&h->pdev->dev,
  5154. "Reset as abort: Failed: Device never recovered from reset: 0x%02x%02x%02x%02x%02x%02x%02x%02x\n",
  5155. psa[0], psa[1], psa[2], psa[3],
  5156. psa[4], psa[5], psa[6], psa[7]);
  5157. return -1; /* failed to recover */
  5158. }
  5159. /* device recovered */
  5160. dev_info(&h->pdev->dev,
  5161. "Reset as abort: Device recovered from reset: scsi3addr 0x%02x%02x%02x%02x%02x%02x%02x%02x\n",
  5162. psa[0], psa[1], psa[2], psa[3],
  5163. psa[4], psa[5], psa[6], psa[7]);
  5164. return rc; /* success */
  5165. }
  5166. static int hpsa_send_abort_ioaccel2(struct ctlr_info *h,
  5167. struct CommandList *abort, int reply_queue)
  5168. {
  5169. int rc = IO_OK;
  5170. struct CommandList *c;
  5171. __le32 taglower, tagupper;
  5172. struct hpsa_scsi_dev_t *dev;
  5173. struct io_accel2_cmd *c2;
  5174. dev = abort->scsi_cmd->device->hostdata;
  5175. if (!dev->offload_enabled && !dev->hba_ioaccel_enabled)
  5176. return -1;
  5177. c = cmd_alloc(h);
  5178. setup_ioaccel2_abort_cmd(c, h, abort, reply_queue);
  5179. c2 = &h->ioaccel2_cmd_pool[c->cmdindex];
  5180. (void) hpsa_scsi_do_simple_cmd(h, c, reply_queue, NO_TIMEOUT);
  5181. hpsa_get_tag(h, abort, &taglower, &tagupper);
  5182. dev_dbg(&h->pdev->dev,
  5183. "%s: Tag:0x%08x:%08x: do_simple_cmd(ioaccel2 abort) completed.\n",
  5184. __func__, tagupper, taglower);
  5185. /* no unmap needed here because no data xfer. */
  5186. dev_dbg(&h->pdev->dev,
  5187. "%s: Tag:0x%08x:%08x: abort service response = 0x%02x.\n",
  5188. __func__, tagupper, taglower, c2->error_data.serv_response);
  5189. switch (c2->error_data.serv_response) {
  5190. case IOACCEL2_SERV_RESPONSE_TMF_COMPLETE:
  5191. case IOACCEL2_SERV_RESPONSE_TMF_SUCCESS:
  5192. rc = 0;
  5193. break;
  5194. case IOACCEL2_SERV_RESPONSE_TMF_REJECTED:
  5195. case IOACCEL2_SERV_RESPONSE_FAILURE:
  5196. case IOACCEL2_SERV_RESPONSE_TMF_WRONG_LUN:
  5197. rc = -1;
  5198. break;
  5199. default:
  5200. dev_warn(&h->pdev->dev,
  5201. "%s: Tag:0x%08x:%08x: unknown abort service response 0x%02x\n",
  5202. __func__, tagupper, taglower,
  5203. c2->error_data.serv_response);
  5204. rc = -1;
  5205. }
  5206. cmd_free(h, c);
  5207. dev_dbg(&h->pdev->dev, "%s: Tag:0x%08x:%08x: Finished.\n", __func__,
  5208. tagupper, taglower);
  5209. return rc;
  5210. }
  5211. static int hpsa_send_abort_both_ways(struct ctlr_info *h,
  5212. unsigned char *scsi3addr, struct CommandList *abort, int reply_queue)
  5213. {
  5214. /*
  5215. * ioccelerator mode 2 commands should be aborted via the
  5216. * accelerated path, since RAID path is unaware of these commands,
  5217. * but not all underlying firmware can handle abort TMF.
  5218. * Change abort to physical device reset when abort TMF is unsupported.
  5219. */
  5220. if (abort->cmd_type == CMD_IOACCEL2) {
  5221. if (HPSATMF_IOACCEL_ENABLED & h->TMFSupportFlags)
  5222. return hpsa_send_abort_ioaccel2(h, abort,
  5223. reply_queue);
  5224. else
  5225. return hpsa_send_reset_as_abort_ioaccel2(h, scsi3addr,
  5226. abort, reply_queue);
  5227. }
  5228. return hpsa_send_abort(h, scsi3addr, abort, reply_queue);
  5229. }
  5230. /* Find out which reply queue a command was meant to return on */
  5231. static int hpsa_extract_reply_queue(struct ctlr_info *h,
  5232. struct CommandList *c)
  5233. {
  5234. if (c->cmd_type == CMD_IOACCEL2)
  5235. return h->ioaccel2_cmd_pool[c->cmdindex].reply_queue;
  5236. return c->Header.ReplyQueue;
  5237. }
  5238. /*
  5239. * Limit concurrency of abort commands to prevent
  5240. * over-subscription of commands
  5241. */
  5242. static inline int wait_for_available_abort_cmd(struct ctlr_info *h)
  5243. {
  5244. #define ABORT_CMD_WAIT_MSECS 5000
  5245. return !wait_event_timeout(h->abort_cmd_wait_queue,
  5246. atomic_dec_if_positive(&h->abort_cmds_available) >= 0,
  5247. msecs_to_jiffies(ABORT_CMD_WAIT_MSECS));
  5248. }
  5249. /* Send an abort for the specified command.
  5250. * If the device and controller support it,
  5251. * send a task abort request.
  5252. */
  5253. static int hpsa_eh_abort_handler(struct scsi_cmnd *sc)
  5254. {
  5255. int rc;
  5256. struct ctlr_info *h;
  5257. struct hpsa_scsi_dev_t *dev;
  5258. struct CommandList *abort; /* pointer to command to be aborted */
  5259. struct scsi_cmnd *as; /* ptr to scsi cmd inside aborted command. */
  5260. char msg[256]; /* For debug messaging. */
  5261. int ml = 0;
  5262. __le32 tagupper, taglower;
  5263. int refcount, reply_queue;
  5264. if (sc == NULL)
  5265. return FAILED;
  5266. if (sc->device == NULL)
  5267. return FAILED;
  5268. /* Find the controller of the command to be aborted */
  5269. h = sdev_to_hba(sc->device);
  5270. if (h == NULL)
  5271. return FAILED;
  5272. /* Find the device of the command to be aborted */
  5273. dev = sc->device->hostdata;
  5274. if (!dev) {
  5275. dev_err(&h->pdev->dev, "%s FAILED, Device lookup failed.\n",
  5276. msg);
  5277. return FAILED;
  5278. }
  5279. /* If controller locked up, we can guarantee command won't complete */
  5280. if (lockup_detected(h)) {
  5281. hpsa_show_dev_msg(KERN_WARNING, h, dev,
  5282. "ABORT FAILED, lockup detected");
  5283. return FAILED;
  5284. }
  5285. /* This is a good time to check if controller lockup has occurred */
  5286. if (detect_controller_lockup(h)) {
  5287. hpsa_show_dev_msg(KERN_WARNING, h, dev,
  5288. "ABORT FAILED, new lockup detected");
  5289. return FAILED;
  5290. }
  5291. /* Check that controller supports some kind of task abort */
  5292. if (!(HPSATMF_PHYS_TASK_ABORT & h->TMFSupportFlags) &&
  5293. !(HPSATMF_LOG_TASK_ABORT & h->TMFSupportFlags))
  5294. return FAILED;
  5295. memset(msg, 0, sizeof(msg));
  5296. ml += sprintf(msg+ml, "scsi %d:%d:%d:%llu %s %p",
  5297. h->scsi_host->host_no, sc->device->channel,
  5298. sc->device->id, sc->device->lun,
  5299. "Aborting command", sc);
  5300. /* Get SCSI command to be aborted */
  5301. abort = (struct CommandList *) sc->host_scribble;
  5302. if (abort == NULL) {
  5303. /* This can happen if the command already completed. */
  5304. return SUCCESS;
  5305. }
  5306. refcount = atomic_inc_return(&abort->refcount);
  5307. if (refcount == 1) { /* Command is done already. */
  5308. cmd_free(h, abort);
  5309. return SUCCESS;
  5310. }
  5311. /* Don't bother trying the abort if we know it won't work. */
  5312. if (abort->cmd_type != CMD_IOACCEL2 &&
  5313. abort->cmd_type != CMD_IOACCEL1 && !dev->supports_aborts) {
  5314. cmd_free(h, abort);
  5315. return FAILED;
  5316. }
  5317. /*
  5318. * Check that we're aborting the right command.
  5319. * It's possible the CommandList already completed and got re-used.
  5320. */
  5321. if (abort->scsi_cmd != sc) {
  5322. cmd_free(h, abort);
  5323. return SUCCESS;
  5324. }
  5325. abort->abort_pending = true;
  5326. hpsa_get_tag(h, abort, &taglower, &tagupper);
  5327. reply_queue = hpsa_extract_reply_queue(h, abort);
  5328. ml += sprintf(msg+ml, "Tag:0x%08x:%08x ", tagupper, taglower);
  5329. as = abort->scsi_cmd;
  5330. if (as != NULL)
  5331. ml += sprintf(msg+ml,
  5332. "CDBLen: %d CDB: 0x%02x%02x... SN: 0x%lx ",
  5333. as->cmd_len, as->cmnd[0], as->cmnd[1],
  5334. as->serial_number);
  5335. dev_warn(&h->pdev->dev, "%s BEING SENT\n", msg);
  5336. hpsa_show_dev_msg(KERN_WARNING, h, dev, "Aborting command");
  5337. /*
  5338. * Command is in flight, or possibly already completed
  5339. * by the firmware (but not to the scsi mid layer) but we can't
  5340. * distinguish which. Send the abort down.
  5341. */
  5342. if (wait_for_available_abort_cmd(h)) {
  5343. dev_warn(&h->pdev->dev,
  5344. "%s FAILED, timeout waiting for an abort command to become available.\n",
  5345. msg);
  5346. cmd_free(h, abort);
  5347. return FAILED;
  5348. }
  5349. rc = hpsa_send_abort_both_ways(h, dev->scsi3addr, abort, reply_queue);
  5350. atomic_inc(&h->abort_cmds_available);
  5351. wake_up_all(&h->abort_cmd_wait_queue);
  5352. if (rc != 0) {
  5353. dev_warn(&h->pdev->dev, "%s SENT, FAILED\n", msg);
  5354. hpsa_show_dev_msg(KERN_WARNING, h, dev,
  5355. "FAILED to abort command");
  5356. cmd_free(h, abort);
  5357. return FAILED;
  5358. }
  5359. dev_info(&h->pdev->dev, "%s SENT, SUCCESS\n", msg);
  5360. wait_event(h->event_sync_wait_queue,
  5361. abort->scsi_cmd != sc || lockup_detected(h));
  5362. cmd_free(h, abort);
  5363. return !lockup_detected(h) ? SUCCESS : FAILED;
  5364. }
  5365. /*
  5366. * For operations with an associated SCSI command, a command block is allocated
  5367. * at init, and managed by cmd_tagged_alloc() and cmd_tagged_free() using the
  5368. * block request tag as an index into a table of entries. cmd_tagged_free() is
  5369. * the complement, although cmd_free() may be called instead.
  5370. */
  5371. static struct CommandList *cmd_tagged_alloc(struct ctlr_info *h,
  5372. struct scsi_cmnd *scmd)
  5373. {
  5374. int idx = hpsa_get_cmd_index(scmd);
  5375. struct CommandList *c = h->cmd_pool + idx;
  5376. if (idx < HPSA_NRESERVED_CMDS || idx >= h->nr_cmds) {
  5377. dev_err(&h->pdev->dev, "Bad block tag: %d not in [%d..%d]\n",
  5378. idx, HPSA_NRESERVED_CMDS, h->nr_cmds - 1);
  5379. /* The index value comes from the block layer, so if it's out of
  5380. * bounds, it's probably not our bug.
  5381. */
  5382. BUG();
  5383. }
  5384. atomic_inc(&c->refcount);
  5385. if (unlikely(!hpsa_is_cmd_idle(c))) {
  5386. /*
  5387. * We expect that the SCSI layer will hand us a unique tag
  5388. * value. Thus, there should never be a collision here between
  5389. * two requests...because if the selected command isn't idle
  5390. * then someone is going to be very disappointed.
  5391. */
  5392. dev_err(&h->pdev->dev,
  5393. "tag collision (tag=%d) in cmd_tagged_alloc().\n",
  5394. idx);
  5395. if (c->scsi_cmd != NULL)
  5396. scsi_print_command(c->scsi_cmd);
  5397. scsi_print_command(scmd);
  5398. }
  5399. hpsa_cmd_partial_init(h, idx, c);
  5400. return c;
  5401. }
  5402. static void cmd_tagged_free(struct ctlr_info *h, struct CommandList *c)
  5403. {
  5404. /*
  5405. * Release our reference to the block. We don't need to do anything
  5406. * else to free it, because it is accessed by index. (There's no point
  5407. * in checking the result of the decrement, since we cannot guarantee
  5408. * that there isn't a concurrent abort which is also accessing it.)
  5409. */
  5410. (void)atomic_dec(&c->refcount);
  5411. }
  5412. /*
  5413. * For operations that cannot sleep, a command block is allocated at init,
  5414. * and managed by cmd_alloc() and cmd_free() using a simple bitmap to track
  5415. * which ones are free or in use. Lock must be held when calling this.
  5416. * cmd_free() is the complement.
  5417. * This function never gives up and returns NULL. If it hangs,
  5418. * another thread must call cmd_free() to free some tags.
  5419. */
  5420. static struct CommandList *cmd_alloc(struct ctlr_info *h)
  5421. {
  5422. struct CommandList *c;
  5423. int refcount, i;
  5424. int offset = 0;
  5425. /*
  5426. * There is some *extremely* small but non-zero chance that that
  5427. * multiple threads could get in here, and one thread could
  5428. * be scanning through the list of bits looking for a free
  5429. * one, but the free ones are always behind him, and other
  5430. * threads sneak in behind him and eat them before he can
  5431. * get to them, so that while there is always a free one, a
  5432. * very unlucky thread might be starved anyway, never able to
  5433. * beat the other threads. In reality, this happens so
  5434. * infrequently as to be indistinguishable from never.
  5435. *
  5436. * Note that we start allocating commands before the SCSI host structure
  5437. * is initialized. Since the search starts at bit zero, this
  5438. * all works, since we have at least one command structure available;
  5439. * however, it means that the structures with the low indexes have to be
  5440. * reserved for driver-initiated requests, while requests from the block
  5441. * layer will use the higher indexes.
  5442. */
  5443. for (;;) {
  5444. i = find_next_zero_bit(h->cmd_pool_bits,
  5445. HPSA_NRESERVED_CMDS,
  5446. offset);
  5447. if (unlikely(i >= HPSA_NRESERVED_CMDS)) {
  5448. offset = 0;
  5449. continue;
  5450. }
  5451. c = h->cmd_pool + i;
  5452. refcount = atomic_inc_return(&c->refcount);
  5453. if (unlikely(refcount > 1)) {
  5454. cmd_free(h, c); /* already in use */
  5455. offset = (i + 1) % HPSA_NRESERVED_CMDS;
  5456. continue;
  5457. }
  5458. set_bit(i & (BITS_PER_LONG - 1),
  5459. h->cmd_pool_bits + (i / BITS_PER_LONG));
  5460. break; /* it's ours now. */
  5461. }
  5462. hpsa_cmd_partial_init(h, i, c);
  5463. return c;
  5464. }
  5465. /*
  5466. * This is the complementary operation to cmd_alloc(). Note, however, in some
  5467. * corner cases it may also be used to free blocks allocated by
  5468. * cmd_tagged_alloc() in which case the ref-count decrement does the trick and
  5469. * the clear-bit is harmless.
  5470. */
  5471. static void cmd_free(struct ctlr_info *h, struct CommandList *c)
  5472. {
  5473. if (atomic_dec_and_test(&c->refcount)) {
  5474. int i;
  5475. i = c - h->cmd_pool;
  5476. clear_bit(i & (BITS_PER_LONG - 1),
  5477. h->cmd_pool_bits + (i / BITS_PER_LONG));
  5478. }
  5479. }
  5480. #ifdef CONFIG_COMPAT
  5481. static int hpsa_ioctl32_passthru(struct scsi_device *dev, int cmd,
  5482. void __user *arg)
  5483. {
  5484. IOCTL32_Command_struct __user *arg32 =
  5485. (IOCTL32_Command_struct __user *) arg;
  5486. IOCTL_Command_struct arg64;
  5487. IOCTL_Command_struct __user *p = compat_alloc_user_space(sizeof(arg64));
  5488. int err;
  5489. u32 cp;
  5490. memset(&arg64, 0, sizeof(arg64));
  5491. err = 0;
  5492. err |= copy_from_user(&arg64.LUN_info, &arg32->LUN_info,
  5493. sizeof(arg64.LUN_info));
  5494. err |= copy_from_user(&arg64.Request, &arg32->Request,
  5495. sizeof(arg64.Request));
  5496. err |= copy_from_user(&arg64.error_info, &arg32->error_info,
  5497. sizeof(arg64.error_info));
  5498. err |= get_user(arg64.buf_size, &arg32->buf_size);
  5499. err |= get_user(cp, &arg32->buf);
  5500. arg64.buf = compat_ptr(cp);
  5501. err |= copy_to_user(p, &arg64, sizeof(arg64));
  5502. if (err)
  5503. return -EFAULT;
  5504. err = hpsa_ioctl(dev, CCISS_PASSTHRU, p);
  5505. if (err)
  5506. return err;
  5507. err |= copy_in_user(&arg32->error_info, &p->error_info,
  5508. sizeof(arg32->error_info));
  5509. if (err)
  5510. return -EFAULT;
  5511. return err;
  5512. }
  5513. static int hpsa_ioctl32_big_passthru(struct scsi_device *dev,
  5514. int cmd, void __user *arg)
  5515. {
  5516. BIG_IOCTL32_Command_struct __user *arg32 =
  5517. (BIG_IOCTL32_Command_struct __user *) arg;
  5518. BIG_IOCTL_Command_struct arg64;
  5519. BIG_IOCTL_Command_struct __user *p =
  5520. compat_alloc_user_space(sizeof(arg64));
  5521. int err;
  5522. u32 cp;
  5523. memset(&arg64, 0, sizeof(arg64));
  5524. err = 0;
  5525. err |= copy_from_user(&arg64.LUN_info, &arg32->LUN_info,
  5526. sizeof(arg64.LUN_info));
  5527. err |= copy_from_user(&arg64.Request, &arg32->Request,
  5528. sizeof(arg64.Request));
  5529. err |= copy_from_user(&arg64.error_info, &arg32->error_info,
  5530. sizeof(arg64.error_info));
  5531. err |= get_user(arg64.buf_size, &arg32->buf_size);
  5532. err |= get_user(arg64.malloc_size, &arg32->malloc_size);
  5533. err |= get_user(cp, &arg32->buf);
  5534. arg64.buf = compat_ptr(cp);
  5535. err |= copy_to_user(p, &arg64, sizeof(arg64));
  5536. if (err)
  5537. return -EFAULT;
  5538. err = hpsa_ioctl(dev, CCISS_BIG_PASSTHRU, p);
  5539. if (err)
  5540. return err;
  5541. err |= copy_in_user(&arg32->error_info, &p->error_info,
  5542. sizeof(arg32->error_info));
  5543. if (err)
  5544. return -EFAULT;
  5545. return err;
  5546. }
  5547. static int hpsa_compat_ioctl(struct scsi_device *dev, int cmd, void __user *arg)
  5548. {
  5549. switch (cmd) {
  5550. case CCISS_GETPCIINFO:
  5551. case CCISS_GETINTINFO:
  5552. case CCISS_SETINTINFO:
  5553. case CCISS_GETNODENAME:
  5554. case CCISS_SETNODENAME:
  5555. case CCISS_GETHEARTBEAT:
  5556. case CCISS_GETBUSTYPES:
  5557. case CCISS_GETFIRMVER:
  5558. case CCISS_GETDRIVVER:
  5559. case CCISS_REVALIDVOLS:
  5560. case CCISS_DEREGDISK:
  5561. case CCISS_REGNEWDISK:
  5562. case CCISS_REGNEWD:
  5563. case CCISS_RESCANDISK:
  5564. case CCISS_GETLUNINFO:
  5565. return hpsa_ioctl(dev, cmd, arg);
  5566. case CCISS_PASSTHRU32:
  5567. return hpsa_ioctl32_passthru(dev, cmd, arg);
  5568. case CCISS_BIG_PASSTHRU32:
  5569. return hpsa_ioctl32_big_passthru(dev, cmd, arg);
  5570. default:
  5571. return -ENOIOCTLCMD;
  5572. }
  5573. }
  5574. #endif
  5575. static int hpsa_getpciinfo_ioctl(struct ctlr_info *h, void __user *argp)
  5576. {
  5577. struct hpsa_pci_info pciinfo;
  5578. if (!argp)
  5579. return -EINVAL;
  5580. pciinfo.domain = pci_domain_nr(h->pdev->bus);
  5581. pciinfo.bus = h->pdev->bus->number;
  5582. pciinfo.dev_fn = h->pdev->devfn;
  5583. pciinfo.board_id = h->board_id;
  5584. if (copy_to_user(argp, &pciinfo, sizeof(pciinfo)))
  5585. return -EFAULT;
  5586. return 0;
  5587. }
  5588. static int hpsa_getdrivver_ioctl(struct ctlr_info *h, void __user *argp)
  5589. {
  5590. DriverVer_type DriverVer;
  5591. unsigned char vmaj, vmin, vsubmin;
  5592. int rc;
  5593. rc = sscanf(HPSA_DRIVER_VERSION, "%hhu.%hhu.%hhu",
  5594. &vmaj, &vmin, &vsubmin);
  5595. if (rc != 3) {
  5596. dev_info(&h->pdev->dev, "driver version string '%s' "
  5597. "unrecognized.", HPSA_DRIVER_VERSION);
  5598. vmaj = 0;
  5599. vmin = 0;
  5600. vsubmin = 0;
  5601. }
  5602. DriverVer = (vmaj << 16) | (vmin << 8) | vsubmin;
  5603. if (!argp)
  5604. return -EINVAL;
  5605. if (copy_to_user(argp, &DriverVer, sizeof(DriverVer_type)))
  5606. return -EFAULT;
  5607. return 0;
  5608. }
  5609. static int hpsa_passthru_ioctl(struct ctlr_info *h, void __user *argp)
  5610. {
  5611. IOCTL_Command_struct iocommand;
  5612. struct CommandList *c;
  5613. char *buff = NULL;
  5614. u64 temp64;
  5615. int rc = 0;
  5616. if (!argp)
  5617. return -EINVAL;
  5618. if (!capable(CAP_SYS_RAWIO))
  5619. return -EPERM;
  5620. if (copy_from_user(&iocommand, argp, sizeof(iocommand)))
  5621. return -EFAULT;
  5622. if ((iocommand.buf_size < 1) &&
  5623. (iocommand.Request.Type.Direction != XFER_NONE)) {
  5624. return -EINVAL;
  5625. }
  5626. if (iocommand.buf_size > 0) {
  5627. buff = kmalloc(iocommand.buf_size, GFP_KERNEL);
  5628. if (buff == NULL)
  5629. return -ENOMEM;
  5630. if (iocommand.Request.Type.Direction & XFER_WRITE) {
  5631. /* Copy the data into the buffer we created */
  5632. if (copy_from_user(buff, iocommand.buf,
  5633. iocommand.buf_size)) {
  5634. rc = -EFAULT;
  5635. goto out_kfree;
  5636. }
  5637. } else {
  5638. memset(buff, 0, iocommand.buf_size);
  5639. }
  5640. }
  5641. c = cmd_alloc(h);
  5642. /* Fill in the command type */
  5643. c->cmd_type = CMD_IOCTL_PEND;
  5644. c->scsi_cmd = SCSI_CMD_BUSY;
  5645. /* Fill in Command Header */
  5646. c->Header.ReplyQueue = 0; /* unused in simple mode */
  5647. if (iocommand.buf_size > 0) { /* buffer to fill */
  5648. c->Header.SGList = 1;
  5649. c->Header.SGTotal = cpu_to_le16(1);
  5650. } else { /* no buffers to fill */
  5651. c->Header.SGList = 0;
  5652. c->Header.SGTotal = cpu_to_le16(0);
  5653. }
  5654. memcpy(&c->Header.LUN, &iocommand.LUN_info, sizeof(c->Header.LUN));
  5655. /* Fill in Request block */
  5656. memcpy(&c->Request, &iocommand.Request,
  5657. sizeof(c->Request));
  5658. /* Fill in the scatter gather information */
  5659. if (iocommand.buf_size > 0) {
  5660. temp64 = pci_map_single(h->pdev, buff,
  5661. iocommand.buf_size, PCI_DMA_BIDIRECTIONAL);
  5662. if (dma_mapping_error(&h->pdev->dev, (dma_addr_t) temp64)) {
  5663. c->SG[0].Addr = cpu_to_le64(0);
  5664. c->SG[0].Len = cpu_to_le32(0);
  5665. rc = -ENOMEM;
  5666. goto out;
  5667. }
  5668. c->SG[0].Addr = cpu_to_le64(temp64);
  5669. c->SG[0].Len = cpu_to_le32(iocommand.buf_size);
  5670. c->SG[0].Ext = cpu_to_le32(HPSA_SG_LAST); /* not chaining */
  5671. }
  5672. rc = hpsa_scsi_do_simple_cmd(h, c, DEFAULT_REPLY_QUEUE, NO_TIMEOUT);
  5673. if (iocommand.buf_size > 0)
  5674. hpsa_pci_unmap(h->pdev, c, 1, PCI_DMA_BIDIRECTIONAL);
  5675. check_ioctl_unit_attention(h, c);
  5676. if (rc) {
  5677. rc = -EIO;
  5678. goto out;
  5679. }
  5680. /* Copy the error information out */
  5681. memcpy(&iocommand.error_info, c->err_info,
  5682. sizeof(iocommand.error_info));
  5683. if (copy_to_user(argp, &iocommand, sizeof(iocommand))) {
  5684. rc = -EFAULT;
  5685. goto out;
  5686. }
  5687. if ((iocommand.Request.Type.Direction & XFER_READ) &&
  5688. iocommand.buf_size > 0) {
  5689. /* Copy the data out of the buffer we created */
  5690. if (copy_to_user(iocommand.buf, buff, iocommand.buf_size)) {
  5691. rc = -EFAULT;
  5692. goto out;
  5693. }
  5694. }
  5695. out:
  5696. cmd_free(h, c);
  5697. out_kfree:
  5698. kfree(buff);
  5699. return rc;
  5700. }
  5701. static int hpsa_big_passthru_ioctl(struct ctlr_info *h, void __user *argp)
  5702. {
  5703. BIG_IOCTL_Command_struct *ioc;
  5704. struct CommandList *c;
  5705. unsigned char **buff = NULL;
  5706. int *buff_size = NULL;
  5707. u64 temp64;
  5708. BYTE sg_used = 0;
  5709. int status = 0;
  5710. u32 left;
  5711. u32 sz;
  5712. BYTE __user *data_ptr;
  5713. if (!argp)
  5714. return -EINVAL;
  5715. if (!capable(CAP_SYS_RAWIO))
  5716. return -EPERM;
  5717. ioc = (BIG_IOCTL_Command_struct *)
  5718. kmalloc(sizeof(*ioc), GFP_KERNEL);
  5719. if (!ioc) {
  5720. status = -ENOMEM;
  5721. goto cleanup1;
  5722. }
  5723. if (copy_from_user(ioc, argp, sizeof(*ioc))) {
  5724. status = -EFAULT;
  5725. goto cleanup1;
  5726. }
  5727. if ((ioc->buf_size < 1) &&
  5728. (ioc->Request.Type.Direction != XFER_NONE)) {
  5729. status = -EINVAL;
  5730. goto cleanup1;
  5731. }
  5732. /* Check kmalloc limits using all SGs */
  5733. if (ioc->malloc_size > MAX_KMALLOC_SIZE) {
  5734. status = -EINVAL;
  5735. goto cleanup1;
  5736. }
  5737. if (ioc->buf_size > ioc->malloc_size * SG_ENTRIES_IN_CMD) {
  5738. status = -EINVAL;
  5739. goto cleanup1;
  5740. }
  5741. buff = kzalloc(SG_ENTRIES_IN_CMD * sizeof(char *), GFP_KERNEL);
  5742. if (!buff) {
  5743. status = -ENOMEM;
  5744. goto cleanup1;
  5745. }
  5746. buff_size = kmalloc(SG_ENTRIES_IN_CMD * sizeof(int), GFP_KERNEL);
  5747. if (!buff_size) {
  5748. status = -ENOMEM;
  5749. goto cleanup1;
  5750. }
  5751. left = ioc->buf_size;
  5752. data_ptr = ioc->buf;
  5753. while (left) {
  5754. sz = (left > ioc->malloc_size) ? ioc->malloc_size : left;
  5755. buff_size[sg_used] = sz;
  5756. buff[sg_used] = kmalloc(sz, GFP_KERNEL);
  5757. if (buff[sg_used] == NULL) {
  5758. status = -ENOMEM;
  5759. goto cleanup1;
  5760. }
  5761. if (ioc->Request.Type.Direction & XFER_WRITE) {
  5762. if (copy_from_user(buff[sg_used], data_ptr, sz)) {
  5763. status = -EFAULT;
  5764. goto cleanup1;
  5765. }
  5766. } else
  5767. memset(buff[sg_used], 0, sz);
  5768. left -= sz;
  5769. data_ptr += sz;
  5770. sg_used++;
  5771. }
  5772. c = cmd_alloc(h);
  5773. c->cmd_type = CMD_IOCTL_PEND;
  5774. c->scsi_cmd = SCSI_CMD_BUSY;
  5775. c->Header.ReplyQueue = 0;
  5776. c->Header.SGList = (u8) sg_used;
  5777. c->Header.SGTotal = cpu_to_le16(sg_used);
  5778. memcpy(&c->Header.LUN, &ioc->LUN_info, sizeof(c->Header.LUN));
  5779. memcpy(&c->Request, &ioc->Request, sizeof(c->Request));
  5780. if (ioc->buf_size > 0) {
  5781. int i;
  5782. for (i = 0; i < sg_used; i++) {
  5783. temp64 = pci_map_single(h->pdev, buff[i],
  5784. buff_size[i], PCI_DMA_BIDIRECTIONAL);
  5785. if (dma_mapping_error(&h->pdev->dev,
  5786. (dma_addr_t) temp64)) {
  5787. c->SG[i].Addr = cpu_to_le64(0);
  5788. c->SG[i].Len = cpu_to_le32(0);
  5789. hpsa_pci_unmap(h->pdev, c, i,
  5790. PCI_DMA_BIDIRECTIONAL);
  5791. status = -ENOMEM;
  5792. goto cleanup0;
  5793. }
  5794. c->SG[i].Addr = cpu_to_le64(temp64);
  5795. c->SG[i].Len = cpu_to_le32(buff_size[i]);
  5796. c->SG[i].Ext = cpu_to_le32(0);
  5797. }
  5798. c->SG[--i].Ext = cpu_to_le32(HPSA_SG_LAST);
  5799. }
  5800. status = hpsa_scsi_do_simple_cmd(h, c, DEFAULT_REPLY_QUEUE, NO_TIMEOUT);
  5801. if (sg_used)
  5802. hpsa_pci_unmap(h->pdev, c, sg_used, PCI_DMA_BIDIRECTIONAL);
  5803. check_ioctl_unit_attention(h, c);
  5804. if (status) {
  5805. status = -EIO;
  5806. goto cleanup0;
  5807. }
  5808. /* Copy the error information out */
  5809. memcpy(&ioc->error_info, c->err_info, sizeof(ioc->error_info));
  5810. if (copy_to_user(argp, ioc, sizeof(*ioc))) {
  5811. status = -EFAULT;
  5812. goto cleanup0;
  5813. }
  5814. if ((ioc->Request.Type.Direction & XFER_READ) && ioc->buf_size > 0) {
  5815. int i;
  5816. /* Copy the data out of the buffer we created */
  5817. BYTE __user *ptr = ioc->buf;
  5818. for (i = 0; i < sg_used; i++) {
  5819. if (copy_to_user(ptr, buff[i], buff_size[i])) {
  5820. status = -EFAULT;
  5821. goto cleanup0;
  5822. }
  5823. ptr += buff_size[i];
  5824. }
  5825. }
  5826. status = 0;
  5827. cleanup0:
  5828. cmd_free(h, c);
  5829. cleanup1:
  5830. if (buff) {
  5831. int i;
  5832. for (i = 0; i < sg_used; i++)
  5833. kfree(buff[i]);
  5834. kfree(buff);
  5835. }
  5836. kfree(buff_size);
  5837. kfree(ioc);
  5838. return status;
  5839. }
  5840. static void check_ioctl_unit_attention(struct ctlr_info *h,
  5841. struct CommandList *c)
  5842. {
  5843. if (c->err_info->CommandStatus == CMD_TARGET_STATUS &&
  5844. c->err_info->ScsiStatus != SAM_STAT_CHECK_CONDITION)
  5845. (void) check_for_unit_attention(h, c);
  5846. }
  5847. /*
  5848. * ioctl
  5849. */
  5850. static int hpsa_ioctl(struct scsi_device *dev, int cmd, void __user *arg)
  5851. {
  5852. struct ctlr_info *h;
  5853. void __user *argp = (void __user *)arg;
  5854. int rc;
  5855. h = sdev_to_hba(dev);
  5856. switch (cmd) {
  5857. case CCISS_DEREGDISK:
  5858. case CCISS_REGNEWDISK:
  5859. case CCISS_REGNEWD:
  5860. hpsa_scan_start(h->scsi_host);
  5861. return 0;
  5862. case CCISS_GETPCIINFO:
  5863. return hpsa_getpciinfo_ioctl(h, argp);
  5864. case CCISS_GETDRIVVER:
  5865. return hpsa_getdrivver_ioctl(h, argp);
  5866. case CCISS_PASSTHRU:
  5867. if (atomic_dec_if_positive(&h->passthru_cmds_avail) < 0)
  5868. return -EAGAIN;
  5869. rc = hpsa_passthru_ioctl(h, argp);
  5870. atomic_inc(&h->passthru_cmds_avail);
  5871. return rc;
  5872. case CCISS_BIG_PASSTHRU:
  5873. if (atomic_dec_if_positive(&h->passthru_cmds_avail) < 0)
  5874. return -EAGAIN;
  5875. rc = hpsa_big_passthru_ioctl(h, argp);
  5876. atomic_inc(&h->passthru_cmds_avail);
  5877. return rc;
  5878. default:
  5879. return -ENOTTY;
  5880. }
  5881. }
  5882. static void hpsa_send_host_reset(struct ctlr_info *h, unsigned char *scsi3addr,
  5883. u8 reset_type)
  5884. {
  5885. struct CommandList *c;
  5886. c = cmd_alloc(h);
  5887. /* fill_cmd can't fail here, no data buffer to map */
  5888. (void) fill_cmd(c, HPSA_DEVICE_RESET_MSG, h, NULL, 0, 0,
  5889. RAID_CTLR_LUNID, TYPE_MSG);
  5890. c->Request.CDB[1] = reset_type; /* fill_cmd defaults to target reset */
  5891. c->waiting = NULL;
  5892. enqueue_cmd_and_start_io(h, c);
  5893. /* Don't wait for completion, the reset won't complete. Don't free
  5894. * the command either. This is the last command we will send before
  5895. * re-initializing everything, so it doesn't matter and won't leak.
  5896. */
  5897. return;
  5898. }
  5899. static int fill_cmd(struct CommandList *c, u8 cmd, struct ctlr_info *h,
  5900. void *buff, size_t size, u16 page_code, unsigned char *scsi3addr,
  5901. int cmd_type)
  5902. {
  5903. int pci_dir = XFER_NONE;
  5904. u64 tag; /* for commands to be aborted */
  5905. c->cmd_type = CMD_IOCTL_PEND;
  5906. c->scsi_cmd = SCSI_CMD_BUSY;
  5907. c->Header.ReplyQueue = 0;
  5908. if (buff != NULL && size > 0) {
  5909. c->Header.SGList = 1;
  5910. c->Header.SGTotal = cpu_to_le16(1);
  5911. } else {
  5912. c->Header.SGList = 0;
  5913. c->Header.SGTotal = cpu_to_le16(0);
  5914. }
  5915. memcpy(c->Header.LUN.LunAddrBytes, scsi3addr, 8);
  5916. if (cmd_type == TYPE_CMD) {
  5917. switch (cmd) {
  5918. case HPSA_INQUIRY:
  5919. /* are we trying to read a vital product page */
  5920. if (page_code & VPD_PAGE) {
  5921. c->Request.CDB[1] = 0x01;
  5922. c->Request.CDB[2] = (page_code & 0xff);
  5923. }
  5924. c->Request.CDBLen = 6;
  5925. c->Request.type_attr_dir =
  5926. TYPE_ATTR_DIR(cmd_type, ATTR_SIMPLE, XFER_READ);
  5927. c->Request.Timeout = 0;
  5928. c->Request.CDB[0] = HPSA_INQUIRY;
  5929. c->Request.CDB[4] = size & 0xFF;
  5930. break;
  5931. case HPSA_REPORT_LOG:
  5932. case HPSA_REPORT_PHYS:
  5933. /* Talking to controller so It's a physical command
  5934. mode = 00 target = 0. Nothing to write.
  5935. */
  5936. c->Request.CDBLen = 12;
  5937. c->Request.type_attr_dir =
  5938. TYPE_ATTR_DIR(cmd_type, ATTR_SIMPLE, XFER_READ);
  5939. c->Request.Timeout = 0;
  5940. c->Request.CDB[0] = cmd;
  5941. c->Request.CDB[6] = (size >> 24) & 0xFF; /* MSB */
  5942. c->Request.CDB[7] = (size >> 16) & 0xFF;
  5943. c->Request.CDB[8] = (size >> 8) & 0xFF;
  5944. c->Request.CDB[9] = size & 0xFF;
  5945. break;
  5946. case BMIC_SENSE_DIAG_OPTIONS:
  5947. c->Request.CDBLen = 16;
  5948. c->Request.type_attr_dir =
  5949. TYPE_ATTR_DIR(cmd_type, ATTR_SIMPLE, XFER_READ);
  5950. c->Request.Timeout = 0;
  5951. /* Spec says this should be BMIC_WRITE */
  5952. c->Request.CDB[0] = BMIC_READ;
  5953. c->Request.CDB[6] = BMIC_SENSE_DIAG_OPTIONS;
  5954. break;
  5955. case BMIC_SET_DIAG_OPTIONS:
  5956. c->Request.CDBLen = 16;
  5957. c->Request.type_attr_dir =
  5958. TYPE_ATTR_DIR(cmd_type,
  5959. ATTR_SIMPLE, XFER_WRITE);
  5960. c->Request.Timeout = 0;
  5961. c->Request.CDB[0] = BMIC_WRITE;
  5962. c->Request.CDB[6] = BMIC_SET_DIAG_OPTIONS;
  5963. break;
  5964. case HPSA_CACHE_FLUSH:
  5965. c->Request.CDBLen = 12;
  5966. c->Request.type_attr_dir =
  5967. TYPE_ATTR_DIR(cmd_type,
  5968. ATTR_SIMPLE, XFER_WRITE);
  5969. c->Request.Timeout = 0;
  5970. c->Request.CDB[0] = BMIC_WRITE;
  5971. c->Request.CDB[6] = BMIC_CACHE_FLUSH;
  5972. c->Request.CDB[7] = (size >> 8) & 0xFF;
  5973. c->Request.CDB[8] = size & 0xFF;
  5974. break;
  5975. case TEST_UNIT_READY:
  5976. c->Request.CDBLen = 6;
  5977. c->Request.type_attr_dir =
  5978. TYPE_ATTR_DIR(cmd_type, ATTR_SIMPLE, XFER_NONE);
  5979. c->Request.Timeout = 0;
  5980. break;
  5981. case HPSA_GET_RAID_MAP:
  5982. c->Request.CDBLen = 12;
  5983. c->Request.type_attr_dir =
  5984. TYPE_ATTR_DIR(cmd_type, ATTR_SIMPLE, XFER_READ);
  5985. c->Request.Timeout = 0;
  5986. c->Request.CDB[0] = HPSA_CISS_READ;
  5987. c->Request.CDB[1] = cmd;
  5988. c->Request.CDB[6] = (size >> 24) & 0xFF; /* MSB */
  5989. c->Request.CDB[7] = (size >> 16) & 0xFF;
  5990. c->Request.CDB[8] = (size >> 8) & 0xFF;
  5991. c->Request.CDB[9] = size & 0xFF;
  5992. break;
  5993. case BMIC_SENSE_CONTROLLER_PARAMETERS:
  5994. c->Request.CDBLen = 10;
  5995. c->Request.type_attr_dir =
  5996. TYPE_ATTR_DIR(cmd_type, ATTR_SIMPLE, XFER_READ);
  5997. c->Request.Timeout = 0;
  5998. c->Request.CDB[0] = BMIC_READ;
  5999. c->Request.CDB[6] = BMIC_SENSE_CONTROLLER_PARAMETERS;
  6000. c->Request.CDB[7] = (size >> 16) & 0xFF;
  6001. c->Request.CDB[8] = (size >> 8) & 0xFF;
  6002. break;
  6003. case BMIC_IDENTIFY_PHYSICAL_DEVICE:
  6004. c->Request.CDBLen = 10;
  6005. c->Request.type_attr_dir =
  6006. TYPE_ATTR_DIR(cmd_type, ATTR_SIMPLE, XFER_READ);
  6007. c->Request.Timeout = 0;
  6008. c->Request.CDB[0] = BMIC_READ;
  6009. c->Request.CDB[6] = BMIC_IDENTIFY_PHYSICAL_DEVICE;
  6010. c->Request.CDB[7] = (size >> 16) & 0xFF;
  6011. c->Request.CDB[8] = (size >> 8) & 0XFF;
  6012. break;
  6013. case BMIC_SENSE_SUBSYSTEM_INFORMATION:
  6014. c->Request.CDBLen = 10;
  6015. c->Request.type_attr_dir =
  6016. TYPE_ATTR_DIR(cmd_type, ATTR_SIMPLE, XFER_READ);
  6017. c->Request.Timeout = 0;
  6018. c->Request.CDB[0] = BMIC_READ;
  6019. c->Request.CDB[6] = BMIC_SENSE_SUBSYSTEM_INFORMATION;
  6020. c->Request.CDB[7] = (size >> 16) & 0xFF;
  6021. c->Request.CDB[8] = (size >> 8) & 0XFF;
  6022. break;
  6023. case BMIC_IDENTIFY_CONTROLLER:
  6024. c->Request.CDBLen = 10;
  6025. c->Request.type_attr_dir =
  6026. TYPE_ATTR_DIR(cmd_type, ATTR_SIMPLE, XFER_READ);
  6027. c->Request.Timeout = 0;
  6028. c->Request.CDB[0] = BMIC_READ;
  6029. c->Request.CDB[1] = 0;
  6030. c->Request.CDB[2] = 0;
  6031. c->Request.CDB[3] = 0;
  6032. c->Request.CDB[4] = 0;
  6033. c->Request.CDB[5] = 0;
  6034. c->Request.CDB[6] = BMIC_IDENTIFY_CONTROLLER;
  6035. c->Request.CDB[7] = (size >> 16) & 0xFF;
  6036. c->Request.CDB[8] = (size >> 8) & 0XFF;
  6037. c->Request.CDB[9] = 0;
  6038. break;
  6039. default:
  6040. dev_warn(&h->pdev->dev, "unknown command 0x%c\n", cmd);
  6041. BUG();
  6042. return -1;
  6043. }
  6044. } else if (cmd_type == TYPE_MSG) {
  6045. switch (cmd) {
  6046. case HPSA_PHYS_TARGET_RESET:
  6047. c->Request.CDBLen = 16;
  6048. c->Request.type_attr_dir =
  6049. TYPE_ATTR_DIR(cmd_type, ATTR_SIMPLE, XFER_NONE);
  6050. c->Request.Timeout = 0; /* Don't time out */
  6051. memset(&c->Request.CDB[0], 0, sizeof(c->Request.CDB));
  6052. c->Request.CDB[0] = HPSA_RESET;
  6053. c->Request.CDB[1] = HPSA_TARGET_RESET_TYPE;
  6054. /* Physical target reset needs no control bytes 4-7*/
  6055. c->Request.CDB[4] = 0x00;
  6056. c->Request.CDB[5] = 0x00;
  6057. c->Request.CDB[6] = 0x00;
  6058. c->Request.CDB[7] = 0x00;
  6059. break;
  6060. case HPSA_DEVICE_RESET_MSG:
  6061. c->Request.CDBLen = 16;
  6062. c->Request.type_attr_dir =
  6063. TYPE_ATTR_DIR(cmd_type, ATTR_SIMPLE, XFER_NONE);
  6064. c->Request.Timeout = 0; /* Don't time out */
  6065. memset(&c->Request.CDB[0], 0, sizeof(c->Request.CDB));
  6066. c->Request.CDB[0] = cmd;
  6067. c->Request.CDB[1] = HPSA_RESET_TYPE_LUN;
  6068. /* If bytes 4-7 are zero, it means reset the */
  6069. /* LunID device */
  6070. c->Request.CDB[4] = 0x00;
  6071. c->Request.CDB[5] = 0x00;
  6072. c->Request.CDB[6] = 0x00;
  6073. c->Request.CDB[7] = 0x00;
  6074. break;
  6075. case HPSA_ABORT_MSG:
  6076. memcpy(&tag, buff, sizeof(tag));
  6077. dev_dbg(&h->pdev->dev,
  6078. "Abort Tag:0x%016llx using rqst Tag:0x%016llx",
  6079. tag, c->Header.tag);
  6080. c->Request.CDBLen = 16;
  6081. c->Request.type_attr_dir =
  6082. TYPE_ATTR_DIR(cmd_type,
  6083. ATTR_SIMPLE, XFER_WRITE);
  6084. c->Request.Timeout = 0; /* Don't time out */
  6085. c->Request.CDB[0] = HPSA_TASK_MANAGEMENT;
  6086. c->Request.CDB[1] = HPSA_TMF_ABORT_TASK;
  6087. c->Request.CDB[2] = 0x00; /* reserved */
  6088. c->Request.CDB[3] = 0x00; /* reserved */
  6089. /* Tag to abort goes in CDB[4]-CDB[11] */
  6090. memcpy(&c->Request.CDB[4], &tag, sizeof(tag));
  6091. c->Request.CDB[12] = 0x00; /* reserved */
  6092. c->Request.CDB[13] = 0x00; /* reserved */
  6093. c->Request.CDB[14] = 0x00; /* reserved */
  6094. c->Request.CDB[15] = 0x00; /* reserved */
  6095. break;
  6096. default:
  6097. dev_warn(&h->pdev->dev, "unknown message type %d\n",
  6098. cmd);
  6099. BUG();
  6100. }
  6101. } else {
  6102. dev_warn(&h->pdev->dev, "unknown command type %d\n", cmd_type);
  6103. BUG();
  6104. }
  6105. switch (GET_DIR(c->Request.type_attr_dir)) {
  6106. case XFER_READ:
  6107. pci_dir = PCI_DMA_FROMDEVICE;
  6108. break;
  6109. case XFER_WRITE:
  6110. pci_dir = PCI_DMA_TODEVICE;
  6111. break;
  6112. case XFER_NONE:
  6113. pci_dir = PCI_DMA_NONE;
  6114. break;
  6115. default:
  6116. pci_dir = PCI_DMA_BIDIRECTIONAL;
  6117. }
  6118. if (hpsa_map_one(h->pdev, c, buff, size, pci_dir))
  6119. return -1;
  6120. return 0;
  6121. }
  6122. /*
  6123. * Map (physical) PCI mem into (virtual) kernel space
  6124. */
  6125. static void __iomem *remap_pci_mem(ulong base, ulong size)
  6126. {
  6127. ulong page_base = ((ulong) base) & PAGE_MASK;
  6128. ulong page_offs = ((ulong) base) - page_base;
  6129. void __iomem *page_remapped = ioremap_nocache(page_base,
  6130. page_offs + size);
  6131. return page_remapped ? (page_remapped + page_offs) : NULL;
  6132. }
  6133. static inline unsigned long get_next_completion(struct ctlr_info *h, u8 q)
  6134. {
  6135. return h->access.command_completed(h, q);
  6136. }
  6137. static inline bool interrupt_pending(struct ctlr_info *h)
  6138. {
  6139. return h->access.intr_pending(h);
  6140. }
  6141. static inline long interrupt_not_for_us(struct ctlr_info *h)
  6142. {
  6143. return (h->access.intr_pending(h) == 0) ||
  6144. (h->interrupts_enabled == 0);
  6145. }
  6146. static inline int bad_tag(struct ctlr_info *h, u32 tag_index,
  6147. u32 raw_tag)
  6148. {
  6149. if (unlikely(tag_index >= h->nr_cmds)) {
  6150. dev_warn(&h->pdev->dev, "bad tag 0x%08x ignored.\n", raw_tag);
  6151. return 1;
  6152. }
  6153. return 0;
  6154. }
  6155. static inline void finish_cmd(struct CommandList *c)
  6156. {
  6157. dial_up_lockup_detection_on_fw_flash_complete(c->h, c);
  6158. if (likely(c->cmd_type == CMD_IOACCEL1 || c->cmd_type == CMD_SCSI
  6159. || c->cmd_type == CMD_IOACCEL2))
  6160. complete_scsi_command(c);
  6161. else if (c->cmd_type == CMD_IOCTL_PEND || c->cmd_type == IOACCEL2_TMF)
  6162. complete(c->waiting);
  6163. }
  6164. /* process completion of an indexed ("direct lookup") command */
  6165. static inline void process_indexed_cmd(struct ctlr_info *h,
  6166. u32 raw_tag)
  6167. {
  6168. u32 tag_index;
  6169. struct CommandList *c;
  6170. tag_index = raw_tag >> DIRECT_LOOKUP_SHIFT;
  6171. if (!bad_tag(h, tag_index, raw_tag)) {
  6172. c = h->cmd_pool + tag_index;
  6173. finish_cmd(c);
  6174. }
  6175. }
  6176. /* Some controllers, like p400, will give us one interrupt
  6177. * after a soft reset, even if we turned interrupts off.
  6178. * Only need to check for this in the hpsa_xxx_discard_completions
  6179. * functions.
  6180. */
  6181. static int ignore_bogus_interrupt(struct ctlr_info *h)
  6182. {
  6183. if (likely(!reset_devices))
  6184. return 0;
  6185. if (likely(h->interrupts_enabled))
  6186. return 0;
  6187. dev_info(&h->pdev->dev, "Received interrupt while interrupts disabled "
  6188. "(known firmware bug.) Ignoring.\n");
  6189. return 1;
  6190. }
  6191. /*
  6192. * Convert &h->q[x] (passed to interrupt handlers) back to h.
  6193. * Relies on (h-q[x] == x) being true for x such that
  6194. * 0 <= x < MAX_REPLY_QUEUES.
  6195. */
  6196. static struct ctlr_info *queue_to_hba(u8 *queue)
  6197. {
  6198. return container_of((queue - *queue), struct ctlr_info, q[0]);
  6199. }
  6200. static irqreturn_t hpsa_intx_discard_completions(int irq, void *queue)
  6201. {
  6202. struct ctlr_info *h = queue_to_hba(queue);
  6203. u8 q = *(u8 *) queue;
  6204. u32 raw_tag;
  6205. if (ignore_bogus_interrupt(h))
  6206. return IRQ_NONE;
  6207. if (interrupt_not_for_us(h))
  6208. return IRQ_NONE;
  6209. h->last_intr_timestamp = get_jiffies_64();
  6210. while (interrupt_pending(h)) {
  6211. raw_tag = get_next_completion(h, q);
  6212. while (raw_tag != FIFO_EMPTY)
  6213. raw_tag = next_command(h, q);
  6214. }
  6215. return IRQ_HANDLED;
  6216. }
  6217. static irqreturn_t hpsa_msix_discard_completions(int irq, void *queue)
  6218. {
  6219. struct ctlr_info *h = queue_to_hba(queue);
  6220. u32 raw_tag;
  6221. u8 q = *(u8 *) queue;
  6222. if (ignore_bogus_interrupt(h))
  6223. return IRQ_NONE;
  6224. h->last_intr_timestamp = get_jiffies_64();
  6225. raw_tag = get_next_completion(h, q);
  6226. while (raw_tag != FIFO_EMPTY)
  6227. raw_tag = next_command(h, q);
  6228. return IRQ_HANDLED;
  6229. }
  6230. static irqreturn_t do_hpsa_intr_intx(int irq, void *queue)
  6231. {
  6232. struct ctlr_info *h = queue_to_hba((u8 *) queue);
  6233. u32 raw_tag;
  6234. u8 q = *(u8 *) queue;
  6235. if (interrupt_not_for_us(h))
  6236. return IRQ_NONE;
  6237. h->last_intr_timestamp = get_jiffies_64();
  6238. while (interrupt_pending(h)) {
  6239. raw_tag = get_next_completion(h, q);
  6240. while (raw_tag != FIFO_EMPTY) {
  6241. process_indexed_cmd(h, raw_tag);
  6242. raw_tag = next_command(h, q);
  6243. }
  6244. }
  6245. return IRQ_HANDLED;
  6246. }
  6247. static irqreturn_t do_hpsa_intr_msi(int irq, void *queue)
  6248. {
  6249. struct ctlr_info *h = queue_to_hba(queue);
  6250. u32 raw_tag;
  6251. u8 q = *(u8 *) queue;
  6252. h->last_intr_timestamp = get_jiffies_64();
  6253. raw_tag = get_next_completion(h, q);
  6254. while (raw_tag != FIFO_EMPTY) {
  6255. process_indexed_cmd(h, raw_tag);
  6256. raw_tag = next_command(h, q);
  6257. }
  6258. return IRQ_HANDLED;
  6259. }
  6260. /* Send a message CDB to the firmware. Careful, this only works
  6261. * in simple mode, not performant mode due to the tag lookup.
  6262. * We only ever use this immediately after a controller reset.
  6263. */
  6264. static int hpsa_message(struct pci_dev *pdev, unsigned char opcode,
  6265. unsigned char type)
  6266. {
  6267. struct Command {
  6268. struct CommandListHeader CommandHeader;
  6269. struct RequestBlock Request;
  6270. struct ErrDescriptor ErrorDescriptor;
  6271. };
  6272. struct Command *cmd;
  6273. static const size_t cmd_sz = sizeof(*cmd) +
  6274. sizeof(cmd->ErrorDescriptor);
  6275. dma_addr_t paddr64;
  6276. __le32 paddr32;
  6277. u32 tag;
  6278. void __iomem *vaddr;
  6279. int i, err;
  6280. vaddr = pci_ioremap_bar(pdev, 0);
  6281. if (vaddr == NULL)
  6282. return -ENOMEM;
  6283. /* The Inbound Post Queue only accepts 32-bit physical addresses for the
  6284. * CCISS commands, so they must be allocated from the lower 4GiB of
  6285. * memory.
  6286. */
  6287. err = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
  6288. if (err) {
  6289. iounmap(vaddr);
  6290. return err;
  6291. }
  6292. cmd = pci_alloc_consistent(pdev, cmd_sz, &paddr64);
  6293. if (cmd == NULL) {
  6294. iounmap(vaddr);
  6295. return -ENOMEM;
  6296. }
  6297. /* This must fit, because of the 32-bit consistent DMA mask. Also,
  6298. * although there's no guarantee, we assume that the address is at
  6299. * least 4-byte aligned (most likely, it's page-aligned).
  6300. */
  6301. paddr32 = cpu_to_le32(paddr64);
  6302. cmd->CommandHeader.ReplyQueue = 0;
  6303. cmd->CommandHeader.SGList = 0;
  6304. cmd->CommandHeader.SGTotal = cpu_to_le16(0);
  6305. cmd->CommandHeader.tag = cpu_to_le64(paddr64);
  6306. memset(&cmd->CommandHeader.LUN.LunAddrBytes, 0, 8);
  6307. cmd->Request.CDBLen = 16;
  6308. cmd->Request.type_attr_dir =
  6309. TYPE_ATTR_DIR(TYPE_MSG, ATTR_HEADOFQUEUE, XFER_NONE);
  6310. cmd->Request.Timeout = 0; /* Don't time out */
  6311. cmd->Request.CDB[0] = opcode;
  6312. cmd->Request.CDB[1] = type;
  6313. memset(&cmd->Request.CDB[2], 0, 14); /* rest of the CDB is reserved */
  6314. cmd->ErrorDescriptor.Addr =
  6315. cpu_to_le64((le32_to_cpu(paddr32) + sizeof(*cmd)));
  6316. cmd->ErrorDescriptor.Len = cpu_to_le32(sizeof(struct ErrorInfo));
  6317. writel(le32_to_cpu(paddr32), vaddr + SA5_REQUEST_PORT_OFFSET);
  6318. for (i = 0; i < HPSA_MSG_SEND_RETRY_LIMIT; i++) {
  6319. tag = readl(vaddr + SA5_REPLY_PORT_OFFSET);
  6320. if ((tag & ~HPSA_SIMPLE_ERROR_BITS) == paddr64)
  6321. break;
  6322. msleep(HPSA_MSG_SEND_RETRY_INTERVAL_MSECS);
  6323. }
  6324. iounmap(vaddr);
  6325. /* we leak the DMA buffer here ... no choice since the controller could
  6326. * still complete the command.
  6327. */
  6328. if (i == HPSA_MSG_SEND_RETRY_LIMIT) {
  6329. dev_err(&pdev->dev, "controller message %02x:%02x timed out\n",
  6330. opcode, type);
  6331. return -ETIMEDOUT;
  6332. }
  6333. pci_free_consistent(pdev, cmd_sz, cmd, paddr64);
  6334. if (tag & HPSA_ERROR_BIT) {
  6335. dev_err(&pdev->dev, "controller message %02x:%02x failed\n",
  6336. opcode, type);
  6337. return -EIO;
  6338. }
  6339. dev_info(&pdev->dev, "controller message %02x:%02x succeeded\n",
  6340. opcode, type);
  6341. return 0;
  6342. }
  6343. #define hpsa_noop(p) hpsa_message(p, 3, 0)
  6344. static int hpsa_controller_hard_reset(struct pci_dev *pdev,
  6345. void __iomem *vaddr, u32 use_doorbell)
  6346. {
  6347. if (use_doorbell) {
  6348. /* For everything after the P600, the PCI power state method
  6349. * of resetting the controller doesn't work, so we have this
  6350. * other way using the doorbell register.
  6351. */
  6352. dev_info(&pdev->dev, "using doorbell to reset controller\n");
  6353. writel(use_doorbell, vaddr + SA5_DOORBELL);
  6354. /* PMC hardware guys tell us we need a 10 second delay after
  6355. * doorbell reset and before any attempt to talk to the board
  6356. * at all to ensure that this actually works and doesn't fall
  6357. * over in some weird corner cases.
  6358. */
  6359. msleep(10000);
  6360. } else { /* Try to do it the PCI power state way */
  6361. /* Quoting from the Open CISS Specification: "The Power
  6362. * Management Control/Status Register (CSR) controls the power
  6363. * state of the device. The normal operating state is D0,
  6364. * CSR=00h. The software off state is D3, CSR=03h. To reset
  6365. * the controller, place the interface device in D3 then to D0,
  6366. * this causes a secondary PCI reset which will reset the
  6367. * controller." */
  6368. int rc = 0;
  6369. dev_info(&pdev->dev, "using PCI PM to reset controller\n");
  6370. /* enter the D3hot power management state */
  6371. rc = pci_set_power_state(pdev, PCI_D3hot);
  6372. if (rc)
  6373. return rc;
  6374. msleep(500);
  6375. /* enter the D0 power management state */
  6376. rc = pci_set_power_state(pdev, PCI_D0);
  6377. if (rc)
  6378. return rc;
  6379. /*
  6380. * The P600 requires a small delay when changing states.
  6381. * Otherwise we may think the board did not reset and we bail.
  6382. * This for kdump only and is particular to the P600.
  6383. */
  6384. msleep(500);
  6385. }
  6386. return 0;
  6387. }
  6388. static void init_driver_version(char *driver_version, int len)
  6389. {
  6390. memset(driver_version, 0, len);
  6391. strncpy(driver_version, HPSA " " HPSA_DRIVER_VERSION, len - 1);
  6392. }
  6393. static int write_driver_ver_to_cfgtable(struct CfgTable __iomem *cfgtable)
  6394. {
  6395. char *driver_version;
  6396. int i, size = sizeof(cfgtable->driver_version);
  6397. driver_version = kmalloc(size, GFP_KERNEL);
  6398. if (!driver_version)
  6399. return -ENOMEM;
  6400. init_driver_version(driver_version, size);
  6401. for (i = 0; i < size; i++)
  6402. writeb(driver_version[i], &cfgtable->driver_version[i]);
  6403. kfree(driver_version);
  6404. return 0;
  6405. }
  6406. static void read_driver_ver_from_cfgtable(struct CfgTable __iomem *cfgtable,
  6407. unsigned char *driver_ver)
  6408. {
  6409. int i;
  6410. for (i = 0; i < sizeof(cfgtable->driver_version); i++)
  6411. driver_ver[i] = readb(&cfgtable->driver_version[i]);
  6412. }
  6413. static int controller_reset_failed(struct CfgTable __iomem *cfgtable)
  6414. {
  6415. char *driver_ver, *old_driver_ver;
  6416. int rc, size = sizeof(cfgtable->driver_version);
  6417. old_driver_ver = kmalloc(2 * size, GFP_KERNEL);
  6418. if (!old_driver_ver)
  6419. return -ENOMEM;
  6420. driver_ver = old_driver_ver + size;
  6421. /* After a reset, the 32 bytes of "driver version" in the cfgtable
  6422. * should have been changed, otherwise we know the reset failed.
  6423. */
  6424. init_driver_version(old_driver_ver, size);
  6425. read_driver_ver_from_cfgtable(cfgtable, driver_ver);
  6426. rc = !memcmp(driver_ver, old_driver_ver, size);
  6427. kfree(old_driver_ver);
  6428. return rc;
  6429. }
  6430. /* This does a hard reset of the controller using PCI power management
  6431. * states or the using the doorbell register.
  6432. */
  6433. static int hpsa_kdump_hard_reset_controller(struct pci_dev *pdev, u32 board_id)
  6434. {
  6435. u64 cfg_offset;
  6436. u32 cfg_base_addr;
  6437. u64 cfg_base_addr_index;
  6438. void __iomem *vaddr;
  6439. unsigned long paddr;
  6440. u32 misc_fw_support;
  6441. int rc;
  6442. struct CfgTable __iomem *cfgtable;
  6443. u32 use_doorbell;
  6444. u16 command_register;
  6445. /* For controllers as old as the P600, this is very nearly
  6446. * the same thing as
  6447. *
  6448. * pci_save_state(pci_dev);
  6449. * pci_set_power_state(pci_dev, PCI_D3hot);
  6450. * pci_set_power_state(pci_dev, PCI_D0);
  6451. * pci_restore_state(pci_dev);
  6452. *
  6453. * For controllers newer than the P600, the pci power state
  6454. * method of resetting doesn't work so we have another way
  6455. * using the doorbell register.
  6456. */
  6457. if (!ctlr_is_resettable(board_id)) {
  6458. dev_warn(&pdev->dev, "Controller not resettable\n");
  6459. return -ENODEV;
  6460. }
  6461. /* if controller is soft- but not hard resettable... */
  6462. if (!ctlr_is_hard_resettable(board_id))
  6463. return -ENOTSUPP; /* try soft reset later. */
  6464. /* Save the PCI command register */
  6465. pci_read_config_word(pdev, 4, &command_register);
  6466. pci_save_state(pdev);
  6467. /* find the first memory BAR, so we can find the cfg table */
  6468. rc = hpsa_pci_find_memory_BAR(pdev, &paddr);
  6469. if (rc)
  6470. return rc;
  6471. vaddr = remap_pci_mem(paddr, 0x250);
  6472. if (!vaddr)
  6473. return -ENOMEM;
  6474. /* find cfgtable in order to check if reset via doorbell is supported */
  6475. rc = hpsa_find_cfg_addrs(pdev, vaddr, &cfg_base_addr,
  6476. &cfg_base_addr_index, &cfg_offset);
  6477. if (rc)
  6478. goto unmap_vaddr;
  6479. cfgtable = remap_pci_mem(pci_resource_start(pdev,
  6480. cfg_base_addr_index) + cfg_offset, sizeof(*cfgtable));
  6481. if (!cfgtable) {
  6482. rc = -ENOMEM;
  6483. goto unmap_vaddr;
  6484. }
  6485. rc = write_driver_ver_to_cfgtable(cfgtable);
  6486. if (rc)
  6487. goto unmap_cfgtable;
  6488. /* If reset via doorbell register is supported, use that.
  6489. * There are two such methods. Favor the newest method.
  6490. */
  6491. misc_fw_support = readl(&cfgtable->misc_fw_support);
  6492. use_doorbell = misc_fw_support & MISC_FW_DOORBELL_RESET2;
  6493. if (use_doorbell) {
  6494. use_doorbell = DOORBELL_CTLR_RESET2;
  6495. } else {
  6496. use_doorbell = misc_fw_support & MISC_FW_DOORBELL_RESET;
  6497. if (use_doorbell) {
  6498. dev_warn(&pdev->dev,
  6499. "Soft reset not supported. Firmware update is required.\n");
  6500. rc = -ENOTSUPP; /* try soft reset */
  6501. goto unmap_cfgtable;
  6502. }
  6503. }
  6504. rc = hpsa_controller_hard_reset(pdev, vaddr, use_doorbell);
  6505. if (rc)
  6506. goto unmap_cfgtable;
  6507. pci_restore_state(pdev);
  6508. pci_write_config_word(pdev, 4, command_register);
  6509. /* Some devices (notably the HP Smart Array 5i Controller)
  6510. need a little pause here */
  6511. msleep(HPSA_POST_RESET_PAUSE_MSECS);
  6512. rc = hpsa_wait_for_board_state(pdev, vaddr, BOARD_READY);
  6513. if (rc) {
  6514. dev_warn(&pdev->dev,
  6515. "Failed waiting for board to become ready after hard reset\n");
  6516. goto unmap_cfgtable;
  6517. }
  6518. rc = controller_reset_failed(vaddr);
  6519. if (rc < 0)
  6520. goto unmap_cfgtable;
  6521. if (rc) {
  6522. dev_warn(&pdev->dev, "Unable to successfully reset "
  6523. "controller. Will try soft reset.\n");
  6524. rc = -ENOTSUPP;
  6525. } else {
  6526. dev_info(&pdev->dev, "board ready after hard reset.\n");
  6527. }
  6528. unmap_cfgtable:
  6529. iounmap(cfgtable);
  6530. unmap_vaddr:
  6531. iounmap(vaddr);
  6532. return rc;
  6533. }
  6534. /*
  6535. * We cannot read the structure directly, for portability we must use
  6536. * the io functions.
  6537. * This is for debug only.
  6538. */
  6539. static void print_cfg_table(struct device *dev, struct CfgTable __iomem *tb)
  6540. {
  6541. #ifdef HPSA_DEBUG
  6542. int i;
  6543. char temp_name[17];
  6544. dev_info(dev, "Controller Configuration information\n");
  6545. dev_info(dev, "------------------------------------\n");
  6546. for (i = 0; i < 4; i++)
  6547. temp_name[i] = readb(&(tb->Signature[i]));
  6548. temp_name[4] = '\0';
  6549. dev_info(dev, " Signature = %s\n", temp_name);
  6550. dev_info(dev, " Spec Number = %d\n", readl(&(tb->SpecValence)));
  6551. dev_info(dev, " Transport methods supported = 0x%x\n",
  6552. readl(&(tb->TransportSupport)));
  6553. dev_info(dev, " Transport methods active = 0x%x\n",
  6554. readl(&(tb->TransportActive)));
  6555. dev_info(dev, " Requested transport Method = 0x%x\n",
  6556. readl(&(tb->HostWrite.TransportRequest)));
  6557. dev_info(dev, " Coalesce Interrupt Delay = 0x%x\n",
  6558. readl(&(tb->HostWrite.CoalIntDelay)));
  6559. dev_info(dev, " Coalesce Interrupt Count = 0x%x\n",
  6560. readl(&(tb->HostWrite.CoalIntCount)));
  6561. dev_info(dev, " Max outstanding commands = %d\n",
  6562. readl(&(tb->CmdsOutMax)));
  6563. dev_info(dev, " Bus Types = 0x%x\n", readl(&(tb->BusTypes)));
  6564. for (i = 0; i < 16; i++)
  6565. temp_name[i] = readb(&(tb->ServerName[i]));
  6566. temp_name[16] = '\0';
  6567. dev_info(dev, " Server Name = %s\n", temp_name);
  6568. dev_info(dev, " Heartbeat Counter = 0x%x\n\n\n",
  6569. readl(&(tb->HeartBeat)));
  6570. #endif /* HPSA_DEBUG */
  6571. }
  6572. static int find_PCI_BAR_index(struct pci_dev *pdev, unsigned long pci_bar_addr)
  6573. {
  6574. int i, offset, mem_type, bar_type;
  6575. if (pci_bar_addr == PCI_BASE_ADDRESS_0) /* looking for BAR zero? */
  6576. return 0;
  6577. offset = 0;
  6578. for (i = 0; i < DEVICE_COUNT_RESOURCE; i++) {
  6579. bar_type = pci_resource_flags(pdev, i) & PCI_BASE_ADDRESS_SPACE;
  6580. if (bar_type == PCI_BASE_ADDRESS_SPACE_IO)
  6581. offset += 4;
  6582. else {
  6583. mem_type = pci_resource_flags(pdev, i) &
  6584. PCI_BASE_ADDRESS_MEM_TYPE_MASK;
  6585. switch (mem_type) {
  6586. case PCI_BASE_ADDRESS_MEM_TYPE_32:
  6587. case PCI_BASE_ADDRESS_MEM_TYPE_1M:
  6588. offset += 4; /* 32 bit */
  6589. break;
  6590. case PCI_BASE_ADDRESS_MEM_TYPE_64:
  6591. offset += 8;
  6592. break;
  6593. default: /* reserved in PCI 2.2 */
  6594. dev_warn(&pdev->dev,
  6595. "base address is invalid\n");
  6596. return -1;
  6597. break;
  6598. }
  6599. }
  6600. if (offset == pci_bar_addr - PCI_BASE_ADDRESS_0)
  6601. return i + 1;
  6602. }
  6603. return -1;
  6604. }
  6605. static void hpsa_disable_interrupt_mode(struct ctlr_info *h)
  6606. {
  6607. if (h->msix_vector) {
  6608. if (h->pdev->msix_enabled)
  6609. pci_disable_msix(h->pdev);
  6610. h->msix_vector = 0;
  6611. } else if (h->msi_vector) {
  6612. if (h->pdev->msi_enabled)
  6613. pci_disable_msi(h->pdev);
  6614. h->msi_vector = 0;
  6615. }
  6616. }
  6617. /* If MSI/MSI-X is supported by the kernel we will try to enable it on
  6618. * controllers that are capable. If not, we use legacy INTx mode.
  6619. */
  6620. static void hpsa_interrupt_mode(struct ctlr_info *h)
  6621. {
  6622. #ifdef CONFIG_PCI_MSI
  6623. int err, i;
  6624. struct msix_entry hpsa_msix_entries[MAX_REPLY_QUEUES];
  6625. for (i = 0; i < MAX_REPLY_QUEUES; i++) {
  6626. hpsa_msix_entries[i].vector = 0;
  6627. hpsa_msix_entries[i].entry = i;
  6628. }
  6629. /* Some boards advertise MSI but don't really support it */
  6630. if ((h->board_id == 0x40700E11) || (h->board_id == 0x40800E11) ||
  6631. (h->board_id == 0x40820E11) || (h->board_id == 0x40830E11))
  6632. goto default_int_mode;
  6633. if (pci_find_capability(h->pdev, PCI_CAP_ID_MSIX)) {
  6634. dev_info(&h->pdev->dev, "MSI-X capable controller\n");
  6635. h->msix_vector = MAX_REPLY_QUEUES;
  6636. if (h->msix_vector > num_online_cpus())
  6637. h->msix_vector = num_online_cpus();
  6638. err = pci_enable_msix_range(h->pdev, hpsa_msix_entries,
  6639. 1, h->msix_vector);
  6640. if (err < 0) {
  6641. dev_warn(&h->pdev->dev, "MSI-X init failed %d\n", err);
  6642. h->msix_vector = 0;
  6643. goto single_msi_mode;
  6644. } else if (err < h->msix_vector) {
  6645. dev_warn(&h->pdev->dev, "only %d MSI-X vectors "
  6646. "available\n", err);
  6647. }
  6648. h->msix_vector = err;
  6649. for (i = 0; i < h->msix_vector; i++)
  6650. h->intr[i] = hpsa_msix_entries[i].vector;
  6651. return;
  6652. }
  6653. single_msi_mode:
  6654. if (pci_find_capability(h->pdev, PCI_CAP_ID_MSI)) {
  6655. dev_info(&h->pdev->dev, "MSI capable controller\n");
  6656. if (!pci_enable_msi(h->pdev))
  6657. h->msi_vector = 1;
  6658. else
  6659. dev_warn(&h->pdev->dev, "MSI init failed\n");
  6660. }
  6661. default_int_mode:
  6662. #endif /* CONFIG_PCI_MSI */
  6663. /* if we get here we're going to use the default interrupt mode */
  6664. h->intr[h->intr_mode] = h->pdev->irq;
  6665. }
  6666. static int hpsa_lookup_board_id(struct pci_dev *pdev, u32 *board_id)
  6667. {
  6668. int i;
  6669. u32 subsystem_vendor_id, subsystem_device_id;
  6670. subsystem_vendor_id = pdev->subsystem_vendor;
  6671. subsystem_device_id = pdev->subsystem_device;
  6672. *board_id = ((subsystem_device_id << 16) & 0xffff0000) |
  6673. subsystem_vendor_id;
  6674. for (i = 0; i < ARRAY_SIZE(products); i++)
  6675. if (*board_id == products[i].board_id)
  6676. return i;
  6677. if ((subsystem_vendor_id != PCI_VENDOR_ID_HP &&
  6678. subsystem_vendor_id != PCI_VENDOR_ID_COMPAQ) ||
  6679. !hpsa_allow_any) {
  6680. dev_warn(&pdev->dev, "unrecognized board ID: "
  6681. "0x%08x, ignoring.\n", *board_id);
  6682. return -ENODEV;
  6683. }
  6684. return ARRAY_SIZE(products) - 1; /* generic unknown smart array */
  6685. }
  6686. static int hpsa_pci_find_memory_BAR(struct pci_dev *pdev,
  6687. unsigned long *memory_bar)
  6688. {
  6689. int i;
  6690. for (i = 0; i < DEVICE_COUNT_RESOURCE; i++)
  6691. if (pci_resource_flags(pdev, i) & IORESOURCE_MEM) {
  6692. /* addressing mode bits already removed */
  6693. *memory_bar = pci_resource_start(pdev, i);
  6694. dev_dbg(&pdev->dev, "memory BAR = %lx\n",
  6695. *memory_bar);
  6696. return 0;
  6697. }
  6698. dev_warn(&pdev->dev, "no memory BAR found\n");
  6699. return -ENODEV;
  6700. }
  6701. static int hpsa_wait_for_board_state(struct pci_dev *pdev, void __iomem *vaddr,
  6702. int wait_for_ready)
  6703. {
  6704. int i, iterations;
  6705. u32 scratchpad;
  6706. if (wait_for_ready)
  6707. iterations = HPSA_BOARD_READY_ITERATIONS;
  6708. else
  6709. iterations = HPSA_BOARD_NOT_READY_ITERATIONS;
  6710. for (i = 0; i < iterations; i++) {
  6711. scratchpad = readl(vaddr + SA5_SCRATCHPAD_OFFSET);
  6712. if (wait_for_ready) {
  6713. if (scratchpad == HPSA_FIRMWARE_READY)
  6714. return 0;
  6715. } else {
  6716. if (scratchpad != HPSA_FIRMWARE_READY)
  6717. return 0;
  6718. }
  6719. msleep(HPSA_BOARD_READY_POLL_INTERVAL_MSECS);
  6720. }
  6721. dev_warn(&pdev->dev, "board not ready, timed out.\n");
  6722. return -ENODEV;
  6723. }
  6724. static int hpsa_find_cfg_addrs(struct pci_dev *pdev, void __iomem *vaddr,
  6725. u32 *cfg_base_addr, u64 *cfg_base_addr_index,
  6726. u64 *cfg_offset)
  6727. {
  6728. *cfg_base_addr = readl(vaddr + SA5_CTCFG_OFFSET);
  6729. *cfg_offset = readl(vaddr + SA5_CTMEM_OFFSET);
  6730. *cfg_base_addr &= (u32) 0x0000ffff;
  6731. *cfg_base_addr_index = find_PCI_BAR_index(pdev, *cfg_base_addr);
  6732. if (*cfg_base_addr_index == -1) {
  6733. dev_warn(&pdev->dev, "cannot find cfg_base_addr_index\n");
  6734. return -ENODEV;
  6735. }
  6736. return 0;
  6737. }
  6738. static void hpsa_free_cfgtables(struct ctlr_info *h)
  6739. {
  6740. if (h->transtable) {
  6741. iounmap(h->transtable);
  6742. h->transtable = NULL;
  6743. }
  6744. if (h->cfgtable) {
  6745. iounmap(h->cfgtable);
  6746. h->cfgtable = NULL;
  6747. }
  6748. }
  6749. /* Find and map CISS config table and transfer table
  6750. + * several items must be unmapped (freed) later
  6751. + * */
  6752. static int hpsa_find_cfgtables(struct ctlr_info *h)
  6753. {
  6754. u64 cfg_offset;
  6755. u32 cfg_base_addr;
  6756. u64 cfg_base_addr_index;
  6757. u32 trans_offset;
  6758. int rc;
  6759. rc = hpsa_find_cfg_addrs(h->pdev, h->vaddr, &cfg_base_addr,
  6760. &cfg_base_addr_index, &cfg_offset);
  6761. if (rc)
  6762. return rc;
  6763. h->cfgtable = remap_pci_mem(pci_resource_start(h->pdev,
  6764. cfg_base_addr_index) + cfg_offset, sizeof(*h->cfgtable));
  6765. if (!h->cfgtable) {
  6766. dev_err(&h->pdev->dev, "Failed mapping cfgtable\n");
  6767. return -ENOMEM;
  6768. }
  6769. rc = write_driver_ver_to_cfgtable(h->cfgtable);
  6770. if (rc)
  6771. return rc;
  6772. /* Find performant mode table. */
  6773. trans_offset = readl(&h->cfgtable->TransMethodOffset);
  6774. h->transtable = remap_pci_mem(pci_resource_start(h->pdev,
  6775. cfg_base_addr_index)+cfg_offset+trans_offset,
  6776. sizeof(*h->transtable));
  6777. if (!h->transtable) {
  6778. dev_err(&h->pdev->dev, "Failed mapping transfer table\n");
  6779. hpsa_free_cfgtables(h);
  6780. return -ENOMEM;
  6781. }
  6782. return 0;
  6783. }
  6784. static void hpsa_get_max_perf_mode_cmds(struct ctlr_info *h)
  6785. {
  6786. #define MIN_MAX_COMMANDS 16
  6787. BUILD_BUG_ON(MIN_MAX_COMMANDS <= HPSA_NRESERVED_CMDS);
  6788. h->max_commands = readl(&h->cfgtable->MaxPerformantModeCommands);
  6789. /* Limit commands in memory limited kdump scenario. */
  6790. if (reset_devices && h->max_commands > 32)
  6791. h->max_commands = 32;
  6792. if (h->max_commands < MIN_MAX_COMMANDS) {
  6793. dev_warn(&h->pdev->dev,
  6794. "Controller reports max supported commands of %d Using %d instead. Ensure that firmware is up to date.\n",
  6795. h->max_commands,
  6796. MIN_MAX_COMMANDS);
  6797. h->max_commands = MIN_MAX_COMMANDS;
  6798. }
  6799. }
  6800. /* If the controller reports that the total max sg entries is greater than 512,
  6801. * then we know that chained SG blocks work. (Original smart arrays did not
  6802. * support chained SG blocks and would return zero for max sg entries.)
  6803. */
  6804. static int hpsa_supports_chained_sg_blocks(struct ctlr_info *h)
  6805. {
  6806. return h->maxsgentries > 512;
  6807. }
  6808. /* Interrogate the hardware for some limits:
  6809. * max commands, max SG elements without chaining, and with chaining,
  6810. * SG chain block size, etc.
  6811. */
  6812. static void hpsa_find_board_params(struct ctlr_info *h)
  6813. {
  6814. hpsa_get_max_perf_mode_cmds(h);
  6815. h->nr_cmds = h->max_commands;
  6816. h->maxsgentries = readl(&(h->cfgtable->MaxScatterGatherElements));
  6817. h->fw_support = readl(&(h->cfgtable->misc_fw_support));
  6818. if (hpsa_supports_chained_sg_blocks(h)) {
  6819. /* Limit in-command s/g elements to 32 save dma'able memory. */
  6820. h->max_cmd_sg_entries = 32;
  6821. h->chainsize = h->maxsgentries - h->max_cmd_sg_entries;
  6822. h->maxsgentries--; /* save one for chain pointer */
  6823. } else {
  6824. /*
  6825. * Original smart arrays supported at most 31 s/g entries
  6826. * embedded inline in the command (trying to use more
  6827. * would lock up the controller)
  6828. */
  6829. h->max_cmd_sg_entries = 31;
  6830. h->maxsgentries = 31; /* default to traditional values */
  6831. h->chainsize = 0;
  6832. }
  6833. /* Find out what task management functions are supported and cache */
  6834. h->TMFSupportFlags = readl(&(h->cfgtable->TMFSupportFlags));
  6835. if (!(HPSATMF_PHYS_TASK_ABORT & h->TMFSupportFlags))
  6836. dev_warn(&h->pdev->dev, "Physical aborts not supported\n");
  6837. if (!(HPSATMF_LOG_TASK_ABORT & h->TMFSupportFlags))
  6838. dev_warn(&h->pdev->dev, "Logical aborts not supported\n");
  6839. if (!(HPSATMF_IOACCEL_ENABLED & h->TMFSupportFlags))
  6840. dev_warn(&h->pdev->dev, "HP SSD Smart Path aborts not supported\n");
  6841. }
  6842. static inline bool hpsa_CISS_signature_present(struct ctlr_info *h)
  6843. {
  6844. if (!check_signature(h->cfgtable->Signature, "CISS", 4)) {
  6845. dev_err(&h->pdev->dev, "not a valid CISS config table\n");
  6846. return false;
  6847. }
  6848. return true;
  6849. }
  6850. static inline void hpsa_set_driver_support_bits(struct ctlr_info *h)
  6851. {
  6852. u32 driver_support;
  6853. driver_support = readl(&(h->cfgtable->driver_support));
  6854. /* Need to enable prefetch in the SCSI core for 6400 in x86 */
  6855. #ifdef CONFIG_X86
  6856. driver_support |= ENABLE_SCSI_PREFETCH;
  6857. #endif
  6858. driver_support |= ENABLE_UNIT_ATTN;
  6859. writel(driver_support, &(h->cfgtable->driver_support));
  6860. }
  6861. /* Disable DMA prefetch for the P600. Otherwise an ASIC bug may result
  6862. * in a prefetch beyond physical memory.
  6863. */
  6864. static inline void hpsa_p600_dma_prefetch_quirk(struct ctlr_info *h)
  6865. {
  6866. u32 dma_prefetch;
  6867. if (h->board_id != 0x3225103C)
  6868. return;
  6869. dma_prefetch = readl(h->vaddr + I2O_DMA1_CFG);
  6870. dma_prefetch |= 0x8000;
  6871. writel(dma_prefetch, h->vaddr + I2O_DMA1_CFG);
  6872. }
  6873. static int hpsa_wait_for_clear_event_notify_ack(struct ctlr_info *h)
  6874. {
  6875. int i;
  6876. u32 doorbell_value;
  6877. unsigned long flags;
  6878. /* wait until the clear_event_notify bit 6 is cleared by controller. */
  6879. for (i = 0; i < MAX_CLEAR_EVENT_WAIT; i++) {
  6880. spin_lock_irqsave(&h->lock, flags);
  6881. doorbell_value = readl(h->vaddr + SA5_DOORBELL);
  6882. spin_unlock_irqrestore(&h->lock, flags);
  6883. if (!(doorbell_value & DOORBELL_CLEAR_EVENTS))
  6884. goto done;
  6885. /* delay and try again */
  6886. msleep(CLEAR_EVENT_WAIT_INTERVAL);
  6887. }
  6888. return -ENODEV;
  6889. done:
  6890. return 0;
  6891. }
  6892. static int hpsa_wait_for_mode_change_ack(struct ctlr_info *h)
  6893. {
  6894. int i;
  6895. u32 doorbell_value;
  6896. unsigned long flags;
  6897. /* under certain very rare conditions, this can take awhile.
  6898. * (e.g.: hot replace a failed 144GB drive in a RAID 5 set right
  6899. * as we enter this code.)
  6900. */
  6901. for (i = 0; i < MAX_MODE_CHANGE_WAIT; i++) {
  6902. if (h->remove_in_progress)
  6903. goto done;
  6904. spin_lock_irqsave(&h->lock, flags);
  6905. doorbell_value = readl(h->vaddr + SA5_DOORBELL);
  6906. spin_unlock_irqrestore(&h->lock, flags);
  6907. if (!(doorbell_value & CFGTBL_ChangeReq))
  6908. goto done;
  6909. /* delay and try again */
  6910. msleep(MODE_CHANGE_WAIT_INTERVAL);
  6911. }
  6912. return -ENODEV;
  6913. done:
  6914. return 0;
  6915. }
  6916. /* return -ENODEV or other reason on error, 0 on success */
  6917. static int hpsa_enter_simple_mode(struct ctlr_info *h)
  6918. {
  6919. u32 trans_support;
  6920. trans_support = readl(&(h->cfgtable->TransportSupport));
  6921. if (!(trans_support & SIMPLE_MODE))
  6922. return -ENOTSUPP;
  6923. h->max_commands = readl(&(h->cfgtable->CmdsOutMax));
  6924. /* Update the field, and then ring the doorbell */
  6925. writel(CFGTBL_Trans_Simple, &(h->cfgtable->HostWrite.TransportRequest));
  6926. writel(0, &h->cfgtable->HostWrite.command_pool_addr_hi);
  6927. writel(CFGTBL_ChangeReq, h->vaddr + SA5_DOORBELL);
  6928. if (hpsa_wait_for_mode_change_ack(h))
  6929. goto error;
  6930. print_cfg_table(&h->pdev->dev, h->cfgtable);
  6931. if (!(readl(&(h->cfgtable->TransportActive)) & CFGTBL_Trans_Simple))
  6932. goto error;
  6933. h->transMethod = CFGTBL_Trans_Simple;
  6934. return 0;
  6935. error:
  6936. dev_err(&h->pdev->dev, "failed to enter simple mode\n");
  6937. return -ENODEV;
  6938. }
  6939. /* free items allocated or mapped by hpsa_pci_init */
  6940. static void hpsa_free_pci_init(struct ctlr_info *h)
  6941. {
  6942. hpsa_free_cfgtables(h); /* pci_init 4 */
  6943. iounmap(h->vaddr); /* pci_init 3 */
  6944. h->vaddr = NULL;
  6945. hpsa_disable_interrupt_mode(h); /* pci_init 2 */
  6946. /*
  6947. * call pci_disable_device before pci_release_regions per
  6948. * Documentation/PCI/pci.txt
  6949. */
  6950. pci_disable_device(h->pdev); /* pci_init 1 */
  6951. pci_release_regions(h->pdev); /* pci_init 2 */
  6952. }
  6953. /* several items must be freed later */
  6954. static int hpsa_pci_init(struct ctlr_info *h)
  6955. {
  6956. int prod_index, err;
  6957. prod_index = hpsa_lookup_board_id(h->pdev, &h->board_id);
  6958. if (prod_index < 0)
  6959. return prod_index;
  6960. h->product_name = products[prod_index].product_name;
  6961. h->access = *(products[prod_index].access);
  6962. h->needs_abort_tags_swizzled =
  6963. ctlr_needs_abort_tags_swizzled(h->board_id);
  6964. pci_disable_link_state(h->pdev, PCIE_LINK_STATE_L0S |
  6965. PCIE_LINK_STATE_L1 | PCIE_LINK_STATE_CLKPM);
  6966. err = pci_enable_device(h->pdev);
  6967. if (err) {
  6968. dev_err(&h->pdev->dev, "failed to enable PCI device\n");
  6969. pci_disable_device(h->pdev);
  6970. return err;
  6971. }
  6972. err = pci_request_regions(h->pdev, HPSA);
  6973. if (err) {
  6974. dev_err(&h->pdev->dev,
  6975. "failed to obtain PCI resources\n");
  6976. pci_disable_device(h->pdev);
  6977. return err;
  6978. }
  6979. pci_set_master(h->pdev);
  6980. hpsa_interrupt_mode(h);
  6981. err = hpsa_pci_find_memory_BAR(h->pdev, &h->paddr);
  6982. if (err)
  6983. goto clean2; /* intmode+region, pci */
  6984. h->vaddr = remap_pci_mem(h->paddr, 0x250);
  6985. if (!h->vaddr) {
  6986. dev_err(&h->pdev->dev, "failed to remap PCI mem\n");
  6987. err = -ENOMEM;
  6988. goto clean2; /* intmode+region, pci */
  6989. }
  6990. err = hpsa_wait_for_board_state(h->pdev, h->vaddr, BOARD_READY);
  6991. if (err)
  6992. goto clean3; /* vaddr, intmode+region, pci */
  6993. err = hpsa_find_cfgtables(h);
  6994. if (err)
  6995. goto clean3; /* vaddr, intmode+region, pci */
  6996. hpsa_find_board_params(h);
  6997. if (!hpsa_CISS_signature_present(h)) {
  6998. err = -ENODEV;
  6999. goto clean4; /* cfgtables, vaddr, intmode+region, pci */
  7000. }
  7001. hpsa_set_driver_support_bits(h);
  7002. hpsa_p600_dma_prefetch_quirk(h);
  7003. err = hpsa_enter_simple_mode(h);
  7004. if (err)
  7005. goto clean4; /* cfgtables, vaddr, intmode+region, pci */
  7006. return 0;
  7007. clean4: /* cfgtables, vaddr, intmode+region, pci */
  7008. hpsa_free_cfgtables(h);
  7009. clean3: /* vaddr, intmode+region, pci */
  7010. iounmap(h->vaddr);
  7011. h->vaddr = NULL;
  7012. clean2: /* intmode+region, pci */
  7013. hpsa_disable_interrupt_mode(h);
  7014. /*
  7015. * call pci_disable_device before pci_release_regions per
  7016. * Documentation/PCI/pci.txt
  7017. */
  7018. pci_disable_device(h->pdev);
  7019. pci_release_regions(h->pdev);
  7020. return err;
  7021. }
  7022. static void hpsa_hba_inquiry(struct ctlr_info *h)
  7023. {
  7024. int rc;
  7025. #define HBA_INQUIRY_BYTE_COUNT 64
  7026. h->hba_inquiry_data = kmalloc(HBA_INQUIRY_BYTE_COUNT, GFP_KERNEL);
  7027. if (!h->hba_inquiry_data)
  7028. return;
  7029. rc = hpsa_scsi_do_inquiry(h, RAID_CTLR_LUNID, 0,
  7030. h->hba_inquiry_data, HBA_INQUIRY_BYTE_COUNT);
  7031. if (rc != 0) {
  7032. kfree(h->hba_inquiry_data);
  7033. h->hba_inquiry_data = NULL;
  7034. }
  7035. }
  7036. static int hpsa_init_reset_devices(struct pci_dev *pdev, u32 board_id)
  7037. {
  7038. int rc, i;
  7039. void __iomem *vaddr;
  7040. if (!reset_devices)
  7041. return 0;
  7042. /* kdump kernel is loading, we don't know in which state is
  7043. * the pci interface. The dev->enable_cnt is equal zero
  7044. * so we call enable+disable, wait a while and switch it on.
  7045. */
  7046. rc = pci_enable_device(pdev);
  7047. if (rc) {
  7048. dev_warn(&pdev->dev, "Failed to enable PCI device\n");
  7049. return -ENODEV;
  7050. }
  7051. pci_disable_device(pdev);
  7052. msleep(260); /* a randomly chosen number */
  7053. rc = pci_enable_device(pdev);
  7054. if (rc) {
  7055. dev_warn(&pdev->dev, "failed to enable device.\n");
  7056. return -ENODEV;
  7057. }
  7058. pci_set_master(pdev);
  7059. vaddr = pci_ioremap_bar(pdev, 0);
  7060. if (vaddr == NULL) {
  7061. rc = -ENOMEM;
  7062. goto out_disable;
  7063. }
  7064. writel(SA5_INTR_OFF, vaddr + SA5_REPLY_INTR_MASK_OFFSET);
  7065. iounmap(vaddr);
  7066. /* Reset the controller with a PCI power-cycle or via doorbell */
  7067. rc = hpsa_kdump_hard_reset_controller(pdev, board_id);
  7068. /* -ENOTSUPP here means we cannot reset the controller
  7069. * but it's already (and still) up and running in
  7070. * "performant mode". Or, it might be 640x, which can't reset
  7071. * due to concerns about shared bbwc between 6402/6404 pair.
  7072. */
  7073. if (rc)
  7074. goto out_disable;
  7075. /* Now try to get the controller to respond to a no-op */
  7076. dev_info(&pdev->dev, "Waiting for controller to respond to no-op\n");
  7077. for (i = 0; i < HPSA_POST_RESET_NOOP_RETRIES; i++) {
  7078. if (hpsa_noop(pdev) == 0)
  7079. break;
  7080. else
  7081. dev_warn(&pdev->dev, "no-op failed%s\n",
  7082. (i < 11 ? "; re-trying" : ""));
  7083. }
  7084. out_disable:
  7085. pci_disable_device(pdev);
  7086. return rc;
  7087. }
  7088. static void hpsa_free_cmd_pool(struct ctlr_info *h)
  7089. {
  7090. kfree(h->cmd_pool_bits);
  7091. h->cmd_pool_bits = NULL;
  7092. if (h->cmd_pool) {
  7093. pci_free_consistent(h->pdev,
  7094. h->nr_cmds * sizeof(struct CommandList),
  7095. h->cmd_pool,
  7096. h->cmd_pool_dhandle);
  7097. h->cmd_pool = NULL;
  7098. h->cmd_pool_dhandle = 0;
  7099. }
  7100. if (h->errinfo_pool) {
  7101. pci_free_consistent(h->pdev,
  7102. h->nr_cmds * sizeof(struct ErrorInfo),
  7103. h->errinfo_pool,
  7104. h->errinfo_pool_dhandle);
  7105. h->errinfo_pool = NULL;
  7106. h->errinfo_pool_dhandle = 0;
  7107. }
  7108. }
  7109. static int hpsa_alloc_cmd_pool(struct ctlr_info *h)
  7110. {
  7111. h->cmd_pool_bits = kzalloc(
  7112. DIV_ROUND_UP(h->nr_cmds, BITS_PER_LONG) *
  7113. sizeof(unsigned long), GFP_KERNEL);
  7114. h->cmd_pool = pci_alloc_consistent(h->pdev,
  7115. h->nr_cmds * sizeof(*h->cmd_pool),
  7116. &(h->cmd_pool_dhandle));
  7117. h->errinfo_pool = pci_alloc_consistent(h->pdev,
  7118. h->nr_cmds * sizeof(*h->errinfo_pool),
  7119. &(h->errinfo_pool_dhandle));
  7120. if ((h->cmd_pool_bits == NULL)
  7121. || (h->cmd_pool == NULL)
  7122. || (h->errinfo_pool == NULL)) {
  7123. dev_err(&h->pdev->dev, "out of memory in %s", __func__);
  7124. goto clean_up;
  7125. }
  7126. hpsa_preinitialize_commands(h);
  7127. return 0;
  7128. clean_up:
  7129. hpsa_free_cmd_pool(h);
  7130. return -ENOMEM;
  7131. }
  7132. static void hpsa_irq_affinity_hints(struct ctlr_info *h)
  7133. {
  7134. int i, cpu;
  7135. cpu = cpumask_first(cpu_online_mask);
  7136. for (i = 0; i < h->msix_vector; i++) {
  7137. irq_set_affinity_hint(h->intr[i], get_cpu_mask(cpu));
  7138. cpu = cpumask_next(cpu, cpu_online_mask);
  7139. }
  7140. }
  7141. /* clear affinity hints and free MSI-X, MSI, or legacy INTx vectors */
  7142. static void hpsa_free_irqs(struct ctlr_info *h)
  7143. {
  7144. int i;
  7145. if (!h->msix_vector || h->intr_mode != PERF_MODE_INT) {
  7146. /* Single reply queue, only one irq to free */
  7147. i = h->intr_mode;
  7148. irq_set_affinity_hint(h->intr[i], NULL);
  7149. free_irq(h->intr[i], &h->q[i]);
  7150. h->q[i] = 0;
  7151. return;
  7152. }
  7153. for (i = 0; i < h->msix_vector; i++) {
  7154. irq_set_affinity_hint(h->intr[i], NULL);
  7155. free_irq(h->intr[i], &h->q[i]);
  7156. h->q[i] = 0;
  7157. }
  7158. for (; i < MAX_REPLY_QUEUES; i++)
  7159. h->q[i] = 0;
  7160. }
  7161. /* returns 0 on success; cleans up and returns -Enn on error */
  7162. static int hpsa_request_irqs(struct ctlr_info *h,
  7163. irqreturn_t (*msixhandler)(int, void *),
  7164. irqreturn_t (*intxhandler)(int, void *))
  7165. {
  7166. int rc, i;
  7167. /*
  7168. * initialize h->q[x] = x so that interrupt handlers know which
  7169. * queue to process.
  7170. */
  7171. for (i = 0; i < MAX_REPLY_QUEUES; i++)
  7172. h->q[i] = (u8) i;
  7173. if (h->intr_mode == PERF_MODE_INT && h->msix_vector > 0) {
  7174. /* If performant mode and MSI-X, use multiple reply queues */
  7175. for (i = 0; i < h->msix_vector; i++) {
  7176. sprintf(h->intrname[i], "%s-msix%d", h->devname, i);
  7177. rc = request_irq(h->intr[i], msixhandler,
  7178. 0, h->intrname[i],
  7179. &h->q[i]);
  7180. if (rc) {
  7181. int j;
  7182. dev_err(&h->pdev->dev,
  7183. "failed to get irq %d for %s\n",
  7184. h->intr[i], h->devname);
  7185. for (j = 0; j < i; j++) {
  7186. free_irq(h->intr[j], &h->q[j]);
  7187. h->q[j] = 0;
  7188. }
  7189. for (; j < MAX_REPLY_QUEUES; j++)
  7190. h->q[j] = 0;
  7191. return rc;
  7192. }
  7193. }
  7194. hpsa_irq_affinity_hints(h);
  7195. } else {
  7196. /* Use single reply pool */
  7197. if (h->msix_vector > 0 || h->msi_vector) {
  7198. if (h->msix_vector)
  7199. sprintf(h->intrname[h->intr_mode],
  7200. "%s-msix", h->devname);
  7201. else
  7202. sprintf(h->intrname[h->intr_mode],
  7203. "%s-msi", h->devname);
  7204. rc = request_irq(h->intr[h->intr_mode],
  7205. msixhandler, 0,
  7206. h->intrname[h->intr_mode],
  7207. &h->q[h->intr_mode]);
  7208. } else {
  7209. sprintf(h->intrname[h->intr_mode],
  7210. "%s-intx", h->devname);
  7211. rc = request_irq(h->intr[h->intr_mode],
  7212. intxhandler, IRQF_SHARED,
  7213. h->intrname[h->intr_mode],
  7214. &h->q[h->intr_mode]);
  7215. }
  7216. irq_set_affinity_hint(h->intr[h->intr_mode], NULL);
  7217. }
  7218. if (rc) {
  7219. dev_err(&h->pdev->dev, "failed to get irq %d for %s\n",
  7220. h->intr[h->intr_mode], h->devname);
  7221. hpsa_free_irqs(h);
  7222. return -ENODEV;
  7223. }
  7224. return 0;
  7225. }
  7226. static int hpsa_kdump_soft_reset(struct ctlr_info *h)
  7227. {
  7228. int rc;
  7229. hpsa_send_host_reset(h, RAID_CTLR_LUNID, HPSA_RESET_TYPE_CONTROLLER);
  7230. dev_info(&h->pdev->dev, "Waiting for board to soft reset.\n");
  7231. rc = hpsa_wait_for_board_state(h->pdev, h->vaddr, BOARD_NOT_READY);
  7232. if (rc) {
  7233. dev_warn(&h->pdev->dev, "Soft reset had no effect.\n");
  7234. return rc;
  7235. }
  7236. dev_info(&h->pdev->dev, "Board reset, awaiting READY status.\n");
  7237. rc = hpsa_wait_for_board_state(h->pdev, h->vaddr, BOARD_READY);
  7238. if (rc) {
  7239. dev_warn(&h->pdev->dev, "Board failed to become ready "
  7240. "after soft reset.\n");
  7241. return rc;
  7242. }
  7243. return 0;
  7244. }
  7245. static void hpsa_free_reply_queues(struct ctlr_info *h)
  7246. {
  7247. int i;
  7248. for (i = 0; i < h->nreply_queues; i++) {
  7249. if (!h->reply_queue[i].head)
  7250. continue;
  7251. pci_free_consistent(h->pdev,
  7252. h->reply_queue_size,
  7253. h->reply_queue[i].head,
  7254. h->reply_queue[i].busaddr);
  7255. h->reply_queue[i].head = NULL;
  7256. h->reply_queue[i].busaddr = 0;
  7257. }
  7258. h->reply_queue_size = 0;
  7259. }
  7260. static void hpsa_undo_allocations_after_kdump_soft_reset(struct ctlr_info *h)
  7261. {
  7262. hpsa_free_performant_mode(h); /* init_one 7 */
  7263. hpsa_free_sg_chain_blocks(h); /* init_one 6 */
  7264. hpsa_free_cmd_pool(h); /* init_one 5 */
  7265. hpsa_free_irqs(h); /* init_one 4 */
  7266. scsi_host_put(h->scsi_host); /* init_one 3 */
  7267. h->scsi_host = NULL; /* init_one 3 */
  7268. hpsa_free_pci_init(h); /* init_one 2_5 */
  7269. free_percpu(h->lockup_detected); /* init_one 2 */
  7270. h->lockup_detected = NULL; /* init_one 2 */
  7271. if (h->resubmit_wq) {
  7272. destroy_workqueue(h->resubmit_wq); /* init_one 1 */
  7273. h->resubmit_wq = NULL;
  7274. }
  7275. if (h->rescan_ctlr_wq) {
  7276. destroy_workqueue(h->rescan_ctlr_wq);
  7277. h->rescan_ctlr_wq = NULL;
  7278. }
  7279. kfree(h); /* init_one 1 */
  7280. }
  7281. /* Called when controller lockup detected. */
  7282. static void fail_all_outstanding_cmds(struct ctlr_info *h)
  7283. {
  7284. int i, refcount;
  7285. struct CommandList *c;
  7286. int failcount = 0;
  7287. flush_workqueue(h->resubmit_wq); /* ensure all cmds are fully built */
  7288. for (i = 0; i < h->nr_cmds; i++) {
  7289. c = h->cmd_pool + i;
  7290. refcount = atomic_inc_return(&c->refcount);
  7291. if (refcount > 1) {
  7292. c->err_info->CommandStatus = CMD_CTLR_LOCKUP;
  7293. finish_cmd(c);
  7294. atomic_dec(&h->commands_outstanding);
  7295. failcount++;
  7296. }
  7297. cmd_free(h, c);
  7298. }
  7299. dev_warn(&h->pdev->dev,
  7300. "failed %d commands in fail_all\n", failcount);
  7301. }
  7302. static void set_lockup_detected_for_all_cpus(struct ctlr_info *h, u32 value)
  7303. {
  7304. int cpu;
  7305. for_each_online_cpu(cpu) {
  7306. u32 *lockup_detected;
  7307. lockup_detected = per_cpu_ptr(h->lockup_detected, cpu);
  7308. *lockup_detected = value;
  7309. }
  7310. wmb(); /* be sure the per-cpu variables are out to memory */
  7311. }
  7312. static void controller_lockup_detected(struct ctlr_info *h)
  7313. {
  7314. unsigned long flags;
  7315. u32 lockup_detected;
  7316. h->access.set_intr_mask(h, HPSA_INTR_OFF);
  7317. spin_lock_irqsave(&h->lock, flags);
  7318. lockup_detected = readl(h->vaddr + SA5_SCRATCHPAD_OFFSET);
  7319. if (!lockup_detected) {
  7320. /* no heartbeat, but controller gave us a zero. */
  7321. dev_warn(&h->pdev->dev,
  7322. "lockup detected after %d but scratchpad register is zero\n",
  7323. h->heartbeat_sample_interval / HZ);
  7324. lockup_detected = 0xffffffff;
  7325. }
  7326. set_lockup_detected_for_all_cpus(h, lockup_detected);
  7327. spin_unlock_irqrestore(&h->lock, flags);
  7328. dev_warn(&h->pdev->dev, "Controller lockup detected: 0x%08x after %d\n",
  7329. lockup_detected, h->heartbeat_sample_interval / HZ);
  7330. pci_disable_device(h->pdev);
  7331. fail_all_outstanding_cmds(h);
  7332. }
  7333. static int detect_controller_lockup(struct ctlr_info *h)
  7334. {
  7335. u64 now;
  7336. u32 heartbeat;
  7337. unsigned long flags;
  7338. now = get_jiffies_64();
  7339. /* If we've received an interrupt recently, we're ok. */
  7340. if (time_after64(h->last_intr_timestamp +
  7341. (h->heartbeat_sample_interval), now))
  7342. return false;
  7343. /*
  7344. * If we've already checked the heartbeat recently, we're ok.
  7345. * This could happen if someone sends us a signal. We
  7346. * otherwise don't care about signals in this thread.
  7347. */
  7348. if (time_after64(h->last_heartbeat_timestamp +
  7349. (h->heartbeat_sample_interval), now))
  7350. return false;
  7351. /* If heartbeat has not changed since we last looked, we're not ok. */
  7352. spin_lock_irqsave(&h->lock, flags);
  7353. heartbeat = readl(&h->cfgtable->HeartBeat);
  7354. spin_unlock_irqrestore(&h->lock, flags);
  7355. if (h->last_heartbeat == heartbeat) {
  7356. controller_lockup_detected(h);
  7357. return true;
  7358. }
  7359. /* We're ok. */
  7360. h->last_heartbeat = heartbeat;
  7361. h->last_heartbeat_timestamp = now;
  7362. return false;
  7363. }
  7364. static void hpsa_ack_ctlr_events(struct ctlr_info *h)
  7365. {
  7366. int i;
  7367. char *event_type;
  7368. if (!(h->fw_support & MISC_FW_EVENT_NOTIFY))
  7369. return;
  7370. /* Ask the controller to clear the events we're handling. */
  7371. if ((h->transMethod & (CFGTBL_Trans_io_accel1
  7372. | CFGTBL_Trans_io_accel2)) &&
  7373. (h->events & HPSA_EVENT_NOTIFY_ACCEL_IO_PATH_STATE_CHANGE ||
  7374. h->events & HPSA_EVENT_NOTIFY_ACCEL_IO_PATH_CONFIG_CHANGE)) {
  7375. if (h->events & HPSA_EVENT_NOTIFY_ACCEL_IO_PATH_STATE_CHANGE)
  7376. event_type = "state change";
  7377. if (h->events & HPSA_EVENT_NOTIFY_ACCEL_IO_PATH_CONFIG_CHANGE)
  7378. event_type = "configuration change";
  7379. /* Stop sending new RAID offload reqs via the IO accelerator */
  7380. scsi_block_requests(h->scsi_host);
  7381. for (i = 0; i < h->ndevices; i++)
  7382. h->dev[i]->offload_enabled = 0;
  7383. hpsa_drain_accel_commands(h);
  7384. /* Set 'accelerator path config change' bit */
  7385. dev_warn(&h->pdev->dev,
  7386. "Acknowledging event: 0x%08x (HP SSD Smart Path %s)\n",
  7387. h->events, event_type);
  7388. writel(h->events, &(h->cfgtable->clear_event_notify));
  7389. /* Set the "clear event notify field update" bit 6 */
  7390. writel(DOORBELL_CLEAR_EVENTS, h->vaddr + SA5_DOORBELL);
  7391. /* Wait until ctlr clears 'clear event notify field', bit 6 */
  7392. hpsa_wait_for_clear_event_notify_ack(h);
  7393. scsi_unblock_requests(h->scsi_host);
  7394. } else {
  7395. /* Acknowledge controller notification events. */
  7396. writel(h->events, &(h->cfgtable->clear_event_notify));
  7397. writel(DOORBELL_CLEAR_EVENTS, h->vaddr + SA5_DOORBELL);
  7398. hpsa_wait_for_clear_event_notify_ack(h);
  7399. #if 0
  7400. writel(CFGTBL_ChangeReq, h->vaddr + SA5_DOORBELL);
  7401. hpsa_wait_for_mode_change_ack(h);
  7402. #endif
  7403. }
  7404. return;
  7405. }
  7406. /* Check a register on the controller to see if there are configuration
  7407. * changes (added/changed/removed logical drives, etc.) which mean that
  7408. * we should rescan the controller for devices.
  7409. * Also check flag for driver-initiated rescan.
  7410. */
  7411. static int hpsa_ctlr_needs_rescan(struct ctlr_info *h)
  7412. {
  7413. if (h->drv_req_rescan) {
  7414. h->drv_req_rescan = 0;
  7415. return 1;
  7416. }
  7417. if (!(h->fw_support & MISC_FW_EVENT_NOTIFY))
  7418. return 0;
  7419. h->events = readl(&(h->cfgtable->event_notify));
  7420. return h->events & RESCAN_REQUIRED_EVENT_BITS;
  7421. }
  7422. /*
  7423. * Check if any of the offline devices have become ready
  7424. */
  7425. static int hpsa_offline_devices_ready(struct ctlr_info *h)
  7426. {
  7427. unsigned long flags;
  7428. struct offline_device_entry *d;
  7429. struct list_head *this, *tmp;
  7430. spin_lock_irqsave(&h->offline_device_lock, flags);
  7431. list_for_each_safe(this, tmp, &h->offline_device_list) {
  7432. d = list_entry(this, struct offline_device_entry,
  7433. offline_list);
  7434. spin_unlock_irqrestore(&h->offline_device_lock, flags);
  7435. if (!hpsa_volume_offline(h, d->scsi3addr)) {
  7436. spin_lock_irqsave(&h->offline_device_lock, flags);
  7437. list_del(&d->offline_list);
  7438. spin_unlock_irqrestore(&h->offline_device_lock, flags);
  7439. return 1;
  7440. }
  7441. spin_lock_irqsave(&h->offline_device_lock, flags);
  7442. }
  7443. spin_unlock_irqrestore(&h->offline_device_lock, flags);
  7444. return 0;
  7445. }
  7446. static int hpsa_luns_changed(struct ctlr_info *h)
  7447. {
  7448. int rc = 1; /* assume there are changes */
  7449. struct ReportLUNdata *logdev = NULL;
  7450. /* if we can't find out if lun data has changed,
  7451. * assume that it has.
  7452. */
  7453. if (!h->lastlogicals)
  7454. goto out;
  7455. logdev = kzalloc(sizeof(*logdev), GFP_KERNEL);
  7456. if (!logdev) {
  7457. dev_warn(&h->pdev->dev,
  7458. "Out of memory, can't track lun changes.\n");
  7459. goto out;
  7460. }
  7461. if (hpsa_scsi_do_report_luns(h, 1, logdev, sizeof(*logdev), 0)) {
  7462. dev_warn(&h->pdev->dev,
  7463. "report luns failed, can't track lun changes.\n");
  7464. goto out;
  7465. }
  7466. if (memcmp(logdev, h->lastlogicals, sizeof(*logdev))) {
  7467. dev_info(&h->pdev->dev,
  7468. "Lun changes detected.\n");
  7469. memcpy(h->lastlogicals, logdev, sizeof(*logdev));
  7470. goto out;
  7471. } else
  7472. rc = 0; /* no changes detected. */
  7473. out:
  7474. kfree(logdev);
  7475. return rc;
  7476. }
  7477. static void hpsa_rescan_ctlr_worker(struct work_struct *work)
  7478. {
  7479. unsigned long flags;
  7480. struct ctlr_info *h = container_of(to_delayed_work(work),
  7481. struct ctlr_info, rescan_ctlr_work);
  7482. if (h->remove_in_progress)
  7483. return;
  7484. if (hpsa_ctlr_needs_rescan(h) || hpsa_offline_devices_ready(h)) {
  7485. scsi_host_get(h->scsi_host);
  7486. hpsa_ack_ctlr_events(h);
  7487. hpsa_scan_start(h->scsi_host);
  7488. scsi_host_put(h->scsi_host);
  7489. } else if (h->discovery_polling) {
  7490. hpsa_disable_rld_caching(h);
  7491. if (hpsa_luns_changed(h)) {
  7492. struct Scsi_Host *sh = NULL;
  7493. dev_info(&h->pdev->dev,
  7494. "driver discovery polling rescan.\n");
  7495. sh = scsi_host_get(h->scsi_host);
  7496. if (sh != NULL) {
  7497. hpsa_scan_start(sh);
  7498. scsi_host_put(sh);
  7499. }
  7500. }
  7501. }
  7502. spin_lock_irqsave(&h->lock, flags);
  7503. if (!h->remove_in_progress)
  7504. queue_delayed_work(h->rescan_ctlr_wq, &h->rescan_ctlr_work,
  7505. h->heartbeat_sample_interval);
  7506. spin_unlock_irqrestore(&h->lock, flags);
  7507. }
  7508. static void hpsa_monitor_ctlr_worker(struct work_struct *work)
  7509. {
  7510. unsigned long flags;
  7511. struct ctlr_info *h = container_of(to_delayed_work(work),
  7512. struct ctlr_info, monitor_ctlr_work);
  7513. detect_controller_lockup(h);
  7514. if (lockup_detected(h))
  7515. return;
  7516. spin_lock_irqsave(&h->lock, flags);
  7517. if (!h->remove_in_progress)
  7518. schedule_delayed_work(&h->monitor_ctlr_work,
  7519. h->heartbeat_sample_interval);
  7520. spin_unlock_irqrestore(&h->lock, flags);
  7521. }
  7522. static struct workqueue_struct *hpsa_create_controller_wq(struct ctlr_info *h,
  7523. char *name)
  7524. {
  7525. struct workqueue_struct *wq = NULL;
  7526. wq = alloc_ordered_workqueue("%s_%d_hpsa", 0, name, h->ctlr);
  7527. if (!wq)
  7528. dev_err(&h->pdev->dev, "failed to create %s workqueue\n", name);
  7529. return wq;
  7530. }
  7531. static int hpsa_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
  7532. {
  7533. int dac, rc;
  7534. struct ctlr_info *h;
  7535. int try_soft_reset = 0;
  7536. unsigned long flags;
  7537. u32 board_id;
  7538. if (number_of_controllers == 0)
  7539. printk(KERN_INFO DRIVER_NAME "\n");
  7540. rc = hpsa_lookup_board_id(pdev, &board_id);
  7541. if (rc < 0) {
  7542. dev_warn(&pdev->dev, "Board ID not found\n");
  7543. return rc;
  7544. }
  7545. rc = hpsa_init_reset_devices(pdev, board_id);
  7546. if (rc) {
  7547. if (rc != -ENOTSUPP)
  7548. return rc;
  7549. /* If the reset fails in a particular way (it has no way to do
  7550. * a proper hard reset, so returns -ENOTSUPP) we can try to do
  7551. * a soft reset once we get the controller configured up to the
  7552. * point that it can accept a command.
  7553. */
  7554. try_soft_reset = 1;
  7555. rc = 0;
  7556. }
  7557. reinit_after_soft_reset:
  7558. /* Command structures must be aligned on a 32-byte boundary because
  7559. * the 5 lower bits of the address are used by the hardware. and by
  7560. * the driver. See comments in hpsa.h for more info.
  7561. */
  7562. BUILD_BUG_ON(sizeof(struct CommandList) % COMMANDLIST_ALIGNMENT);
  7563. h = kzalloc(sizeof(*h), GFP_KERNEL);
  7564. if (!h) {
  7565. dev_err(&pdev->dev, "Failed to allocate controller head\n");
  7566. return -ENOMEM;
  7567. }
  7568. h->pdev = pdev;
  7569. h->intr_mode = hpsa_simple_mode ? SIMPLE_MODE_INT : PERF_MODE_INT;
  7570. INIT_LIST_HEAD(&h->offline_device_list);
  7571. spin_lock_init(&h->lock);
  7572. spin_lock_init(&h->offline_device_lock);
  7573. spin_lock_init(&h->scan_lock);
  7574. atomic_set(&h->passthru_cmds_avail, HPSA_MAX_CONCURRENT_PASSTHRUS);
  7575. atomic_set(&h->abort_cmds_available, HPSA_CMDS_RESERVED_FOR_ABORTS);
  7576. /* Allocate and clear per-cpu variable lockup_detected */
  7577. h->lockup_detected = alloc_percpu(u32);
  7578. if (!h->lockup_detected) {
  7579. dev_err(&h->pdev->dev, "Failed to allocate lockup detector\n");
  7580. rc = -ENOMEM;
  7581. goto clean1; /* aer/h */
  7582. }
  7583. set_lockup_detected_for_all_cpus(h, 0);
  7584. rc = hpsa_pci_init(h);
  7585. if (rc)
  7586. goto clean2; /* lu, aer/h */
  7587. /* relies on h-> settings made by hpsa_pci_init, including
  7588. * interrupt_mode h->intr */
  7589. rc = hpsa_scsi_host_alloc(h);
  7590. if (rc)
  7591. goto clean2_5; /* pci, lu, aer/h */
  7592. sprintf(h->devname, HPSA "%d", h->scsi_host->host_no);
  7593. h->ctlr = number_of_controllers;
  7594. number_of_controllers++;
  7595. /* configure PCI DMA stuff */
  7596. rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(64));
  7597. if (rc == 0) {
  7598. dac = 1;
  7599. } else {
  7600. rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
  7601. if (rc == 0) {
  7602. dac = 0;
  7603. } else {
  7604. dev_err(&pdev->dev, "no suitable DMA available\n");
  7605. goto clean3; /* shost, pci, lu, aer/h */
  7606. }
  7607. }
  7608. /* make sure the board interrupts are off */
  7609. h->access.set_intr_mask(h, HPSA_INTR_OFF);
  7610. rc = hpsa_request_irqs(h, do_hpsa_intr_msi, do_hpsa_intr_intx);
  7611. if (rc)
  7612. goto clean3; /* shost, pci, lu, aer/h */
  7613. rc = hpsa_alloc_cmd_pool(h);
  7614. if (rc)
  7615. goto clean4; /* irq, shost, pci, lu, aer/h */
  7616. rc = hpsa_alloc_sg_chain_blocks(h);
  7617. if (rc)
  7618. goto clean5; /* cmd, irq, shost, pci, lu, aer/h */
  7619. init_waitqueue_head(&h->scan_wait_queue);
  7620. init_waitqueue_head(&h->abort_cmd_wait_queue);
  7621. init_waitqueue_head(&h->event_sync_wait_queue);
  7622. mutex_init(&h->reset_mutex);
  7623. h->scan_finished = 1; /* no scan currently in progress */
  7624. h->scan_waiting = 0;
  7625. pci_set_drvdata(pdev, h);
  7626. h->ndevices = 0;
  7627. spin_lock_init(&h->devlock);
  7628. rc = hpsa_put_ctlr_into_performant_mode(h);
  7629. if (rc)
  7630. goto clean6; /* sg, cmd, irq, shost, pci, lu, aer/h */
  7631. /* hook into SCSI subsystem */
  7632. rc = hpsa_scsi_add_host(h);
  7633. if (rc)
  7634. goto clean7; /* perf, sg, cmd, irq, shost, pci, lu, aer/h */
  7635. /* create the resubmit workqueue */
  7636. h->rescan_ctlr_wq = hpsa_create_controller_wq(h, "rescan");
  7637. if (!h->rescan_ctlr_wq) {
  7638. rc = -ENOMEM;
  7639. goto clean7;
  7640. }
  7641. h->resubmit_wq = hpsa_create_controller_wq(h, "resubmit");
  7642. if (!h->resubmit_wq) {
  7643. rc = -ENOMEM;
  7644. goto clean7; /* aer/h */
  7645. }
  7646. /*
  7647. * At this point, the controller is ready to take commands.
  7648. * Now, if reset_devices and the hard reset didn't work, try
  7649. * the soft reset and see if that works.
  7650. */
  7651. if (try_soft_reset) {
  7652. /* This is kind of gross. We may or may not get a completion
  7653. * from the soft reset command, and if we do, then the value
  7654. * from the fifo may or may not be valid. So, we wait 10 secs
  7655. * after the reset throwing away any completions we get during
  7656. * that time. Unregister the interrupt handler and register
  7657. * fake ones to scoop up any residual completions.
  7658. */
  7659. spin_lock_irqsave(&h->lock, flags);
  7660. h->access.set_intr_mask(h, HPSA_INTR_OFF);
  7661. spin_unlock_irqrestore(&h->lock, flags);
  7662. hpsa_free_irqs(h);
  7663. rc = hpsa_request_irqs(h, hpsa_msix_discard_completions,
  7664. hpsa_intx_discard_completions);
  7665. if (rc) {
  7666. dev_warn(&h->pdev->dev,
  7667. "Failed to request_irq after soft reset.\n");
  7668. /*
  7669. * cannot goto clean7 or free_irqs will be called
  7670. * again. Instead, do its work
  7671. */
  7672. hpsa_free_performant_mode(h); /* clean7 */
  7673. hpsa_free_sg_chain_blocks(h); /* clean6 */
  7674. hpsa_free_cmd_pool(h); /* clean5 */
  7675. /*
  7676. * skip hpsa_free_irqs(h) clean4 since that
  7677. * was just called before request_irqs failed
  7678. */
  7679. goto clean3;
  7680. }
  7681. rc = hpsa_kdump_soft_reset(h);
  7682. if (rc)
  7683. /* Neither hard nor soft reset worked, we're hosed. */
  7684. goto clean7;
  7685. dev_info(&h->pdev->dev, "Board READY.\n");
  7686. dev_info(&h->pdev->dev,
  7687. "Waiting for stale completions to drain.\n");
  7688. h->access.set_intr_mask(h, HPSA_INTR_ON);
  7689. msleep(10000);
  7690. h->access.set_intr_mask(h, HPSA_INTR_OFF);
  7691. rc = controller_reset_failed(h->cfgtable);
  7692. if (rc)
  7693. dev_info(&h->pdev->dev,
  7694. "Soft reset appears to have failed.\n");
  7695. /* since the controller's reset, we have to go back and re-init
  7696. * everything. Easiest to just forget what we've done and do it
  7697. * all over again.
  7698. */
  7699. hpsa_undo_allocations_after_kdump_soft_reset(h);
  7700. try_soft_reset = 0;
  7701. if (rc)
  7702. /* don't goto clean, we already unallocated */
  7703. return -ENODEV;
  7704. goto reinit_after_soft_reset;
  7705. }
  7706. /* Enable Accelerated IO path at driver layer */
  7707. h->acciopath_status = 1;
  7708. /* Disable discovery polling.*/
  7709. h->discovery_polling = 0;
  7710. /* Turn the interrupts on so we can service requests */
  7711. h->access.set_intr_mask(h, HPSA_INTR_ON);
  7712. hpsa_hba_inquiry(h);
  7713. h->lastlogicals = kzalloc(sizeof(*(h->lastlogicals)), GFP_KERNEL);
  7714. if (!h->lastlogicals)
  7715. dev_info(&h->pdev->dev,
  7716. "Can't track change to report lun data\n");
  7717. /* Monitor the controller for firmware lockups */
  7718. h->heartbeat_sample_interval = HEARTBEAT_SAMPLE_INTERVAL;
  7719. INIT_DELAYED_WORK(&h->monitor_ctlr_work, hpsa_monitor_ctlr_worker);
  7720. schedule_delayed_work(&h->monitor_ctlr_work,
  7721. h->heartbeat_sample_interval);
  7722. INIT_DELAYED_WORK(&h->rescan_ctlr_work, hpsa_rescan_ctlr_worker);
  7723. queue_delayed_work(h->rescan_ctlr_wq, &h->rescan_ctlr_work,
  7724. h->heartbeat_sample_interval);
  7725. return 0;
  7726. clean7: /* perf, sg, cmd, irq, shost, pci, lu, aer/h */
  7727. hpsa_free_performant_mode(h);
  7728. h->access.set_intr_mask(h, HPSA_INTR_OFF);
  7729. clean6: /* sg, cmd, irq, pci, lockup, wq/aer/h */
  7730. hpsa_free_sg_chain_blocks(h);
  7731. clean5: /* cmd, irq, shost, pci, lu, aer/h */
  7732. hpsa_free_cmd_pool(h);
  7733. clean4: /* irq, shost, pci, lu, aer/h */
  7734. hpsa_free_irqs(h);
  7735. clean3: /* shost, pci, lu, aer/h */
  7736. scsi_host_put(h->scsi_host);
  7737. h->scsi_host = NULL;
  7738. clean2_5: /* pci, lu, aer/h */
  7739. hpsa_free_pci_init(h);
  7740. clean2: /* lu, aer/h */
  7741. if (h->lockup_detected) {
  7742. free_percpu(h->lockup_detected);
  7743. h->lockup_detected = NULL;
  7744. }
  7745. clean1: /* wq/aer/h */
  7746. if (h->resubmit_wq) {
  7747. destroy_workqueue(h->resubmit_wq);
  7748. h->resubmit_wq = NULL;
  7749. }
  7750. if (h->rescan_ctlr_wq) {
  7751. destroy_workqueue(h->rescan_ctlr_wq);
  7752. h->rescan_ctlr_wq = NULL;
  7753. }
  7754. kfree(h);
  7755. return rc;
  7756. }
  7757. static void hpsa_flush_cache(struct ctlr_info *h)
  7758. {
  7759. char *flush_buf;
  7760. struct CommandList *c;
  7761. int rc;
  7762. if (unlikely(lockup_detected(h)))
  7763. return;
  7764. flush_buf = kzalloc(4, GFP_KERNEL);
  7765. if (!flush_buf)
  7766. return;
  7767. c = cmd_alloc(h);
  7768. if (fill_cmd(c, HPSA_CACHE_FLUSH, h, flush_buf, 4, 0,
  7769. RAID_CTLR_LUNID, TYPE_CMD)) {
  7770. goto out;
  7771. }
  7772. rc = hpsa_scsi_do_simple_cmd_with_retry(h, c,
  7773. PCI_DMA_TODEVICE, NO_TIMEOUT);
  7774. if (rc)
  7775. goto out;
  7776. if (c->err_info->CommandStatus != 0)
  7777. out:
  7778. dev_warn(&h->pdev->dev,
  7779. "error flushing cache on controller\n");
  7780. cmd_free(h, c);
  7781. kfree(flush_buf);
  7782. }
  7783. /* Make controller gather fresh report lun data each time we
  7784. * send down a report luns request
  7785. */
  7786. static void hpsa_disable_rld_caching(struct ctlr_info *h)
  7787. {
  7788. u32 *options;
  7789. struct CommandList *c;
  7790. int rc;
  7791. /* Don't bother trying to set diag options if locked up */
  7792. if (unlikely(h->lockup_detected))
  7793. return;
  7794. options = kzalloc(sizeof(*options), GFP_KERNEL);
  7795. if (!options) {
  7796. dev_err(&h->pdev->dev,
  7797. "Error: failed to disable rld caching, during alloc.\n");
  7798. return;
  7799. }
  7800. c = cmd_alloc(h);
  7801. /* first, get the current diag options settings */
  7802. if (fill_cmd(c, BMIC_SENSE_DIAG_OPTIONS, h, options, 4, 0,
  7803. RAID_CTLR_LUNID, TYPE_CMD))
  7804. goto errout;
  7805. rc = hpsa_scsi_do_simple_cmd_with_retry(h, c,
  7806. PCI_DMA_FROMDEVICE, NO_TIMEOUT);
  7807. if ((rc != 0) || (c->err_info->CommandStatus != 0))
  7808. goto errout;
  7809. /* Now, set the bit for disabling the RLD caching */
  7810. *options |= HPSA_DIAG_OPTS_DISABLE_RLD_CACHING;
  7811. if (fill_cmd(c, BMIC_SET_DIAG_OPTIONS, h, options, 4, 0,
  7812. RAID_CTLR_LUNID, TYPE_CMD))
  7813. goto errout;
  7814. rc = hpsa_scsi_do_simple_cmd_with_retry(h, c,
  7815. PCI_DMA_TODEVICE, NO_TIMEOUT);
  7816. if ((rc != 0) || (c->err_info->CommandStatus != 0))
  7817. goto errout;
  7818. /* Now verify that it got set: */
  7819. if (fill_cmd(c, BMIC_SENSE_DIAG_OPTIONS, h, options, 4, 0,
  7820. RAID_CTLR_LUNID, TYPE_CMD))
  7821. goto errout;
  7822. rc = hpsa_scsi_do_simple_cmd_with_retry(h, c,
  7823. PCI_DMA_FROMDEVICE, NO_TIMEOUT);
  7824. if ((rc != 0) || (c->err_info->CommandStatus != 0))
  7825. goto errout;
  7826. if (*options & HPSA_DIAG_OPTS_DISABLE_RLD_CACHING)
  7827. goto out;
  7828. errout:
  7829. dev_err(&h->pdev->dev,
  7830. "Error: failed to disable report lun data caching.\n");
  7831. out:
  7832. cmd_free(h, c);
  7833. kfree(options);
  7834. }
  7835. static void hpsa_shutdown(struct pci_dev *pdev)
  7836. {
  7837. struct ctlr_info *h;
  7838. h = pci_get_drvdata(pdev);
  7839. /* Turn board interrupts off and send the flush cache command
  7840. * sendcmd will turn off interrupt, and send the flush...
  7841. * To write all data in the battery backed cache to disks
  7842. */
  7843. hpsa_flush_cache(h);
  7844. h->access.set_intr_mask(h, HPSA_INTR_OFF);
  7845. hpsa_free_irqs(h); /* init_one 4 */
  7846. hpsa_disable_interrupt_mode(h); /* pci_init 2 */
  7847. }
  7848. static void hpsa_free_device_info(struct ctlr_info *h)
  7849. {
  7850. int i;
  7851. for (i = 0; i < h->ndevices; i++) {
  7852. kfree(h->dev[i]);
  7853. h->dev[i] = NULL;
  7854. }
  7855. }
  7856. static void hpsa_remove_one(struct pci_dev *pdev)
  7857. {
  7858. struct ctlr_info *h;
  7859. unsigned long flags;
  7860. if (pci_get_drvdata(pdev) == NULL) {
  7861. dev_err(&pdev->dev, "unable to remove device\n");
  7862. return;
  7863. }
  7864. h = pci_get_drvdata(pdev);
  7865. /* Get rid of any controller monitoring work items */
  7866. spin_lock_irqsave(&h->lock, flags);
  7867. h->remove_in_progress = 1;
  7868. spin_unlock_irqrestore(&h->lock, flags);
  7869. cancel_delayed_work_sync(&h->monitor_ctlr_work);
  7870. cancel_delayed_work_sync(&h->rescan_ctlr_work);
  7871. destroy_workqueue(h->rescan_ctlr_wq);
  7872. destroy_workqueue(h->resubmit_wq);
  7873. hpsa_delete_sas_host(h);
  7874. /*
  7875. * Call before disabling interrupts.
  7876. * scsi_remove_host can trigger I/O operations especially
  7877. * when multipath is enabled. There can be SYNCHRONIZE CACHE
  7878. * operations which cannot complete and will hang the system.
  7879. */
  7880. if (h->scsi_host)
  7881. scsi_remove_host(h->scsi_host); /* init_one 8 */
  7882. /* includes hpsa_free_irqs - init_one 4 */
  7883. /* includes hpsa_disable_interrupt_mode - pci_init 2 */
  7884. hpsa_shutdown(pdev);
  7885. hpsa_free_device_info(h); /* scan */
  7886. kfree(h->hba_inquiry_data); /* init_one 10 */
  7887. h->hba_inquiry_data = NULL; /* init_one 10 */
  7888. hpsa_free_ioaccel2_sg_chain_blocks(h);
  7889. hpsa_free_performant_mode(h); /* init_one 7 */
  7890. hpsa_free_sg_chain_blocks(h); /* init_one 6 */
  7891. hpsa_free_cmd_pool(h); /* init_one 5 */
  7892. kfree(h->lastlogicals);
  7893. /* hpsa_free_irqs already called via hpsa_shutdown init_one 4 */
  7894. scsi_host_put(h->scsi_host); /* init_one 3 */
  7895. h->scsi_host = NULL; /* init_one 3 */
  7896. /* includes hpsa_disable_interrupt_mode - pci_init 2 */
  7897. hpsa_free_pci_init(h); /* init_one 2.5 */
  7898. free_percpu(h->lockup_detected); /* init_one 2 */
  7899. h->lockup_detected = NULL; /* init_one 2 */
  7900. /* (void) pci_disable_pcie_error_reporting(pdev); */ /* init_one 1 */
  7901. kfree(h); /* init_one 1 */
  7902. }
  7903. static int hpsa_suspend(__attribute__((unused)) struct pci_dev *pdev,
  7904. __attribute__((unused)) pm_message_t state)
  7905. {
  7906. return -ENOSYS;
  7907. }
  7908. static int hpsa_resume(__attribute__((unused)) struct pci_dev *pdev)
  7909. {
  7910. return -ENOSYS;
  7911. }
  7912. static struct pci_driver hpsa_pci_driver = {
  7913. .name = HPSA,
  7914. .probe = hpsa_init_one,
  7915. .remove = hpsa_remove_one,
  7916. .id_table = hpsa_pci_device_id, /* id_table */
  7917. .shutdown = hpsa_shutdown,
  7918. .suspend = hpsa_suspend,
  7919. .resume = hpsa_resume,
  7920. };
  7921. /* Fill in bucket_map[], given nsgs (the max number of
  7922. * scatter gather elements supported) and bucket[],
  7923. * which is an array of 8 integers. The bucket[] array
  7924. * contains 8 different DMA transfer sizes (in 16
  7925. * byte increments) which the controller uses to fetch
  7926. * commands. This function fills in bucket_map[], which
  7927. * maps a given number of scatter gather elements to one of
  7928. * the 8 DMA transfer sizes. The point of it is to allow the
  7929. * controller to only do as much DMA as needed to fetch the
  7930. * command, with the DMA transfer size encoded in the lower
  7931. * bits of the command address.
  7932. */
  7933. static void calc_bucket_map(int bucket[], int num_buckets,
  7934. int nsgs, int min_blocks, u32 *bucket_map)
  7935. {
  7936. int i, j, b, size;
  7937. /* Note, bucket_map must have nsgs+1 entries. */
  7938. for (i = 0; i <= nsgs; i++) {
  7939. /* Compute size of a command with i SG entries */
  7940. size = i + min_blocks;
  7941. b = num_buckets; /* Assume the biggest bucket */
  7942. /* Find the bucket that is just big enough */
  7943. for (j = 0; j < num_buckets; j++) {
  7944. if (bucket[j] >= size) {
  7945. b = j;
  7946. break;
  7947. }
  7948. }
  7949. /* for a command with i SG entries, use bucket b. */
  7950. bucket_map[i] = b;
  7951. }
  7952. }
  7953. /*
  7954. * return -ENODEV on err, 0 on success (or no action)
  7955. * allocates numerous items that must be freed later
  7956. */
  7957. static int hpsa_enter_performant_mode(struct ctlr_info *h, u32 trans_support)
  7958. {
  7959. int i;
  7960. unsigned long register_value;
  7961. unsigned long transMethod = CFGTBL_Trans_Performant |
  7962. (trans_support & CFGTBL_Trans_use_short_tags) |
  7963. CFGTBL_Trans_enable_directed_msix |
  7964. (trans_support & (CFGTBL_Trans_io_accel1 |
  7965. CFGTBL_Trans_io_accel2));
  7966. struct access_method access = SA5_performant_access;
  7967. /* This is a bit complicated. There are 8 registers on
  7968. * the controller which we write to to tell it 8 different
  7969. * sizes of commands which there may be. It's a way of
  7970. * reducing the DMA done to fetch each command. Encoded into
  7971. * each command's tag are 3 bits which communicate to the controller
  7972. * which of the eight sizes that command fits within. The size of
  7973. * each command depends on how many scatter gather entries there are.
  7974. * Each SG entry requires 16 bytes. The eight registers are programmed
  7975. * with the number of 16-byte blocks a command of that size requires.
  7976. * The smallest command possible requires 5 such 16 byte blocks.
  7977. * the largest command possible requires SG_ENTRIES_IN_CMD + 4 16-byte
  7978. * blocks. Note, this only extends to the SG entries contained
  7979. * within the command block, and does not extend to chained blocks
  7980. * of SG elements. bft[] contains the eight values we write to
  7981. * the registers. They are not evenly distributed, but have more
  7982. * sizes for small commands, and fewer sizes for larger commands.
  7983. */
  7984. int bft[8] = {5, 6, 8, 10, 12, 20, 28, SG_ENTRIES_IN_CMD + 4};
  7985. #define MIN_IOACCEL2_BFT_ENTRY 5
  7986. #define HPSA_IOACCEL2_HEADER_SZ 4
  7987. int bft2[16] = {MIN_IOACCEL2_BFT_ENTRY, 6, 7, 8, 9, 10, 11, 12,
  7988. 13, 14, 15, 16, 17, 18, 19,
  7989. HPSA_IOACCEL2_HEADER_SZ + IOACCEL2_MAXSGENTRIES};
  7990. BUILD_BUG_ON(ARRAY_SIZE(bft2) != 16);
  7991. BUILD_BUG_ON(ARRAY_SIZE(bft) != 8);
  7992. BUILD_BUG_ON(offsetof(struct io_accel2_cmd, sg) >
  7993. 16 * MIN_IOACCEL2_BFT_ENTRY);
  7994. BUILD_BUG_ON(sizeof(struct ioaccel2_sg_element) != 16);
  7995. BUILD_BUG_ON(28 > SG_ENTRIES_IN_CMD + 4);
  7996. /* 5 = 1 s/g entry or 4k
  7997. * 6 = 2 s/g entry or 8k
  7998. * 8 = 4 s/g entry or 16k
  7999. * 10 = 6 s/g entry or 24k
  8000. */
  8001. /* If the controller supports either ioaccel method then
  8002. * we can also use the RAID stack submit path that does not
  8003. * perform the superfluous readl() after each command submission.
  8004. */
  8005. if (trans_support & (CFGTBL_Trans_io_accel1 | CFGTBL_Trans_io_accel2))
  8006. access = SA5_performant_access_no_read;
  8007. /* Controller spec: zero out this buffer. */
  8008. for (i = 0; i < h->nreply_queues; i++)
  8009. memset(h->reply_queue[i].head, 0, h->reply_queue_size);
  8010. bft[7] = SG_ENTRIES_IN_CMD + 4;
  8011. calc_bucket_map(bft, ARRAY_SIZE(bft),
  8012. SG_ENTRIES_IN_CMD, 4, h->blockFetchTable);
  8013. for (i = 0; i < 8; i++)
  8014. writel(bft[i], &h->transtable->BlockFetch[i]);
  8015. /* size of controller ring buffer */
  8016. writel(h->max_commands, &h->transtable->RepQSize);
  8017. writel(h->nreply_queues, &h->transtable->RepQCount);
  8018. writel(0, &h->transtable->RepQCtrAddrLow32);
  8019. writel(0, &h->transtable->RepQCtrAddrHigh32);
  8020. for (i = 0; i < h->nreply_queues; i++) {
  8021. writel(0, &h->transtable->RepQAddr[i].upper);
  8022. writel(h->reply_queue[i].busaddr,
  8023. &h->transtable->RepQAddr[i].lower);
  8024. }
  8025. writel(0, &h->cfgtable->HostWrite.command_pool_addr_hi);
  8026. writel(transMethod, &(h->cfgtable->HostWrite.TransportRequest));
  8027. /*
  8028. * enable outbound interrupt coalescing in accelerator mode;
  8029. */
  8030. if (trans_support & CFGTBL_Trans_io_accel1) {
  8031. access = SA5_ioaccel_mode1_access;
  8032. writel(10, &h->cfgtable->HostWrite.CoalIntDelay);
  8033. writel(4, &h->cfgtable->HostWrite.CoalIntCount);
  8034. } else {
  8035. if (trans_support & CFGTBL_Trans_io_accel2) {
  8036. access = SA5_ioaccel_mode2_access;
  8037. writel(10, &h->cfgtable->HostWrite.CoalIntDelay);
  8038. writel(4, &h->cfgtable->HostWrite.CoalIntCount);
  8039. }
  8040. }
  8041. writel(CFGTBL_ChangeReq, h->vaddr + SA5_DOORBELL);
  8042. if (hpsa_wait_for_mode_change_ack(h)) {
  8043. dev_err(&h->pdev->dev,
  8044. "performant mode problem - doorbell timeout\n");
  8045. return -ENODEV;
  8046. }
  8047. register_value = readl(&(h->cfgtable->TransportActive));
  8048. if (!(register_value & CFGTBL_Trans_Performant)) {
  8049. dev_err(&h->pdev->dev,
  8050. "performant mode problem - transport not active\n");
  8051. return -ENODEV;
  8052. }
  8053. /* Change the access methods to the performant access methods */
  8054. h->access = access;
  8055. h->transMethod = transMethod;
  8056. if (!((trans_support & CFGTBL_Trans_io_accel1) ||
  8057. (trans_support & CFGTBL_Trans_io_accel2)))
  8058. return 0;
  8059. if (trans_support & CFGTBL_Trans_io_accel1) {
  8060. /* Set up I/O accelerator mode */
  8061. for (i = 0; i < h->nreply_queues; i++) {
  8062. writel(i, h->vaddr + IOACCEL_MODE1_REPLY_QUEUE_INDEX);
  8063. h->reply_queue[i].current_entry =
  8064. readl(h->vaddr + IOACCEL_MODE1_PRODUCER_INDEX);
  8065. }
  8066. bft[7] = h->ioaccel_maxsg + 8;
  8067. calc_bucket_map(bft, ARRAY_SIZE(bft), h->ioaccel_maxsg, 8,
  8068. h->ioaccel1_blockFetchTable);
  8069. /* initialize all reply queue entries to unused */
  8070. for (i = 0; i < h->nreply_queues; i++)
  8071. memset(h->reply_queue[i].head,
  8072. (u8) IOACCEL_MODE1_REPLY_UNUSED,
  8073. h->reply_queue_size);
  8074. /* set all the constant fields in the accelerator command
  8075. * frames once at init time to save CPU cycles later.
  8076. */
  8077. for (i = 0; i < h->nr_cmds; i++) {
  8078. struct io_accel1_cmd *cp = &h->ioaccel_cmd_pool[i];
  8079. cp->function = IOACCEL1_FUNCTION_SCSIIO;
  8080. cp->err_info = (u32) (h->errinfo_pool_dhandle +
  8081. (i * sizeof(struct ErrorInfo)));
  8082. cp->err_info_len = sizeof(struct ErrorInfo);
  8083. cp->sgl_offset = IOACCEL1_SGLOFFSET;
  8084. cp->host_context_flags =
  8085. cpu_to_le16(IOACCEL1_HCFLAGS_CISS_FORMAT);
  8086. cp->timeout_sec = 0;
  8087. cp->ReplyQueue = 0;
  8088. cp->tag =
  8089. cpu_to_le64((i << DIRECT_LOOKUP_SHIFT));
  8090. cp->host_addr =
  8091. cpu_to_le64(h->ioaccel_cmd_pool_dhandle +
  8092. (i * sizeof(struct io_accel1_cmd)));
  8093. }
  8094. } else if (trans_support & CFGTBL_Trans_io_accel2) {
  8095. u64 cfg_offset, cfg_base_addr_index;
  8096. u32 bft2_offset, cfg_base_addr;
  8097. int rc;
  8098. rc = hpsa_find_cfg_addrs(h->pdev, h->vaddr, &cfg_base_addr,
  8099. &cfg_base_addr_index, &cfg_offset);
  8100. BUILD_BUG_ON(offsetof(struct io_accel2_cmd, sg) != 64);
  8101. bft2[15] = h->ioaccel_maxsg + HPSA_IOACCEL2_HEADER_SZ;
  8102. calc_bucket_map(bft2, ARRAY_SIZE(bft2), h->ioaccel_maxsg,
  8103. 4, h->ioaccel2_blockFetchTable);
  8104. bft2_offset = readl(&h->cfgtable->io_accel_request_size_offset);
  8105. BUILD_BUG_ON(offsetof(struct CfgTable,
  8106. io_accel_request_size_offset) != 0xb8);
  8107. h->ioaccel2_bft2_regs =
  8108. remap_pci_mem(pci_resource_start(h->pdev,
  8109. cfg_base_addr_index) +
  8110. cfg_offset + bft2_offset,
  8111. ARRAY_SIZE(bft2) *
  8112. sizeof(*h->ioaccel2_bft2_regs));
  8113. for (i = 0; i < ARRAY_SIZE(bft2); i++)
  8114. writel(bft2[i], &h->ioaccel2_bft2_regs[i]);
  8115. }
  8116. writel(CFGTBL_ChangeReq, h->vaddr + SA5_DOORBELL);
  8117. if (hpsa_wait_for_mode_change_ack(h)) {
  8118. dev_err(&h->pdev->dev,
  8119. "performant mode problem - enabling ioaccel mode\n");
  8120. return -ENODEV;
  8121. }
  8122. return 0;
  8123. }
  8124. /* Free ioaccel1 mode command blocks and block fetch table */
  8125. static void hpsa_free_ioaccel1_cmd_and_bft(struct ctlr_info *h)
  8126. {
  8127. if (h->ioaccel_cmd_pool) {
  8128. pci_free_consistent(h->pdev,
  8129. h->nr_cmds * sizeof(*h->ioaccel_cmd_pool),
  8130. h->ioaccel_cmd_pool,
  8131. h->ioaccel_cmd_pool_dhandle);
  8132. h->ioaccel_cmd_pool = NULL;
  8133. h->ioaccel_cmd_pool_dhandle = 0;
  8134. }
  8135. kfree(h->ioaccel1_blockFetchTable);
  8136. h->ioaccel1_blockFetchTable = NULL;
  8137. }
  8138. /* Allocate ioaccel1 mode command blocks and block fetch table */
  8139. static int hpsa_alloc_ioaccel1_cmd_and_bft(struct ctlr_info *h)
  8140. {
  8141. h->ioaccel_maxsg =
  8142. readl(&(h->cfgtable->io_accel_max_embedded_sg_count));
  8143. if (h->ioaccel_maxsg > IOACCEL1_MAXSGENTRIES)
  8144. h->ioaccel_maxsg = IOACCEL1_MAXSGENTRIES;
  8145. /* Command structures must be aligned on a 128-byte boundary
  8146. * because the 7 lower bits of the address are used by the
  8147. * hardware.
  8148. */
  8149. BUILD_BUG_ON(sizeof(struct io_accel1_cmd) %
  8150. IOACCEL1_COMMANDLIST_ALIGNMENT);
  8151. h->ioaccel_cmd_pool =
  8152. pci_alloc_consistent(h->pdev,
  8153. h->nr_cmds * sizeof(*h->ioaccel_cmd_pool),
  8154. &(h->ioaccel_cmd_pool_dhandle));
  8155. h->ioaccel1_blockFetchTable =
  8156. kmalloc(((h->ioaccel_maxsg + 1) *
  8157. sizeof(u32)), GFP_KERNEL);
  8158. if ((h->ioaccel_cmd_pool == NULL) ||
  8159. (h->ioaccel1_blockFetchTable == NULL))
  8160. goto clean_up;
  8161. memset(h->ioaccel_cmd_pool, 0,
  8162. h->nr_cmds * sizeof(*h->ioaccel_cmd_pool));
  8163. return 0;
  8164. clean_up:
  8165. hpsa_free_ioaccel1_cmd_and_bft(h);
  8166. return -ENOMEM;
  8167. }
  8168. /* Free ioaccel2 mode command blocks and block fetch table */
  8169. static void hpsa_free_ioaccel2_cmd_and_bft(struct ctlr_info *h)
  8170. {
  8171. hpsa_free_ioaccel2_sg_chain_blocks(h);
  8172. if (h->ioaccel2_cmd_pool) {
  8173. pci_free_consistent(h->pdev,
  8174. h->nr_cmds * sizeof(*h->ioaccel2_cmd_pool),
  8175. h->ioaccel2_cmd_pool,
  8176. h->ioaccel2_cmd_pool_dhandle);
  8177. h->ioaccel2_cmd_pool = NULL;
  8178. h->ioaccel2_cmd_pool_dhandle = 0;
  8179. }
  8180. kfree(h->ioaccel2_blockFetchTable);
  8181. h->ioaccel2_blockFetchTable = NULL;
  8182. }
  8183. /* Allocate ioaccel2 mode command blocks and block fetch table */
  8184. static int hpsa_alloc_ioaccel2_cmd_and_bft(struct ctlr_info *h)
  8185. {
  8186. int rc;
  8187. /* Allocate ioaccel2 mode command blocks and block fetch table */
  8188. h->ioaccel_maxsg =
  8189. readl(&(h->cfgtable->io_accel_max_embedded_sg_count));
  8190. if (h->ioaccel_maxsg > IOACCEL2_MAXSGENTRIES)
  8191. h->ioaccel_maxsg = IOACCEL2_MAXSGENTRIES;
  8192. BUILD_BUG_ON(sizeof(struct io_accel2_cmd) %
  8193. IOACCEL2_COMMANDLIST_ALIGNMENT);
  8194. h->ioaccel2_cmd_pool =
  8195. pci_alloc_consistent(h->pdev,
  8196. h->nr_cmds * sizeof(*h->ioaccel2_cmd_pool),
  8197. &(h->ioaccel2_cmd_pool_dhandle));
  8198. h->ioaccel2_blockFetchTable =
  8199. kmalloc(((h->ioaccel_maxsg + 1) *
  8200. sizeof(u32)), GFP_KERNEL);
  8201. if ((h->ioaccel2_cmd_pool == NULL) ||
  8202. (h->ioaccel2_blockFetchTable == NULL)) {
  8203. rc = -ENOMEM;
  8204. goto clean_up;
  8205. }
  8206. rc = hpsa_allocate_ioaccel2_sg_chain_blocks(h);
  8207. if (rc)
  8208. goto clean_up;
  8209. memset(h->ioaccel2_cmd_pool, 0,
  8210. h->nr_cmds * sizeof(*h->ioaccel2_cmd_pool));
  8211. return 0;
  8212. clean_up:
  8213. hpsa_free_ioaccel2_cmd_and_bft(h);
  8214. return rc;
  8215. }
  8216. /* Free items allocated by hpsa_put_ctlr_into_performant_mode */
  8217. static void hpsa_free_performant_mode(struct ctlr_info *h)
  8218. {
  8219. kfree(h->blockFetchTable);
  8220. h->blockFetchTable = NULL;
  8221. hpsa_free_reply_queues(h);
  8222. hpsa_free_ioaccel1_cmd_and_bft(h);
  8223. hpsa_free_ioaccel2_cmd_and_bft(h);
  8224. }
  8225. /* return -ENODEV on error, 0 on success (or no action)
  8226. * allocates numerous items that must be freed later
  8227. */
  8228. static int hpsa_put_ctlr_into_performant_mode(struct ctlr_info *h)
  8229. {
  8230. u32 trans_support;
  8231. unsigned long transMethod = CFGTBL_Trans_Performant |
  8232. CFGTBL_Trans_use_short_tags;
  8233. int i, rc;
  8234. if (hpsa_simple_mode)
  8235. return 0;
  8236. trans_support = readl(&(h->cfgtable->TransportSupport));
  8237. if (!(trans_support & PERFORMANT_MODE))
  8238. return 0;
  8239. /* Check for I/O accelerator mode support */
  8240. if (trans_support & CFGTBL_Trans_io_accel1) {
  8241. transMethod |= CFGTBL_Trans_io_accel1 |
  8242. CFGTBL_Trans_enable_directed_msix;
  8243. rc = hpsa_alloc_ioaccel1_cmd_and_bft(h);
  8244. if (rc)
  8245. return rc;
  8246. } else if (trans_support & CFGTBL_Trans_io_accel2) {
  8247. transMethod |= CFGTBL_Trans_io_accel2 |
  8248. CFGTBL_Trans_enable_directed_msix;
  8249. rc = hpsa_alloc_ioaccel2_cmd_and_bft(h);
  8250. if (rc)
  8251. return rc;
  8252. }
  8253. h->nreply_queues = h->msix_vector > 0 ? h->msix_vector : 1;
  8254. hpsa_get_max_perf_mode_cmds(h);
  8255. /* Performant mode ring buffer and supporting data structures */
  8256. h->reply_queue_size = h->max_commands * sizeof(u64);
  8257. for (i = 0; i < h->nreply_queues; i++) {
  8258. h->reply_queue[i].head = pci_alloc_consistent(h->pdev,
  8259. h->reply_queue_size,
  8260. &(h->reply_queue[i].busaddr));
  8261. if (!h->reply_queue[i].head) {
  8262. rc = -ENOMEM;
  8263. goto clean1; /* rq, ioaccel */
  8264. }
  8265. h->reply_queue[i].size = h->max_commands;
  8266. h->reply_queue[i].wraparound = 1; /* spec: init to 1 */
  8267. h->reply_queue[i].current_entry = 0;
  8268. }
  8269. /* Need a block fetch table for performant mode */
  8270. h->blockFetchTable = kmalloc(((SG_ENTRIES_IN_CMD + 1) *
  8271. sizeof(u32)), GFP_KERNEL);
  8272. if (!h->blockFetchTable) {
  8273. rc = -ENOMEM;
  8274. goto clean1; /* rq, ioaccel */
  8275. }
  8276. rc = hpsa_enter_performant_mode(h, trans_support);
  8277. if (rc)
  8278. goto clean2; /* bft, rq, ioaccel */
  8279. return 0;
  8280. clean2: /* bft, rq, ioaccel */
  8281. kfree(h->blockFetchTable);
  8282. h->blockFetchTable = NULL;
  8283. clean1: /* rq, ioaccel */
  8284. hpsa_free_reply_queues(h);
  8285. hpsa_free_ioaccel1_cmd_and_bft(h);
  8286. hpsa_free_ioaccel2_cmd_and_bft(h);
  8287. return rc;
  8288. }
  8289. static int is_accelerated_cmd(struct CommandList *c)
  8290. {
  8291. return c->cmd_type == CMD_IOACCEL1 || c->cmd_type == CMD_IOACCEL2;
  8292. }
  8293. static void hpsa_drain_accel_commands(struct ctlr_info *h)
  8294. {
  8295. struct CommandList *c = NULL;
  8296. int i, accel_cmds_out;
  8297. int refcount;
  8298. do { /* wait for all outstanding ioaccel commands to drain out */
  8299. accel_cmds_out = 0;
  8300. for (i = 0; i < h->nr_cmds; i++) {
  8301. c = h->cmd_pool + i;
  8302. refcount = atomic_inc_return(&c->refcount);
  8303. if (refcount > 1) /* Command is allocated */
  8304. accel_cmds_out += is_accelerated_cmd(c);
  8305. cmd_free(h, c);
  8306. }
  8307. if (accel_cmds_out <= 0)
  8308. break;
  8309. msleep(100);
  8310. } while (1);
  8311. }
  8312. static struct hpsa_sas_phy *hpsa_alloc_sas_phy(
  8313. struct hpsa_sas_port *hpsa_sas_port)
  8314. {
  8315. struct hpsa_sas_phy *hpsa_sas_phy;
  8316. struct sas_phy *phy;
  8317. hpsa_sas_phy = kzalloc(sizeof(*hpsa_sas_phy), GFP_KERNEL);
  8318. if (!hpsa_sas_phy)
  8319. return NULL;
  8320. phy = sas_phy_alloc(hpsa_sas_port->parent_node->parent_dev,
  8321. hpsa_sas_port->next_phy_index);
  8322. if (!phy) {
  8323. kfree(hpsa_sas_phy);
  8324. return NULL;
  8325. }
  8326. hpsa_sas_port->next_phy_index++;
  8327. hpsa_sas_phy->phy = phy;
  8328. hpsa_sas_phy->parent_port = hpsa_sas_port;
  8329. return hpsa_sas_phy;
  8330. }
  8331. static void hpsa_free_sas_phy(struct hpsa_sas_phy *hpsa_sas_phy)
  8332. {
  8333. struct sas_phy *phy = hpsa_sas_phy->phy;
  8334. sas_port_delete_phy(hpsa_sas_phy->parent_port->port, phy);
  8335. if (hpsa_sas_phy->added_to_port)
  8336. list_del(&hpsa_sas_phy->phy_list_entry);
  8337. sas_phy_delete(phy);
  8338. kfree(hpsa_sas_phy);
  8339. }
  8340. static int hpsa_sas_port_add_phy(struct hpsa_sas_phy *hpsa_sas_phy)
  8341. {
  8342. int rc;
  8343. struct hpsa_sas_port *hpsa_sas_port;
  8344. struct sas_phy *phy;
  8345. struct sas_identify *identify;
  8346. hpsa_sas_port = hpsa_sas_phy->parent_port;
  8347. phy = hpsa_sas_phy->phy;
  8348. identify = &phy->identify;
  8349. memset(identify, 0, sizeof(*identify));
  8350. identify->sas_address = hpsa_sas_port->sas_address;
  8351. identify->device_type = SAS_END_DEVICE;
  8352. identify->initiator_port_protocols = SAS_PROTOCOL_STP;
  8353. identify->target_port_protocols = SAS_PROTOCOL_STP;
  8354. phy->minimum_linkrate_hw = SAS_LINK_RATE_UNKNOWN;
  8355. phy->maximum_linkrate_hw = SAS_LINK_RATE_UNKNOWN;
  8356. phy->minimum_linkrate = SAS_LINK_RATE_UNKNOWN;
  8357. phy->maximum_linkrate = SAS_LINK_RATE_UNKNOWN;
  8358. phy->negotiated_linkrate = SAS_LINK_RATE_UNKNOWN;
  8359. rc = sas_phy_add(hpsa_sas_phy->phy);
  8360. if (rc)
  8361. return rc;
  8362. sas_port_add_phy(hpsa_sas_port->port, hpsa_sas_phy->phy);
  8363. list_add_tail(&hpsa_sas_phy->phy_list_entry,
  8364. &hpsa_sas_port->phy_list_head);
  8365. hpsa_sas_phy->added_to_port = true;
  8366. return 0;
  8367. }
  8368. static int
  8369. hpsa_sas_port_add_rphy(struct hpsa_sas_port *hpsa_sas_port,
  8370. struct sas_rphy *rphy)
  8371. {
  8372. struct sas_identify *identify;
  8373. identify = &rphy->identify;
  8374. identify->sas_address = hpsa_sas_port->sas_address;
  8375. identify->initiator_port_protocols = SAS_PROTOCOL_STP;
  8376. identify->target_port_protocols = SAS_PROTOCOL_STP;
  8377. return sas_rphy_add(rphy);
  8378. }
  8379. static struct hpsa_sas_port
  8380. *hpsa_alloc_sas_port(struct hpsa_sas_node *hpsa_sas_node,
  8381. u64 sas_address)
  8382. {
  8383. int rc;
  8384. struct hpsa_sas_port *hpsa_sas_port;
  8385. struct sas_port *port;
  8386. hpsa_sas_port = kzalloc(sizeof(*hpsa_sas_port), GFP_KERNEL);
  8387. if (!hpsa_sas_port)
  8388. return NULL;
  8389. INIT_LIST_HEAD(&hpsa_sas_port->phy_list_head);
  8390. hpsa_sas_port->parent_node = hpsa_sas_node;
  8391. port = sas_port_alloc_num(hpsa_sas_node->parent_dev);
  8392. if (!port)
  8393. goto free_hpsa_port;
  8394. rc = sas_port_add(port);
  8395. if (rc)
  8396. goto free_sas_port;
  8397. hpsa_sas_port->port = port;
  8398. hpsa_sas_port->sas_address = sas_address;
  8399. list_add_tail(&hpsa_sas_port->port_list_entry,
  8400. &hpsa_sas_node->port_list_head);
  8401. return hpsa_sas_port;
  8402. free_sas_port:
  8403. sas_port_free(port);
  8404. free_hpsa_port:
  8405. kfree(hpsa_sas_port);
  8406. return NULL;
  8407. }
  8408. static void hpsa_free_sas_port(struct hpsa_sas_port *hpsa_sas_port)
  8409. {
  8410. struct hpsa_sas_phy *hpsa_sas_phy;
  8411. struct hpsa_sas_phy *next;
  8412. list_for_each_entry_safe(hpsa_sas_phy, next,
  8413. &hpsa_sas_port->phy_list_head, phy_list_entry)
  8414. hpsa_free_sas_phy(hpsa_sas_phy);
  8415. sas_port_delete(hpsa_sas_port->port);
  8416. list_del(&hpsa_sas_port->port_list_entry);
  8417. kfree(hpsa_sas_port);
  8418. }
  8419. static struct hpsa_sas_node *hpsa_alloc_sas_node(struct device *parent_dev)
  8420. {
  8421. struct hpsa_sas_node *hpsa_sas_node;
  8422. hpsa_sas_node = kzalloc(sizeof(*hpsa_sas_node), GFP_KERNEL);
  8423. if (hpsa_sas_node) {
  8424. hpsa_sas_node->parent_dev = parent_dev;
  8425. INIT_LIST_HEAD(&hpsa_sas_node->port_list_head);
  8426. }
  8427. return hpsa_sas_node;
  8428. }
  8429. static void hpsa_free_sas_node(struct hpsa_sas_node *hpsa_sas_node)
  8430. {
  8431. struct hpsa_sas_port *hpsa_sas_port;
  8432. struct hpsa_sas_port *next;
  8433. if (!hpsa_sas_node)
  8434. return;
  8435. list_for_each_entry_safe(hpsa_sas_port, next,
  8436. &hpsa_sas_node->port_list_head, port_list_entry)
  8437. hpsa_free_sas_port(hpsa_sas_port);
  8438. kfree(hpsa_sas_node);
  8439. }
  8440. static struct hpsa_scsi_dev_t
  8441. *hpsa_find_device_by_sas_rphy(struct ctlr_info *h,
  8442. struct sas_rphy *rphy)
  8443. {
  8444. int i;
  8445. struct hpsa_scsi_dev_t *device;
  8446. for (i = 0; i < h->ndevices; i++) {
  8447. device = h->dev[i];
  8448. if (!device->sas_port)
  8449. continue;
  8450. if (device->sas_port->rphy == rphy)
  8451. return device;
  8452. }
  8453. return NULL;
  8454. }
  8455. static int hpsa_add_sas_host(struct ctlr_info *h)
  8456. {
  8457. int rc;
  8458. struct device *parent_dev;
  8459. struct hpsa_sas_node *hpsa_sas_node;
  8460. struct hpsa_sas_port *hpsa_sas_port;
  8461. struct hpsa_sas_phy *hpsa_sas_phy;
  8462. parent_dev = &h->scsi_host->shost_gendev;
  8463. hpsa_sas_node = hpsa_alloc_sas_node(parent_dev);
  8464. if (!hpsa_sas_node)
  8465. return -ENOMEM;
  8466. hpsa_sas_port = hpsa_alloc_sas_port(hpsa_sas_node, h->sas_address);
  8467. if (!hpsa_sas_port) {
  8468. rc = -ENODEV;
  8469. goto free_sas_node;
  8470. }
  8471. hpsa_sas_phy = hpsa_alloc_sas_phy(hpsa_sas_port);
  8472. if (!hpsa_sas_phy) {
  8473. rc = -ENODEV;
  8474. goto free_sas_port;
  8475. }
  8476. rc = hpsa_sas_port_add_phy(hpsa_sas_phy);
  8477. if (rc)
  8478. goto free_sas_phy;
  8479. h->sas_host = hpsa_sas_node;
  8480. return 0;
  8481. free_sas_phy:
  8482. hpsa_free_sas_phy(hpsa_sas_phy);
  8483. free_sas_port:
  8484. hpsa_free_sas_port(hpsa_sas_port);
  8485. free_sas_node:
  8486. hpsa_free_sas_node(hpsa_sas_node);
  8487. return rc;
  8488. }
  8489. static void hpsa_delete_sas_host(struct ctlr_info *h)
  8490. {
  8491. hpsa_free_sas_node(h->sas_host);
  8492. }
  8493. static int hpsa_add_sas_device(struct hpsa_sas_node *hpsa_sas_node,
  8494. struct hpsa_scsi_dev_t *device)
  8495. {
  8496. int rc;
  8497. struct hpsa_sas_port *hpsa_sas_port;
  8498. struct sas_rphy *rphy;
  8499. hpsa_sas_port = hpsa_alloc_sas_port(hpsa_sas_node, device->sas_address);
  8500. if (!hpsa_sas_port)
  8501. return -ENOMEM;
  8502. rphy = sas_end_device_alloc(hpsa_sas_port->port);
  8503. if (!rphy) {
  8504. rc = -ENODEV;
  8505. goto free_sas_port;
  8506. }
  8507. hpsa_sas_port->rphy = rphy;
  8508. device->sas_port = hpsa_sas_port;
  8509. rc = hpsa_sas_port_add_rphy(hpsa_sas_port, rphy);
  8510. if (rc)
  8511. goto free_sas_port;
  8512. return 0;
  8513. free_sas_port:
  8514. hpsa_free_sas_port(hpsa_sas_port);
  8515. device->sas_port = NULL;
  8516. return rc;
  8517. }
  8518. static void hpsa_remove_sas_device(struct hpsa_scsi_dev_t *device)
  8519. {
  8520. if (device->sas_port) {
  8521. hpsa_free_sas_port(device->sas_port);
  8522. device->sas_port = NULL;
  8523. }
  8524. }
  8525. static int
  8526. hpsa_sas_get_linkerrors(struct sas_phy *phy)
  8527. {
  8528. return 0;
  8529. }
  8530. static int
  8531. hpsa_sas_get_enclosure_identifier(struct sas_rphy *rphy, u64 *identifier)
  8532. {
  8533. return 0;
  8534. }
  8535. static int
  8536. hpsa_sas_get_bay_identifier(struct sas_rphy *rphy)
  8537. {
  8538. return -ENXIO;
  8539. }
  8540. static int
  8541. hpsa_sas_phy_reset(struct sas_phy *phy, int hard_reset)
  8542. {
  8543. return 0;
  8544. }
  8545. static int
  8546. hpsa_sas_phy_enable(struct sas_phy *phy, int enable)
  8547. {
  8548. return 0;
  8549. }
  8550. static int
  8551. hpsa_sas_phy_setup(struct sas_phy *phy)
  8552. {
  8553. return 0;
  8554. }
  8555. static void
  8556. hpsa_sas_phy_release(struct sas_phy *phy)
  8557. {
  8558. }
  8559. static int
  8560. hpsa_sas_phy_speed(struct sas_phy *phy, struct sas_phy_linkrates *rates)
  8561. {
  8562. return -EINVAL;
  8563. }
  8564. /* SMP = Serial Management Protocol */
  8565. static int
  8566. hpsa_sas_smp_handler(struct Scsi_Host *shost, struct sas_rphy *rphy,
  8567. struct request *req)
  8568. {
  8569. return -EINVAL;
  8570. }
  8571. static struct sas_function_template hpsa_sas_transport_functions = {
  8572. .get_linkerrors = hpsa_sas_get_linkerrors,
  8573. .get_enclosure_identifier = hpsa_sas_get_enclosure_identifier,
  8574. .get_bay_identifier = hpsa_sas_get_bay_identifier,
  8575. .phy_reset = hpsa_sas_phy_reset,
  8576. .phy_enable = hpsa_sas_phy_enable,
  8577. .phy_setup = hpsa_sas_phy_setup,
  8578. .phy_release = hpsa_sas_phy_release,
  8579. .set_phy_speed = hpsa_sas_phy_speed,
  8580. .smp_handler = hpsa_sas_smp_handler,
  8581. };
  8582. /*
  8583. * This is it. Register the PCI driver information for the cards we control
  8584. * the OS will call our registered routines when it finds one of our cards.
  8585. */
  8586. static int __init hpsa_init(void)
  8587. {
  8588. int rc;
  8589. hpsa_sas_transport_template =
  8590. sas_attach_transport(&hpsa_sas_transport_functions);
  8591. if (!hpsa_sas_transport_template)
  8592. return -ENODEV;
  8593. rc = pci_register_driver(&hpsa_pci_driver);
  8594. if (rc)
  8595. sas_release_transport(hpsa_sas_transport_template);
  8596. return rc;
  8597. }
  8598. static void __exit hpsa_cleanup(void)
  8599. {
  8600. pci_unregister_driver(&hpsa_pci_driver);
  8601. sas_release_transport(hpsa_sas_transport_template);
  8602. }
  8603. static void __attribute__((unused)) verify_offsets(void)
  8604. {
  8605. #define VERIFY_OFFSET(member, offset) \
  8606. BUILD_BUG_ON(offsetof(struct raid_map_data, member) != offset)
  8607. VERIFY_OFFSET(structure_size, 0);
  8608. VERIFY_OFFSET(volume_blk_size, 4);
  8609. VERIFY_OFFSET(volume_blk_cnt, 8);
  8610. VERIFY_OFFSET(phys_blk_shift, 16);
  8611. VERIFY_OFFSET(parity_rotation_shift, 17);
  8612. VERIFY_OFFSET(strip_size, 18);
  8613. VERIFY_OFFSET(disk_starting_blk, 20);
  8614. VERIFY_OFFSET(disk_blk_cnt, 28);
  8615. VERIFY_OFFSET(data_disks_per_row, 36);
  8616. VERIFY_OFFSET(metadata_disks_per_row, 38);
  8617. VERIFY_OFFSET(row_cnt, 40);
  8618. VERIFY_OFFSET(layout_map_count, 42);
  8619. VERIFY_OFFSET(flags, 44);
  8620. VERIFY_OFFSET(dekindex, 46);
  8621. /* VERIFY_OFFSET(reserved, 48 */
  8622. VERIFY_OFFSET(data, 64);
  8623. #undef VERIFY_OFFSET
  8624. #define VERIFY_OFFSET(member, offset) \
  8625. BUILD_BUG_ON(offsetof(struct io_accel2_cmd, member) != offset)
  8626. VERIFY_OFFSET(IU_type, 0);
  8627. VERIFY_OFFSET(direction, 1);
  8628. VERIFY_OFFSET(reply_queue, 2);
  8629. /* VERIFY_OFFSET(reserved1, 3); */
  8630. VERIFY_OFFSET(scsi_nexus, 4);
  8631. VERIFY_OFFSET(Tag, 8);
  8632. VERIFY_OFFSET(cdb, 16);
  8633. VERIFY_OFFSET(cciss_lun, 32);
  8634. VERIFY_OFFSET(data_len, 40);
  8635. VERIFY_OFFSET(cmd_priority_task_attr, 44);
  8636. VERIFY_OFFSET(sg_count, 45);
  8637. /* VERIFY_OFFSET(reserved3 */
  8638. VERIFY_OFFSET(err_ptr, 48);
  8639. VERIFY_OFFSET(err_len, 56);
  8640. /* VERIFY_OFFSET(reserved4 */
  8641. VERIFY_OFFSET(sg, 64);
  8642. #undef VERIFY_OFFSET
  8643. #define VERIFY_OFFSET(member, offset) \
  8644. BUILD_BUG_ON(offsetof(struct io_accel1_cmd, member) != offset)
  8645. VERIFY_OFFSET(dev_handle, 0x00);
  8646. VERIFY_OFFSET(reserved1, 0x02);
  8647. VERIFY_OFFSET(function, 0x03);
  8648. VERIFY_OFFSET(reserved2, 0x04);
  8649. VERIFY_OFFSET(err_info, 0x0C);
  8650. VERIFY_OFFSET(reserved3, 0x10);
  8651. VERIFY_OFFSET(err_info_len, 0x12);
  8652. VERIFY_OFFSET(reserved4, 0x13);
  8653. VERIFY_OFFSET(sgl_offset, 0x14);
  8654. VERIFY_OFFSET(reserved5, 0x15);
  8655. VERIFY_OFFSET(transfer_len, 0x1C);
  8656. VERIFY_OFFSET(reserved6, 0x20);
  8657. VERIFY_OFFSET(io_flags, 0x24);
  8658. VERIFY_OFFSET(reserved7, 0x26);
  8659. VERIFY_OFFSET(LUN, 0x34);
  8660. VERIFY_OFFSET(control, 0x3C);
  8661. VERIFY_OFFSET(CDB, 0x40);
  8662. VERIFY_OFFSET(reserved8, 0x50);
  8663. VERIFY_OFFSET(host_context_flags, 0x60);
  8664. VERIFY_OFFSET(timeout_sec, 0x62);
  8665. VERIFY_OFFSET(ReplyQueue, 0x64);
  8666. VERIFY_OFFSET(reserved9, 0x65);
  8667. VERIFY_OFFSET(tag, 0x68);
  8668. VERIFY_OFFSET(host_addr, 0x70);
  8669. VERIFY_OFFSET(CISS_LUN, 0x78);
  8670. VERIFY_OFFSET(SG, 0x78 + 8);
  8671. #undef VERIFY_OFFSET
  8672. }
  8673. module_init(hpsa_init);
  8674. module_exit(hpsa_cleanup);