spi-xtensa-xtfpga.c 4.0 KB

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  1. /*
  2. * Xtensa xtfpga SPI controller driver
  3. *
  4. * Copyright (c) 2014 Cadence Design Systems Inc.
  5. *
  6. * This program is free software; you can redistribute it and/or modify
  7. * it under the terms of the GNU General Public License version 2 as
  8. * published by the Free Software Foundation.
  9. */
  10. #include <linux/delay.h>
  11. #include <linux/io.h>
  12. #include <linux/module.h>
  13. #include <linux/of.h>
  14. #include <linux/platform_device.h>
  15. #include <linux/spi/spi.h>
  16. #include <linux/spi/spi_bitbang.h>
  17. #define XTFPGA_SPI_NAME "xtfpga_spi"
  18. #define XTFPGA_SPI_START 0x0
  19. #define XTFPGA_SPI_BUSY 0x4
  20. #define XTFPGA_SPI_DATA 0x8
  21. #define BUSY_WAIT_US 100
  22. struct xtfpga_spi {
  23. struct spi_bitbang bitbang;
  24. void __iomem *regs;
  25. u32 data;
  26. unsigned data_sz;
  27. };
  28. static inline void xtfpga_spi_write32(const struct xtfpga_spi *spi,
  29. unsigned addr, u32 val)
  30. {
  31. __raw_writel(val, spi->regs + addr);
  32. }
  33. static inline unsigned int xtfpga_spi_read32(const struct xtfpga_spi *spi,
  34. unsigned addr)
  35. {
  36. return __raw_readl(spi->regs + addr);
  37. }
  38. static inline void xtfpga_spi_wait_busy(struct xtfpga_spi *xspi)
  39. {
  40. unsigned i;
  41. for (i = 0; xtfpga_spi_read32(xspi, XTFPGA_SPI_BUSY) &&
  42. i < BUSY_WAIT_US; ++i)
  43. udelay(1);
  44. WARN_ON_ONCE(i == BUSY_WAIT_US);
  45. }
  46. static u32 xtfpga_spi_txrx_word(struct spi_device *spi, unsigned nsecs,
  47. u32 v, u8 bits)
  48. {
  49. struct xtfpga_spi *xspi = spi_master_get_devdata(spi->master);
  50. xspi->data = (xspi->data << bits) | (v & GENMASK(bits - 1, 0));
  51. xspi->data_sz += bits;
  52. if (xspi->data_sz >= 16) {
  53. xtfpga_spi_write32(xspi, XTFPGA_SPI_DATA,
  54. xspi->data >> (xspi->data_sz - 16));
  55. xspi->data_sz -= 16;
  56. xtfpga_spi_write32(xspi, XTFPGA_SPI_START, 1);
  57. xtfpga_spi_wait_busy(xspi);
  58. xtfpga_spi_write32(xspi, XTFPGA_SPI_START, 0);
  59. }
  60. return 0;
  61. }
  62. static void xtfpga_spi_chipselect(struct spi_device *spi, int is_on)
  63. {
  64. struct xtfpga_spi *xspi = spi_master_get_devdata(spi->master);
  65. WARN_ON(xspi->data_sz != 0);
  66. xspi->data_sz = 0;
  67. }
  68. static int xtfpga_spi_probe(struct platform_device *pdev)
  69. {
  70. struct xtfpga_spi *xspi;
  71. struct resource *mem;
  72. int ret;
  73. struct spi_master *master;
  74. master = spi_alloc_master(&pdev->dev, sizeof(struct xtfpga_spi));
  75. if (!master)
  76. return -ENOMEM;
  77. master->flags = SPI_MASTER_NO_RX;
  78. master->bits_per_word_mask = SPI_BPW_RANGE_MASK(1, 16);
  79. master->bus_num = pdev->dev.id;
  80. master->dev.of_node = pdev->dev.of_node;
  81. xspi = spi_master_get_devdata(master);
  82. xspi->bitbang.master = master;
  83. xspi->bitbang.chipselect = xtfpga_spi_chipselect;
  84. xspi->bitbang.txrx_word[SPI_MODE_0] = xtfpga_spi_txrx_word;
  85. mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  86. if (!mem) {
  87. dev_err(&pdev->dev, "No memory resource\n");
  88. ret = -ENODEV;
  89. goto err;
  90. }
  91. xspi->regs = devm_ioremap_resource(&pdev->dev, mem);
  92. if (IS_ERR(xspi->regs)) {
  93. ret = PTR_ERR(xspi->regs);
  94. goto err;
  95. }
  96. xtfpga_spi_write32(xspi, XTFPGA_SPI_START, 0);
  97. usleep_range(1000, 2000);
  98. if (xtfpga_spi_read32(xspi, XTFPGA_SPI_BUSY)) {
  99. dev_err(&pdev->dev, "Device stuck in busy state\n");
  100. ret = -EBUSY;
  101. goto err;
  102. }
  103. ret = spi_bitbang_start(&xspi->bitbang);
  104. if (ret < 0) {
  105. dev_err(&pdev->dev, "spi_bitbang_start failed\n");
  106. goto err;
  107. }
  108. platform_set_drvdata(pdev, master);
  109. return 0;
  110. err:
  111. spi_master_put(master);
  112. return ret;
  113. }
  114. static int xtfpga_spi_remove(struct platform_device *pdev)
  115. {
  116. struct spi_master *master = platform_get_drvdata(pdev);
  117. struct xtfpga_spi *xspi = spi_master_get_devdata(master);
  118. spi_bitbang_stop(&xspi->bitbang);
  119. spi_master_put(master);
  120. return 0;
  121. }
  122. MODULE_ALIAS("platform:" XTFPGA_SPI_NAME);
  123. #ifdef CONFIG_OF
  124. static const struct of_device_id xtfpga_spi_of_match[] = {
  125. { .compatible = "cdns,xtfpga-spi", },
  126. {}
  127. };
  128. MODULE_DEVICE_TABLE(of, xtfpga_spi_of_match);
  129. #endif
  130. static struct platform_driver xtfpga_spi_driver = {
  131. .probe = xtfpga_spi_probe,
  132. .remove = xtfpga_spi_remove,
  133. .driver = {
  134. .name = XTFPGA_SPI_NAME,
  135. .of_match_table = of_match_ptr(xtfpga_spi_of_match),
  136. },
  137. };
  138. module_platform_driver(xtfpga_spi_driver);
  139. MODULE_AUTHOR("Max Filippov <jcmvbkbc@gmail.com>");
  140. MODULE_DESCRIPTION("xtensa xtfpga SPI driver");
  141. MODULE_LICENSE("GPL");