driver_chipcommon_pmu.c 22 KB

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  1. /*
  2. * Sonics Silicon Backplane
  3. * Broadcom ChipCommon Power Management Unit driver
  4. *
  5. * Copyright 2009, Michael Buesch <m@bues.ch>
  6. * Copyright 2007, Broadcom Corporation
  7. *
  8. * Licensed under the GNU/GPL. See COPYING for details.
  9. */
  10. #include <linux/ssb/ssb.h>
  11. #include <linux/ssb/ssb_regs.h>
  12. #include <linux/ssb/ssb_driver_chipcommon.h>
  13. #include <linux/delay.h>
  14. #include <linux/export.h>
  15. #ifdef CONFIG_BCM47XX
  16. #include <linux/bcm47xx_nvram.h>
  17. #endif
  18. #include "ssb_private.h"
  19. static u32 ssb_chipco_pll_read(struct ssb_chipcommon *cc, u32 offset)
  20. {
  21. chipco_write32(cc, SSB_CHIPCO_PLLCTL_ADDR, offset);
  22. return chipco_read32(cc, SSB_CHIPCO_PLLCTL_DATA);
  23. }
  24. static void ssb_chipco_pll_write(struct ssb_chipcommon *cc,
  25. u32 offset, u32 value)
  26. {
  27. chipco_write32(cc, SSB_CHIPCO_PLLCTL_ADDR, offset);
  28. chipco_write32(cc, SSB_CHIPCO_PLLCTL_DATA, value);
  29. }
  30. static void ssb_chipco_regctl_maskset(struct ssb_chipcommon *cc,
  31. u32 offset, u32 mask, u32 set)
  32. {
  33. u32 value;
  34. chipco_read32(cc, SSB_CHIPCO_REGCTL_ADDR);
  35. chipco_write32(cc, SSB_CHIPCO_REGCTL_ADDR, offset);
  36. chipco_read32(cc, SSB_CHIPCO_REGCTL_ADDR);
  37. value = chipco_read32(cc, SSB_CHIPCO_REGCTL_DATA);
  38. value &= mask;
  39. value |= set;
  40. chipco_write32(cc, SSB_CHIPCO_REGCTL_DATA, value);
  41. chipco_read32(cc, SSB_CHIPCO_REGCTL_DATA);
  42. }
  43. struct pmu0_plltab_entry {
  44. u16 freq; /* Crystal frequency in kHz.*/
  45. u8 xf; /* Crystal frequency value for PMU control */
  46. u8 wb_int;
  47. u32 wb_frac;
  48. };
  49. static const struct pmu0_plltab_entry pmu0_plltab[] = {
  50. { .freq = 12000, .xf = 1, .wb_int = 73, .wb_frac = 349525, },
  51. { .freq = 13000, .xf = 2, .wb_int = 67, .wb_frac = 725937, },
  52. { .freq = 14400, .xf = 3, .wb_int = 61, .wb_frac = 116508, },
  53. { .freq = 15360, .xf = 4, .wb_int = 57, .wb_frac = 305834, },
  54. { .freq = 16200, .xf = 5, .wb_int = 54, .wb_frac = 336579, },
  55. { .freq = 16800, .xf = 6, .wb_int = 52, .wb_frac = 399457, },
  56. { .freq = 19200, .xf = 7, .wb_int = 45, .wb_frac = 873813, },
  57. { .freq = 19800, .xf = 8, .wb_int = 44, .wb_frac = 466033, },
  58. { .freq = 20000, .xf = 9, .wb_int = 44, .wb_frac = 0, },
  59. { .freq = 25000, .xf = 10, .wb_int = 70, .wb_frac = 419430, },
  60. { .freq = 26000, .xf = 11, .wb_int = 67, .wb_frac = 725937, },
  61. { .freq = 30000, .xf = 12, .wb_int = 58, .wb_frac = 699050, },
  62. { .freq = 38400, .xf = 13, .wb_int = 45, .wb_frac = 873813, },
  63. { .freq = 40000, .xf = 14, .wb_int = 45, .wb_frac = 0, },
  64. };
  65. #define SSB_PMU0_DEFAULT_XTALFREQ 20000
  66. static const struct pmu0_plltab_entry * pmu0_plltab_find_entry(u32 crystalfreq)
  67. {
  68. const struct pmu0_plltab_entry *e;
  69. unsigned int i;
  70. for (i = 0; i < ARRAY_SIZE(pmu0_plltab); i++) {
  71. e = &pmu0_plltab[i];
  72. if (e->freq == crystalfreq)
  73. return e;
  74. }
  75. return NULL;
  76. }
  77. /* Tune the PLL to the crystal speed. crystalfreq is in kHz. */
  78. static void ssb_pmu0_pllinit_r0(struct ssb_chipcommon *cc,
  79. u32 crystalfreq)
  80. {
  81. struct ssb_bus *bus = cc->dev->bus;
  82. const struct pmu0_plltab_entry *e = NULL;
  83. u32 pmuctl, tmp, pllctl;
  84. unsigned int i;
  85. if (crystalfreq)
  86. e = pmu0_plltab_find_entry(crystalfreq);
  87. if (!e)
  88. e = pmu0_plltab_find_entry(SSB_PMU0_DEFAULT_XTALFREQ);
  89. BUG_ON(!e);
  90. crystalfreq = e->freq;
  91. cc->pmu.crystalfreq = e->freq;
  92. /* Check if the PLL already is programmed to this frequency. */
  93. pmuctl = chipco_read32(cc, SSB_CHIPCO_PMU_CTL);
  94. if (((pmuctl & SSB_CHIPCO_PMU_CTL_XTALFREQ) >> SSB_CHIPCO_PMU_CTL_XTALFREQ_SHIFT) == e->xf) {
  95. /* We're already there... */
  96. return;
  97. }
  98. ssb_info("Programming PLL to %u.%03u MHz\n",
  99. crystalfreq / 1000, crystalfreq % 1000);
  100. /* First turn the PLL off. */
  101. switch (bus->chip_id) {
  102. case 0x4328:
  103. chipco_mask32(cc, SSB_CHIPCO_PMU_MINRES_MSK,
  104. ~(1 << SSB_PMURES_4328_BB_PLL_PU));
  105. chipco_mask32(cc, SSB_CHIPCO_PMU_MAXRES_MSK,
  106. ~(1 << SSB_PMURES_4328_BB_PLL_PU));
  107. break;
  108. case 0x5354:
  109. chipco_mask32(cc, SSB_CHIPCO_PMU_MINRES_MSK,
  110. ~(1 << SSB_PMURES_5354_BB_PLL_PU));
  111. chipco_mask32(cc, SSB_CHIPCO_PMU_MAXRES_MSK,
  112. ~(1 << SSB_PMURES_5354_BB_PLL_PU));
  113. break;
  114. default:
  115. SSB_WARN_ON(1);
  116. }
  117. for (i = 1500; i; i--) {
  118. tmp = chipco_read32(cc, SSB_CHIPCO_CLKCTLST);
  119. if (!(tmp & SSB_CHIPCO_CLKCTLST_HAVEHT))
  120. break;
  121. udelay(10);
  122. }
  123. tmp = chipco_read32(cc, SSB_CHIPCO_CLKCTLST);
  124. if (tmp & SSB_CHIPCO_CLKCTLST_HAVEHT)
  125. ssb_emerg("Failed to turn the PLL off!\n");
  126. /* Set PDIV in PLL control 0. */
  127. pllctl = ssb_chipco_pll_read(cc, SSB_PMU0_PLLCTL0);
  128. if (crystalfreq >= SSB_PMU0_PLLCTL0_PDIV_FREQ)
  129. pllctl |= SSB_PMU0_PLLCTL0_PDIV_MSK;
  130. else
  131. pllctl &= ~SSB_PMU0_PLLCTL0_PDIV_MSK;
  132. ssb_chipco_pll_write(cc, SSB_PMU0_PLLCTL0, pllctl);
  133. /* Set WILD in PLL control 1. */
  134. pllctl = ssb_chipco_pll_read(cc, SSB_PMU0_PLLCTL1);
  135. pllctl &= ~SSB_PMU0_PLLCTL1_STOPMOD;
  136. pllctl &= ~(SSB_PMU0_PLLCTL1_WILD_IMSK | SSB_PMU0_PLLCTL1_WILD_FMSK);
  137. pllctl |= ((u32)e->wb_int << SSB_PMU0_PLLCTL1_WILD_IMSK_SHIFT) & SSB_PMU0_PLLCTL1_WILD_IMSK;
  138. pllctl |= ((u32)e->wb_frac << SSB_PMU0_PLLCTL1_WILD_FMSK_SHIFT) & SSB_PMU0_PLLCTL1_WILD_FMSK;
  139. if (e->wb_frac == 0)
  140. pllctl |= SSB_PMU0_PLLCTL1_STOPMOD;
  141. ssb_chipco_pll_write(cc, SSB_PMU0_PLLCTL1, pllctl);
  142. /* Set WILD in PLL control 2. */
  143. pllctl = ssb_chipco_pll_read(cc, SSB_PMU0_PLLCTL2);
  144. pllctl &= ~SSB_PMU0_PLLCTL2_WILD_IMSKHI;
  145. pllctl |= (((u32)e->wb_int >> 4) << SSB_PMU0_PLLCTL2_WILD_IMSKHI_SHIFT) & SSB_PMU0_PLLCTL2_WILD_IMSKHI;
  146. ssb_chipco_pll_write(cc, SSB_PMU0_PLLCTL2, pllctl);
  147. /* Set the crystalfrequency and the divisor. */
  148. pmuctl = chipco_read32(cc, SSB_CHIPCO_PMU_CTL);
  149. pmuctl &= ~SSB_CHIPCO_PMU_CTL_ILP_DIV;
  150. pmuctl |= (((crystalfreq + 127) / 128 - 1) << SSB_CHIPCO_PMU_CTL_ILP_DIV_SHIFT)
  151. & SSB_CHIPCO_PMU_CTL_ILP_DIV;
  152. pmuctl &= ~SSB_CHIPCO_PMU_CTL_XTALFREQ;
  153. pmuctl |= ((u32)e->xf << SSB_CHIPCO_PMU_CTL_XTALFREQ_SHIFT) & SSB_CHIPCO_PMU_CTL_XTALFREQ;
  154. chipco_write32(cc, SSB_CHIPCO_PMU_CTL, pmuctl);
  155. }
  156. struct pmu1_plltab_entry {
  157. u16 freq; /* Crystal frequency in kHz.*/
  158. u8 xf; /* Crystal frequency value for PMU control */
  159. u8 ndiv_int;
  160. u32 ndiv_frac;
  161. u8 p1div;
  162. u8 p2div;
  163. };
  164. static const struct pmu1_plltab_entry pmu1_plltab[] = {
  165. { .freq = 12000, .xf = 1, .p1div = 3, .p2div = 22, .ndiv_int = 0x9, .ndiv_frac = 0xFFFFEF, },
  166. { .freq = 13000, .xf = 2, .p1div = 1, .p2div = 6, .ndiv_int = 0xb, .ndiv_frac = 0x483483, },
  167. { .freq = 14400, .xf = 3, .p1div = 1, .p2div = 10, .ndiv_int = 0xa, .ndiv_frac = 0x1C71C7, },
  168. { .freq = 15360, .xf = 4, .p1div = 1, .p2div = 5, .ndiv_int = 0xb, .ndiv_frac = 0x755555, },
  169. { .freq = 16200, .xf = 5, .p1div = 1, .p2div = 10, .ndiv_int = 0x5, .ndiv_frac = 0x6E9E06, },
  170. { .freq = 16800, .xf = 6, .p1div = 1, .p2div = 10, .ndiv_int = 0x5, .ndiv_frac = 0x3CF3CF, },
  171. { .freq = 19200, .xf = 7, .p1div = 1, .p2div = 9, .ndiv_int = 0x5, .ndiv_frac = 0x17B425, },
  172. { .freq = 19800, .xf = 8, .p1div = 1, .p2div = 11, .ndiv_int = 0x4, .ndiv_frac = 0xA57EB, },
  173. { .freq = 20000, .xf = 9, .p1div = 1, .p2div = 11, .ndiv_int = 0x4, .ndiv_frac = 0, },
  174. { .freq = 24000, .xf = 10, .p1div = 3, .p2div = 11, .ndiv_int = 0xa, .ndiv_frac = 0, },
  175. { .freq = 25000, .xf = 11, .p1div = 5, .p2div = 16, .ndiv_int = 0xb, .ndiv_frac = 0, },
  176. { .freq = 26000, .xf = 12, .p1div = 1, .p2div = 2, .ndiv_int = 0x10, .ndiv_frac = 0xEC4EC4, },
  177. { .freq = 30000, .xf = 13, .p1div = 3, .p2div = 8, .ndiv_int = 0xb, .ndiv_frac = 0, },
  178. { .freq = 38400, .xf = 14, .p1div = 1, .p2div = 5, .ndiv_int = 0x4, .ndiv_frac = 0x955555, },
  179. { .freq = 40000, .xf = 15, .p1div = 1, .p2div = 2, .ndiv_int = 0xb, .ndiv_frac = 0, },
  180. };
  181. #define SSB_PMU1_DEFAULT_XTALFREQ 15360
  182. static const struct pmu1_plltab_entry * pmu1_plltab_find_entry(u32 crystalfreq)
  183. {
  184. const struct pmu1_plltab_entry *e;
  185. unsigned int i;
  186. for (i = 0; i < ARRAY_SIZE(pmu1_plltab); i++) {
  187. e = &pmu1_plltab[i];
  188. if (e->freq == crystalfreq)
  189. return e;
  190. }
  191. return NULL;
  192. }
  193. /* Tune the PLL to the crystal speed. crystalfreq is in kHz. */
  194. static void ssb_pmu1_pllinit_r0(struct ssb_chipcommon *cc,
  195. u32 crystalfreq)
  196. {
  197. struct ssb_bus *bus = cc->dev->bus;
  198. const struct pmu1_plltab_entry *e = NULL;
  199. u32 buffer_strength = 0;
  200. u32 tmp, pllctl, pmuctl;
  201. unsigned int i;
  202. if (bus->chip_id == 0x4312) {
  203. /* We do not touch the BCM4312 PLL and assume
  204. * the default crystal settings work out-of-the-box. */
  205. cc->pmu.crystalfreq = 20000;
  206. return;
  207. }
  208. if (crystalfreq)
  209. e = pmu1_plltab_find_entry(crystalfreq);
  210. if (!e)
  211. e = pmu1_plltab_find_entry(SSB_PMU1_DEFAULT_XTALFREQ);
  212. BUG_ON(!e);
  213. crystalfreq = e->freq;
  214. cc->pmu.crystalfreq = e->freq;
  215. /* Check if the PLL already is programmed to this frequency. */
  216. pmuctl = chipco_read32(cc, SSB_CHIPCO_PMU_CTL);
  217. if (((pmuctl & SSB_CHIPCO_PMU_CTL_XTALFREQ) >> SSB_CHIPCO_PMU_CTL_XTALFREQ_SHIFT) == e->xf) {
  218. /* We're already there... */
  219. return;
  220. }
  221. ssb_info("Programming PLL to %u.%03u MHz\n",
  222. crystalfreq / 1000, crystalfreq % 1000);
  223. /* First turn the PLL off. */
  224. switch (bus->chip_id) {
  225. case 0x4325:
  226. chipco_mask32(cc, SSB_CHIPCO_PMU_MINRES_MSK,
  227. ~((1 << SSB_PMURES_4325_BBPLL_PWRSW_PU) |
  228. (1 << SSB_PMURES_4325_HT_AVAIL)));
  229. chipco_mask32(cc, SSB_CHIPCO_PMU_MAXRES_MSK,
  230. ~((1 << SSB_PMURES_4325_BBPLL_PWRSW_PU) |
  231. (1 << SSB_PMURES_4325_HT_AVAIL)));
  232. /* Adjust the BBPLL to 2 on all channels later. */
  233. buffer_strength = 0x222222;
  234. break;
  235. default:
  236. SSB_WARN_ON(1);
  237. }
  238. for (i = 1500; i; i--) {
  239. tmp = chipco_read32(cc, SSB_CHIPCO_CLKCTLST);
  240. if (!(tmp & SSB_CHIPCO_CLKCTLST_HAVEHT))
  241. break;
  242. udelay(10);
  243. }
  244. tmp = chipco_read32(cc, SSB_CHIPCO_CLKCTLST);
  245. if (tmp & SSB_CHIPCO_CLKCTLST_HAVEHT)
  246. ssb_emerg("Failed to turn the PLL off!\n");
  247. /* Set p1div and p2div. */
  248. pllctl = ssb_chipco_pll_read(cc, SSB_PMU1_PLLCTL0);
  249. pllctl &= ~(SSB_PMU1_PLLCTL0_P1DIV | SSB_PMU1_PLLCTL0_P2DIV);
  250. pllctl |= ((u32)e->p1div << SSB_PMU1_PLLCTL0_P1DIV_SHIFT) & SSB_PMU1_PLLCTL0_P1DIV;
  251. pllctl |= ((u32)e->p2div << SSB_PMU1_PLLCTL0_P2DIV_SHIFT) & SSB_PMU1_PLLCTL0_P2DIV;
  252. ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL0, pllctl);
  253. /* Set ndiv int and ndiv mode */
  254. pllctl = ssb_chipco_pll_read(cc, SSB_PMU1_PLLCTL2);
  255. pllctl &= ~(SSB_PMU1_PLLCTL2_NDIVINT | SSB_PMU1_PLLCTL2_NDIVMODE);
  256. pllctl |= ((u32)e->ndiv_int << SSB_PMU1_PLLCTL2_NDIVINT_SHIFT) & SSB_PMU1_PLLCTL2_NDIVINT;
  257. pllctl |= (1 << SSB_PMU1_PLLCTL2_NDIVMODE_SHIFT) & SSB_PMU1_PLLCTL2_NDIVMODE;
  258. ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL2, pllctl);
  259. /* Set ndiv frac */
  260. pllctl = ssb_chipco_pll_read(cc, SSB_PMU1_PLLCTL3);
  261. pllctl &= ~SSB_PMU1_PLLCTL3_NDIVFRAC;
  262. pllctl |= ((u32)e->ndiv_frac << SSB_PMU1_PLLCTL3_NDIVFRAC_SHIFT) & SSB_PMU1_PLLCTL3_NDIVFRAC;
  263. ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL3, pllctl);
  264. /* Change the drive strength, if required. */
  265. if (buffer_strength) {
  266. pllctl = ssb_chipco_pll_read(cc, SSB_PMU1_PLLCTL5);
  267. pllctl &= ~SSB_PMU1_PLLCTL5_CLKDRV;
  268. pllctl |= (buffer_strength << SSB_PMU1_PLLCTL5_CLKDRV_SHIFT) & SSB_PMU1_PLLCTL5_CLKDRV;
  269. ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL5, pllctl);
  270. }
  271. /* Tune the crystalfreq and the divisor. */
  272. pmuctl = chipco_read32(cc, SSB_CHIPCO_PMU_CTL);
  273. pmuctl &= ~(SSB_CHIPCO_PMU_CTL_ILP_DIV | SSB_CHIPCO_PMU_CTL_XTALFREQ);
  274. pmuctl |= ((((u32)e->freq + 127) / 128 - 1) << SSB_CHIPCO_PMU_CTL_ILP_DIV_SHIFT)
  275. & SSB_CHIPCO_PMU_CTL_ILP_DIV;
  276. pmuctl |= ((u32)e->xf << SSB_CHIPCO_PMU_CTL_XTALFREQ_SHIFT) & SSB_CHIPCO_PMU_CTL_XTALFREQ;
  277. chipco_write32(cc, SSB_CHIPCO_PMU_CTL, pmuctl);
  278. }
  279. static void ssb_pmu_pll_init(struct ssb_chipcommon *cc)
  280. {
  281. struct ssb_bus *bus = cc->dev->bus;
  282. u32 crystalfreq = 0; /* in kHz. 0 = keep default freq. */
  283. if (bus->bustype == SSB_BUSTYPE_SSB) {
  284. #ifdef CONFIG_BCM47XX
  285. char buf[20];
  286. if (bcm47xx_nvram_getenv("xtalfreq", buf, sizeof(buf)) >= 0)
  287. crystalfreq = simple_strtoul(buf, NULL, 0);
  288. #endif
  289. }
  290. switch (bus->chip_id) {
  291. case 0x4312:
  292. case 0x4325:
  293. ssb_pmu1_pllinit_r0(cc, crystalfreq);
  294. break;
  295. case 0x4328:
  296. ssb_pmu0_pllinit_r0(cc, crystalfreq);
  297. break;
  298. case 0x5354:
  299. if (crystalfreq == 0)
  300. crystalfreq = 25000;
  301. ssb_pmu0_pllinit_r0(cc, crystalfreq);
  302. break;
  303. case 0x4322:
  304. if (cc->pmu.rev == 2) {
  305. chipco_write32(cc, SSB_CHIPCO_PLLCTL_ADDR, 0x0000000A);
  306. chipco_write32(cc, SSB_CHIPCO_PLLCTL_DATA, 0x380005C0);
  307. }
  308. break;
  309. case 43222:
  310. break;
  311. default:
  312. ssb_err("ERROR: PLL init unknown for device %04X\n",
  313. bus->chip_id);
  314. }
  315. }
  316. struct pmu_res_updown_tab_entry {
  317. u8 resource; /* The resource number */
  318. u16 updown; /* The updown value */
  319. };
  320. enum pmu_res_depend_tab_task {
  321. PMU_RES_DEP_SET = 1,
  322. PMU_RES_DEP_ADD,
  323. PMU_RES_DEP_REMOVE,
  324. };
  325. struct pmu_res_depend_tab_entry {
  326. u8 resource; /* The resource number */
  327. u8 task; /* SET | ADD | REMOVE */
  328. u32 depend; /* The depend mask */
  329. };
  330. static const struct pmu_res_updown_tab_entry pmu_res_updown_tab_4328a0[] = {
  331. { .resource = SSB_PMURES_4328_EXT_SWITCHER_PWM, .updown = 0x0101, },
  332. { .resource = SSB_PMURES_4328_BB_SWITCHER_PWM, .updown = 0x1F01, },
  333. { .resource = SSB_PMURES_4328_BB_SWITCHER_BURST, .updown = 0x010F, },
  334. { .resource = SSB_PMURES_4328_BB_EXT_SWITCHER_BURST, .updown = 0x0101, },
  335. { .resource = SSB_PMURES_4328_ILP_REQUEST, .updown = 0x0202, },
  336. { .resource = SSB_PMURES_4328_RADIO_SWITCHER_PWM, .updown = 0x0F01, },
  337. { .resource = SSB_PMURES_4328_RADIO_SWITCHER_BURST, .updown = 0x0F01, },
  338. { .resource = SSB_PMURES_4328_ROM_SWITCH, .updown = 0x0101, },
  339. { .resource = SSB_PMURES_4328_PA_REF_LDO, .updown = 0x0F01, },
  340. { .resource = SSB_PMURES_4328_RADIO_LDO, .updown = 0x0F01, },
  341. { .resource = SSB_PMURES_4328_AFE_LDO, .updown = 0x0F01, },
  342. { .resource = SSB_PMURES_4328_PLL_LDO, .updown = 0x0F01, },
  343. { .resource = SSB_PMURES_4328_BG_FILTBYP, .updown = 0x0101, },
  344. { .resource = SSB_PMURES_4328_TX_FILTBYP, .updown = 0x0101, },
  345. { .resource = SSB_PMURES_4328_RX_FILTBYP, .updown = 0x0101, },
  346. { .resource = SSB_PMURES_4328_XTAL_PU, .updown = 0x0101, },
  347. { .resource = SSB_PMURES_4328_XTAL_EN, .updown = 0xA001, },
  348. { .resource = SSB_PMURES_4328_BB_PLL_FILTBYP, .updown = 0x0101, },
  349. { .resource = SSB_PMURES_4328_RF_PLL_FILTBYP, .updown = 0x0101, },
  350. { .resource = SSB_PMURES_4328_BB_PLL_PU, .updown = 0x0701, },
  351. };
  352. static const struct pmu_res_depend_tab_entry pmu_res_depend_tab_4328a0[] = {
  353. {
  354. /* Adjust ILP Request to avoid forcing EXT/BB into burst mode. */
  355. .resource = SSB_PMURES_4328_ILP_REQUEST,
  356. .task = PMU_RES_DEP_SET,
  357. .depend = ((1 << SSB_PMURES_4328_EXT_SWITCHER_PWM) |
  358. (1 << SSB_PMURES_4328_BB_SWITCHER_PWM)),
  359. },
  360. };
  361. static const struct pmu_res_updown_tab_entry pmu_res_updown_tab_4325a0[] = {
  362. { .resource = SSB_PMURES_4325_XTAL_PU, .updown = 0x1501, },
  363. };
  364. static const struct pmu_res_depend_tab_entry pmu_res_depend_tab_4325a0[] = {
  365. {
  366. /* Adjust HT-Available dependencies. */
  367. .resource = SSB_PMURES_4325_HT_AVAIL,
  368. .task = PMU_RES_DEP_ADD,
  369. .depend = ((1 << SSB_PMURES_4325_RX_PWRSW_PU) |
  370. (1 << SSB_PMURES_4325_TX_PWRSW_PU) |
  371. (1 << SSB_PMURES_4325_LOGEN_PWRSW_PU) |
  372. (1 << SSB_PMURES_4325_AFE_PWRSW_PU)),
  373. },
  374. };
  375. static void ssb_pmu_resources_init(struct ssb_chipcommon *cc)
  376. {
  377. struct ssb_bus *bus = cc->dev->bus;
  378. u32 min_msk = 0, max_msk = 0;
  379. unsigned int i;
  380. const struct pmu_res_updown_tab_entry *updown_tab = NULL;
  381. unsigned int updown_tab_size = 0;
  382. const struct pmu_res_depend_tab_entry *depend_tab = NULL;
  383. unsigned int depend_tab_size = 0;
  384. switch (bus->chip_id) {
  385. case 0x4312:
  386. min_msk = 0xCBB;
  387. break;
  388. case 0x4322:
  389. case 43222:
  390. /* We keep the default settings:
  391. * min_msk = 0xCBB
  392. * max_msk = 0x7FFFF
  393. */
  394. break;
  395. case 0x4325:
  396. /* Power OTP down later. */
  397. min_msk = (1 << SSB_PMURES_4325_CBUCK_BURST) |
  398. (1 << SSB_PMURES_4325_LNLDO2_PU);
  399. if (chipco_read32(cc, SSB_CHIPCO_CHIPSTAT) &
  400. SSB_CHIPCO_CHST_4325_PMUTOP_2B)
  401. min_msk |= (1 << SSB_PMURES_4325_CLDO_CBUCK_BURST);
  402. /* The PLL may turn on, if it decides so. */
  403. max_msk = 0xFFFFF;
  404. updown_tab = pmu_res_updown_tab_4325a0;
  405. updown_tab_size = ARRAY_SIZE(pmu_res_updown_tab_4325a0);
  406. depend_tab = pmu_res_depend_tab_4325a0;
  407. depend_tab_size = ARRAY_SIZE(pmu_res_depend_tab_4325a0);
  408. break;
  409. case 0x4328:
  410. min_msk = (1 << SSB_PMURES_4328_EXT_SWITCHER_PWM) |
  411. (1 << SSB_PMURES_4328_BB_SWITCHER_PWM) |
  412. (1 << SSB_PMURES_4328_XTAL_EN);
  413. /* The PLL may turn on, if it decides so. */
  414. max_msk = 0xFFFFF;
  415. updown_tab = pmu_res_updown_tab_4328a0;
  416. updown_tab_size = ARRAY_SIZE(pmu_res_updown_tab_4328a0);
  417. depend_tab = pmu_res_depend_tab_4328a0;
  418. depend_tab_size = ARRAY_SIZE(pmu_res_depend_tab_4328a0);
  419. break;
  420. case 0x5354:
  421. /* The PLL may turn on, if it decides so. */
  422. max_msk = 0xFFFFF;
  423. break;
  424. default:
  425. ssb_err("ERROR: PMU resource config unknown for device %04X\n",
  426. bus->chip_id);
  427. }
  428. if (updown_tab) {
  429. for (i = 0; i < updown_tab_size; i++) {
  430. chipco_write32(cc, SSB_CHIPCO_PMU_RES_TABSEL,
  431. updown_tab[i].resource);
  432. chipco_write32(cc, SSB_CHIPCO_PMU_RES_UPDNTM,
  433. updown_tab[i].updown);
  434. }
  435. }
  436. if (depend_tab) {
  437. for (i = 0; i < depend_tab_size; i++) {
  438. chipco_write32(cc, SSB_CHIPCO_PMU_RES_TABSEL,
  439. depend_tab[i].resource);
  440. switch (depend_tab[i].task) {
  441. case PMU_RES_DEP_SET:
  442. chipco_write32(cc, SSB_CHIPCO_PMU_RES_DEPMSK,
  443. depend_tab[i].depend);
  444. break;
  445. case PMU_RES_DEP_ADD:
  446. chipco_set32(cc, SSB_CHIPCO_PMU_RES_DEPMSK,
  447. depend_tab[i].depend);
  448. break;
  449. case PMU_RES_DEP_REMOVE:
  450. chipco_mask32(cc, SSB_CHIPCO_PMU_RES_DEPMSK,
  451. ~(depend_tab[i].depend));
  452. break;
  453. default:
  454. SSB_WARN_ON(1);
  455. }
  456. }
  457. }
  458. /* Set the resource masks. */
  459. if (min_msk)
  460. chipco_write32(cc, SSB_CHIPCO_PMU_MINRES_MSK, min_msk);
  461. if (max_msk)
  462. chipco_write32(cc, SSB_CHIPCO_PMU_MAXRES_MSK, max_msk);
  463. }
  464. /* http://bcm-v4.sipsolutions.net/802.11/SSB/PmuInit */
  465. void ssb_pmu_init(struct ssb_chipcommon *cc)
  466. {
  467. u32 pmucap;
  468. if (!(cc->capabilities & SSB_CHIPCO_CAP_PMU))
  469. return;
  470. pmucap = chipco_read32(cc, SSB_CHIPCO_PMU_CAP);
  471. cc->pmu.rev = (pmucap & SSB_CHIPCO_PMU_CAP_REVISION);
  472. ssb_dbg("Found rev %u PMU (capabilities 0x%08X)\n",
  473. cc->pmu.rev, pmucap);
  474. if (cc->pmu.rev == 1)
  475. chipco_mask32(cc, SSB_CHIPCO_PMU_CTL,
  476. ~SSB_CHIPCO_PMU_CTL_NOILPONW);
  477. else
  478. chipco_set32(cc, SSB_CHIPCO_PMU_CTL,
  479. SSB_CHIPCO_PMU_CTL_NOILPONW);
  480. ssb_pmu_pll_init(cc);
  481. ssb_pmu_resources_init(cc);
  482. }
  483. void ssb_pmu_set_ldo_voltage(struct ssb_chipcommon *cc,
  484. enum ssb_pmu_ldo_volt_id id, u32 voltage)
  485. {
  486. struct ssb_bus *bus = cc->dev->bus;
  487. u32 addr, shift, mask;
  488. switch (bus->chip_id) {
  489. case 0x4328:
  490. case 0x5354:
  491. switch (id) {
  492. case LDO_VOLT1:
  493. addr = 2;
  494. shift = 25;
  495. mask = 0xF;
  496. break;
  497. case LDO_VOLT2:
  498. addr = 3;
  499. shift = 1;
  500. mask = 0xF;
  501. break;
  502. case LDO_VOLT3:
  503. addr = 3;
  504. shift = 9;
  505. mask = 0xF;
  506. break;
  507. case LDO_PAREF:
  508. addr = 3;
  509. shift = 17;
  510. mask = 0x3F;
  511. break;
  512. default:
  513. SSB_WARN_ON(1);
  514. return;
  515. }
  516. break;
  517. case 0x4312:
  518. if (SSB_WARN_ON(id != LDO_PAREF))
  519. return;
  520. addr = 0;
  521. shift = 21;
  522. mask = 0x3F;
  523. break;
  524. default:
  525. return;
  526. }
  527. ssb_chipco_regctl_maskset(cc, addr, ~(mask << shift),
  528. (voltage & mask) << shift);
  529. }
  530. void ssb_pmu_set_ldo_paref(struct ssb_chipcommon *cc, bool on)
  531. {
  532. struct ssb_bus *bus = cc->dev->bus;
  533. int ldo;
  534. switch (bus->chip_id) {
  535. case 0x4312:
  536. ldo = SSB_PMURES_4312_PA_REF_LDO;
  537. break;
  538. case 0x4328:
  539. ldo = SSB_PMURES_4328_PA_REF_LDO;
  540. break;
  541. case 0x5354:
  542. ldo = SSB_PMURES_5354_PA_REF_LDO;
  543. break;
  544. default:
  545. return;
  546. }
  547. if (on)
  548. chipco_set32(cc, SSB_CHIPCO_PMU_MINRES_MSK, 1 << ldo);
  549. else
  550. chipco_mask32(cc, SSB_CHIPCO_PMU_MINRES_MSK, ~(1 << ldo));
  551. chipco_read32(cc, SSB_CHIPCO_PMU_MINRES_MSK); //SPEC FIXME found via mmiotrace - dummy read?
  552. }
  553. EXPORT_SYMBOL(ssb_pmu_set_ldo_voltage);
  554. EXPORT_SYMBOL(ssb_pmu_set_ldo_paref);
  555. static u32 ssb_pmu_get_alp_clock_clk0(struct ssb_chipcommon *cc)
  556. {
  557. u32 crystalfreq;
  558. const struct pmu0_plltab_entry *e = NULL;
  559. crystalfreq = (chipco_read32(cc, SSB_CHIPCO_PMU_CTL) &
  560. SSB_CHIPCO_PMU_CTL_XTALFREQ) >> SSB_CHIPCO_PMU_CTL_XTALFREQ_SHIFT;
  561. e = pmu0_plltab_find_entry(crystalfreq);
  562. BUG_ON(!e);
  563. return e->freq * 1000;
  564. }
  565. u32 ssb_pmu_get_alp_clock(struct ssb_chipcommon *cc)
  566. {
  567. struct ssb_bus *bus = cc->dev->bus;
  568. switch (bus->chip_id) {
  569. case 0x5354:
  570. return ssb_pmu_get_alp_clock_clk0(cc);
  571. default:
  572. ssb_err("ERROR: PMU alp clock unknown for device %04X\n",
  573. bus->chip_id);
  574. return 0;
  575. }
  576. }
  577. u32 ssb_pmu_get_cpu_clock(struct ssb_chipcommon *cc)
  578. {
  579. struct ssb_bus *bus = cc->dev->bus;
  580. switch (bus->chip_id) {
  581. case 0x5354:
  582. /* 5354 chip uses a non programmable PLL of frequency 240MHz */
  583. return 240000000;
  584. default:
  585. ssb_err("ERROR: PMU cpu clock unknown for device %04X\n",
  586. bus->chip_id);
  587. return 0;
  588. }
  589. }
  590. u32 ssb_pmu_get_controlclock(struct ssb_chipcommon *cc)
  591. {
  592. struct ssb_bus *bus = cc->dev->bus;
  593. switch (bus->chip_id) {
  594. case 0x5354:
  595. return 120000000;
  596. default:
  597. ssb_err("ERROR: PMU controlclock unknown for device %04X\n",
  598. bus->chip_id);
  599. return 0;
  600. }
  601. }
  602. void ssb_pmu_spuravoid_pllupdate(struct ssb_chipcommon *cc, int spuravoid)
  603. {
  604. u32 pmu_ctl = 0;
  605. switch (cc->dev->bus->chip_id) {
  606. case 0x4322:
  607. ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL0, 0x11100070);
  608. ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL1, 0x1014140a);
  609. ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL5, 0x88888854);
  610. if (spuravoid == 1)
  611. ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL2, 0x05201828);
  612. else
  613. ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL2, 0x05001828);
  614. pmu_ctl = SSB_CHIPCO_PMU_CTL_PLL_UPD;
  615. break;
  616. case 43222:
  617. if (spuravoid == 1) {
  618. ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL0, 0x11500008);
  619. ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL1, 0x0C000C06);
  620. ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL2, 0x0F600a08);
  621. ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL3, 0x00000000);
  622. ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL4, 0x2001E920);
  623. ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL5, 0x88888815);
  624. } else {
  625. ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL0, 0x11100008);
  626. ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL1, 0x0c000c06);
  627. ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL2, 0x03000a08);
  628. ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL3, 0x00000000);
  629. ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL4, 0x200005c0);
  630. ssb_chipco_pll_write(cc, SSB_PMU1_PLLCTL5, 0x88888855);
  631. }
  632. pmu_ctl = SSB_CHIPCO_PMU_CTL_PLL_UPD;
  633. break;
  634. default:
  635. ssb_printk(KERN_ERR PFX
  636. "Unknown spuravoidance settings for chip 0x%04X, not changing PLL\n",
  637. cc->dev->bus->chip_id);
  638. return;
  639. }
  640. chipco_set32(cc, SSB_CHIPCO_PMU_CTL, pmu_ctl);
  641. }
  642. EXPORT_SYMBOL_GPL(ssb_pmu_spuravoid_pllupdate);