amba-pl010.c 20 KB

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  1. /*
  2. * Driver for AMBA serial ports
  3. *
  4. * Based on drivers/char/serial.c, by Linus Torvalds, Theodore Ts'o.
  5. *
  6. * Copyright 1999 ARM Limited
  7. * Copyright (C) 2000 Deep Blue Solutions Ltd.
  8. *
  9. * This program is free software; you can redistribute it and/or modify
  10. * it under the terms of the GNU General Public License as published by
  11. * the Free Software Foundation; either version 2 of the License, or
  12. * (at your option) any later version.
  13. *
  14. * This program is distributed in the hope that it will be useful,
  15. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  17. * GNU General Public License for more details.
  18. *
  19. * You should have received a copy of the GNU General Public License
  20. * along with this program; if not, write to the Free Software
  21. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  22. *
  23. * This is a generic driver for ARM AMBA-type serial ports. They
  24. * have a lot of 16550-like features, but are not register compatible.
  25. * Note that although they do have CTS, DCD and DSR inputs, they do
  26. * not have an RI input, nor do they have DTR or RTS outputs. If
  27. * required, these have to be supplied via some other means (eg, GPIO)
  28. * and hooked into this driver.
  29. */
  30. #if defined(CONFIG_SERIAL_AMBA_PL010_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
  31. #define SUPPORT_SYSRQ
  32. #endif
  33. #include <linux/module.h>
  34. #include <linux/ioport.h>
  35. #include <linux/init.h>
  36. #include <linux/console.h>
  37. #include <linux/sysrq.h>
  38. #include <linux/device.h>
  39. #include <linux/tty.h>
  40. #include <linux/tty_flip.h>
  41. #include <linux/serial_core.h>
  42. #include <linux/serial.h>
  43. #include <linux/amba/bus.h>
  44. #include <linux/amba/serial.h>
  45. #include <linux/clk.h>
  46. #include <linux/slab.h>
  47. #include <linux/io.h>
  48. #define UART_NR 8
  49. #define SERIAL_AMBA_MAJOR 204
  50. #define SERIAL_AMBA_MINOR 16
  51. #define SERIAL_AMBA_NR UART_NR
  52. #define AMBA_ISR_PASS_LIMIT 256
  53. #define UART_RX_DATA(s) (((s) & UART01x_FR_RXFE) == 0)
  54. #define UART_TX_READY(s) (((s) & UART01x_FR_TXFF) == 0)
  55. #define UART_DUMMY_RSR_RX 256
  56. #define UART_PORT_SIZE 64
  57. /*
  58. * We wrap our port structure around the generic uart_port.
  59. */
  60. struct uart_amba_port {
  61. struct uart_port port;
  62. struct clk *clk;
  63. struct amba_device *dev;
  64. struct amba_pl010_data *data;
  65. unsigned int old_status;
  66. };
  67. static void pl010_stop_tx(struct uart_port *port)
  68. {
  69. struct uart_amba_port *uap =
  70. container_of(port, struct uart_amba_port, port);
  71. unsigned int cr;
  72. cr = readb(uap->port.membase + UART010_CR);
  73. cr &= ~UART010_CR_TIE;
  74. writel(cr, uap->port.membase + UART010_CR);
  75. }
  76. static void pl010_start_tx(struct uart_port *port)
  77. {
  78. struct uart_amba_port *uap =
  79. container_of(port, struct uart_amba_port, port);
  80. unsigned int cr;
  81. cr = readb(uap->port.membase + UART010_CR);
  82. cr |= UART010_CR_TIE;
  83. writel(cr, uap->port.membase + UART010_CR);
  84. }
  85. static void pl010_stop_rx(struct uart_port *port)
  86. {
  87. struct uart_amba_port *uap =
  88. container_of(port, struct uart_amba_port, port);
  89. unsigned int cr;
  90. cr = readb(uap->port.membase + UART010_CR);
  91. cr &= ~(UART010_CR_RIE | UART010_CR_RTIE);
  92. writel(cr, uap->port.membase + UART010_CR);
  93. }
  94. static void pl010_disable_ms(struct uart_port *port)
  95. {
  96. struct uart_amba_port *uap = (struct uart_amba_port *)port;
  97. unsigned int cr;
  98. cr = readb(uap->port.membase + UART010_CR);
  99. cr &= ~UART010_CR_MSIE;
  100. writel(cr, uap->port.membase + UART010_CR);
  101. }
  102. static void pl010_enable_ms(struct uart_port *port)
  103. {
  104. struct uart_amba_port *uap =
  105. container_of(port, struct uart_amba_port, port);
  106. unsigned int cr;
  107. cr = readb(uap->port.membase + UART010_CR);
  108. cr |= UART010_CR_MSIE;
  109. writel(cr, uap->port.membase + UART010_CR);
  110. }
  111. static void pl010_rx_chars(struct uart_amba_port *uap)
  112. {
  113. unsigned int status, ch, flag, rsr, max_count = 256;
  114. status = readb(uap->port.membase + UART01x_FR);
  115. while (UART_RX_DATA(status) && max_count--) {
  116. ch = readb(uap->port.membase + UART01x_DR);
  117. flag = TTY_NORMAL;
  118. uap->port.icount.rx++;
  119. /*
  120. * Note that the error handling code is
  121. * out of the main execution path
  122. */
  123. rsr = readb(uap->port.membase + UART01x_RSR) | UART_DUMMY_RSR_RX;
  124. if (unlikely(rsr & UART01x_RSR_ANY)) {
  125. writel(0, uap->port.membase + UART01x_ECR);
  126. if (rsr & UART01x_RSR_BE) {
  127. rsr &= ~(UART01x_RSR_FE | UART01x_RSR_PE);
  128. uap->port.icount.brk++;
  129. if (uart_handle_break(&uap->port))
  130. goto ignore_char;
  131. } else if (rsr & UART01x_RSR_PE)
  132. uap->port.icount.parity++;
  133. else if (rsr & UART01x_RSR_FE)
  134. uap->port.icount.frame++;
  135. if (rsr & UART01x_RSR_OE)
  136. uap->port.icount.overrun++;
  137. rsr &= uap->port.read_status_mask;
  138. if (rsr & UART01x_RSR_BE)
  139. flag = TTY_BREAK;
  140. else if (rsr & UART01x_RSR_PE)
  141. flag = TTY_PARITY;
  142. else if (rsr & UART01x_RSR_FE)
  143. flag = TTY_FRAME;
  144. }
  145. if (uart_handle_sysrq_char(&uap->port, ch))
  146. goto ignore_char;
  147. uart_insert_char(&uap->port, rsr, UART01x_RSR_OE, ch, flag);
  148. ignore_char:
  149. status = readb(uap->port.membase + UART01x_FR);
  150. }
  151. spin_unlock(&uap->port.lock);
  152. tty_flip_buffer_push(&uap->port.state->port);
  153. spin_lock(&uap->port.lock);
  154. }
  155. static void pl010_tx_chars(struct uart_amba_port *uap)
  156. {
  157. struct circ_buf *xmit = &uap->port.state->xmit;
  158. int count;
  159. if (uap->port.x_char) {
  160. writel(uap->port.x_char, uap->port.membase + UART01x_DR);
  161. uap->port.icount.tx++;
  162. uap->port.x_char = 0;
  163. return;
  164. }
  165. if (uart_circ_empty(xmit) || uart_tx_stopped(&uap->port)) {
  166. pl010_stop_tx(&uap->port);
  167. return;
  168. }
  169. count = uap->port.fifosize >> 1;
  170. do {
  171. writel(xmit->buf[xmit->tail], uap->port.membase + UART01x_DR);
  172. xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
  173. uap->port.icount.tx++;
  174. if (uart_circ_empty(xmit))
  175. break;
  176. } while (--count > 0);
  177. if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
  178. uart_write_wakeup(&uap->port);
  179. if (uart_circ_empty(xmit))
  180. pl010_stop_tx(&uap->port);
  181. }
  182. static void pl010_modem_status(struct uart_amba_port *uap)
  183. {
  184. unsigned int status, delta;
  185. writel(0, uap->port.membase + UART010_ICR);
  186. status = readb(uap->port.membase + UART01x_FR) & UART01x_FR_MODEM_ANY;
  187. delta = status ^ uap->old_status;
  188. uap->old_status = status;
  189. if (!delta)
  190. return;
  191. if (delta & UART01x_FR_DCD)
  192. uart_handle_dcd_change(&uap->port, status & UART01x_FR_DCD);
  193. if (delta & UART01x_FR_DSR)
  194. uap->port.icount.dsr++;
  195. if (delta & UART01x_FR_CTS)
  196. uart_handle_cts_change(&uap->port, status & UART01x_FR_CTS);
  197. wake_up_interruptible(&uap->port.state->port.delta_msr_wait);
  198. }
  199. static irqreturn_t pl010_int(int irq, void *dev_id)
  200. {
  201. struct uart_amba_port *uap = dev_id;
  202. unsigned int status, pass_counter = AMBA_ISR_PASS_LIMIT;
  203. int handled = 0;
  204. spin_lock(&uap->port.lock);
  205. status = readb(uap->port.membase + UART010_IIR);
  206. if (status) {
  207. do {
  208. if (status & (UART010_IIR_RTIS | UART010_IIR_RIS))
  209. pl010_rx_chars(uap);
  210. if (status & UART010_IIR_MIS)
  211. pl010_modem_status(uap);
  212. if (status & UART010_IIR_TIS)
  213. pl010_tx_chars(uap);
  214. if (pass_counter-- == 0)
  215. break;
  216. status = readb(uap->port.membase + UART010_IIR);
  217. } while (status & (UART010_IIR_RTIS | UART010_IIR_RIS |
  218. UART010_IIR_TIS));
  219. handled = 1;
  220. }
  221. spin_unlock(&uap->port.lock);
  222. return IRQ_RETVAL(handled);
  223. }
  224. static unsigned int pl010_tx_empty(struct uart_port *port)
  225. {
  226. struct uart_amba_port *uap =
  227. container_of(port, struct uart_amba_port, port);
  228. unsigned int status = readb(uap->port.membase + UART01x_FR);
  229. return status & UART01x_FR_BUSY ? 0 : TIOCSER_TEMT;
  230. }
  231. static unsigned int pl010_get_mctrl(struct uart_port *port)
  232. {
  233. struct uart_amba_port *uap =
  234. container_of(port, struct uart_amba_port, port);
  235. unsigned int result = 0;
  236. unsigned int status;
  237. status = readb(uap->port.membase + UART01x_FR);
  238. if (status & UART01x_FR_DCD)
  239. result |= TIOCM_CAR;
  240. if (status & UART01x_FR_DSR)
  241. result |= TIOCM_DSR;
  242. if (status & UART01x_FR_CTS)
  243. result |= TIOCM_CTS;
  244. return result;
  245. }
  246. static void pl010_set_mctrl(struct uart_port *port, unsigned int mctrl)
  247. {
  248. struct uart_amba_port *uap =
  249. container_of(port, struct uart_amba_port, port);
  250. if (uap->data)
  251. uap->data->set_mctrl(uap->dev, uap->port.membase, mctrl);
  252. }
  253. static void pl010_break_ctl(struct uart_port *port, int break_state)
  254. {
  255. struct uart_amba_port *uap =
  256. container_of(port, struct uart_amba_port, port);
  257. unsigned long flags;
  258. unsigned int lcr_h;
  259. spin_lock_irqsave(&uap->port.lock, flags);
  260. lcr_h = readb(uap->port.membase + UART010_LCRH);
  261. if (break_state == -1)
  262. lcr_h |= UART01x_LCRH_BRK;
  263. else
  264. lcr_h &= ~UART01x_LCRH_BRK;
  265. writel(lcr_h, uap->port.membase + UART010_LCRH);
  266. spin_unlock_irqrestore(&uap->port.lock, flags);
  267. }
  268. static int pl010_startup(struct uart_port *port)
  269. {
  270. struct uart_amba_port *uap =
  271. container_of(port, struct uart_amba_port, port);
  272. int retval;
  273. /*
  274. * Try to enable the clock producer.
  275. */
  276. retval = clk_prepare_enable(uap->clk);
  277. if (retval)
  278. goto out;
  279. uap->port.uartclk = clk_get_rate(uap->clk);
  280. /*
  281. * Allocate the IRQ
  282. */
  283. retval = request_irq(uap->port.irq, pl010_int, 0, "uart-pl010", uap);
  284. if (retval)
  285. goto clk_dis;
  286. /*
  287. * initialise the old status of the modem signals
  288. */
  289. uap->old_status = readb(uap->port.membase + UART01x_FR) & UART01x_FR_MODEM_ANY;
  290. /*
  291. * Finally, enable interrupts
  292. */
  293. writel(UART01x_CR_UARTEN | UART010_CR_RIE | UART010_CR_RTIE,
  294. uap->port.membase + UART010_CR);
  295. return 0;
  296. clk_dis:
  297. clk_disable_unprepare(uap->clk);
  298. out:
  299. return retval;
  300. }
  301. static void pl010_shutdown(struct uart_port *port)
  302. {
  303. struct uart_amba_port *uap =
  304. container_of(port, struct uart_amba_port, port);
  305. /*
  306. * Free the interrupt
  307. */
  308. free_irq(uap->port.irq, uap);
  309. /*
  310. * disable all interrupts, disable the port
  311. */
  312. writel(0, uap->port.membase + UART010_CR);
  313. /* disable break condition and fifos */
  314. writel(readb(uap->port.membase + UART010_LCRH) &
  315. ~(UART01x_LCRH_BRK | UART01x_LCRH_FEN),
  316. uap->port.membase + UART010_LCRH);
  317. /*
  318. * Shut down the clock producer
  319. */
  320. clk_disable_unprepare(uap->clk);
  321. }
  322. static void
  323. pl010_set_termios(struct uart_port *port, struct ktermios *termios,
  324. struct ktermios *old)
  325. {
  326. struct uart_amba_port *uap =
  327. container_of(port, struct uart_amba_port, port);
  328. unsigned int lcr_h, old_cr;
  329. unsigned long flags;
  330. unsigned int baud, quot;
  331. /*
  332. * Ask the core to calculate the divisor for us.
  333. */
  334. baud = uart_get_baud_rate(port, termios, old, 0, uap->port.uartclk/16);
  335. quot = uart_get_divisor(port, baud);
  336. switch (termios->c_cflag & CSIZE) {
  337. case CS5:
  338. lcr_h = UART01x_LCRH_WLEN_5;
  339. break;
  340. case CS6:
  341. lcr_h = UART01x_LCRH_WLEN_6;
  342. break;
  343. case CS7:
  344. lcr_h = UART01x_LCRH_WLEN_7;
  345. break;
  346. default: // CS8
  347. lcr_h = UART01x_LCRH_WLEN_8;
  348. break;
  349. }
  350. if (termios->c_cflag & CSTOPB)
  351. lcr_h |= UART01x_LCRH_STP2;
  352. if (termios->c_cflag & PARENB) {
  353. lcr_h |= UART01x_LCRH_PEN;
  354. if (!(termios->c_cflag & PARODD))
  355. lcr_h |= UART01x_LCRH_EPS;
  356. }
  357. if (uap->port.fifosize > 1)
  358. lcr_h |= UART01x_LCRH_FEN;
  359. spin_lock_irqsave(&uap->port.lock, flags);
  360. /*
  361. * Update the per-port timeout.
  362. */
  363. uart_update_timeout(port, termios->c_cflag, baud);
  364. uap->port.read_status_mask = UART01x_RSR_OE;
  365. if (termios->c_iflag & INPCK)
  366. uap->port.read_status_mask |= UART01x_RSR_FE | UART01x_RSR_PE;
  367. if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
  368. uap->port.read_status_mask |= UART01x_RSR_BE;
  369. /*
  370. * Characters to ignore
  371. */
  372. uap->port.ignore_status_mask = 0;
  373. if (termios->c_iflag & IGNPAR)
  374. uap->port.ignore_status_mask |= UART01x_RSR_FE | UART01x_RSR_PE;
  375. if (termios->c_iflag & IGNBRK) {
  376. uap->port.ignore_status_mask |= UART01x_RSR_BE;
  377. /*
  378. * If we're ignoring parity and break indicators,
  379. * ignore overruns too (for real raw support).
  380. */
  381. if (termios->c_iflag & IGNPAR)
  382. uap->port.ignore_status_mask |= UART01x_RSR_OE;
  383. }
  384. /*
  385. * Ignore all characters if CREAD is not set.
  386. */
  387. if ((termios->c_cflag & CREAD) == 0)
  388. uap->port.ignore_status_mask |= UART_DUMMY_RSR_RX;
  389. /* first, disable everything */
  390. old_cr = readb(uap->port.membase + UART010_CR) & ~UART010_CR_MSIE;
  391. if (UART_ENABLE_MS(port, termios->c_cflag))
  392. old_cr |= UART010_CR_MSIE;
  393. writel(0, uap->port.membase + UART010_CR);
  394. /* Set baud rate */
  395. quot -= 1;
  396. writel((quot & 0xf00) >> 8, uap->port.membase + UART010_LCRM);
  397. writel(quot & 0xff, uap->port.membase + UART010_LCRL);
  398. /*
  399. * ----------v----------v----------v----------v-----
  400. * NOTE: MUST BE WRITTEN AFTER UARTLCR_M & UARTLCR_L
  401. * ----------^----------^----------^----------^-----
  402. */
  403. writel(lcr_h, uap->port.membase + UART010_LCRH);
  404. writel(old_cr, uap->port.membase + UART010_CR);
  405. spin_unlock_irqrestore(&uap->port.lock, flags);
  406. }
  407. static void pl010_set_ldisc(struct uart_port *port, struct ktermios *termios)
  408. {
  409. if (termios->c_line == N_PPS) {
  410. port->flags |= UPF_HARDPPS_CD;
  411. spin_lock_irq(&port->lock);
  412. pl010_enable_ms(port);
  413. spin_unlock_irq(&port->lock);
  414. } else {
  415. port->flags &= ~UPF_HARDPPS_CD;
  416. if (!UART_ENABLE_MS(port, termios->c_cflag)) {
  417. spin_lock_irq(&port->lock);
  418. pl010_disable_ms(port);
  419. spin_unlock_irq(&port->lock);
  420. }
  421. }
  422. }
  423. static const char *pl010_type(struct uart_port *port)
  424. {
  425. return port->type == PORT_AMBA ? "AMBA" : NULL;
  426. }
  427. /*
  428. * Release the memory region(s) being used by 'port'
  429. */
  430. static void pl010_release_port(struct uart_port *port)
  431. {
  432. release_mem_region(port->mapbase, UART_PORT_SIZE);
  433. }
  434. /*
  435. * Request the memory region(s) being used by 'port'
  436. */
  437. static int pl010_request_port(struct uart_port *port)
  438. {
  439. return request_mem_region(port->mapbase, UART_PORT_SIZE, "uart-pl010")
  440. != NULL ? 0 : -EBUSY;
  441. }
  442. /*
  443. * Configure/autoconfigure the port.
  444. */
  445. static void pl010_config_port(struct uart_port *port, int flags)
  446. {
  447. if (flags & UART_CONFIG_TYPE) {
  448. port->type = PORT_AMBA;
  449. pl010_request_port(port);
  450. }
  451. }
  452. /*
  453. * verify the new serial_struct (for TIOCSSERIAL).
  454. */
  455. static int pl010_verify_port(struct uart_port *port, struct serial_struct *ser)
  456. {
  457. int ret = 0;
  458. if (ser->type != PORT_UNKNOWN && ser->type != PORT_AMBA)
  459. ret = -EINVAL;
  460. if (ser->irq < 0 || ser->irq >= nr_irqs)
  461. ret = -EINVAL;
  462. if (ser->baud_base < 9600)
  463. ret = -EINVAL;
  464. return ret;
  465. }
  466. static struct uart_ops amba_pl010_pops = {
  467. .tx_empty = pl010_tx_empty,
  468. .set_mctrl = pl010_set_mctrl,
  469. .get_mctrl = pl010_get_mctrl,
  470. .stop_tx = pl010_stop_tx,
  471. .start_tx = pl010_start_tx,
  472. .stop_rx = pl010_stop_rx,
  473. .enable_ms = pl010_enable_ms,
  474. .break_ctl = pl010_break_ctl,
  475. .startup = pl010_startup,
  476. .shutdown = pl010_shutdown,
  477. .set_termios = pl010_set_termios,
  478. .set_ldisc = pl010_set_ldisc,
  479. .type = pl010_type,
  480. .release_port = pl010_release_port,
  481. .request_port = pl010_request_port,
  482. .config_port = pl010_config_port,
  483. .verify_port = pl010_verify_port,
  484. };
  485. static struct uart_amba_port *amba_ports[UART_NR];
  486. #ifdef CONFIG_SERIAL_AMBA_PL010_CONSOLE
  487. static void pl010_console_putchar(struct uart_port *port, int ch)
  488. {
  489. struct uart_amba_port *uap =
  490. container_of(port, struct uart_amba_port, port);
  491. unsigned int status;
  492. do {
  493. status = readb(uap->port.membase + UART01x_FR);
  494. barrier();
  495. } while (!UART_TX_READY(status));
  496. writel(ch, uap->port.membase + UART01x_DR);
  497. }
  498. static void
  499. pl010_console_write(struct console *co, const char *s, unsigned int count)
  500. {
  501. struct uart_amba_port *uap = amba_ports[co->index];
  502. unsigned int status, old_cr;
  503. clk_enable(uap->clk);
  504. /*
  505. * First save the CR then disable the interrupts
  506. */
  507. old_cr = readb(uap->port.membase + UART010_CR);
  508. writel(UART01x_CR_UARTEN, uap->port.membase + UART010_CR);
  509. uart_console_write(&uap->port, s, count, pl010_console_putchar);
  510. /*
  511. * Finally, wait for transmitter to become empty
  512. * and restore the TCR
  513. */
  514. do {
  515. status = readb(uap->port.membase + UART01x_FR);
  516. barrier();
  517. } while (status & UART01x_FR_BUSY);
  518. writel(old_cr, uap->port.membase + UART010_CR);
  519. clk_disable(uap->clk);
  520. }
  521. static void __init
  522. pl010_console_get_options(struct uart_amba_port *uap, int *baud,
  523. int *parity, int *bits)
  524. {
  525. if (readb(uap->port.membase + UART010_CR) & UART01x_CR_UARTEN) {
  526. unsigned int lcr_h, quot;
  527. lcr_h = readb(uap->port.membase + UART010_LCRH);
  528. *parity = 'n';
  529. if (lcr_h & UART01x_LCRH_PEN) {
  530. if (lcr_h & UART01x_LCRH_EPS)
  531. *parity = 'e';
  532. else
  533. *parity = 'o';
  534. }
  535. if ((lcr_h & 0x60) == UART01x_LCRH_WLEN_7)
  536. *bits = 7;
  537. else
  538. *bits = 8;
  539. quot = readb(uap->port.membase + UART010_LCRL) |
  540. readb(uap->port.membase + UART010_LCRM) << 8;
  541. *baud = uap->port.uartclk / (16 * (quot + 1));
  542. }
  543. }
  544. static int __init pl010_console_setup(struct console *co, char *options)
  545. {
  546. struct uart_amba_port *uap;
  547. int baud = 38400;
  548. int bits = 8;
  549. int parity = 'n';
  550. int flow = 'n';
  551. int ret;
  552. /*
  553. * Check whether an invalid uart number has been specified, and
  554. * if so, search for the first available port that does have
  555. * console support.
  556. */
  557. if (co->index >= UART_NR)
  558. co->index = 0;
  559. uap = amba_ports[co->index];
  560. if (!uap)
  561. return -ENODEV;
  562. ret = clk_prepare(uap->clk);
  563. if (ret)
  564. return ret;
  565. uap->port.uartclk = clk_get_rate(uap->clk);
  566. if (options)
  567. uart_parse_options(options, &baud, &parity, &bits, &flow);
  568. else
  569. pl010_console_get_options(uap, &baud, &parity, &bits);
  570. return uart_set_options(&uap->port, co, baud, parity, bits, flow);
  571. }
  572. static struct uart_driver amba_reg;
  573. static struct console amba_console = {
  574. .name = "ttyAM",
  575. .write = pl010_console_write,
  576. .device = uart_console_device,
  577. .setup = pl010_console_setup,
  578. .flags = CON_PRINTBUFFER,
  579. .index = -1,
  580. .data = &amba_reg,
  581. };
  582. #define AMBA_CONSOLE &amba_console
  583. #else
  584. #define AMBA_CONSOLE NULL
  585. #endif
  586. static struct uart_driver amba_reg = {
  587. .owner = THIS_MODULE,
  588. .driver_name = "ttyAM",
  589. .dev_name = "ttyAM",
  590. .major = SERIAL_AMBA_MAJOR,
  591. .minor = SERIAL_AMBA_MINOR,
  592. .nr = UART_NR,
  593. .cons = AMBA_CONSOLE,
  594. };
  595. static int pl010_probe(struct amba_device *dev, const struct amba_id *id)
  596. {
  597. struct uart_amba_port *uap;
  598. void __iomem *base;
  599. int i, ret;
  600. for (i = 0; i < ARRAY_SIZE(amba_ports); i++)
  601. if (amba_ports[i] == NULL)
  602. break;
  603. if (i == ARRAY_SIZE(amba_ports))
  604. return -EBUSY;
  605. uap = devm_kzalloc(&dev->dev, sizeof(struct uart_amba_port),
  606. GFP_KERNEL);
  607. if (!uap)
  608. return -ENOMEM;
  609. base = devm_ioremap(&dev->dev, dev->res.start,
  610. resource_size(&dev->res));
  611. if (!base)
  612. return -ENOMEM;
  613. uap->clk = devm_clk_get(&dev->dev, NULL);
  614. if (IS_ERR(uap->clk))
  615. return PTR_ERR(uap->clk);
  616. uap->port.dev = &dev->dev;
  617. uap->port.mapbase = dev->res.start;
  618. uap->port.membase = base;
  619. uap->port.iotype = UPIO_MEM;
  620. uap->port.irq = dev->irq[0];
  621. uap->port.fifosize = 16;
  622. uap->port.ops = &amba_pl010_pops;
  623. uap->port.flags = UPF_BOOT_AUTOCONF;
  624. uap->port.line = i;
  625. uap->dev = dev;
  626. uap->data = dev_get_platdata(&dev->dev);
  627. amba_ports[i] = uap;
  628. amba_set_drvdata(dev, uap);
  629. ret = uart_add_one_port(&amba_reg, &uap->port);
  630. if (ret)
  631. amba_ports[i] = NULL;
  632. return ret;
  633. }
  634. static int pl010_remove(struct amba_device *dev)
  635. {
  636. struct uart_amba_port *uap = amba_get_drvdata(dev);
  637. int i;
  638. uart_remove_one_port(&amba_reg, &uap->port);
  639. for (i = 0; i < ARRAY_SIZE(amba_ports); i++)
  640. if (amba_ports[i] == uap)
  641. amba_ports[i] = NULL;
  642. return 0;
  643. }
  644. #ifdef CONFIG_PM_SLEEP
  645. static int pl010_suspend(struct device *dev)
  646. {
  647. struct uart_amba_port *uap = dev_get_drvdata(dev);
  648. if (uap)
  649. uart_suspend_port(&amba_reg, &uap->port);
  650. return 0;
  651. }
  652. static int pl010_resume(struct device *dev)
  653. {
  654. struct uart_amba_port *uap = dev_get_drvdata(dev);
  655. if (uap)
  656. uart_resume_port(&amba_reg, &uap->port);
  657. return 0;
  658. }
  659. #endif
  660. static SIMPLE_DEV_PM_OPS(pl010_dev_pm_ops, pl010_suspend, pl010_resume);
  661. static struct amba_id pl010_ids[] = {
  662. {
  663. .id = 0x00041010,
  664. .mask = 0x000fffff,
  665. },
  666. { 0, 0 },
  667. };
  668. MODULE_DEVICE_TABLE(amba, pl010_ids);
  669. static struct amba_driver pl010_driver = {
  670. .drv = {
  671. .name = "uart-pl010",
  672. .pm = &pl010_dev_pm_ops,
  673. },
  674. .id_table = pl010_ids,
  675. .probe = pl010_probe,
  676. .remove = pl010_remove,
  677. };
  678. static int __init pl010_init(void)
  679. {
  680. int ret;
  681. printk(KERN_INFO "Serial: AMBA driver\n");
  682. ret = uart_register_driver(&amba_reg);
  683. if (ret == 0) {
  684. ret = amba_driver_register(&pl010_driver);
  685. if (ret)
  686. uart_unregister_driver(&amba_reg);
  687. }
  688. return ret;
  689. }
  690. static void __exit pl010_exit(void)
  691. {
  692. amba_driver_unregister(&pl010_driver);
  693. uart_unregister_driver(&amba_reg);
  694. }
  695. module_init(pl010_init);
  696. module_exit(pl010_exit);
  697. MODULE_AUTHOR("ARM Ltd/Deep Blue Solutions Ltd");
  698. MODULE_DESCRIPTION("ARM AMBA serial port driver");
  699. MODULE_LICENSE("GPL");