sirfsoc_uart.c 47 KB

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  1. /*
  2. * Driver for CSR SiRFprimaII onboard UARTs.
  3. *
  4. * Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
  5. *
  6. * Licensed under GPLv2 or later.
  7. */
  8. #include <linux/module.h>
  9. #include <linux/ioport.h>
  10. #include <linux/platform_device.h>
  11. #include <linux/init.h>
  12. #include <linux/sysrq.h>
  13. #include <linux/console.h>
  14. #include <linux/tty.h>
  15. #include <linux/tty_flip.h>
  16. #include <linux/serial_core.h>
  17. #include <linux/serial.h>
  18. #include <linux/clk.h>
  19. #include <linux/of.h>
  20. #include <linux/slab.h>
  21. #include <linux/io.h>
  22. #include <linux/of_gpio.h>
  23. #include <linux/dmaengine.h>
  24. #include <linux/dma-direction.h>
  25. #include <linux/dma-mapping.h>
  26. #include <asm/irq.h>
  27. #include <asm/mach/irq.h>
  28. #include "sirfsoc_uart.h"
  29. static unsigned int
  30. sirfsoc_uart_pio_tx_chars(struct sirfsoc_uart_port *sirfport, int count);
  31. static unsigned int
  32. sirfsoc_uart_pio_rx_chars(struct uart_port *port, unsigned int max_rx_count);
  33. static struct uart_driver sirfsoc_uart_drv;
  34. static void sirfsoc_uart_tx_dma_complete_callback(void *param);
  35. static const struct sirfsoc_baudrate_to_regv baudrate_to_regv[] = {
  36. {4000000, 2359296},
  37. {3500000, 1310721},
  38. {3000000, 1572865},
  39. {2500000, 1245186},
  40. {2000000, 1572866},
  41. {1500000, 1245188},
  42. {1152000, 1638404},
  43. {1000000, 1572869},
  44. {921600, 1114120},
  45. {576000, 1245196},
  46. {500000, 1245198},
  47. {460800, 1572876},
  48. {230400, 1310750},
  49. {115200, 1310781},
  50. {57600, 1310843},
  51. {38400, 1114328},
  52. {19200, 1114545},
  53. {9600, 1114979},
  54. };
  55. static struct sirfsoc_uart_port *sirf_ports[SIRFSOC_UART_NR];
  56. static inline struct sirfsoc_uart_port *to_sirfport(struct uart_port *port)
  57. {
  58. return container_of(port, struct sirfsoc_uart_port, port);
  59. }
  60. static inline unsigned int sirfsoc_uart_tx_empty(struct uart_port *port)
  61. {
  62. unsigned long reg;
  63. struct sirfsoc_uart_port *sirfport = to_sirfport(port);
  64. struct sirfsoc_register *ureg = &sirfport->uart_reg->uart_reg;
  65. struct sirfsoc_fifo_status *ufifo_st = &sirfport->uart_reg->fifo_status;
  66. reg = rd_regl(port, ureg->sirfsoc_tx_fifo_status);
  67. return (reg & ufifo_st->ff_empty(port)) ? TIOCSER_TEMT : 0;
  68. }
  69. static unsigned int sirfsoc_uart_get_mctrl(struct uart_port *port)
  70. {
  71. struct sirfsoc_uart_port *sirfport = to_sirfport(port);
  72. struct sirfsoc_register *ureg = &sirfport->uart_reg->uart_reg;
  73. if (!sirfport->hw_flow_ctrl || !sirfport->ms_enabled)
  74. goto cts_asserted;
  75. if (sirfport->uart_reg->uart_type == SIRF_REAL_UART) {
  76. if (!(rd_regl(port, ureg->sirfsoc_afc_ctrl) &
  77. SIRFUART_AFC_CTS_STATUS))
  78. goto cts_asserted;
  79. else
  80. goto cts_deasserted;
  81. } else {
  82. if (!gpio_get_value(sirfport->cts_gpio))
  83. goto cts_asserted;
  84. else
  85. goto cts_deasserted;
  86. }
  87. cts_deasserted:
  88. return TIOCM_CAR | TIOCM_DSR;
  89. cts_asserted:
  90. return TIOCM_CAR | TIOCM_DSR | TIOCM_CTS;
  91. }
  92. static void sirfsoc_uart_set_mctrl(struct uart_port *port, unsigned int mctrl)
  93. {
  94. struct sirfsoc_uart_port *sirfport = to_sirfport(port);
  95. struct sirfsoc_register *ureg = &sirfport->uart_reg->uart_reg;
  96. unsigned int assert = mctrl & TIOCM_RTS;
  97. unsigned int val = assert ? SIRFUART_AFC_CTRL_RX_THD : 0x0;
  98. unsigned int current_val;
  99. if (mctrl & TIOCM_LOOP) {
  100. if (sirfport->uart_reg->uart_type == SIRF_REAL_UART)
  101. wr_regl(port, ureg->sirfsoc_line_ctrl,
  102. rd_regl(port, ureg->sirfsoc_line_ctrl) |
  103. SIRFUART_LOOP_BACK);
  104. else
  105. wr_regl(port, ureg->sirfsoc_mode1,
  106. rd_regl(port, ureg->sirfsoc_mode1) |
  107. SIRFSOC_USP_LOOP_BACK_CTRL);
  108. } else {
  109. if (sirfport->uart_reg->uart_type == SIRF_REAL_UART)
  110. wr_regl(port, ureg->sirfsoc_line_ctrl,
  111. rd_regl(port, ureg->sirfsoc_line_ctrl) &
  112. ~SIRFUART_LOOP_BACK);
  113. else
  114. wr_regl(port, ureg->sirfsoc_mode1,
  115. rd_regl(port, ureg->sirfsoc_mode1) &
  116. ~SIRFSOC_USP_LOOP_BACK_CTRL);
  117. }
  118. if (!sirfport->hw_flow_ctrl || !sirfport->ms_enabled)
  119. return;
  120. if (sirfport->uart_reg->uart_type == SIRF_REAL_UART) {
  121. current_val = rd_regl(port, ureg->sirfsoc_afc_ctrl) & ~0xFF;
  122. val |= current_val;
  123. wr_regl(port, ureg->sirfsoc_afc_ctrl, val);
  124. } else {
  125. if (!val)
  126. gpio_set_value(sirfport->rts_gpio, 1);
  127. else
  128. gpio_set_value(sirfport->rts_gpio, 0);
  129. }
  130. }
  131. static void sirfsoc_uart_stop_tx(struct uart_port *port)
  132. {
  133. struct sirfsoc_uart_port *sirfport = to_sirfport(port);
  134. struct sirfsoc_register *ureg = &sirfport->uart_reg->uart_reg;
  135. struct sirfsoc_int_en *uint_en = &sirfport->uart_reg->uart_int_en;
  136. if (sirfport->tx_dma_chan) {
  137. if (sirfport->tx_dma_state == TX_DMA_RUNNING) {
  138. dmaengine_pause(sirfport->tx_dma_chan);
  139. sirfport->tx_dma_state = TX_DMA_PAUSE;
  140. } else {
  141. if (!sirfport->is_atlas7)
  142. wr_regl(port, ureg->sirfsoc_int_en_reg,
  143. rd_regl(port, ureg->sirfsoc_int_en_reg) &
  144. ~uint_en->sirfsoc_txfifo_empty_en);
  145. else
  146. wr_regl(port, ureg->sirfsoc_int_en_clr_reg,
  147. uint_en->sirfsoc_txfifo_empty_en);
  148. }
  149. } else {
  150. if (sirfport->uart_reg->uart_type == SIRF_USP_UART)
  151. wr_regl(port, ureg->sirfsoc_tx_rx_en, rd_regl(port,
  152. ureg->sirfsoc_tx_rx_en) & ~SIRFUART_TX_EN);
  153. if (!sirfport->is_atlas7)
  154. wr_regl(port, ureg->sirfsoc_int_en_reg,
  155. rd_regl(port, ureg->sirfsoc_int_en_reg) &
  156. ~uint_en->sirfsoc_txfifo_empty_en);
  157. else
  158. wr_regl(port, ureg->sirfsoc_int_en_clr_reg,
  159. uint_en->sirfsoc_txfifo_empty_en);
  160. }
  161. }
  162. static void sirfsoc_uart_tx_with_dma(struct sirfsoc_uart_port *sirfport)
  163. {
  164. struct uart_port *port = &sirfport->port;
  165. struct sirfsoc_register *ureg = &sirfport->uart_reg->uart_reg;
  166. struct sirfsoc_int_en *uint_en = &sirfport->uart_reg->uart_int_en;
  167. struct circ_buf *xmit = &port->state->xmit;
  168. unsigned long tran_size;
  169. unsigned long tran_start;
  170. unsigned long pio_tx_size;
  171. tran_size = CIRC_CNT_TO_END(xmit->head, xmit->tail, UART_XMIT_SIZE);
  172. tran_start = (unsigned long)(xmit->buf + xmit->tail);
  173. if (uart_circ_empty(xmit) || uart_tx_stopped(port) ||
  174. !tran_size)
  175. return;
  176. if (sirfport->tx_dma_state == TX_DMA_PAUSE) {
  177. dmaengine_resume(sirfport->tx_dma_chan);
  178. return;
  179. }
  180. if (sirfport->tx_dma_state == TX_DMA_RUNNING)
  181. return;
  182. if (!sirfport->is_atlas7)
  183. wr_regl(port, ureg->sirfsoc_int_en_reg,
  184. rd_regl(port, ureg->sirfsoc_int_en_reg)&
  185. ~(uint_en->sirfsoc_txfifo_empty_en));
  186. else
  187. wr_regl(port, ureg->sirfsoc_int_en_clr_reg,
  188. uint_en->sirfsoc_txfifo_empty_en);
  189. /*
  190. * DMA requires buffer address and buffer length are both aligned with
  191. * 4 bytes, so we use PIO for
  192. * 1. if address is not aligned with 4bytes, use PIO for the first 1~3
  193. * bytes, and move to DMA for the left part aligned with 4bytes
  194. * 2. if buffer length is not aligned with 4bytes, use DMA for aligned
  195. * part first, move to PIO for the left 1~3 bytes
  196. */
  197. if (tran_size < 4 || BYTES_TO_ALIGN(tran_start)) {
  198. wr_regl(port, ureg->sirfsoc_tx_fifo_op, SIRFUART_FIFO_STOP);
  199. wr_regl(port, ureg->sirfsoc_tx_dma_io_ctrl,
  200. rd_regl(port, ureg->sirfsoc_tx_dma_io_ctrl)|
  201. SIRFUART_IO_MODE);
  202. if (BYTES_TO_ALIGN(tran_start)) {
  203. pio_tx_size = sirfsoc_uart_pio_tx_chars(sirfport,
  204. BYTES_TO_ALIGN(tran_start));
  205. tran_size -= pio_tx_size;
  206. }
  207. if (tran_size < 4)
  208. sirfsoc_uart_pio_tx_chars(sirfport, tran_size);
  209. if (!sirfport->is_atlas7)
  210. wr_regl(port, ureg->sirfsoc_int_en_reg,
  211. rd_regl(port, ureg->sirfsoc_int_en_reg)|
  212. uint_en->sirfsoc_txfifo_empty_en);
  213. else
  214. wr_regl(port, ureg->sirfsoc_int_en_reg,
  215. uint_en->sirfsoc_txfifo_empty_en);
  216. wr_regl(port, ureg->sirfsoc_tx_fifo_op, SIRFUART_FIFO_START);
  217. } else {
  218. /* tx transfer mode switch into dma mode */
  219. wr_regl(port, ureg->sirfsoc_tx_fifo_op, SIRFUART_FIFO_STOP);
  220. wr_regl(port, ureg->sirfsoc_tx_dma_io_ctrl,
  221. rd_regl(port, ureg->sirfsoc_tx_dma_io_ctrl)&
  222. ~SIRFUART_IO_MODE);
  223. wr_regl(port, ureg->sirfsoc_tx_fifo_op, SIRFUART_FIFO_START);
  224. tran_size &= ~(0x3);
  225. sirfport->tx_dma_addr = dma_map_single(port->dev,
  226. xmit->buf + xmit->tail,
  227. tran_size, DMA_TO_DEVICE);
  228. sirfport->tx_dma_desc = dmaengine_prep_slave_single(
  229. sirfport->tx_dma_chan, sirfport->tx_dma_addr,
  230. tran_size, DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT);
  231. if (!sirfport->tx_dma_desc) {
  232. dev_err(port->dev, "DMA prep slave single fail\n");
  233. return;
  234. }
  235. sirfport->tx_dma_desc->callback =
  236. sirfsoc_uart_tx_dma_complete_callback;
  237. sirfport->tx_dma_desc->callback_param = (void *)sirfport;
  238. sirfport->transfer_size = tran_size;
  239. dmaengine_submit(sirfport->tx_dma_desc);
  240. dma_async_issue_pending(sirfport->tx_dma_chan);
  241. sirfport->tx_dma_state = TX_DMA_RUNNING;
  242. }
  243. }
  244. static void sirfsoc_uart_start_tx(struct uart_port *port)
  245. {
  246. struct sirfsoc_uart_port *sirfport = to_sirfport(port);
  247. struct sirfsoc_register *ureg = &sirfport->uart_reg->uart_reg;
  248. struct sirfsoc_int_en *uint_en = &sirfport->uart_reg->uart_int_en;
  249. if (sirfport->tx_dma_chan)
  250. sirfsoc_uart_tx_with_dma(sirfport);
  251. else {
  252. if (sirfport->uart_reg->uart_type == SIRF_USP_UART)
  253. wr_regl(port, ureg->sirfsoc_tx_rx_en, rd_regl(port,
  254. ureg->sirfsoc_tx_rx_en) | SIRFUART_TX_EN);
  255. wr_regl(port, ureg->sirfsoc_tx_fifo_op, SIRFUART_FIFO_STOP);
  256. sirfsoc_uart_pio_tx_chars(sirfport, port->fifosize);
  257. wr_regl(port, ureg->sirfsoc_tx_fifo_op, SIRFUART_FIFO_START);
  258. if (!sirfport->is_atlas7)
  259. wr_regl(port, ureg->sirfsoc_int_en_reg,
  260. rd_regl(port, ureg->sirfsoc_int_en_reg)|
  261. uint_en->sirfsoc_txfifo_empty_en);
  262. else
  263. wr_regl(port, ureg->sirfsoc_int_en_reg,
  264. uint_en->sirfsoc_txfifo_empty_en);
  265. }
  266. }
  267. static void sirfsoc_uart_stop_rx(struct uart_port *port)
  268. {
  269. struct sirfsoc_uart_port *sirfport = to_sirfport(port);
  270. struct sirfsoc_register *ureg = &sirfport->uart_reg->uart_reg;
  271. struct sirfsoc_int_en *uint_en = &sirfport->uart_reg->uart_int_en;
  272. wr_regl(port, ureg->sirfsoc_rx_fifo_op, 0);
  273. if (sirfport->rx_dma_chan) {
  274. if (!sirfport->is_atlas7)
  275. wr_regl(port, ureg->sirfsoc_int_en_reg,
  276. rd_regl(port, ureg->sirfsoc_int_en_reg) &
  277. ~(SIRFUART_RX_DMA_INT_EN(uint_en,
  278. sirfport->uart_reg->uart_type) |
  279. uint_en->sirfsoc_rx_done_en));
  280. else
  281. wr_regl(port, ureg->sirfsoc_int_en_clr_reg,
  282. SIRFUART_RX_DMA_INT_EN(uint_en,
  283. sirfport->uart_reg->uart_type)|
  284. uint_en->sirfsoc_rx_done_en);
  285. dmaengine_terminate_all(sirfport->rx_dma_chan);
  286. } else {
  287. if (!sirfport->is_atlas7)
  288. wr_regl(port, ureg->sirfsoc_int_en_reg,
  289. rd_regl(port, ureg->sirfsoc_int_en_reg)&
  290. ~(SIRFUART_RX_IO_INT_EN(uint_en,
  291. sirfport->uart_reg->uart_type)));
  292. else
  293. wr_regl(port, ureg->sirfsoc_int_en_clr_reg,
  294. SIRFUART_RX_IO_INT_EN(uint_en,
  295. sirfport->uart_reg->uart_type));
  296. }
  297. }
  298. static void sirfsoc_uart_disable_ms(struct uart_port *port)
  299. {
  300. struct sirfsoc_uart_port *sirfport = to_sirfport(port);
  301. struct sirfsoc_register *ureg = &sirfport->uart_reg->uart_reg;
  302. struct sirfsoc_int_en *uint_en = &sirfport->uart_reg->uart_int_en;
  303. if (!sirfport->hw_flow_ctrl)
  304. return;
  305. sirfport->ms_enabled = false;
  306. if (sirfport->uart_reg->uart_type == SIRF_REAL_UART) {
  307. wr_regl(port, ureg->sirfsoc_afc_ctrl,
  308. rd_regl(port, ureg->sirfsoc_afc_ctrl) & ~0x3FF);
  309. if (!sirfport->is_atlas7)
  310. wr_regl(port, ureg->sirfsoc_int_en_reg,
  311. rd_regl(port, ureg->sirfsoc_int_en_reg)&
  312. ~uint_en->sirfsoc_cts_en);
  313. else
  314. wr_regl(port, ureg->sirfsoc_int_en_clr_reg,
  315. uint_en->sirfsoc_cts_en);
  316. } else
  317. disable_irq(gpio_to_irq(sirfport->cts_gpio));
  318. }
  319. static irqreturn_t sirfsoc_uart_usp_cts_handler(int irq, void *dev_id)
  320. {
  321. struct sirfsoc_uart_port *sirfport = (struct sirfsoc_uart_port *)dev_id;
  322. struct uart_port *port = &sirfport->port;
  323. spin_lock(&port->lock);
  324. if (gpio_is_valid(sirfport->cts_gpio) && sirfport->ms_enabled)
  325. uart_handle_cts_change(port,
  326. !gpio_get_value(sirfport->cts_gpio));
  327. spin_unlock(&port->lock);
  328. return IRQ_HANDLED;
  329. }
  330. static void sirfsoc_uart_enable_ms(struct uart_port *port)
  331. {
  332. struct sirfsoc_uart_port *sirfport = to_sirfport(port);
  333. struct sirfsoc_register *ureg = &sirfport->uart_reg->uart_reg;
  334. struct sirfsoc_int_en *uint_en = &sirfport->uart_reg->uart_int_en;
  335. if (!sirfport->hw_flow_ctrl)
  336. return;
  337. sirfport->ms_enabled = true;
  338. if (sirfport->uart_reg->uart_type == SIRF_REAL_UART) {
  339. wr_regl(port, ureg->sirfsoc_afc_ctrl,
  340. rd_regl(port, ureg->sirfsoc_afc_ctrl) |
  341. SIRFUART_AFC_TX_EN | SIRFUART_AFC_RX_EN |
  342. SIRFUART_AFC_CTRL_RX_THD);
  343. if (!sirfport->is_atlas7)
  344. wr_regl(port, ureg->sirfsoc_int_en_reg,
  345. rd_regl(port, ureg->sirfsoc_int_en_reg)
  346. | uint_en->sirfsoc_cts_en);
  347. else
  348. wr_regl(port, ureg->sirfsoc_int_en_reg,
  349. uint_en->sirfsoc_cts_en);
  350. } else
  351. enable_irq(gpio_to_irq(sirfport->cts_gpio));
  352. }
  353. static void sirfsoc_uart_break_ctl(struct uart_port *port, int break_state)
  354. {
  355. struct sirfsoc_uart_port *sirfport = to_sirfport(port);
  356. struct sirfsoc_register *ureg = &sirfport->uart_reg->uart_reg;
  357. if (sirfport->uart_reg->uart_type == SIRF_REAL_UART) {
  358. unsigned long ulcon = rd_regl(port, ureg->sirfsoc_line_ctrl);
  359. if (break_state)
  360. ulcon |= SIRFUART_SET_BREAK;
  361. else
  362. ulcon &= ~SIRFUART_SET_BREAK;
  363. wr_regl(port, ureg->sirfsoc_line_ctrl, ulcon);
  364. }
  365. }
  366. static unsigned int
  367. sirfsoc_uart_pio_rx_chars(struct uart_port *port, unsigned int max_rx_count)
  368. {
  369. struct sirfsoc_uart_port *sirfport = to_sirfport(port);
  370. struct sirfsoc_register *ureg = &sirfport->uart_reg->uart_reg;
  371. struct sirfsoc_fifo_status *ufifo_st = &sirfport->uart_reg->fifo_status;
  372. unsigned int ch, rx_count = 0;
  373. struct tty_struct *tty;
  374. tty = tty_port_tty_get(&port->state->port);
  375. if (!tty)
  376. return -ENODEV;
  377. while (!(rd_regl(port, ureg->sirfsoc_rx_fifo_status) &
  378. ufifo_st->ff_empty(port))) {
  379. ch = rd_regl(port, ureg->sirfsoc_rx_fifo_data) |
  380. SIRFUART_DUMMY_READ;
  381. if (unlikely(uart_handle_sysrq_char(port, ch)))
  382. continue;
  383. uart_insert_char(port, 0, 0, ch, TTY_NORMAL);
  384. rx_count++;
  385. if (rx_count >= max_rx_count)
  386. break;
  387. }
  388. port->icount.rx += rx_count;
  389. return rx_count;
  390. }
  391. static unsigned int
  392. sirfsoc_uart_pio_tx_chars(struct sirfsoc_uart_port *sirfport, int count)
  393. {
  394. struct uart_port *port = &sirfport->port;
  395. struct sirfsoc_register *ureg = &sirfport->uart_reg->uart_reg;
  396. struct sirfsoc_fifo_status *ufifo_st = &sirfport->uart_reg->fifo_status;
  397. struct circ_buf *xmit = &port->state->xmit;
  398. unsigned int num_tx = 0;
  399. while (!uart_circ_empty(xmit) &&
  400. !(rd_regl(port, ureg->sirfsoc_tx_fifo_status) &
  401. ufifo_st->ff_full(port)) &&
  402. count--) {
  403. wr_regl(port, ureg->sirfsoc_tx_fifo_data,
  404. xmit->buf[xmit->tail]);
  405. xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
  406. port->icount.tx++;
  407. num_tx++;
  408. }
  409. if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
  410. uart_write_wakeup(port);
  411. return num_tx;
  412. }
  413. static void sirfsoc_uart_tx_dma_complete_callback(void *param)
  414. {
  415. struct sirfsoc_uart_port *sirfport = (struct sirfsoc_uart_port *)param;
  416. struct uart_port *port = &sirfport->port;
  417. struct circ_buf *xmit = &port->state->xmit;
  418. unsigned long flags;
  419. spin_lock_irqsave(&port->lock, flags);
  420. xmit->tail = (xmit->tail + sirfport->transfer_size) &
  421. (UART_XMIT_SIZE - 1);
  422. port->icount.tx += sirfport->transfer_size;
  423. if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
  424. uart_write_wakeup(port);
  425. if (sirfport->tx_dma_addr)
  426. dma_unmap_single(port->dev, sirfport->tx_dma_addr,
  427. sirfport->transfer_size, DMA_TO_DEVICE);
  428. sirfport->tx_dma_state = TX_DMA_IDLE;
  429. sirfsoc_uart_tx_with_dma(sirfport);
  430. spin_unlock_irqrestore(&port->lock, flags);
  431. }
  432. static irqreturn_t sirfsoc_uart_isr(int irq, void *dev_id)
  433. {
  434. unsigned long intr_status;
  435. unsigned long cts_status;
  436. unsigned long flag = TTY_NORMAL;
  437. struct sirfsoc_uart_port *sirfport = (struct sirfsoc_uart_port *)dev_id;
  438. struct uart_port *port = &sirfport->port;
  439. struct sirfsoc_register *ureg = &sirfport->uart_reg->uart_reg;
  440. struct sirfsoc_fifo_status *ufifo_st = &sirfport->uart_reg->fifo_status;
  441. struct sirfsoc_int_status *uint_st = &sirfport->uart_reg->uart_int_st;
  442. struct sirfsoc_int_en *uint_en = &sirfport->uart_reg->uart_int_en;
  443. struct uart_state *state = port->state;
  444. struct circ_buf *xmit = &port->state->xmit;
  445. spin_lock(&port->lock);
  446. intr_status = rd_regl(port, ureg->sirfsoc_int_st_reg);
  447. wr_regl(port, ureg->sirfsoc_int_st_reg, intr_status);
  448. intr_status &= rd_regl(port, ureg->sirfsoc_int_en_reg);
  449. if (unlikely(intr_status & (SIRFUART_ERR_INT_STAT(uint_st,
  450. sirfport->uart_reg->uart_type)))) {
  451. if (intr_status & uint_st->sirfsoc_rxd_brk) {
  452. port->icount.brk++;
  453. if (uart_handle_break(port))
  454. goto recv_char;
  455. }
  456. if (intr_status & uint_st->sirfsoc_rx_oflow) {
  457. port->icount.overrun++;
  458. flag = TTY_OVERRUN;
  459. }
  460. if (intr_status & uint_st->sirfsoc_frm_err) {
  461. port->icount.frame++;
  462. flag = TTY_FRAME;
  463. }
  464. if (intr_status & uint_st->sirfsoc_parity_err) {
  465. port->icount.parity++;
  466. flag = TTY_PARITY;
  467. }
  468. wr_regl(port, ureg->sirfsoc_rx_fifo_op, SIRFUART_FIFO_RESET);
  469. wr_regl(port, ureg->sirfsoc_rx_fifo_op, 0);
  470. wr_regl(port, ureg->sirfsoc_rx_fifo_op, SIRFUART_FIFO_START);
  471. intr_status &= port->read_status_mask;
  472. uart_insert_char(port, intr_status,
  473. uint_en->sirfsoc_rx_oflow_en, 0, flag);
  474. }
  475. recv_char:
  476. if ((sirfport->uart_reg->uart_type == SIRF_REAL_UART) &&
  477. (intr_status & SIRFUART_CTS_INT_ST(uint_st)) &&
  478. !sirfport->tx_dma_state) {
  479. cts_status = rd_regl(port, ureg->sirfsoc_afc_ctrl) &
  480. SIRFUART_AFC_CTS_STATUS;
  481. if (cts_status != 0)
  482. cts_status = 0;
  483. else
  484. cts_status = 1;
  485. uart_handle_cts_change(port, cts_status);
  486. wake_up_interruptible(&state->port.delta_msr_wait);
  487. }
  488. if (!sirfport->rx_dma_chan &&
  489. (intr_status & SIRFUART_RX_IO_INT_ST(uint_st))) {
  490. /*
  491. * chip will trigger continuous RX_TIMEOUT interrupt
  492. * in RXFIFO empty and not trigger if RXFIFO recevice
  493. * data in limit time, original method use RX_TIMEOUT
  494. * will trigger lots of useless interrupt in RXFIFO
  495. * empty.RXFIFO received one byte will trigger RX_DONE
  496. * interrupt.use RX_DONE to wait for data received
  497. * into RXFIFO, use RX_THD/RX_FULL for lots data receive
  498. * and use RX_TIMEOUT for the last left data.
  499. */
  500. if (intr_status & uint_st->sirfsoc_rx_done) {
  501. if (!sirfport->is_atlas7) {
  502. wr_regl(port, ureg->sirfsoc_int_en_reg,
  503. rd_regl(port, ureg->sirfsoc_int_en_reg)
  504. & ~(uint_en->sirfsoc_rx_done_en));
  505. wr_regl(port, ureg->sirfsoc_int_en_reg,
  506. rd_regl(port, ureg->sirfsoc_int_en_reg)
  507. | (uint_en->sirfsoc_rx_timeout_en));
  508. } else {
  509. wr_regl(port, ureg->sirfsoc_int_en_clr_reg,
  510. uint_en->sirfsoc_rx_done_en);
  511. wr_regl(port, ureg->sirfsoc_int_en_reg,
  512. uint_en->sirfsoc_rx_timeout_en);
  513. }
  514. } else {
  515. if (intr_status & uint_st->sirfsoc_rx_timeout) {
  516. if (!sirfport->is_atlas7) {
  517. wr_regl(port, ureg->sirfsoc_int_en_reg,
  518. rd_regl(port, ureg->sirfsoc_int_en_reg)
  519. & ~(uint_en->sirfsoc_rx_timeout_en));
  520. wr_regl(port, ureg->sirfsoc_int_en_reg,
  521. rd_regl(port, ureg->sirfsoc_int_en_reg)
  522. | (uint_en->sirfsoc_rx_done_en));
  523. } else {
  524. wr_regl(port,
  525. ureg->sirfsoc_int_en_clr_reg,
  526. uint_en->sirfsoc_rx_timeout_en);
  527. wr_regl(port, ureg->sirfsoc_int_en_reg,
  528. uint_en->sirfsoc_rx_done_en);
  529. }
  530. }
  531. sirfsoc_uart_pio_rx_chars(port, port->fifosize);
  532. }
  533. }
  534. spin_unlock(&port->lock);
  535. tty_flip_buffer_push(&state->port);
  536. spin_lock(&port->lock);
  537. if (intr_status & uint_st->sirfsoc_txfifo_empty) {
  538. if (sirfport->tx_dma_chan)
  539. sirfsoc_uart_tx_with_dma(sirfport);
  540. else {
  541. if (uart_circ_empty(xmit) || uart_tx_stopped(port)) {
  542. spin_unlock(&port->lock);
  543. return IRQ_HANDLED;
  544. } else {
  545. sirfsoc_uart_pio_tx_chars(sirfport,
  546. port->fifosize);
  547. if ((uart_circ_empty(xmit)) &&
  548. (rd_regl(port, ureg->sirfsoc_tx_fifo_status) &
  549. ufifo_st->ff_empty(port)))
  550. sirfsoc_uart_stop_tx(port);
  551. }
  552. }
  553. }
  554. spin_unlock(&port->lock);
  555. return IRQ_HANDLED;
  556. }
  557. static void sirfsoc_uart_rx_dma_complete_callback(void *param)
  558. {
  559. }
  560. /* submit rx dma task into dmaengine */
  561. static void sirfsoc_uart_start_next_rx_dma(struct uart_port *port)
  562. {
  563. struct sirfsoc_uart_port *sirfport = to_sirfport(port);
  564. struct sirfsoc_register *ureg = &sirfport->uart_reg->uart_reg;
  565. struct sirfsoc_int_en *uint_en = &sirfport->uart_reg->uart_int_en;
  566. wr_regl(port, ureg->sirfsoc_rx_dma_io_ctrl,
  567. rd_regl(port, ureg->sirfsoc_rx_dma_io_ctrl) &
  568. ~SIRFUART_IO_MODE);
  569. sirfport->rx_dma_items.xmit.tail =
  570. sirfport->rx_dma_items.xmit.head = 0;
  571. sirfport->rx_dma_items.desc =
  572. dmaengine_prep_dma_cyclic(sirfport->rx_dma_chan,
  573. sirfport->rx_dma_items.dma_addr, SIRFSOC_RX_DMA_BUF_SIZE,
  574. SIRFSOC_RX_DMA_BUF_SIZE / 2,
  575. DMA_DEV_TO_MEM, DMA_PREP_INTERRUPT);
  576. if (IS_ERR_OR_NULL(sirfport->rx_dma_items.desc)) {
  577. dev_err(port->dev, "DMA slave single fail\n");
  578. return;
  579. }
  580. sirfport->rx_dma_items.desc->callback =
  581. sirfsoc_uart_rx_dma_complete_callback;
  582. sirfport->rx_dma_items.desc->callback_param = sirfport;
  583. sirfport->rx_dma_items.cookie =
  584. dmaengine_submit(sirfport->rx_dma_items.desc);
  585. dma_async_issue_pending(sirfport->rx_dma_chan);
  586. if (!sirfport->is_atlas7)
  587. wr_regl(port, ureg->sirfsoc_int_en_reg,
  588. rd_regl(port, ureg->sirfsoc_int_en_reg) |
  589. SIRFUART_RX_DMA_INT_EN(uint_en,
  590. sirfport->uart_reg->uart_type));
  591. else
  592. wr_regl(port, ureg->sirfsoc_int_en_reg,
  593. SIRFUART_RX_DMA_INT_EN(uint_en,
  594. sirfport->uart_reg->uart_type));
  595. }
  596. static unsigned int
  597. sirfsoc_usp_calc_sample_div(unsigned long set_rate,
  598. unsigned long ioclk_rate, unsigned long *sample_reg)
  599. {
  600. unsigned long min_delta = ~0UL;
  601. unsigned short sample_div;
  602. unsigned long ioclk_div = 0;
  603. unsigned long temp_delta;
  604. for (sample_div = SIRF_USP_MIN_SAMPLE_DIV;
  605. sample_div <= SIRF_MAX_SAMPLE_DIV; sample_div++) {
  606. temp_delta = ioclk_rate -
  607. (ioclk_rate + (set_rate * sample_div) / 2)
  608. / (set_rate * sample_div) * set_rate * sample_div;
  609. temp_delta = (temp_delta > 0) ? temp_delta : -temp_delta;
  610. if (temp_delta < min_delta) {
  611. ioclk_div = (2 * ioclk_rate /
  612. (set_rate * sample_div) + 1) / 2 - 1;
  613. if (ioclk_div > SIRF_IOCLK_DIV_MAX)
  614. continue;
  615. min_delta = temp_delta;
  616. *sample_reg = sample_div;
  617. if (!temp_delta)
  618. break;
  619. }
  620. }
  621. return ioclk_div;
  622. }
  623. static unsigned int
  624. sirfsoc_uart_calc_sample_div(unsigned long baud_rate,
  625. unsigned long ioclk_rate, unsigned long *set_baud)
  626. {
  627. unsigned long min_delta = ~0UL;
  628. unsigned short sample_div;
  629. unsigned int regv = 0;
  630. unsigned long ioclk_div;
  631. unsigned long baud_tmp;
  632. int temp_delta;
  633. for (sample_div = SIRF_MIN_SAMPLE_DIV;
  634. sample_div <= SIRF_MAX_SAMPLE_DIV; sample_div++) {
  635. ioclk_div = (ioclk_rate / (baud_rate * (sample_div + 1))) - 1;
  636. if (ioclk_div > SIRF_IOCLK_DIV_MAX)
  637. continue;
  638. baud_tmp = ioclk_rate / ((ioclk_div + 1) * (sample_div + 1));
  639. temp_delta = baud_tmp - baud_rate;
  640. temp_delta = (temp_delta > 0) ? temp_delta : -temp_delta;
  641. if (temp_delta < min_delta) {
  642. regv = regv & (~SIRF_IOCLK_DIV_MASK);
  643. regv = regv | ioclk_div;
  644. regv = regv & (~SIRF_SAMPLE_DIV_MASK);
  645. regv = regv | (sample_div << SIRF_SAMPLE_DIV_SHIFT);
  646. min_delta = temp_delta;
  647. *set_baud = baud_tmp;
  648. }
  649. }
  650. return regv;
  651. }
  652. static void sirfsoc_uart_set_termios(struct uart_port *port,
  653. struct ktermios *termios,
  654. struct ktermios *old)
  655. {
  656. struct sirfsoc_uart_port *sirfport = to_sirfport(port);
  657. struct sirfsoc_register *ureg = &sirfport->uart_reg->uart_reg;
  658. struct sirfsoc_int_en *uint_en = &sirfport->uart_reg->uart_int_en;
  659. unsigned long config_reg = 0;
  660. unsigned long baud_rate;
  661. unsigned long set_baud;
  662. unsigned long flags;
  663. unsigned long ic;
  664. unsigned int clk_div_reg = 0;
  665. unsigned long txfifo_op_reg, ioclk_rate;
  666. unsigned long rx_time_out;
  667. int threshold_div;
  668. u32 data_bit_len, stop_bit_len, len_val;
  669. unsigned long sample_div_reg = 0xf;
  670. ioclk_rate = port->uartclk;
  671. switch (termios->c_cflag & CSIZE) {
  672. default:
  673. case CS8:
  674. data_bit_len = 8;
  675. config_reg |= SIRFUART_DATA_BIT_LEN_8;
  676. break;
  677. case CS7:
  678. data_bit_len = 7;
  679. config_reg |= SIRFUART_DATA_BIT_LEN_7;
  680. break;
  681. case CS6:
  682. data_bit_len = 6;
  683. config_reg |= SIRFUART_DATA_BIT_LEN_6;
  684. break;
  685. case CS5:
  686. data_bit_len = 5;
  687. config_reg |= SIRFUART_DATA_BIT_LEN_5;
  688. break;
  689. }
  690. if (termios->c_cflag & CSTOPB) {
  691. config_reg |= SIRFUART_STOP_BIT_LEN_2;
  692. stop_bit_len = 2;
  693. } else
  694. stop_bit_len = 1;
  695. spin_lock_irqsave(&port->lock, flags);
  696. port->read_status_mask = uint_en->sirfsoc_rx_oflow_en;
  697. port->ignore_status_mask = 0;
  698. if (sirfport->uart_reg->uart_type == SIRF_REAL_UART) {
  699. if (termios->c_iflag & INPCK)
  700. port->read_status_mask |= uint_en->sirfsoc_frm_err_en |
  701. uint_en->sirfsoc_parity_err_en;
  702. } else {
  703. if (termios->c_iflag & INPCK)
  704. port->read_status_mask |= uint_en->sirfsoc_frm_err_en;
  705. }
  706. if (termios->c_iflag & (IGNBRK | BRKINT | PARMRK))
  707. port->read_status_mask |= uint_en->sirfsoc_rxd_brk_en;
  708. if (sirfport->uart_reg->uart_type == SIRF_REAL_UART) {
  709. if (termios->c_iflag & IGNPAR)
  710. port->ignore_status_mask |=
  711. uint_en->sirfsoc_frm_err_en |
  712. uint_en->sirfsoc_parity_err_en;
  713. if (termios->c_cflag & PARENB) {
  714. if (termios->c_cflag & CMSPAR) {
  715. if (termios->c_cflag & PARODD)
  716. config_reg |= SIRFUART_STICK_BIT_MARK;
  717. else
  718. config_reg |= SIRFUART_STICK_BIT_SPACE;
  719. } else {
  720. if (termios->c_cflag & PARODD)
  721. config_reg |= SIRFUART_STICK_BIT_ODD;
  722. else
  723. config_reg |= SIRFUART_STICK_BIT_EVEN;
  724. }
  725. }
  726. } else {
  727. if (termios->c_iflag & IGNPAR)
  728. port->ignore_status_mask |=
  729. uint_en->sirfsoc_frm_err_en;
  730. if (termios->c_cflag & PARENB)
  731. dev_warn(port->dev,
  732. "USP-UART not support parity err\n");
  733. }
  734. if (termios->c_iflag & IGNBRK) {
  735. port->ignore_status_mask |=
  736. uint_en->sirfsoc_rxd_brk_en;
  737. if (termios->c_iflag & IGNPAR)
  738. port->ignore_status_mask |=
  739. uint_en->sirfsoc_rx_oflow_en;
  740. }
  741. if ((termios->c_cflag & CREAD) == 0)
  742. port->ignore_status_mask |= SIRFUART_DUMMY_READ;
  743. /* Hardware Flow Control Settings */
  744. if (UART_ENABLE_MS(port, termios->c_cflag)) {
  745. if (!sirfport->ms_enabled)
  746. sirfsoc_uart_enable_ms(port);
  747. } else {
  748. if (sirfport->ms_enabled)
  749. sirfsoc_uart_disable_ms(port);
  750. }
  751. baud_rate = uart_get_baud_rate(port, termios, old, 0, 4000000);
  752. if (ioclk_rate == 150000000) {
  753. for (ic = 0; ic < SIRF_BAUD_RATE_SUPPORT_NR; ic++)
  754. if (baud_rate == baudrate_to_regv[ic].baud_rate)
  755. clk_div_reg = baudrate_to_regv[ic].reg_val;
  756. }
  757. set_baud = baud_rate;
  758. if (sirfport->uart_reg->uart_type == SIRF_REAL_UART) {
  759. if (unlikely(clk_div_reg == 0))
  760. clk_div_reg = sirfsoc_uart_calc_sample_div(baud_rate,
  761. ioclk_rate, &set_baud);
  762. wr_regl(port, ureg->sirfsoc_divisor, clk_div_reg);
  763. } else {
  764. clk_div_reg = sirfsoc_usp_calc_sample_div(baud_rate,
  765. ioclk_rate, &sample_div_reg);
  766. sample_div_reg--;
  767. set_baud = ((ioclk_rate / (clk_div_reg+1) - 1) /
  768. (sample_div_reg + 1));
  769. /* setting usp mode 2 */
  770. len_val = ((1 << SIRFSOC_USP_MODE2_RXD_DELAY_OFFSET) |
  771. (1 << SIRFSOC_USP_MODE2_TXD_DELAY_OFFSET));
  772. len_val |= ((clk_div_reg & SIRFSOC_USP_MODE2_CLK_DIVISOR_MASK)
  773. << SIRFSOC_USP_MODE2_CLK_DIVISOR_OFFSET);
  774. wr_regl(port, ureg->sirfsoc_mode2, len_val);
  775. }
  776. if (tty_termios_baud_rate(termios))
  777. tty_termios_encode_baud_rate(termios, set_baud, set_baud);
  778. /* set receive timeout && data bits len */
  779. rx_time_out = SIRFSOC_UART_RX_TIMEOUT(set_baud, 20000);
  780. rx_time_out = SIRFUART_RECV_TIMEOUT_VALUE(rx_time_out);
  781. txfifo_op_reg = rd_regl(port, ureg->sirfsoc_tx_fifo_op);
  782. wr_regl(port, ureg->sirfsoc_tx_fifo_op,
  783. (txfifo_op_reg & ~SIRFUART_FIFO_START));
  784. if (sirfport->uart_reg->uart_type == SIRF_REAL_UART) {
  785. config_reg |= SIRFUART_UART_RECV_TIMEOUT(rx_time_out);
  786. wr_regl(port, ureg->sirfsoc_line_ctrl, config_reg);
  787. } else {
  788. /*tx frame ctrl*/
  789. len_val = (data_bit_len - 1) << SIRFSOC_USP_TX_DATA_LEN_OFFSET;
  790. len_val |= (data_bit_len + 1 + stop_bit_len - 1) <<
  791. SIRFSOC_USP_TX_FRAME_LEN_OFFSET;
  792. len_val |= ((data_bit_len - 1) <<
  793. SIRFSOC_USP_TX_SHIFTER_LEN_OFFSET);
  794. len_val |= (((clk_div_reg & 0xc00) >> 10) <<
  795. SIRFSOC_USP_TX_CLK_DIVISOR_OFFSET);
  796. wr_regl(port, ureg->sirfsoc_tx_frame_ctrl, len_val);
  797. /*rx frame ctrl*/
  798. len_val = (data_bit_len - 1) << SIRFSOC_USP_RX_DATA_LEN_OFFSET;
  799. len_val |= (data_bit_len + 1 + stop_bit_len - 1) <<
  800. SIRFSOC_USP_RX_FRAME_LEN_OFFSET;
  801. len_val |= (data_bit_len - 1) <<
  802. SIRFSOC_USP_RX_SHIFTER_LEN_OFFSET;
  803. len_val |= (((clk_div_reg & 0xf000) >> 12) <<
  804. SIRFSOC_USP_RX_CLK_DIVISOR_OFFSET);
  805. wr_regl(port, ureg->sirfsoc_rx_frame_ctrl, len_val);
  806. /*async param*/
  807. wr_regl(port, ureg->sirfsoc_async_param_reg,
  808. (SIRFUART_USP_RECV_TIMEOUT(rx_time_out)) |
  809. (sample_div_reg & SIRFSOC_USP_ASYNC_DIV2_MASK) <<
  810. SIRFSOC_USP_ASYNC_DIV2_OFFSET);
  811. }
  812. if (sirfport->tx_dma_chan)
  813. wr_regl(port, ureg->sirfsoc_tx_dma_io_ctrl, SIRFUART_DMA_MODE);
  814. else
  815. wr_regl(port, ureg->sirfsoc_tx_dma_io_ctrl, SIRFUART_IO_MODE);
  816. if (sirfport->rx_dma_chan)
  817. wr_regl(port, ureg->sirfsoc_rx_dma_io_ctrl,
  818. rd_regl(port, ureg->sirfsoc_rx_dma_io_ctrl) &
  819. ~SIRFUART_IO_MODE);
  820. else
  821. wr_regl(port, ureg->sirfsoc_rx_dma_io_ctrl,
  822. rd_regl(port, ureg->sirfsoc_rx_dma_io_ctrl) |
  823. SIRFUART_IO_MODE);
  824. sirfport->rx_period_time = 20000000;
  825. /* Reset Rx/Tx FIFO Threshold level for proper baudrate */
  826. if (set_baud < 1000000)
  827. threshold_div = 1;
  828. else
  829. threshold_div = 2;
  830. wr_regl(port, ureg->sirfsoc_tx_fifo_ctrl,
  831. SIRFUART_FIFO_THD(port) / threshold_div);
  832. wr_regl(port, ureg->sirfsoc_rx_fifo_ctrl,
  833. SIRFUART_FIFO_THD(port) / threshold_div);
  834. txfifo_op_reg |= SIRFUART_FIFO_START;
  835. wr_regl(port, ureg->sirfsoc_tx_fifo_op, txfifo_op_reg);
  836. uart_update_timeout(port, termios->c_cflag, set_baud);
  837. wr_regl(port, ureg->sirfsoc_tx_rx_en, SIRFUART_TX_EN | SIRFUART_RX_EN);
  838. spin_unlock_irqrestore(&port->lock, flags);
  839. }
  840. static void sirfsoc_uart_pm(struct uart_port *port, unsigned int state,
  841. unsigned int oldstate)
  842. {
  843. struct sirfsoc_uart_port *sirfport = to_sirfport(port);
  844. if (!state)
  845. clk_prepare_enable(sirfport->clk);
  846. else
  847. clk_disable_unprepare(sirfport->clk);
  848. }
  849. static int sirfsoc_uart_startup(struct uart_port *port)
  850. {
  851. struct sirfsoc_uart_port *sirfport = to_sirfport(port);
  852. struct sirfsoc_register *ureg = &sirfport->uart_reg->uart_reg;
  853. struct sirfsoc_int_en *uint_en = &sirfport->uart_reg->uart_int_en;
  854. unsigned int index = port->line;
  855. int ret;
  856. irq_modify_status(port->irq, IRQ_NOREQUEST, IRQ_NOAUTOEN);
  857. ret = request_irq(port->irq,
  858. sirfsoc_uart_isr,
  859. 0,
  860. SIRFUART_PORT_NAME,
  861. sirfport);
  862. if (ret != 0) {
  863. dev_err(port->dev, "UART%d request IRQ line (%d) failed.\n",
  864. index, port->irq);
  865. goto irq_err;
  866. }
  867. /* initial hardware settings */
  868. wr_regl(port, ureg->sirfsoc_tx_dma_io_ctrl,
  869. rd_regl(port, ureg->sirfsoc_tx_dma_io_ctrl) |
  870. SIRFUART_IO_MODE);
  871. wr_regl(port, ureg->sirfsoc_rx_dma_io_ctrl,
  872. rd_regl(port, ureg->sirfsoc_rx_dma_io_ctrl) |
  873. SIRFUART_IO_MODE);
  874. wr_regl(port, ureg->sirfsoc_rx_dma_io_ctrl,
  875. rd_regl(port, ureg->sirfsoc_rx_dma_io_ctrl) &
  876. ~SIRFUART_RX_DMA_FLUSH);
  877. wr_regl(port, ureg->sirfsoc_tx_dma_io_len, 0);
  878. wr_regl(port, ureg->sirfsoc_rx_dma_io_len, 0);
  879. wr_regl(port, ureg->sirfsoc_tx_rx_en, SIRFUART_RX_EN | SIRFUART_TX_EN);
  880. if (sirfport->uart_reg->uart_type == SIRF_USP_UART)
  881. wr_regl(port, ureg->sirfsoc_mode1,
  882. SIRFSOC_USP_ENDIAN_CTRL_LSBF |
  883. SIRFSOC_USP_EN);
  884. wr_regl(port, ureg->sirfsoc_tx_fifo_op, SIRFUART_FIFO_RESET);
  885. wr_regl(port, ureg->sirfsoc_rx_fifo_op, SIRFUART_FIFO_RESET);
  886. wr_regl(port, ureg->sirfsoc_rx_fifo_op, 0);
  887. wr_regl(port, ureg->sirfsoc_tx_fifo_ctrl, SIRFUART_FIFO_THD(port));
  888. wr_regl(port, ureg->sirfsoc_rx_fifo_ctrl, SIRFUART_FIFO_THD(port));
  889. if (sirfport->rx_dma_chan)
  890. wr_regl(port, ureg->sirfsoc_rx_fifo_level_chk,
  891. SIRFUART_RX_FIFO_CHK_SC(port->line, 0x1) |
  892. SIRFUART_RX_FIFO_CHK_LC(port->line, 0x2) |
  893. SIRFUART_RX_FIFO_CHK_HC(port->line, 0x4));
  894. if (sirfport->tx_dma_chan) {
  895. sirfport->tx_dma_state = TX_DMA_IDLE;
  896. wr_regl(port, ureg->sirfsoc_tx_fifo_level_chk,
  897. SIRFUART_TX_FIFO_CHK_SC(port->line, 0x1b) |
  898. SIRFUART_TX_FIFO_CHK_LC(port->line, 0xe) |
  899. SIRFUART_TX_FIFO_CHK_HC(port->line, 0x4));
  900. }
  901. sirfport->ms_enabled = false;
  902. if (sirfport->uart_reg->uart_type == SIRF_USP_UART &&
  903. sirfport->hw_flow_ctrl) {
  904. irq_modify_status(gpio_to_irq(sirfport->cts_gpio),
  905. IRQ_NOREQUEST, IRQ_NOAUTOEN);
  906. ret = request_irq(gpio_to_irq(sirfport->cts_gpio),
  907. sirfsoc_uart_usp_cts_handler, IRQF_TRIGGER_FALLING |
  908. IRQF_TRIGGER_RISING, "usp_cts_irq", sirfport);
  909. if (ret != 0) {
  910. dev_err(port->dev, "UART-USP:request gpio irq fail\n");
  911. goto init_rx_err;
  912. }
  913. }
  914. if (sirfport->uart_reg->uart_type == SIRF_REAL_UART &&
  915. sirfport->rx_dma_chan)
  916. wr_regl(port, ureg->sirfsoc_swh_dma_io,
  917. SIRFUART_CLEAR_RX_ADDR_EN);
  918. if (sirfport->uart_reg->uart_type == SIRF_USP_UART &&
  919. sirfport->rx_dma_chan)
  920. wr_regl(port, ureg->sirfsoc_rx_dma_io_ctrl,
  921. rd_regl(port, ureg->sirfsoc_rx_dma_io_ctrl) |
  922. SIRFSOC_USP_FRADDR_CLR_EN);
  923. if (sirfport->rx_dma_chan && !sirfport->is_hrt_enabled) {
  924. sirfport->is_hrt_enabled = true;
  925. sirfport->rx_period_time = 20000000;
  926. sirfport->rx_last_pos = -1;
  927. sirfport->pio_fetch_cnt = 0;
  928. sirfport->rx_dma_items.xmit.tail =
  929. sirfport->rx_dma_items.xmit.head = 0;
  930. hrtimer_start(&sirfport->hrt,
  931. ns_to_ktime(sirfport->rx_period_time),
  932. HRTIMER_MODE_REL);
  933. }
  934. wr_regl(port, ureg->sirfsoc_rx_fifo_op, SIRFUART_FIFO_START);
  935. if (sirfport->rx_dma_chan)
  936. sirfsoc_uart_start_next_rx_dma(port);
  937. else {
  938. if (!sirfport->is_atlas7)
  939. wr_regl(port, ureg->sirfsoc_int_en_reg,
  940. rd_regl(port, ureg->sirfsoc_int_en_reg) |
  941. SIRFUART_RX_IO_INT_EN(uint_en,
  942. sirfport->uart_reg->uart_type));
  943. else
  944. wr_regl(port, ureg->sirfsoc_int_en_reg,
  945. SIRFUART_RX_IO_INT_EN(uint_en,
  946. sirfport->uart_reg->uart_type));
  947. }
  948. enable_irq(port->irq);
  949. return 0;
  950. init_rx_err:
  951. free_irq(port->irq, sirfport);
  952. irq_err:
  953. return ret;
  954. }
  955. static void sirfsoc_uart_shutdown(struct uart_port *port)
  956. {
  957. struct sirfsoc_uart_port *sirfport = to_sirfport(port);
  958. struct sirfsoc_register *ureg = &sirfport->uart_reg->uart_reg;
  959. struct circ_buf *xmit;
  960. xmit = &sirfport->rx_dma_items.xmit;
  961. if (!sirfport->is_atlas7)
  962. wr_regl(port, ureg->sirfsoc_int_en_reg, 0);
  963. else
  964. wr_regl(port, ureg->sirfsoc_int_en_clr_reg, ~0UL);
  965. free_irq(port->irq, sirfport);
  966. if (sirfport->ms_enabled)
  967. sirfsoc_uart_disable_ms(port);
  968. if (sirfport->uart_reg->uart_type == SIRF_USP_UART &&
  969. sirfport->hw_flow_ctrl) {
  970. gpio_set_value(sirfport->rts_gpio, 1);
  971. free_irq(gpio_to_irq(sirfport->cts_gpio), sirfport);
  972. }
  973. if (sirfport->tx_dma_chan)
  974. sirfport->tx_dma_state = TX_DMA_IDLE;
  975. if (sirfport->rx_dma_chan && sirfport->is_hrt_enabled) {
  976. while (((rd_regl(port, ureg->sirfsoc_rx_fifo_status) &
  977. SIRFUART_RX_FIFO_MASK) > sirfport->pio_fetch_cnt) &&
  978. !CIRC_CNT(xmit->head, xmit->tail,
  979. SIRFSOC_RX_DMA_BUF_SIZE))
  980. ;
  981. sirfport->is_hrt_enabled = false;
  982. hrtimer_cancel(&sirfport->hrt);
  983. }
  984. }
  985. static const char *sirfsoc_uart_type(struct uart_port *port)
  986. {
  987. return port->type == SIRFSOC_PORT_TYPE ? SIRFUART_PORT_NAME : NULL;
  988. }
  989. static int sirfsoc_uart_request_port(struct uart_port *port)
  990. {
  991. struct sirfsoc_uart_port *sirfport = to_sirfport(port);
  992. struct sirfsoc_uart_param *uart_param = &sirfport->uart_reg->uart_param;
  993. void *ret;
  994. ret = request_mem_region(port->mapbase,
  995. SIRFUART_MAP_SIZE, uart_param->port_name);
  996. return ret ? 0 : -EBUSY;
  997. }
  998. static void sirfsoc_uart_release_port(struct uart_port *port)
  999. {
  1000. release_mem_region(port->mapbase, SIRFUART_MAP_SIZE);
  1001. }
  1002. static void sirfsoc_uart_config_port(struct uart_port *port, int flags)
  1003. {
  1004. if (flags & UART_CONFIG_TYPE) {
  1005. port->type = SIRFSOC_PORT_TYPE;
  1006. sirfsoc_uart_request_port(port);
  1007. }
  1008. }
  1009. static struct uart_ops sirfsoc_uart_ops = {
  1010. .tx_empty = sirfsoc_uart_tx_empty,
  1011. .get_mctrl = sirfsoc_uart_get_mctrl,
  1012. .set_mctrl = sirfsoc_uart_set_mctrl,
  1013. .stop_tx = sirfsoc_uart_stop_tx,
  1014. .start_tx = sirfsoc_uart_start_tx,
  1015. .stop_rx = sirfsoc_uart_stop_rx,
  1016. .enable_ms = sirfsoc_uart_enable_ms,
  1017. .break_ctl = sirfsoc_uart_break_ctl,
  1018. .startup = sirfsoc_uart_startup,
  1019. .shutdown = sirfsoc_uart_shutdown,
  1020. .set_termios = sirfsoc_uart_set_termios,
  1021. .pm = sirfsoc_uart_pm,
  1022. .type = sirfsoc_uart_type,
  1023. .release_port = sirfsoc_uart_release_port,
  1024. .request_port = sirfsoc_uart_request_port,
  1025. .config_port = sirfsoc_uart_config_port,
  1026. };
  1027. #ifdef CONFIG_SERIAL_SIRFSOC_CONSOLE
  1028. static int __init
  1029. sirfsoc_uart_console_setup(struct console *co, char *options)
  1030. {
  1031. unsigned int baud = 115200;
  1032. unsigned int bits = 8;
  1033. unsigned int parity = 'n';
  1034. unsigned int flow = 'n';
  1035. struct sirfsoc_uart_port *sirfport;
  1036. struct sirfsoc_register *ureg;
  1037. if (co->index < 0 || co->index >= SIRFSOC_UART_NR)
  1038. co->index = 1;
  1039. sirfport = sirf_ports[co->index];
  1040. if (!sirfport)
  1041. return -ENODEV;
  1042. ureg = &sirfport->uart_reg->uart_reg;
  1043. if (!sirfport->port.mapbase)
  1044. return -ENODEV;
  1045. /* enable usp in mode1 register */
  1046. if (sirfport->uart_reg->uart_type == SIRF_USP_UART)
  1047. wr_regl(&sirfport->port, ureg->sirfsoc_mode1, SIRFSOC_USP_EN |
  1048. SIRFSOC_USP_ENDIAN_CTRL_LSBF);
  1049. if (options)
  1050. uart_parse_options(options, &baud, &parity, &bits, &flow);
  1051. sirfport->port.cons = co;
  1052. /* default console tx/rx transfer using io mode */
  1053. sirfport->rx_dma_chan = NULL;
  1054. sirfport->tx_dma_chan = NULL;
  1055. return uart_set_options(&sirfport->port, co, baud, parity, bits, flow);
  1056. }
  1057. static void sirfsoc_uart_console_putchar(struct uart_port *port, int ch)
  1058. {
  1059. struct sirfsoc_uart_port *sirfport = to_sirfport(port);
  1060. struct sirfsoc_register *ureg = &sirfport->uart_reg->uart_reg;
  1061. struct sirfsoc_fifo_status *ufifo_st = &sirfport->uart_reg->fifo_status;
  1062. while (rd_regl(port, ureg->sirfsoc_tx_fifo_status) &
  1063. ufifo_st->ff_full(port))
  1064. cpu_relax();
  1065. wr_regl(port, ureg->sirfsoc_tx_fifo_data, ch);
  1066. }
  1067. static void sirfsoc_uart_console_write(struct console *co, const char *s,
  1068. unsigned int count)
  1069. {
  1070. struct sirfsoc_uart_port *sirfport = sirf_ports[co->index];
  1071. uart_console_write(&sirfport->port, s, count,
  1072. sirfsoc_uart_console_putchar);
  1073. }
  1074. static struct console sirfsoc_uart_console = {
  1075. .name = SIRFSOC_UART_NAME,
  1076. .device = uart_console_device,
  1077. .flags = CON_PRINTBUFFER,
  1078. .index = -1,
  1079. .write = sirfsoc_uart_console_write,
  1080. .setup = sirfsoc_uart_console_setup,
  1081. .data = &sirfsoc_uart_drv,
  1082. };
  1083. static int __init sirfsoc_uart_console_init(void)
  1084. {
  1085. register_console(&sirfsoc_uart_console);
  1086. return 0;
  1087. }
  1088. console_initcall(sirfsoc_uart_console_init);
  1089. #endif
  1090. static struct uart_driver sirfsoc_uart_drv = {
  1091. .owner = THIS_MODULE,
  1092. .driver_name = SIRFUART_PORT_NAME,
  1093. .nr = SIRFSOC_UART_NR,
  1094. .dev_name = SIRFSOC_UART_NAME,
  1095. .major = SIRFSOC_UART_MAJOR,
  1096. .minor = SIRFSOC_UART_MINOR,
  1097. #ifdef CONFIG_SERIAL_SIRFSOC_CONSOLE
  1098. .cons = &sirfsoc_uart_console,
  1099. #else
  1100. .cons = NULL,
  1101. #endif
  1102. };
  1103. static enum hrtimer_restart
  1104. sirfsoc_uart_rx_dma_hrtimer_callback(struct hrtimer *hrt)
  1105. {
  1106. struct sirfsoc_uart_port *sirfport;
  1107. struct uart_port *port;
  1108. int count, inserted;
  1109. struct dma_tx_state tx_state;
  1110. struct tty_struct *tty;
  1111. struct sirfsoc_register *ureg;
  1112. struct circ_buf *xmit;
  1113. struct sirfsoc_fifo_status *ufifo_st;
  1114. int max_pio_cnt;
  1115. sirfport = container_of(hrt, struct sirfsoc_uart_port, hrt);
  1116. port = &sirfport->port;
  1117. inserted = 0;
  1118. tty = port->state->port.tty;
  1119. ureg = &sirfport->uart_reg->uart_reg;
  1120. xmit = &sirfport->rx_dma_items.xmit;
  1121. ufifo_st = &sirfport->uart_reg->fifo_status;
  1122. dmaengine_tx_status(sirfport->rx_dma_chan,
  1123. sirfport->rx_dma_items.cookie, &tx_state);
  1124. if (SIRFSOC_RX_DMA_BUF_SIZE - tx_state.residue !=
  1125. sirfport->rx_last_pos) {
  1126. xmit->head = SIRFSOC_RX_DMA_BUF_SIZE - tx_state.residue;
  1127. sirfport->rx_last_pos = xmit->head;
  1128. sirfport->pio_fetch_cnt = 0;
  1129. }
  1130. count = CIRC_CNT_TO_END(xmit->head, xmit->tail,
  1131. SIRFSOC_RX_DMA_BUF_SIZE);
  1132. while (count > 0) {
  1133. inserted = tty_insert_flip_string(tty->port,
  1134. (const unsigned char *)&xmit->buf[xmit->tail], count);
  1135. if (!inserted)
  1136. goto next_hrt;
  1137. port->icount.rx += inserted;
  1138. xmit->tail = (xmit->tail + inserted) &
  1139. (SIRFSOC_RX_DMA_BUF_SIZE - 1);
  1140. count = CIRC_CNT_TO_END(xmit->head, xmit->tail,
  1141. SIRFSOC_RX_DMA_BUF_SIZE);
  1142. tty_flip_buffer_push(tty->port);
  1143. }
  1144. /*
  1145. * if RX DMA buffer data have all push into tty buffer, and there is
  1146. * only little data(less than a dma transfer unit) left in rxfifo,
  1147. * fetch it out in pio mode and switch back to dma immediately
  1148. */
  1149. if (!inserted && !count &&
  1150. ((rd_regl(port, ureg->sirfsoc_rx_fifo_status) &
  1151. SIRFUART_RX_FIFO_MASK) > sirfport->pio_fetch_cnt)) {
  1152. dmaengine_pause(sirfport->rx_dma_chan);
  1153. /* switch to pio mode */
  1154. wr_regl(port, ureg->sirfsoc_rx_dma_io_ctrl,
  1155. rd_regl(port, ureg->sirfsoc_rx_dma_io_ctrl) |
  1156. SIRFUART_IO_MODE);
  1157. /*
  1158. * UART controller SWH_DMA_IO register have CLEAR_RX_ADDR_EN
  1159. * When found changing I/O to DMA mode, it clears
  1160. * two low bits of read point;
  1161. * USP have similar FRADDR_CLR_EN bit in USP_RX_DMA_IO_CTRL.
  1162. * Fetch data out from rxfifo into DMA buffer in PIO mode,
  1163. * while switch back to DMA mode, the data fetched will override
  1164. * by DMA, as hardware have a strange behaviour:
  1165. * after switch back to DMA mode, check rxfifo status it will
  1166. * be the number PIO fetched, so record the fetched data count
  1167. * to avoid the repeated fetch
  1168. */
  1169. max_pio_cnt = 3;
  1170. while (!(rd_regl(port, ureg->sirfsoc_rx_fifo_status) &
  1171. ufifo_st->ff_empty(port)) && max_pio_cnt--) {
  1172. xmit->buf[xmit->head] =
  1173. rd_regl(port, ureg->sirfsoc_rx_fifo_data);
  1174. xmit->head = (xmit->head + 1) &
  1175. (SIRFSOC_RX_DMA_BUF_SIZE - 1);
  1176. sirfport->pio_fetch_cnt++;
  1177. }
  1178. /* switch back to dma mode */
  1179. wr_regl(port, ureg->sirfsoc_rx_dma_io_ctrl,
  1180. rd_regl(port, ureg->sirfsoc_rx_dma_io_ctrl) &
  1181. ~SIRFUART_IO_MODE);
  1182. dmaengine_resume(sirfport->rx_dma_chan);
  1183. }
  1184. next_hrt:
  1185. hrtimer_forward_now(hrt, ns_to_ktime(sirfport->rx_period_time));
  1186. return HRTIMER_RESTART;
  1187. }
  1188. static struct of_device_id sirfsoc_uart_ids[] = {
  1189. { .compatible = "sirf,prima2-uart", .data = &sirfsoc_uart,},
  1190. { .compatible = "sirf,atlas7-uart", .data = &sirfsoc_uart},
  1191. { .compatible = "sirf,prima2-usp-uart", .data = &sirfsoc_usp},
  1192. { .compatible = "sirf,atlas7-usp-uart", .data = &sirfsoc_usp},
  1193. {}
  1194. };
  1195. MODULE_DEVICE_TABLE(of, sirfsoc_uart_ids);
  1196. static int sirfsoc_uart_probe(struct platform_device *pdev)
  1197. {
  1198. struct sirfsoc_uart_port *sirfport;
  1199. struct uart_port *port;
  1200. struct resource *res;
  1201. int ret;
  1202. struct dma_slave_config slv_cfg = {
  1203. .src_maxburst = 1,
  1204. };
  1205. struct dma_slave_config tx_slv_cfg = {
  1206. .dst_maxburst = 2,
  1207. };
  1208. const struct of_device_id *match;
  1209. match = of_match_node(sirfsoc_uart_ids, pdev->dev.of_node);
  1210. sirfport = devm_kzalloc(&pdev->dev, sizeof(*sirfport), GFP_KERNEL);
  1211. if (!sirfport) {
  1212. ret = -ENOMEM;
  1213. goto err;
  1214. }
  1215. sirfport->port.line = of_alias_get_id(pdev->dev.of_node, "serial");
  1216. sirf_ports[sirfport->port.line] = sirfport;
  1217. sirfport->port.iotype = UPIO_MEM;
  1218. sirfport->port.flags = UPF_BOOT_AUTOCONF;
  1219. port = &sirfport->port;
  1220. port->dev = &pdev->dev;
  1221. port->private_data = sirfport;
  1222. sirfport->uart_reg = (struct sirfsoc_uart_register *)match->data;
  1223. sirfport->hw_flow_ctrl = of_property_read_bool(pdev->dev.of_node,
  1224. "sirf,uart-has-rtscts");
  1225. if (of_device_is_compatible(pdev->dev.of_node, "sirf,prima2-uart") ||
  1226. of_device_is_compatible(pdev->dev.of_node, "sirf,atlas7-uart"))
  1227. sirfport->uart_reg->uart_type = SIRF_REAL_UART;
  1228. if (of_device_is_compatible(pdev->dev.of_node,
  1229. "sirf,prima2-usp-uart") || of_device_is_compatible(
  1230. pdev->dev.of_node, "sirf,atlas7-usp-uart")) {
  1231. sirfport->uart_reg->uart_type = SIRF_USP_UART;
  1232. if (!sirfport->hw_flow_ctrl)
  1233. goto usp_no_flow_control;
  1234. if (of_find_property(pdev->dev.of_node, "cts-gpios", NULL))
  1235. sirfport->cts_gpio = of_get_named_gpio(
  1236. pdev->dev.of_node, "cts-gpios", 0);
  1237. else
  1238. sirfport->cts_gpio = -1;
  1239. if (of_find_property(pdev->dev.of_node, "rts-gpios", NULL))
  1240. sirfport->rts_gpio = of_get_named_gpio(
  1241. pdev->dev.of_node, "rts-gpios", 0);
  1242. else
  1243. sirfport->rts_gpio = -1;
  1244. if ((!gpio_is_valid(sirfport->cts_gpio) ||
  1245. !gpio_is_valid(sirfport->rts_gpio))) {
  1246. ret = -EINVAL;
  1247. dev_err(&pdev->dev,
  1248. "Usp flow control must have cts and rts gpio");
  1249. goto err;
  1250. }
  1251. ret = devm_gpio_request(&pdev->dev, sirfport->cts_gpio,
  1252. "usp-cts-gpio");
  1253. if (ret) {
  1254. dev_err(&pdev->dev, "Unable request cts gpio");
  1255. goto err;
  1256. }
  1257. gpio_direction_input(sirfport->cts_gpio);
  1258. ret = devm_gpio_request(&pdev->dev, sirfport->rts_gpio,
  1259. "usp-rts-gpio");
  1260. if (ret) {
  1261. dev_err(&pdev->dev, "Unable request rts gpio");
  1262. goto err;
  1263. }
  1264. gpio_direction_output(sirfport->rts_gpio, 1);
  1265. }
  1266. usp_no_flow_control:
  1267. if (of_device_is_compatible(pdev->dev.of_node, "sirf,atlas7-uart") ||
  1268. of_device_is_compatible(pdev->dev.of_node, "sirf,atlas7-usp-uart"))
  1269. sirfport->is_atlas7 = true;
  1270. if (of_property_read_u32(pdev->dev.of_node,
  1271. "fifosize",
  1272. &port->fifosize)) {
  1273. dev_err(&pdev->dev,
  1274. "Unable to find fifosize in uart node.\n");
  1275. ret = -EFAULT;
  1276. goto err;
  1277. }
  1278. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  1279. if (res == NULL) {
  1280. dev_err(&pdev->dev, "Insufficient resources.\n");
  1281. ret = -EFAULT;
  1282. goto err;
  1283. }
  1284. port->mapbase = res->start;
  1285. port->membase = devm_ioremap(&pdev->dev,
  1286. res->start, resource_size(res));
  1287. if (!port->membase) {
  1288. dev_err(&pdev->dev, "Cannot remap resource.\n");
  1289. ret = -ENOMEM;
  1290. goto err;
  1291. }
  1292. res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
  1293. if (res == NULL) {
  1294. dev_err(&pdev->dev, "Insufficient resources.\n");
  1295. ret = -EFAULT;
  1296. goto err;
  1297. }
  1298. port->irq = res->start;
  1299. sirfport->clk = devm_clk_get(&pdev->dev, NULL);
  1300. if (IS_ERR(sirfport->clk)) {
  1301. ret = PTR_ERR(sirfport->clk);
  1302. goto err;
  1303. }
  1304. port->uartclk = clk_get_rate(sirfport->clk);
  1305. port->ops = &sirfsoc_uart_ops;
  1306. spin_lock_init(&port->lock);
  1307. platform_set_drvdata(pdev, sirfport);
  1308. ret = uart_add_one_port(&sirfsoc_uart_drv, port);
  1309. if (ret != 0) {
  1310. dev_err(&pdev->dev, "Cannot add UART port(%d).\n", pdev->id);
  1311. goto err;
  1312. }
  1313. sirfport->rx_dma_chan = dma_request_slave_channel(port->dev, "rx");
  1314. sirfport->rx_dma_items.xmit.buf =
  1315. dma_alloc_coherent(port->dev, SIRFSOC_RX_DMA_BUF_SIZE,
  1316. &sirfport->rx_dma_items.dma_addr, GFP_KERNEL);
  1317. if (!sirfport->rx_dma_items.xmit.buf) {
  1318. dev_err(port->dev, "Uart alloc bufa failed\n");
  1319. ret = -ENOMEM;
  1320. goto alloc_coherent_err;
  1321. }
  1322. sirfport->rx_dma_items.xmit.head =
  1323. sirfport->rx_dma_items.xmit.tail = 0;
  1324. if (sirfport->rx_dma_chan)
  1325. dmaengine_slave_config(sirfport->rx_dma_chan, &slv_cfg);
  1326. sirfport->tx_dma_chan = dma_request_slave_channel(port->dev, "tx");
  1327. if (sirfport->tx_dma_chan)
  1328. dmaengine_slave_config(sirfport->tx_dma_chan, &tx_slv_cfg);
  1329. if (sirfport->rx_dma_chan) {
  1330. hrtimer_init(&sirfport->hrt, CLOCK_MONOTONIC, HRTIMER_MODE_REL);
  1331. sirfport->hrt.function = sirfsoc_uart_rx_dma_hrtimer_callback;
  1332. sirfport->is_hrt_enabled = false;
  1333. }
  1334. return 0;
  1335. alloc_coherent_err:
  1336. dma_free_coherent(port->dev, SIRFSOC_RX_DMA_BUF_SIZE,
  1337. sirfport->rx_dma_items.xmit.buf,
  1338. sirfport->rx_dma_items.dma_addr);
  1339. dma_release_channel(sirfport->rx_dma_chan);
  1340. err:
  1341. return ret;
  1342. }
  1343. static int sirfsoc_uart_remove(struct platform_device *pdev)
  1344. {
  1345. struct sirfsoc_uart_port *sirfport = platform_get_drvdata(pdev);
  1346. struct uart_port *port = &sirfport->port;
  1347. uart_remove_one_port(&sirfsoc_uart_drv, port);
  1348. if (sirfport->rx_dma_chan) {
  1349. dmaengine_terminate_all(sirfport->rx_dma_chan);
  1350. dma_release_channel(sirfport->rx_dma_chan);
  1351. dma_free_coherent(port->dev, SIRFSOC_RX_DMA_BUF_SIZE,
  1352. sirfport->rx_dma_items.xmit.buf,
  1353. sirfport->rx_dma_items.dma_addr);
  1354. }
  1355. if (sirfport->tx_dma_chan) {
  1356. dmaengine_terminate_all(sirfport->tx_dma_chan);
  1357. dma_release_channel(sirfport->tx_dma_chan);
  1358. }
  1359. return 0;
  1360. }
  1361. #ifdef CONFIG_PM_SLEEP
  1362. static int
  1363. sirfsoc_uart_suspend(struct device *pdev)
  1364. {
  1365. struct sirfsoc_uart_port *sirfport = dev_get_drvdata(pdev);
  1366. struct uart_port *port = &sirfport->port;
  1367. uart_suspend_port(&sirfsoc_uart_drv, port);
  1368. return 0;
  1369. }
  1370. static int sirfsoc_uart_resume(struct device *pdev)
  1371. {
  1372. struct sirfsoc_uart_port *sirfport = dev_get_drvdata(pdev);
  1373. struct uart_port *port = &sirfport->port;
  1374. uart_resume_port(&sirfsoc_uart_drv, port);
  1375. return 0;
  1376. }
  1377. #endif
  1378. static const struct dev_pm_ops sirfsoc_uart_pm_ops = {
  1379. SET_SYSTEM_SLEEP_PM_OPS(sirfsoc_uart_suspend, sirfsoc_uart_resume)
  1380. };
  1381. static struct platform_driver sirfsoc_uart_driver = {
  1382. .probe = sirfsoc_uart_probe,
  1383. .remove = sirfsoc_uart_remove,
  1384. .driver = {
  1385. .name = SIRFUART_PORT_NAME,
  1386. .of_match_table = sirfsoc_uart_ids,
  1387. .pm = &sirfsoc_uart_pm_ops,
  1388. },
  1389. };
  1390. static int __init sirfsoc_uart_init(void)
  1391. {
  1392. int ret = 0;
  1393. ret = uart_register_driver(&sirfsoc_uart_drv);
  1394. if (ret)
  1395. goto out;
  1396. ret = platform_driver_register(&sirfsoc_uart_driver);
  1397. if (ret)
  1398. uart_unregister_driver(&sirfsoc_uart_drv);
  1399. out:
  1400. return ret;
  1401. }
  1402. module_init(sirfsoc_uart_init);
  1403. static void __exit sirfsoc_uart_exit(void)
  1404. {
  1405. platform_driver_unregister(&sirfsoc_uart_driver);
  1406. uart_unregister_driver(&sirfsoc_uart_drv);
  1407. }
  1408. module_exit(sirfsoc_uart_exit);
  1409. MODULE_LICENSE("GPL v2");
  1410. MODULE_AUTHOR("Bin Shi <Bin.Shi@csr.com>, Rong Wang<Rong.Wang@csr.com>");
  1411. MODULE_DESCRIPTION("CSR SiRFprimaII Uart Driver");