vr41xx_siu.c 20 KB

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  1. /*
  2. * Driver for NEC VR4100 series Serial Interface Unit.
  3. *
  4. * Copyright (C) 2004-2008 Yoichi Yuasa <yuasa@linux-mips.org>
  5. *
  6. * Based on drivers/serial/8250.c, by Russell King.
  7. *
  8. * This program is free software; you can redistribute it and/or modify
  9. * it under the terms of the GNU General Public License as published by
  10. * the Free Software Foundation; either version 2 of the License, or
  11. * (at your option) any later version.
  12. *
  13. * This program is distributed in the hope that it will be useful,
  14. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16. * GNU General Public License for more details.
  17. *
  18. * You should have received a copy of the GNU General Public License
  19. * along with this program; if not, write to the Free Software
  20. * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
  21. */
  22. #if defined(CONFIG_SERIAL_VR41XX_CONSOLE) && defined(CONFIG_MAGIC_SYSRQ)
  23. #define SUPPORT_SYSRQ
  24. #endif
  25. #include <linux/console.h>
  26. #include <linux/errno.h>
  27. #include <linux/init.h>
  28. #include <linux/interrupt.h>
  29. #include <linux/ioport.h>
  30. #include <linux/module.h>
  31. #include <linux/platform_device.h>
  32. #include <linux/serial.h>
  33. #include <linux/serial_core.h>
  34. #include <linux/serial_reg.h>
  35. #include <linux/tty.h>
  36. #include <linux/tty_flip.h>
  37. #include <asm/io.h>
  38. #include <asm/vr41xx/siu.h>
  39. #include <asm/vr41xx/vr41xx.h>
  40. #define SIU_BAUD_BASE 1152000
  41. #define SIU_MAJOR 204
  42. #define SIU_MINOR_BASE 82
  43. #define RX_MAX_COUNT 256
  44. #define TX_MAX_COUNT 15
  45. #define SIUIRSEL 0x08
  46. #define TMICMODE 0x20
  47. #define TMICTX 0x10
  48. #define IRMSEL 0x0c
  49. #define IRMSEL_HP 0x08
  50. #define IRMSEL_TEMIC 0x04
  51. #define IRMSEL_SHARP 0x00
  52. #define IRUSESEL 0x02
  53. #define SIRSEL 0x01
  54. static struct uart_port siu_uart_ports[SIU_PORTS_MAX] = {
  55. [0 ... SIU_PORTS_MAX-1] = {
  56. .lock = __SPIN_LOCK_UNLOCKED(siu_uart_ports->lock),
  57. .irq = 0,
  58. },
  59. };
  60. #ifdef CONFIG_SERIAL_VR41XX_CONSOLE
  61. static uint8_t lsr_break_flag[SIU_PORTS_MAX];
  62. #endif
  63. #define siu_read(port, offset) readb((port)->membase + (offset))
  64. #define siu_write(port, offset, value) writeb((value), (port)->membase + (offset))
  65. void vr41xx_select_siu_interface(siu_interface_t interface)
  66. {
  67. struct uart_port *port;
  68. unsigned long flags;
  69. uint8_t irsel;
  70. port = &siu_uart_ports[0];
  71. spin_lock_irqsave(&port->lock, flags);
  72. irsel = siu_read(port, SIUIRSEL);
  73. if (interface == SIU_INTERFACE_IRDA)
  74. irsel |= SIRSEL;
  75. else
  76. irsel &= ~SIRSEL;
  77. siu_write(port, SIUIRSEL, irsel);
  78. spin_unlock_irqrestore(&port->lock, flags);
  79. }
  80. EXPORT_SYMBOL_GPL(vr41xx_select_siu_interface);
  81. void vr41xx_use_irda(irda_use_t use)
  82. {
  83. struct uart_port *port;
  84. unsigned long flags;
  85. uint8_t irsel;
  86. port = &siu_uart_ports[0];
  87. spin_lock_irqsave(&port->lock, flags);
  88. irsel = siu_read(port, SIUIRSEL);
  89. if (use == FIR_USE_IRDA)
  90. irsel |= IRUSESEL;
  91. else
  92. irsel &= ~IRUSESEL;
  93. siu_write(port, SIUIRSEL, irsel);
  94. spin_unlock_irqrestore(&port->lock, flags);
  95. }
  96. EXPORT_SYMBOL_GPL(vr41xx_use_irda);
  97. void vr41xx_select_irda_module(irda_module_t module, irda_speed_t speed)
  98. {
  99. struct uart_port *port;
  100. unsigned long flags;
  101. uint8_t irsel;
  102. port = &siu_uart_ports[0];
  103. spin_lock_irqsave(&port->lock, flags);
  104. irsel = siu_read(port, SIUIRSEL);
  105. irsel &= ~(IRMSEL | TMICTX | TMICMODE);
  106. switch (module) {
  107. case SHARP_IRDA:
  108. irsel |= IRMSEL_SHARP;
  109. break;
  110. case TEMIC_IRDA:
  111. irsel |= IRMSEL_TEMIC | TMICMODE;
  112. if (speed == IRDA_TX_4MBPS)
  113. irsel |= TMICTX;
  114. break;
  115. case HP_IRDA:
  116. irsel |= IRMSEL_HP;
  117. break;
  118. default:
  119. break;
  120. }
  121. siu_write(port, SIUIRSEL, irsel);
  122. spin_unlock_irqrestore(&port->lock, flags);
  123. }
  124. EXPORT_SYMBOL_GPL(vr41xx_select_irda_module);
  125. static inline void siu_clear_fifo(struct uart_port *port)
  126. {
  127. siu_write(port, UART_FCR, UART_FCR_ENABLE_FIFO);
  128. siu_write(port, UART_FCR, UART_FCR_ENABLE_FIFO | UART_FCR_CLEAR_RCVR |
  129. UART_FCR_CLEAR_XMIT);
  130. siu_write(port, UART_FCR, 0);
  131. }
  132. static inline unsigned long siu_port_size(struct uart_port *port)
  133. {
  134. switch (port->type) {
  135. case PORT_VR41XX_SIU:
  136. return 11UL;
  137. case PORT_VR41XX_DSIU:
  138. return 8UL;
  139. }
  140. return 0;
  141. }
  142. static inline unsigned int siu_check_type(struct uart_port *port)
  143. {
  144. if (port->line == 0)
  145. return PORT_VR41XX_SIU;
  146. if (port->line == 1 && port->irq)
  147. return PORT_VR41XX_DSIU;
  148. return PORT_UNKNOWN;
  149. }
  150. static inline const char *siu_type_name(struct uart_port *port)
  151. {
  152. switch (port->type) {
  153. case PORT_VR41XX_SIU:
  154. return "SIU";
  155. case PORT_VR41XX_DSIU:
  156. return "DSIU";
  157. }
  158. return NULL;
  159. }
  160. static unsigned int siu_tx_empty(struct uart_port *port)
  161. {
  162. uint8_t lsr;
  163. lsr = siu_read(port, UART_LSR);
  164. if (lsr & UART_LSR_TEMT)
  165. return TIOCSER_TEMT;
  166. return 0;
  167. }
  168. static void siu_set_mctrl(struct uart_port *port, unsigned int mctrl)
  169. {
  170. uint8_t mcr = 0;
  171. if (mctrl & TIOCM_DTR)
  172. mcr |= UART_MCR_DTR;
  173. if (mctrl & TIOCM_RTS)
  174. mcr |= UART_MCR_RTS;
  175. if (mctrl & TIOCM_OUT1)
  176. mcr |= UART_MCR_OUT1;
  177. if (mctrl & TIOCM_OUT2)
  178. mcr |= UART_MCR_OUT2;
  179. if (mctrl & TIOCM_LOOP)
  180. mcr |= UART_MCR_LOOP;
  181. siu_write(port, UART_MCR, mcr);
  182. }
  183. static unsigned int siu_get_mctrl(struct uart_port *port)
  184. {
  185. uint8_t msr;
  186. unsigned int mctrl = 0;
  187. msr = siu_read(port, UART_MSR);
  188. if (msr & UART_MSR_DCD)
  189. mctrl |= TIOCM_CAR;
  190. if (msr & UART_MSR_RI)
  191. mctrl |= TIOCM_RNG;
  192. if (msr & UART_MSR_DSR)
  193. mctrl |= TIOCM_DSR;
  194. if (msr & UART_MSR_CTS)
  195. mctrl |= TIOCM_CTS;
  196. return mctrl;
  197. }
  198. static void siu_stop_tx(struct uart_port *port)
  199. {
  200. unsigned long flags;
  201. uint8_t ier;
  202. spin_lock_irqsave(&port->lock, flags);
  203. ier = siu_read(port, UART_IER);
  204. ier &= ~UART_IER_THRI;
  205. siu_write(port, UART_IER, ier);
  206. spin_unlock_irqrestore(&port->lock, flags);
  207. }
  208. static void siu_start_tx(struct uart_port *port)
  209. {
  210. unsigned long flags;
  211. uint8_t ier;
  212. spin_lock_irqsave(&port->lock, flags);
  213. ier = siu_read(port, UART_IER);
  214. ier |= UART_IER_THRI;
  215. siu_write(port, UART_IER, ier);
  216. spin_unlock_irqrestore(&port->lock, flags);
  217. }
  218. static void siu_stop_rx(struct uart_port *port)
  219. {
  220. unsigned long flags;
  221. uint8_t ier;
  222. spin_lock_irqsave(&port->lock, flags);
  223. ier = siu_read(port, UART_IER);
  224. ier &= ~UART_IER_RLSI;
  225. siu_write(port, UART_IER, ier);
  226. port->read_status_mask &= ~UART_LSR_DR;
  227. spin_unlock_irqrestore(&port->lock, flags);
  228. }
  229. static void siu_enable_ms(struct uart_port *port)
  230. {
  231. unsigned long flags;
  232. uint8_t ier;
  233. spin_lock_irqsave(&port->lock, flags);
  234. ier = siu_read(port, UART_IER);
  235. ier |= UART_IER_MSI;
  236. siu_write(port, UART_IER, ier);
  237. spin_unlock_irqrestore(&port->lock, flags);
  238. }
  239. static void siu_break_ctl(struct uart_port *port, int ctl)
  240. {
  241. unsigned long flags;
  242. uint8_t lcr;
  243. spin_lock_irqsave(&port->lock, flags);
  244. lcr = siu_read(port, UART_LCR);
  245. if (ctl == -1)
  246. lcr |= UART_LCR_SBC;
  247. else
  248. lcr &= ~UART_LCR_SBC;
  249. siu_write(port, UART_LCR, lcr);
  250. spin_unlock_irqrestore(&port->lock, flags);
  251. }
  252. static inline void receive_chars(struct uart_port *port, uint8_t *status)
  253. {
  254. uint8_t lsr, ch;
  255. char flag;
  256. int max_count = RX_MAX_COUNT;
  257. lsr = *status;
  258. do {
  259. ch = siu_read(port, UART_RX);
  260. port->icount.rx++;
  261. flag = TTY_NORMAL;
  262. #ifdef CONFIG_SERIAL_VR41XX_CONSOLE
  263. lsr |= lsr_break_flag[port->line];
  264. lsr_break_flag[port->line] = 0;
  265. #endif
  266. if (unlikely(lsr & (UART_LSR_BI | UART_LSR_FE |
  267. UART_LSR_PE | UART_LSR_OE))) {
  268. if (lsr & UART_LSR_BI) {
  269. lsr &= ~(UART_LSR_FE | UART_LSR_PE);
  270. port->icount.brk++;
  271. if (uart_handle_break(port))
  272. goto ignore_char;
  273. }
  274. if (lsr & UART_LSR_FE)
  275. port->icount.frame++;
  276. if (lsr & UART_LSR_PE)
  277. port->icount.parity++;
  278. if (lsr & UART_LSR_OE)
  279. port->icount.overrun++;
  280. lsr &= port->read_status_mask;
  281. if (lsr & UART_LSR_BI)
  282. flag = TTY_BREAK;
  283. if (lsr & UART_LSR_FE)
  284. flag = TTY_FRAME;
  285. if (lsr & UART_LSR_PE)
  286. flag = TTY_PARITY;
  287. }
  288. if (uart_handle_sysrq_char(port, ch))
  289. goto ignore_char;
  290. uart_insert_char(port, lsr, UART_LSR_OE, ch, flag);
  291. ignore_char:
  292. lsr = siu_read(port, UART_LSR);
  293. } while ((lsr & UART_LSR_DR) && (max_count-- > 0));
  294. tty_flip_buffer_push(&port->state->port);
  295. *status = lsr;
  296. }
  297. static inline void check_modem_status(struct uart_port *port)
  298. {
  299. uint8_t msr;
  300. msr = siu_read(port, UART_MSR);
  301. if ((msr & UART_MSR_ANY_DELTA) == 0)
  302. return;
  303. if (msr & UART_MSR_DDCD)
  304. uart_handle_dcd_change(port, msr & UART_MSR_DCD);
  305. if (msr & UART_MSR_TERI)
  306. port->icount.rng++;
  307. if (msr & UART_MSR_DDSR)
  308. port->icount.dsr++;
  309. if (msr & UART_MSR_DCTS)
  310. uart_handle_cts_change(port, msr & UART_MSR_CTS);
  311. wake_up_interruptible(&port->state->port.delta_msr_wait);
  312. }
  313. static inline void transmit_chars(struct uart_port *port)
  314. {
  315. struct circ_buf *xmit;
  316. int max_count = TX_MAX_COUNT;
  317. xmit = &port->state->xmit;
  318. if (port->x_char) {
  319. siu_write(port, UART_TX, port->x_char);
  320. port->icount.tx++;
  321. port->x_char = 0;
  322. return;
  323. }
  324. if (uart_circ_empty(xmit) || uart_tx_stopped(port)) {
  325. siu_stop_tx(port);
  326. return;
  327. }
  328. do {
  329. siu_write(port, UART_TX, xmit->buf[xmit->tail]);
  330. xmit->tail = (xmit->tail + 1) & (UART_XMIT_SIZE - 1);
  331. port->icount.tx++;
  332. if (uart_circ_empty(xmit))
  333. break;
  334. } while (max_count-- > 0);
  335. if (uart_circ_chars_pending(xmit) < WAKEUP_CHARS)
  336. uart_write_wakeup(port);
  337. if (uart_circ_empty(xmit))
  338. siu_stop_tx(port);
  339. }
  340. static irqreturn_t siu_interrupt(int irq, void *dev_id)
  341. {
  342. struct uart_port *port;
  343. uint8_t iir, lsr;
  344. port = (struct uart_port *)dev_id;
  345. iir = siu_read(port, UART_IIR);
  346. if (iir & UART_IIR_NO_INT)
  347. return IRQ_NONE;
  348. lsr = siu_read(port, UART_LSR);
  349. if (lsr & UART_LSR_DR)
  350. receive_chars(port, &lsr);
  351. check_modem_status(port);
  352. if (lsr & UART_LSR_THRE)
  353. transmit_chars(port);
  354. return IRQ_HANDLED;
  355. }
  356. static int siu_startup(struct uart_port *port)
  357. {
  358. int retval;
  359. if (port->membase == NULL)
  360. return -ENODEV;
  361. siu_clear_fifo(port);
  362. (void)siu_read(port, UART_LSR);
  363. (void)siu_read(port, UART_RX);
  364. (void)siu_read(port, UART_IIR);
  365. (void)siu_read(port, UART_MSR);
  366. if (siu_read(port, UART_LSR) == 0xff)
  367. return -ENODEV;
  368. retval = request_irq(port->irq, siu_interrupt, 0, siu_type_name(port), port);
  369. if (retval)
  370. return retval;
  371. if (port->type == PORT_VR41XX_DSIU)
  372. vr41xx_enable_dsiuint(DSIUINT_ALL);
  373. siu_write(port, UART_LCR, UART_LCR_WLEN8);
  374. spin_lock_irq(&port->lock);
  375. siu_set_mctrl(port, port->mctrl);
  376. spin_unlock_irq(&port->lock);
  377. siu_write(port, UART_IER, UART_IER_RLSI | UART_IER_RDI);
  378. (void)siu_read(port, UART_LSR);
  379. (void)siu_read(port, UART_RX);
  380. (void)siu_read(port, UART_IIR);
  381. (void)siu_read(port, UART_MSR);
  382. return 0;
  383. }
  384. static void siu_shutdown(struct uart_port *port)
  385. {
  386. unsigned long flags;
  387. uint8_t lcr;
  388. siu_write(port, UART_IER, 0);
  389. spin_lock_irqsave(&port->lock, flags);
  390. port->mctrl &= ~TIOCM_OUT2;
  391. siu_set_mctrl(port, port->mctrl);
  392. spin_unlock_irqrestore(&port->lock, flags);
  393. lcr = siu_read(port, UART_LCR);
  394. lcr &= ~UART_LCR_SBC;
  395. siu_write(port, UART_LCR, lcr);
  396. siu_clear_fifo(port);
  397. (void)siu_read(port, UART_RX);
  398. if (port->type == PORT_VR41XX_DSIU)
  399. vr41xx_disable_dsiuint(DSIUINT_ALL);
  400. free_irq(port->irq, port);
  401. }
  402. static void siu_set_termios(struct uart_port *port, struct ktermios *new,
  403. struct ktermios *old)
  404. {
  405. tcflag_t c_cflag, c_iflag;
  406. uint8_t lcr, fcr, ier;
  407. unsigned int baud, quot;
  408. unsigned long flags;
  409. c_cflag = new->c_cflag;
  410. switch (c_cflag & CSIZE) {
  411. case CS5:
  412. lcr = UART_LCR_WLEN5;
  413. break;
  414. case CS6:
  415. lcr = UART_LCR_WLEN6;
  416. break;
  417. case CS7:
  418. lcr = UART_LCR_WLEN7;
  419. break;
  420. default:
  421. lcr = UART_LCR_WLEN8;
  422. break;
  423. }
  424. if (c_cflag & CSTOPB)
  425. lcr |= UART_LCR_STOP;
  426. if (c_cflag & PARENB)
  427. lcr |= UART_LCR_PARITY;
  428. if ((c_cflag & PARODD) != PARODD)
  429. lcr |= UART_LCR_EPAR;
  430. if (c_cflag & CMSPAR)
  431. lcr |= UART_LCR_SPAR;
  432. baud = uart_get_baud_rate(port, new, old, 0, port->uartclk/16);
  433. quot = uart_get_divisor(port, baud);
  434. fcr = UART_FCR_ENABLE_FIFO | UART_FCR_R_TRIG_10;
  435. spin_lock_irqsave(&port->lock, flags);
  436. uart_update_timeout(port, c_cflag, baud);
  437. c_iflag = new->c_iflag;
  438. port->read_status_mask = UART_LSR_THRE | UART_LSR_OE | UART_LSR_DR;
  439. if (c_iflag & INPCK)
  440. port->read_status_mask |= UART_LSR_FE | UART_LSR_PE;
  441. if (c_iflag & (IGNBRK | BRKINT | PARMRK))
  442. port->read_status_mask |= UART_LSR_BI;
  443. port->ignore_status_mask = 0;
  444. if (c_iflag & IGNPAR)
  445. port->ignore_status_mask |= UART_LSR_FE | UART_LSR_PE;
  446. if (c_iflag & IGNBRK) {
  447. port->ignore_status_mask |= UART_LSR_BI;
  448. if (c_iflag & IGNPAR)
  449. port->ignore_status_mask |= UART_LSR_OE;
  450. }
  451. if ((c_cflag & CREAD) == 0)
  452. port->ignore_status_mask |= UART_LSR_DR;
  453. ier = siu_read(port, UART_IER);
  454. ier &= ~UART_IER_MSI;
  455. if (UART_ENABLE_MS(port, c_cflag))
  456. ier |= UART_IER_MSI;
  457. siu_write(port, UART_IER, ier);
  458. siu_write(port, UART_LCR, lcr | UART_LCR_DLAB);
  459. siu_write(port, UART_DLL, (uint8_t)quot);
  460. siu_write(port, UART_DLM, (uint8_t)(quot >> 8));
  461. siu_write(port, UART_LCR, lcr);
  462. siu_write(port, UART_FCR, fcr);
  463. siu_set_mctrl(port, port->mctrl);
  464. spin_unlock_irqrestore(&port->lock, flags);
  465. }
  466. static void siu_pm(struct uart_port *port, unsigned int state, unsigned int oldstate)
  467. {
  468. switch (state) {
  469. case 0:
  470. switch (port->type) {
  471. case PORT_VR41XX_SIU:
  472. vr41xx_supply_clock(SIU_CLOCK);
  473. break;
  474. case PORT_VR41XX_DSIU:
  475. vr41xx_supply_clock(DSIU_CLOCK);
  476. break;
  477. }
  478. break;
  479. case 3:
  480. switch (port->type) {
  481. case PORT_VR41XX_SIU:
  482. vr41xx_mask_clock(SIU_CLOCK);
  483. break;
  484. case PORT_VR41XX_DSIU:
  485. vr41xx_mask_clock(DSIU_CLOCK);
  486. break;
  487. }
  488. break;
  489. }
  490. }
  491. static const char *siu_type(struct uart_port *port)
  492. {
  493. return siu_type_name(port);
  494. }
  495. static void siu_release_port(struct uart_port *port)
  496. {
  497. unsigned long size;
  498. if (port->flags & UPF_IOREMAP) {
  499. iounmap(port->membase);
  500. port->membase = NULL;
  501. }
  502. size = siu_port_size(port);
  503. release_mem_region(port->mapbase, size);
  504. }
  505. static int siu_request_port(struct uart_port *port)
  506. {
  507. unsigned long size;
  508. struct resource *res;
  509. size = siu_port_size(port);
  510. res = request_mem_region(port->mapbase, size, siu_type_name(port));
  511. if (res == NULL)
  512. return -EBUSY;
  513. if (port->flags & UPF_IOREMAP) {
  514. port->membase = ioremap(port->mapbase, size);
  515. if (port->membase == NULL) {
  516. release_resource(res);
  517. return -ENOMEM;
  518. }
  519. }
  520. return 0;
  521. }
  522. static void siu_config_port(struct uart_port *port, int flags)
  523. {
  524. if (flags & UART_CONFIG_TYPE) {
  525. port->type = siu_check_type(port);
  526. (void)siu_request_port(port);
  527. }
  528. }
  529. static int siu_verify_port(struct uart_port *port, struct serial_struct *serial)
  530. {
  531. if (port->type != PORT_VR41XX_SIU && port->type != PORT_VR41XX_DSIU)
  532. return -EINVAL;
  533. if (port->irq != serial->irq)
  534. return -EINVAL;
  535. if (port->iotype != serial->io_type)
  536. return -EINVAL;
  537. if (port->mapbase != (unsigned long)serial->iomem_base)
  538. return -EINVAL;
  539. return 0;
  540. }
  541. static struct uart_ops siu_uart_ops = {
  542. .tx_empty = siu_tx_empty,
  543. .set_mctrl = siu_set_mctrl,
  544. .get_mctrl = siu_get_mctrl,
  545. .stop_tx = siu_stop_tx,
  546. .start_tx = siu_start_tx,
  547. .stop_rx = siu_stop_rx,
  548. .enable_ms = siu_enable_ms,
  549. .break_ctl = siu_break_ctl,
  550. .startup = siu_startup,
  551. .shutdown = siu_shutdown,
  552. .set_termios = siu_set_termios,
  553. .pm = siu_pm,
  554. .type = siu_type,
  555. .release_port = siu_release_port,
  556. .request_port = siu_request_port,
  557. .config_port = siu_config_port,
  558. .verify_port = siu_verify_port,
  559. };
  560. static int siu_init_ports(struct platform_device *pdev)
  561. {
  562. struct uart_port *port;
  563. struct resource *res;
  564. int *type = dev_get_platdata(&pdev->dev);
  565. int i;
  566. if (!type)
  567. return 0;
  568. port = siu_uart_ports;
  569. for (i = 0; i < SIU_PORTS_MAX; i++) {
  570. port->type = type[i];
  571. if (port->type == PORT_UNKNOWN)
  572. continue;
  573. port->irq = platform_get_irq(pdev, i);
  574. port->uartclk = SIU_BAUD_BASE * 16;
  575. port->fifosize = 16;
  576. port->regshift = 0;
  577. port->iotype = UPIO_MEM;
  578. port->flags = UPF_IOREMAP | UPF_BOOT_AUTOCONF;
  579. port->line = i;
  580. res = platform_get_resource(pdev, IORESOURCE_MEM, i);
  581. port->mapbase = res->start;
  582. port++;
  583. }
  584. return i;
  585. }
  586. #ifdef CONFIG_SERIAL_VR41XX_CONSOLE
  587. #define BOTH_EMPTY (UART_LSR_TEMT | UART_LSR_THRE)
  588. static void wait_for_xmitr(struct uart_port *port)
  589. {
  590. int timeout = 10000;
  591. uint8_t lsr, msr;
  592. do {
  593. lsr = siu_read(port, UART_LSR);
  594. if (lsr & UART_LSR_BI)
  595. lsr_break_flag[port->line] = UART_LSR_BI;
  596. if ((lsr & BOTH_EMPTY) == BOTH_EMPTY)
  597. break;
  598. } while (timeout-- > 0);
  599. if (port->flags & UPF_CONS_FLOW) {
  600. timeout = 1000000;
  601. do {
  602. msr = siu_read(port, UART_MSR);
  603. if ((msr & UART_MSR_CTS) != 0)
  604. break;
  605. } while (timeout-- > 0);
  606. }
  607. }
  608. static void siu_console_putchar(struct uart_port *port, int ch)
  609. {
  610. wait_for_xmitr(port);
  611. siu_write(port, UART_TX, ch);
  612. }
  613. static void siu_console_write(struct console *con, const char *s, unsigned count)
  614. {
  615. struct uart_port *port;
  616. uint8_t ier;
  617. port = &siu_uart_ports[con->index];
  618. ier = siu_read(port, UART_IER);
  619. siu_write(port, UART_IER, 0);
  620. uart_console_write(port, s, count, siu_console_putchar);
  621. wait_for_xmitr(port);
  622. siu_write(port, UART_IER, ier);
  623. }
  624. static int __init siu_console_setup(struct console *con, char *options)
  625. {
  626. struct uart_port *port;
  627. int baud = 9600;
  628. int parity = 'n';
  629. int bits = 8;
  630. int flow = 'n';
  631. if (con->index >= SIU_PORTS_MAX)
  632. con->index = 0;
  633. port = &siu_uart_ports[con->index];
  634. if (port->membase == NULL) {
  635. if (port->mapbase == 0)
  636. return -ENODEV;
  637. port->membase = ioremap(port->mapbase, siu_port_size(port));
  638. }
  639. if (port->type == PORT_VR41XX_SIU)
  640. vr41xx_select_siu_interface(SIU_INTERFACE_RS232C);
  641. if (options != NULL)
  642. uart_parse_options(options, &baud, &parity, &bits, &flow);
  643. return uart_set_options(port, con, baud, parity, bits, flow);
  644. }
  645. static struct uart_driver siu_uart_driver;
  646. static struct console siu_console = {
  647. .name = "ttyVR",
  648. .write = siu_console_write,
  649. .device = uart_console_device,
  650. .setup = siu_console_setup,
  651. .flags = CON_PRINTBUFFER,
  652. .index = -1,
  653. .data = &siu_uart_driver,
  654. };
  655. static int siu_console_init(void)
  656. {
  657. struct uart_port *port;
  658. int i;
  659. for (i = 0; i < SIU_PORTS_MAX; i++) {
  660. port = &siu_uart_ports[i];
  661. port->ops = &siu_uart_ops;
  662. }
  663. register_console(&siu_console);
  664. return 0;
  665. }
  666. console_initcall(siu_console_init);
  667. void __init vr41xx_siu_early_setup(struct uart_port *port)
  668. {
  669. if (port->type == PORT_UNKNOWN)
  670. return;
  671. siu_uart_ports[port->line].line = port->line;
  672. siu_uart_ports[port->line].type = port->type;
  673. siu_uart_ports[port->line].uartclk = SIU_BAUD_BASE * 16;
  674. siu_uart_ports[port->line].mapbase = port->mapbase;
  675. siu_uart_ports[port->line].ops = &siu_uart_ops;
  676. }
  677. #define SERIAL_VR41XX_CONSOLE &siu_console
  678. #else
  679. #define SERIAL_VR41XX_CONSOLE NULL
  680. #endif
  681. static struct uart_driver siu_uart_driver = {
  682. .owner = THIS_MODULE,
  683. .driver_name = "SIU",
  684. .dev_name = "ttyVR",
  685. .major = SIU_MAJOR,
  686. .minor = SIU_MINOR_BASE,
  687. .cons = SERIAL_VR41XX_CONSOLE,
  688. };
  689. static int siu_probe(struct platform_device *dev)
  690. {
  691. struct uart_port *port;
  692. int num, i, retval;
  693. num = siu_init_ports(dev);
  694. if (num <= 0)
  695. return -ENODEV;
  696. siu_uart_driver.nr = num;
  697. retval = uart_register_driver(&siu_uart_driver);
  698. if (retval)
  699. return retval;
  700. for (i = 0; i < num; i++) {
  701. port = &siu_uart_ports[i];
  702. port->ops = &siu_uart_ops;
  703. port->dev = &dev->dev;
  704. retval = uart_add_one_port(&siu_uart_driver, port);
  705. if (retval < 0) {
  706. port->dev = NULL;
  707. break;
  708. }
  709. }
  710. if (i == 0 && retval < 0) {
  711. uart_unregister_driver(&siu_uart_driver);
  712. return retval;
  713. }
  714. return 0;
  715. }
  716. static int siu_remove(struct platform_device *dev)
  717. {
  718. struct uart_port *port;
  719. int i;
  720. for (i = 0; i < siu_uart_driver.nr; i++) {
  721. port = &siu_uart_ports[i];
  722. if (port->dev == &dev->dev) {
  723. uart_remove_one_port(&siu_uart_driver, port);
  724. port->dev = NULL;
  725. }
  726. }
  727. uart_unregister_driver(&siu_uart_driver);
  728. return 0;
  729. }
  730. static int siu_suspend(struct platform_device *dev, pm_message_t state)
  731. {
  732. struct uart_port *port;
  733. int i;
  734. for (i = 0; i < siu_uart_driver.nr; i++) {
  735. port = &siu_uart_ports[i];
  736. if ((port->type == PORT_VR41XX_SIU ||
  737. port->type == PORT_VR41XX_DSIU) && port->dev == &dev->dev)
  738. uart_suspend_port(&siu_uart_driver, port);
  739. }
  740. return 0;
  741. }
  742. static int siu_resume(struct platform_device *dev)
  743. {
  744. struct uart_port *port;
  745. int i;
  746. for (i = 0; i < siu_uart_driver.nr; i++) {
  747. port = &siu_uart_ports[i];
  748. if ((port->type == PORT_VR41XX_SIU ||
  749. port->type == PORT_VR41XX_DSIU) && port->dev == &dev->dev)
  750. uart_resume_port(&siu_uart_driver, port);
  751. }
  752. return 0;
  753. }
  754. static struct platform_driver siu_device_driver = {
  755. .probe = siu_probe,
  756. .remove = siu_remove,
  757. .suspend = siu_suspend,
  758. .resume = siu_resume,
  759. .driver = {
  760. .name = "SIU",
  761. },
  762. };
  763. module_platform_driver(siu_device_driver);
  764. MODULE_LICENSE("GPL");
  765. MODULE_ALIAS("platform:SIU");