core_intr.c 17 KB

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  1. /*
  2. * core_intr.c - DesignWare HS OTG Controller common interrupt handling
  3. *
  4. * Copyright (C) 2004-2013 Synopsys, Inc.
  5. *
  6. * Redistribution and use in source and binary forms, with or without
  7. * modification, are permitted provided that the following conditions
  8. * are met:
  9. * 1. Redistributions of source code must retain the above copyright
  10. * notice, this list of conditions, and the following disclaimer,
  11. * without modification.
  12. * 2. Redistributions in binary form must reproduce the above copyright
  13. * notice, this list of conditions and the following disclaimer in the
  14. * documentation and/or other materials provided with the distribution.
  15. * 3. The names of the above-listed copyright holders may not be used
  16. * to endorse or promote products derived from this software without
  17. * specific prior written permission.
  18. *
  19. * ALTERNATIVELY, this software may be distributed under the terms of the
  20. * GNU General Public License ("GPL") as published by the Free Software
  21. * Foundation; either version 2 of the License, or (at your option) any
  22. * later version.
  23. *
  24. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS
  25. * IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO,
  26. * THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
  27. * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR
  28. * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
  29. * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO,
  30. * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR
  31. * PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
  32. * LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
  33. * NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
  34. * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  35. */
  36. /*
  37. * This file contains the common interrupt handlers
  38. */
  39. #include <linux/kernel.h>
  40. #include <linux/module.h>
  41. #include <linux/moduleparam.h>
  42. #include <linux/spinlock.h>
  43. #include <linux/interrupt.h>
  44. #include <linux/dma-mapping.h>
  45. #include <linux/io.h>
  46. #include <linux/slab.h>
  47. #include <linux/usb.h>
  48. #include <linux/usb/hcd.h>
  49. #include <linux/usb/ch11.h>
  50. #include "core.h"
  51. #include "hcd.h"
  52. static const char *dwc2_op_state_str(struct dwc2_hsotg *hsotg)
  53. {
  54. switch (hsotg->op_state) {
  55. case OTG_STATE_A_HOST:
  56. return "a_host";
  57. case OTG_STATE_A_SUSPEND:
  58. return "a_suspend";
  59. case OTG_STATE_A_PERIPHERAL:
  60. return "a_peripheral";
  61. case OTG_STATE_B_PERIPHERAL:
  62. return "b_peripheral";
  63. case OTG_STATE_B_HOST:
  64. return "b_host";
  65. default:
  66. return "unknown";
  67. }
  68. }
  69. /**
  70. * dwc2_handle_usb_port_intr - handles OTG PRTINT interrupts.
  71. * When the PRTINT interrupt fires, there are certain status bits in the Host
  72. * Port that needs to get cleared.
  73. *
  74. * @hsotg: Programming view of DWC_otg controller
  75. */
  76. static void dwc2_handle_usb_port_intr(struct dwc2_hsotg *hsotg)
  77. {
  78. u32 hprt0 = dwc2_readl(hsotg->regs + HPRT0);
  79. if (hprt0 & HPRT0_ENACHG) {
  80. hprt0 &= ~HPRT0_ENA;
  81. dwc2_writel(hprt0, hsotg->regs + HPRT0);
  82. }
  83. /* Clear interrupt */
  84. dwc2_writel(GINTSTS_PRTINT, hsotg->regs + GINTSTS);
  85. }
  86. /**
  87. * dwc2_handle_mode_mismatch_intr() - Logs a mode mismatch warning message
  88. *
  89. * @hsotg: Programming view of DWC_otg controller
  90. */
  91. static void dwc2_handle_mode_mismatch_intr(struct dwc2_hsotg *hsotg)
  92. {
  93. dev_warn(hsotg->dev, "Mode Mismatch Interrupt: currently in %s mode\n",
  94. dwc2_is_host_mode(hsotg) ? "Host" : "Device");
  95. /* Clear interrupt */
  96. dwc2_writel(GINTSTS_MODEMIS, hsotg->regs + GINTSTS);
  97. }
  98. /**
  99. * dwc2_handle_otg_intr() - Handles the OTG Interrupts. It reads the OTG
  100. * Interrupt Register (GOTGINT) to determine what interrupt has occurred.
  101. *
  102. * @hsotg: Programming view of DWC_otg controller
  103. */
  104. static void dwc2_handle_otg_intr(struct dwc2_hsotg *hsotg)
  105. {
  106. u32 gotgint;
  107. u32 gotgctl;
  108. u32 gintmsk;
  109. gotgint = dwc2_readl(hsotg->regs + GOTGINT);
  110. gotgctl = dwc2_readl(hsotg->regs + GOTGCTL);
  111. dev_dbg(hsotg->dev, "++OTG Interrupt gotgint=%0x [%s]\n", gotgint,
  112. dwc2_op_state_str(hsotg));
  113. if (gotgint & GOTGINT_SES_END_DET) {
  114. dev_dbg(hsotg->dev,
  115. " ++OTG Interrupt: Session End Detected++ (%s)\n",
  116. dwc2_op_state_str(hsotg));
  117. gotgctl = dwc2_readl(hsotg->regs + GOTGCTL);
  118. if (dwc2_is_device_mode(hsotg))
  119. dwc2_hsotg_disconnect(hsotg);
  120. if (hsotg->op_state == OTG_STATE_B_HOST) {
  121. hsotg->op_state = OTG_STATE_B_PERIPHERAL;
  122. } else {
  123. /*
  124. * If not B_HOST and Device HNP still set, HNP did
  125. * not succeed!
  126. */
  127. if (gotgctl & GOTGCTL_DEVHNPEN) {
  128. dev_dbg(hsotg->dev, "Session End Detected\n");
  129. dev_err(hsotg->dev,
  130. "Device Not Connected/Responding!\n");
  131. }
  132. /*
  133. * If Session End Detected the B-Cable has been
  134. * disconnected
  135. */
  136. /* Reset to a clean state */
  137. hsotg->lx_state = DWC2_L0;
  138. }
  139. gotgctl = dwc2_readl(hsotg->regs + GOTGCTL);
  140. gotgctl &= ~GOTGCTL_DEVHNPEN;
  141. dwc2_writel(gotgctl, hsotg->regs + GOTGCTL);
  142. }
  143. if (gotgint & GOTGINT_SES_REQ_SUC_STS_CHNG) {
  144. dev_dbg(hsotg->dev,
  145. " ++OTG Interrupt: Session Request Success Status Change++\n");
  146. gotgctl = dwc2_readl(hsotg->regs + GOTGCTL);
  147. if (gotgctl & GOTGCTL_SESREQSCS) {
  148. if (hsotg->core_params->phy_type ==
  149. DWC2_PHY_TYPE_PARAM_FS
  150. && hsotg->core_params->i2c_enable > 0) {
  151. hsotg->srp_success = 1;
  152. } else {
  153. /* Clear Session Request */
  154. gotgctl = dwc2_readl(hsotg->regs + GOTGCTL);
  155. gotgctl &= ~GOTGCTL_SESREQ;
  156. dwc2_writel(gotgctl, hsotg->regs + GOTGCTL);
  157. }
  158. }
  159. }
  160. if (gotgint & GOTGINT_HST_NEG_SUC_STS_CHNG) {
  161. /*
  162. * Print statements during the HNP interrupt handling
  163. * can cause it to fail
  164. */
  165. gotgctl = dwc2_readl(hsotg->regs + GOTGCTL);
  166. /*
  167. * WA for 3.00a- HW is not setting cur_mode, even sometimes
  168. * this does not help
  169. */
  170. if (hsotg->hw_params.snpsid >= DWC2_CORE_REV_3_00a)
  171. udelay(100);
  172. if (gotgctl & GOTGCTL_HSTNEGSCS) {
  173. if (dwc2_is_host_mode(hsotg)) {
  174. hsotg->op_state = OTG_STATE_B_HOST;
  175. /*
  176. * Need to disable SOF interrupt immediately.
  177. * When switching from device to host, the PCD
  178. * interrupt handler won't handle the interrupt
  179. * if host mode is already set. The HCD
  180. * interrupt handler won't get called if the
  181. * HCD state is HALT. This means that the
  182. * interrupt does not get handled and Linux
  183. * complains loudly.
  184. */
  185. gintmsk = dwc2_readl(hsotg->regs + GINTMSK);
  186. gintmsk &= ~GINTSTS_SOF;
  187. dwc2_writel(gintmsk, hsotg->regs + GINTMSK);
  188. /*
  189. * Call callback function with spin lock
  190. * released
  191. */
  192. spin_unlock(&hsotg->lock);
  193. /* Initialize the Core for Host mode */
  194. dwc2_hcd_start(hsotg);
  195. spin_lock(&hsotg->lock);
  196. hsotg->op_state = OTG_STATE_B_HOST;
  197. }
  198. } else {
  199. gotgctl = dwc2_readl(hsotg->regs + GOTGCTL);
  200. gotgctl &= ~(GOTGCTL_HNPREQ | GOTGCTL_DEVHNPEN);
  201. dwc2_writel(gotgctl, hsotg->regs + GOTGCTL);
  202. dev_dbg(hsotg->dev, "HNP Failed\n");
  203. dev_err(hsotg->dev,
  204. "Device Not Connected/Responding\n");
  205. }
  206. }
  207. if (gotgint & GOTGINT_HST_NEG_DET) {
  208. /*
  209. * The disconnect interrupt is set at the same time as
  210. * Host Negotiation Detected. During the mode switch all
  211. * interrupts are cleared so the disconnect interrupt
  212. * handler will not get executed.
  213. */
  214. dev_dbg(hsotg->dev,
  215. " ++OTG Interrupt: Host Negotiation Detected++ (%s)\n",
  216. (dwc2_is_host_mode(hsotg) ? "Host" : "Device"));
  217. if (dwc2_is_device_mode(hsotg)) {
  218. dev_dbg(hsotg->dev, "a_suspend->a_peripheral (%d)\n",
  219. hsotg->op_state);
  220. spin_unlock(&hsotg->lock);
  221. dwc2_hcd_disconnect(hsotg);
  222. spin_lock(&hsotg->lock);
  223. hsotg->op_state = OTG_STATE_A_PERIPHERAL;
  224. } else {
  225. /* Need to disable SOF interrupt immediately */
  226. gintmsk = dwc2_readl(hsotg->regs + GINTMSK);
  227. gintmsk &= ~GINTSTS_SOF;
  228. dwc2_writel(gintmsk, hsotg->regs + GINTMSK);
  229. spin_unlock(&hsotg->lock);
  230. dwc2_hcd_start(hsotg);
  231. spin_lock(&hsotg->lock);
  232. hsotg->op_state = OTG_STATE_A_HOST;
  233. }
  234. }
  235. if (gotgint & GOTGINT_A_DEV_TOUT_CHG)
  236. dev_dbg(hsotg->dev,
  237. " ++OTG Interrupt: A-Device Timeout Change++\n");
  238. if (gotgint & GOTGINT_DBNCE_DONE)
  239. dev_dbg(hsotg->dev, " ++OTG Interrupt: Debounce Done++\n");
  240. /* Clear GOTGINT */
  241. dwc2_writel(gotgint, hsotg->regs + GOTGINT);
  242. }
  243. /**
  244. * dwc2_handle_conn_id_status_change_intr() - Handles the Connector ID Status
  245. * Change Interrupt
  246. *
  247. * @hsotg: Programming view of DWC_otg controller
  248. *
  249. * Reads the OTG Interrupt Register (GOTCTL) to determine whether this is a
  250. * Device to Host Mode transition or a Host to Device Mode transition. This only
  251. * occurs when the cable is connected/removed from the PHY connector.
  252. */
  253. static void dwc2_handle_conn_id_status_change_intr(struct dwc2_hsotg *hsotg)
  254. {
  255. u32 gintmsk = dwc2_readl(hsotg->regs + GINTMSK);
  256. /* Need to disable SOF interrupt immediately */
  257. gintmsk &= ~GINTSTS_SOF;
  258. dwc2_writel(gintmsk, hsotg->regs + GINTMSK);
  259. dev_dbg(hsotg->dev, " ++Connector ID Status Change Interrupt++ (%s)\n",
  260. dwc2_is_host_mode(hsotg) ? "Host" : "Device");
  261. /*
  262. * Need to schedule a work, as there are possible DELAY function calls.
  263. * Release lock before scheduling workq as it holds spinlock during
  264. * scheduling.
  265. */
  266. if (hsotg->wq_otg) {
  267. spin_unlock(&hsotg->lock);
  268. queue_work(hsotg->wq_otg, &hsotg->wf_otg);
  269. spin_lock(&hsotg->lock);
  270. }
  271. /* Clear interrupt */
  272. dwc2_writel(GINTSTS_CONIDSTSCHNG, hsotg->regs + GINTSTS);
  273. }
  274. /**
  275. * dwc2_handle_session_req_intr() - This interrupt indicates that a device is
  276. * initiating the Session Request Protocol to request the host to turn on bus
  277. * power so a new session can begin
  278. *
  279. * @hsotg: Programming view of DWC_otg controller
  280. *
  281. * This handler responds by turning on bus power. If the DWC_otg controller is
  282. * in low power mode, this handler brings the controller out of low power mode
  283. * before turning on bus power.
  284. */
  285. static void dwc2_handle_session_req_intr(struct dwc2_hsotg *hsotg)
  286. {
  287. int ret;
  288. dev_dbg(hsotg->dev, "Session request interrupt - lx_state=%d\n",
  289. hsotg->lx_state);
  290. /* Clear interrupt */
  291. dwc2_writel(GINTSTS_SESSREQINT, hsotg->regs + GINTSTS);
  292. if (dwc2_is_device_mode(hsotg)) {
  293. if (hsotg->lx_state == DWC2_L2) {
  294. ret = dwc2_exit_hibernation(hsotg, true);
  295. if (ret && (ret != -ENOTSUPP))
  296. dev_err(hsotg->dev,
  297. "exit hibernation failed\n");
  298. }
  299. /*
  300. * Report disconnect if there is any previous session
  301. * established
  302. */
  303. dwc2_hsotg_disconnect(hsotg);
  304. }
  305. }
  306. /*
  307. * This interrupt indicates that the DWC_otg controller has detected a
  308. * resume or remote wakeup sequence. If the DWC_otg controller is in
  309. * low power mode, the handler must brings the controller out of low
  310. * power mode. The controller automatically begins resume signaling.
  311. * The handler schedules a time to stop resume signaling.
  312. */
  313. static void dwc2_handle_wakeup_detected_intr(struct dwc2_hsotg *hsotg)
  314. {
  315. int ret;
  316. dev_dbg(hsotg->dev, "++Resume or Remote Wakeup Detected Interrupt++\n");
  317. dev_dbg(hsotg->dev, "%s lxstate = %d\n", __func__, hsotg->lx_state);
  318. if (dwc2_is_device_mode(hsotg)) {
  319. dev_dbg(hsotg->dev, "DSTS=0x%0x\n",
  320. dwc2_readl(hsotg->regs + DSTS));
  321. if (hsotg->lx_state == DWC2_L2) {
  322. u32 dctl = dwc2_readl(hsotg->regs + DCTL);
  323. /* Clear Remote Wakeup Signaling */
  324. dctl &= ~DCTL_RMTWKUPSIG;
  325. dwc2_writel(dctl, hsotg->regs + DCTL);
  326. ret = dwc2_exit_hibernation(hsotg, true);
  327. if (ret && (ret != -ENOTSUPP))
  328. dev_err(hsotg->dev, "exit hibernation failed\n");
  329. call_gadget(hsotg, resume);
  330. }
  331. /* Change to L0 state */
  332. hsotg->lx_state = DWC2_L0;
  333. } else {
  334. if (hsotg->core_params->hibernation) {
  335. dwc2_writel(GINTSTS_WKUPINT, hsotg->regs + GINTSTS);
  336. return;
  337. }
  338. if (hsotg->lx_state != DWC2_L1) {
  339. u32 pcgcctl = dwc2_readl(hsotg->regs + PCGCTL);
  340. /* Restart the Phy Clock */
  341. pcgcctl &= ~PCGCTL_STOPPCLK;
  342. dwc2_writel(pcgcctl, hsotg->regs + PCGCTL);
  343. mod_timer(&hsotg->wkp_timer,
  344. jiffies + msecs_to_jiffies(71));
  345. } else {
  346. /* Change to L0 state */
  347. hsotg->lx_state = DWC2_L0;
  348. }
  349. }
  350. /* Clear interrupt */
  351. dwc2_writel(GINTSTS_WKUPINT, hsotg->regs + GINTSTS);
  352. }
  353. /*
  354. * This interrupt indicates that a device has been disconnected from the
  355. * root port
  356. */
  357. static void dwc2_handle_disconnect_intr(struct dwc2_hsotg *hsotg)
  358. {
  359. dev_dbg(hsotg->dev, "++Disconnect Detected Interrupt++ (%s) %s\n",
  360. dwc2_is_host_mode(hsotg) ? "Host" : "Device",
  361. dwc2_op_state_str(hsotg));
  362. if (hsotg->op_state == OTG_STATE_A_HOST)
  363. dwc2_hcd_disconnect(hsotg);
  364. dwc2_writel(GINTSTS_DISCONNINT, hsotg->regs + GINTSTS);
  365. }
  366. /*
  367. * This interrupt indicates that SUSPEND state has been detected on the USB.
  368. *
  369. * For HNP the USB Suspend interrupt signals the change from "a_peripheral"
  370. * to "a_host".
  371. *
  372. * When power management is enabled the core will be put in low power mode.
  373. */
  374. static void dwc2_handle_usb_suspend_intr(struct dwc2_hsotg *hsotg)
  375. {
  376. u32 dsts;
  377. int ret;
  378. dev_dbg(hsotg->dev, "USB SUSPEND\n");
  379. if (dwc2_is_device_mode(hsotg)) {
  380. /*
  381. * Check the Device status register to determine if the Suspend
  382. * state is active
  383. */
  384. dsts = dwc2_readl(hsotg->regs + DSTS);
  385. dev_dbg(hsotg->dev, "DSTS=0x%0x\n", dsts);
  386. dev_dbg(hsotg->dev,
  387. "DSTS.Suspend Status=%d HWCFG4.Power Optimize=%d\n",
  388. !!(dsts & DSTS_SUSPSTS),
  389. hsotg->hw_params.power_optimized);
  390. if ((dsts & DSTS_SUSPSTS) && hsotg->hw_params.power_optimized) {
  391. /* Ignore suspend request before enumeration */
  392. if (!dwc2_is_device_connected(hsotg)) {
  393. dev_dbg(hsotg->dev,
  394. "ignore suspend request before enumeration\n");
  395. goto clear_int;
  396. }
  397. ret = dwc2_enter_hibernation(hsotg);
  398. if (ret) {
  399. if (ret != -ENOTSUPP)
  400. dev_err(hsotg->dev,
  401. "enter hibernation failed\n");
  402. goto skip_power_saving;
  403. }
  404. udelay(100);
  405. /* Ask phy to be suspended */
  406. if (!IS_ERR_OR_NULL(hsotg->uphy))
  407. usb_phy_set_suspend(hsotg->uphy, true);
  408. skip_power_saving:
  409. /*
  410. * Change to L2 (suspend) state before releasing
  411. * spinlock
  412. */
  413. hsotg->lx_state = DWC2_L2;
  414. /* Call gadget suspend callback */
  415. call_gadget(hsotg, suspend);
  416. }
  417. } else {
  418. if (hsotg->op_state == OTG_STATE_A_PERIPHERAL) {
  419. dev_dbg(hsotg->dev, "a_peripheral->a_host\n");
  420. /* Change to L2 (suspend) state */
  421. hsotg->lx_state = DWC2_L2;
  422. /* Clear the a_peripheral flag, back to a_host */
  423. spin_unlock(&hsotg->lock);
  424. dwc2_hcd_start(hsotg);
  425. spin_lock(&hsotg->lock);
  426. hsotg->op_state = OTG_STATE_A_HOST;
  427. }
  428. }
  429. clear_int:
  430. /* Clear interrupt */
  431. dwc2_writel(GINTSTS_USBSUSP, hsotg->regs + GINTSTS);
  432. }
  433. #define GINTMSK_COMMON (GINTSTS_WKUPINT | GINTSTS_SESSREQINT | \
  434. GINTSTS_CONIDSTSCHNG | GINTSTS_OTGINT | \
  435. GINTSTS_MODEMIS | GINTSTS_DISCONNINT | \
  436. GINTSTS_USBSUSP | GINTSTS_PRTINT)
  437. /*
  438. * This function returns the Core Interrupt register
  439. */
  440. static u32 dwc2_read_common_intr(struct dwc2_hsotg *hsotg)
  441. {
  442. u32 gintsts;
  443. u32 gintmsk;
  444. u32 gahbcfg;
  445. u32 gintmsk_common = GINTMSK_COMMON;
  446. gintsts = dwc2_readl(hsotg->regs + GINTSTS);
  447. gintmsk = dwc2_readl(hsotg->regs + GINTMSK);
  448. gahbcfg = dwc2_readl(hsotg->regs + GAHBCFG);
  449. /* If any common interrupts set */
  450. if (gintsts & gintmsk_common)
  451. dev_dbg(hsotg->dev, "gintsts=%08x gintmsk=%08x\n",
  452. gintsts, gintmsk);
  453. if (gahbcfg & GAHBCFG_GLBL_INTR_EN)
  454. return gintsts & gintmsk & gintmsk_common;
  455. else
  456. return 0;
  457. }
  458. /*
  459. * Common interrupt handler
  460. *
  461. * The common interrupts are those that occur in both Host and Device mode.
  462. * This handler handles the following interrupts:
  463. * - Mode Mismatch Interrupt
  464. * - OTG Interrupt
  465. * - Connector ID Status Change Interrupt
  466. * - Disconnect Interrupt
  467. * - Session Request Interrupt
  468. * - Resume / Remote Wakeup Detected Interrupt
  469. * - Suspend Interrupt
  470. */
  471. irqreturn_t dwc2_handle_common_intr(int irq, void *dev)
  472. {
  473. struct dwc2_hsotg *hsotg = dev;
  474. u32 gintsts;
  475. irqreturn_t retval = IRQ_NONE;
  476. spin_lock(&hsotg->lock);
  477. if (!dwc2_is_controller_alive(hsotg)) {
  478. dev_warn(hsotg->dev, "Controller is dead\n");
  479. goto out;
  480. }
  481. gintsts = dwc2_read_common_intr(hsotg);
  482. if (gintsts & ~GINTSTS_PRTINT)
  483. retval = IRQ_HANDLED;
  484. if (gintsts & GINTSTS_MODEMIS)
  485. dwc2_handle_mode_mismatch_intr(hsotg);
  486. if (gintsts & GINTSTS_OTGINT)
  487. dwc2_handle_otg_intr(hsotg);
  488. if (gintsts & GINTSTS_CONIDSTSCHNG)
  489. dwc2_handle_conn_id_status_change_intr(hsotg);
  490. if (gintsts & GINTSTS_DISCONNINT)
  491. dwc2_handle_disconnect_intr(hsotg);
  492. if (gintsts & GINTSTS_SESSREQINT)
  493. dwc2_handle_session_req_intr(hsotg);
  494. if (gintsts & GINTSTS_WKUPINT)
  495. dwc2_handle_wakeup_detected_intr(hsotg);
  496. if (gintsts & GINTSTS_USBSUSP)
  497. dwc2_handle_usb_suspend_intr(hsotg);
  498. if (gintsts & GINTSTS_PRTINT) {
  499. /*
  500. * The port interrupt occurs while in device mode with HPRT0
  501. * Port Enable/Disable
  502. */
  503. if (dwc2_is_device_mode(hsotg)) {
  504. dev_dbg(hsotg->dev,
  505. " --Port interrupt received in Device mode--\n");
  506. dwc2_handle_usb_port_intr(hsotg);
  507. retval = IRQ_HANDLED;
  508. }
  509. }
  510. out:
  511. spin_unlock(&hsotg->lock);
  512. return retval;
  513. }