blackfin.c 15 KB

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  1. /*
  2. * MUSB OTG controller driver for Blackfin Processors
  3. *
  4. * Copyright 2006-2008 Analog Devices Inc.
  5. *
  6. * Enter bugs at http://blackfin.uclinux.org/
  7. *
  8. * Licensed under the GPL-2 or later.
  9. */
  10. #include <linux/module.h>
  11. #include <linux/kernel.h>
  12. #include <linux/sched.h>
  13. #include <linux/list.h>
  14. #include <linux/gpio.h>
  15. #include <linux/io.h>
  16. #include <linux/err.h>
  17. #include <linux/platform_device.h>
  18. #include <linux/dma-mapping.h>
  19. #include <linux/prefetch.h>
  20. #include <linux/usb/usb_phy_generic.h>
  21. #include <asm/cacheflush.h>
  22. #include "musb_core.h"
  23. #include "musbhsdma.h"
  24. #include "blackfin.h"
  25. struct bfin_glue {
  26. struct device *dev;
  27. struct platform_device *musb;
  28. struct platform_device *phy;
  29. };
  30. #define glue_to_musb(g) platform_get_drvdata(g->musb)
  31. static u32 bfin_fifo_offset(u8 epnum)
  32. {
  33. return USB_OFFSET(USB_EP0_FIFO) + (epnum * 8);
  34. }
  35. static u8 bfin_readb(const void __iomem *addr, unsigned offset)
  36. {
  37. return (u8)(bfin_read16(addr + offset));
  38. }
  39. static u16 bfin_readw(const void __iomem *addr, unsigned offset)
  40. {
  41. return bfin_read16(addr + offset);
  42. }
  43. static u32 bfin_readl(const void __iomem *addr, unsigned offset)
  44. {
  45. return (u32)(bfin_read16(addr + offset));
  46. }
  47. static void bfin_writeb(void __iomem *addr, unsigned offset, u8 data)
  48. {
  49. bfin_write16(addr + offset, (u16)data);
  50. }
  51. static void bfin_writew(void __iomem *addr, unsigned offset, u16 data)
  52. {
  53. bfin_write16(addr + offset, data);
  54. }
  55. static void bfin_writel(void __iomem *addr, unsigned offset, u32 data)
  56. {
  57. bfin_write16(addr + offset, (u16)data);
  58. }
  59. /*
  60. * Load an endpoint's FIFO
  61. */
  62. static void bfin_write_fifo(struct musb_hw_ep *hw_ep, u16 len, const u8 *src)
  63. {
  64. struct musb *musb = hw_ep->musb;
  65. void __iomem *fifo = hw_ep->fifo;
  66. void __iomem *epio = hw_ep->regs;
  67. u8 epnum = hw_ep->epnum;
  68. prefetch((u8 *)src);
  69. musb_writew(epio, MUSB_TXCOUNT, len);
  70. dev_dbg(musb->controller, "TX ep%d fifo %p count %d buf %p, epio %p\n",
  71. hw_ep->epnum, fifo, len, src, epio);
  72. dump_fifo_data(src, len);
  73. if (!ANOMALY_05000380 && epnum != 0) {
  74. u16 dma_reg;
  75. flush_dcache_range((unsigned long)src,
  76. (unsigned long)(src + len));
  77. /* Setup DMA address register */
  78. dma_reg = (u32)src;
  79. bfin_write16(USB_DMA_REG(epnum, USB_DMAx_ADDR_LOW), dma_reg);
  80. SSYNC();
  81. dma_reg = (u32)src >> 16;
  82. bfin_write16(USB_DMA_REG(epnum, USB_DMAx_ADDR_HIGH), dma_reg);
  83. SSYNC();
  84. /* Setup DMA count register */
  85. bfin_write16(USB_DMA_REG(epnum, USB_DMAx_COUNT_LOW), len);
  86. bfin_write16(USB_DMA_REG(epnum, USB_DMAx_COUNT_HIGH), 0);
  87. SSYNC();
  88. /* Enable the DMA */
  89. dma_reg = (epnum << 4) | DMA_ENA | INT_ENA | DIRECTION;
  90. bfin_write16(USB_DMA_REG(epnum, USB_DMAx_CTRL), dma_reg);
  91. SSYNC();
  92. /* Wait for complete */
  93. while (!(bfin_read_USB_DMA_INTERRUPT() & (1 << epnum)))
  94. cpu_relax();
  95. /* acknowledge dma interrupt */
  96. bfin_write_USB_DMA_INTERRUPT(1 << epnum);
  97. SSYNC();
  98. /* Reset DMA */
  99. bfin_write16(USB_DMA_REG(epnum, USB_DMAx_CTRL), 0);
  100. SSYNC();
  101. } else {
  102. SSYNC();
  103. if (unlikely((unsigned long)src & 0x01))
  104. outsw_8((unsigned long)fifo, src, (len + 1) >> 1);
  105. else
  106. outsw((unsigned long)fifo, src, (len + 1) >> 1);
  107. }
  108. }
  109. /*
  110. * Unload an endpoint's FIFO
  111. */
  112. static void bfin_read_fifo(struct musb_hw_ep *hw_ep, u16 len, u8 *dst)
  113. {
  114. struct musb *musb = hw_ep->musb;
  115. void __iomem *fifo = hw_ep->fifo;
  116. u8 epnum = hw_ep->epnum;
  117. if (ANOMALY_05000467 && epnum != 0) {
  118. u16 dma_reg;
  119. invalidate_dcache_range((unsigned long)dst,
  120. (unsigned long)(dst + len));
  121. /* Setup DMA address register */
  122. dma_reg = (u32)dst;
  123. bfin_write16(USB_DMA_REG(epnum, USB_DMAx_ADDR_LOW), dma_reg);
  124. SSYNC();
  125. dma_reg = (u32)dst >> 16;
  126. bfin_write16(USB_DMA_REG(epnum, USB_DMAx_ADDR_HIGH), dma_reg);
  127. SSYNC();
  128. /* Setup DMA count register */
  129. bfin_write16(USB_DMA_REG(epnum, USB_DMAx_COUNT_LOW), len);
  130. bfin_write16(USB_DMA_REG(epnum, USB_DMAx_COUNT_HIGH), 0);
  131. SSYNC();
  132. /* Enable the DMA */
  133. dma_reg = (epnum << 4) | DMA_ENA | INT_ENA;
  134. bfin_write16(USB_DMA_REG(epnum, USB_DMAx_CTRL), dma_reg);
  135. SSYNC();
  136. /* Wait for complete */
  137. while (!(bfin_read_USB_DMA_INTERRUPT() & (1 << epnum)))
  138. cpu_relax();
  139. /* acknowledge dma interrupt */
  140. bfin_write_USB_DMA_INTERRUPT(1 << epnum);
  141. SSYNC();
  142. /* Reset DMA */
  143. bfin_write16(USB_DMA_REG(epnum, USB_DMAx_CTRL), 0);
  144. SSYNC();
  145. } else {
  146. SSYNC();
  147. /* Read the last byte of packet with odd size from address fifo + 4
  148. * to trigger 1 byte access to EP0 FIFO.
  149. */
  150. if (len == 1)
  151. *dst = (u8)inw((unsigned long)fifo + 4);
  152. else {
  153. if (unlikely((unsigned long)dst & 0x01))
  154. insw_8((unsigned long)fifo, dst, len >> 1);
  155. else
  156. insw((unsigned long)fifo, dst, len >> 1);
  157. if (len & 0x01)
  158. *(dst + len - 1) = (u8)inw((unsigned long)fifo + 4);
  159. }
  160. }
  161. dev_dbg(musb->controller, "%cX ep%d fifo %p count %d buf %p\n",
  162. 'R', hw_ep->epnum, fifo, len, dst);
  163. dump_fifo_data(dst, len);
  164. }
  165. static irqreturn_t blackfin_interrupt(int irq, void *__hci)
  166. {
  167. unsigned long flags;
  168. irqreturn_t retval = IRQ_NONE;
  169. struct musb *musb = __hci;
  170. spin_lock_irqsave(&musb->lock, flags);
  171. musb->int_usb = musb_readb(musb->mregs, MUSB_INTRUSB);
  172. musb->int_tx = musb_readw(musb->mregs, MUSB_INTRTX);
  173. musb->int_rx = musb_readw(musb->mregs, MUSB_INTRRX);
  174. if (musb->int_usb || musb->int_tx || musb->int_rx) {
  175. musb_writeb(musb->mregs, MUSB_INTRUSB, musb->int_usb);
  176. musb_writew(musb->mregs, MUSB_INTRTX, musb->int_tx);
  177. musb_writew(musb->mregs, MUSB_INTRRX, musb->int_rx);
  178. retval = musb_interrupt(musb);
  179. }
  180. /* Start sampling ID pin, when plug is removed from MUSB */
  181. if ((musb->xceiv->otg->state == OTG_STATE_B_IDLE
  182. || musb->xceiv->otg->state == OTG_STATE_A_WAIT_BCON) ||
  183. (musb->int_usb & MUSB_INTR_DISCONNECT && is_host_active(musb))) {
  184. mod_timer(&musb_conn_timer, jiffies + TIMER_DELAY);
  185. musb->a_wait_bcon = TIMER_DELAY;
  186. }
  187. spin_unlock_irqrestore(&musb->lock, flags);
  188. return retval;
  189. }
  190. static void musb_conn_timer_handler(unsigned long _musb)
  191. {
  192. struct musb *musb = (void *)_musb;
  193. unsigned long flags;
  194. u16 val;
  195. static u8 toggle;
  196. spin_lock_irqsave(&musb->lock, flags);
  197. switch (musb->xceiv->otg->state) {
  198. case OTG_STATE_A_IDLE:
  199. case OTG_STATE_A_WAIT_BCON:
  200. /* Start a new session */
  201. val = musb_readw(musb->mregs, MUSB_DEVCTL);
  202. val &= ~MUSB_DEVCTL_SESSION;
  203. musb_writew(musb->mregs, MUSB_DEVCTL, val);
  204. val |= MUSB_DEVCTL_SESSION;
  205. musb_writew(musb->mregs, MUSB_DEVCTL, val);
  206. /* Check if musb is host or peripheral. */
  207. val = musb_readw(musb->mregs, MUSB_DEVCTL);
  208. if (!(val & MUSB_DEVCTL_BDEVICE)) {
  209. gpio_set_value(musb->config->gpio_vrsel, 1);
  210. musb->xceiv->otg->state = OTG_STATE_A_WAIT_BCON;
  211. } else {
  212. gpio_set_value(musb->config->gpio_vrsel, 0);
  213. /* Ignore VBUSERROR and SUSPEND IRQ */
  214. val = musb_readb(musb->mregs, MUSB_INTRUSBE);
  215. val &= ~MUSB_INTR_VBUSERROR;
  216. musb_writeb(musb->mregs, MUSB_INTRUSBE, val);
  217. val = MUSB_INTR_SUSPEND | MUSB_INTR_VBUSERROR;
  218. musb_writeb(musb->mregs, MUSB_INTRUSB, val);
  219. musb->xceiv->otg->state = OTG_STATE_B_IDLE;
  220. }
  221. mod_timer(&musb_conn_timer, jiffies + TIMER_DELAY);
  222. break;
  223. case OTG_STATE_B_IDLE:
  224. /*
  225. * Start a new session. It seems that MUSB needs taking
  226. * some time to recognize the type of the plug inserted?
  227. */
  228. val = musb_readw(musb->mregs, MUSB_DEVCTL);
  229. val |= MUSB_DEVCTL_SESSION;
  230. musb_writew(musb->mregs, MUSB_DEVCTL, val);
  231. val = musb_readw(musb->mregs, MUSB_DEVCTL);
  232. if (!(val & MUSB_DEVCTL_BDEVICE)) {
  233. gpio_set_value(musb->config->gpio_vrsel, 1);
  234. musb->xceiv->otg->state = OTG_STATE_A_WAIT_BCON;
  235. } else {
  236. gpio_set_value(musb->config->gpio_vrsel, 0);
  237. /* Ignore VBUSERROR and SUSPEND IRQ */
  238. val = musb_readb(musb->mregs, MUSB_INTRUSBE);
  239. val &= ~MUSB_INTR_VBUSERROR;
  240. musb_writeb(musb->mregs, MUSB_INTRUSBE, val);
  241. val = MUSB_INTR_SUSPEND | MUSB_INTR_VBUSERROR;
  242. musb_writeb(musb->mregs, MUSB_INTRUSB, val);
  243. /* Toggle the Soft Conn bit, so that we can response to
  244. * the inserting of either A-plug or B-plug.
  245. */
  246. if (toggle) {
  247. val = musb_readb(musb->mregs, MUSB_POWER);
  248. val &= ~MUSB_POWER_SOFTCONN;
  249. musb_writeb(musb->mregs, MUSB_POWER, val);
  250. toggle = 0;
  251. } else {
  252. val = musb_readb(musb->mregs, MUSB_POWER);
  253. val |= MUSB_POWER_SOFTCONN;
  254. musb_writeb(musb->mregs, MUSB_POWER, val);
  255. toggle = 1;
  256. }
  257. /* The delay time is set to 1/4 second by default,
  258. * shortening it, if accelerating A-plug detection
  259. * is needed in OTG mode.
  260. */
  261. mod_timer(&musb_conn_timer, jiffies + TIMER_DELAY / 4);
  262. }
  263. break;
  264. default:
  265. dev_dbg(musb->controller, "%s state not handled\n",
  266. usb_otg_state_string(musb->xceiv->otg->state));
  267. break;
  268. }
  269. spin_unlock_irqrestore(&musb->lock, flags);
  270. dev_dbg(musb->controller, "state is %s\n",
  271. usb_otg_state_string(musb->xceiv->otg->state));
  272. }
  273. static void bfin_musb_enable(struct musb *musb)
  274. {
  275. /* REVISIT is this really correct ? */
  276. }
  277. static void bfin_musb_disable(struct musb *musb)
  278. {
  279. }
  280. static void bfin_musb_set_vbus(struct musb *musb, int is_on)
  281. {
  282. int value = musb->config->gpio_vrsel_active;
  283. if (!is_on)
  284. value = !value;
  285. gpio_set_value(musb->config->gpio_vrsel, value);
  286. dev_dbg(musb->controller, "VBUS %s, devctl %02x "
  287. /* otg %3x conf %08x prcm %08x */ "\n",
  288. usb_otg_state_string(musb->xceiv->otg->state),
  289. musb_readb(musb->mregs, MUSB_DEVCTL));
  290. }
  291. static int bfin_musb_set_power(struct usb_phy *x, unsigned mA)
  292. {
  293. return 0;
  294. }
  295. static int bfin_musb_vbus_status(struct musb *musb)
  296. {
  297. return 0;
  298. }
  299. static int bfin_musb_set_mode(struct musb *musb, u8 musb_mode)
  300. {
  301. return -EIO;
  302. }
  303. static int bfin_musb_adjust_channel_params(struct dma_channel *channel,
  304. u16 packet_sz, u8 *mode,
  305. dma_addr_t *dma_addr, u32 *len)
  306. {
  307. struct musb_dma_channel *musb_channel = channel->private_data;
  308. /*
  309. * Anomaly 05000450 might cause data corruption when using DMA
  310. * MODE 1 transmits with short packet. So to work around this,
  311. * we truncate all MODE 1 transfers down to a multiple of the
  312. * max packet size, and then do the last short packet transfer
  313. * (if there is any) using MODE 0.
  314. */
  315. if (ANOMALY_05000450) {
  316. if (musb_channel->transmit && *mode == 1)
  317. *len = *len - (*len % packet_sz);
  318. }
  319. return 0;
  320. }
  321. static void bfin_musb_reg_init(struct musb *musb)
  322. {
  323. if (ANOMALY_05000346) {
  324. bfin_write_USB_APHY_CALIB(ANOMALY_05000346_value);
  325. SSYNC();
  326. }
  327. if (ANOMALY_05000347) {
  328. bfin_write_USB_APHY_CNTRL(0x0);
  329. SSYNC();
  330. }
  331. /* Configure PLL oscillator register */
  332. bfin_write_USB_PLLOSC_CTRL(0x3080 |
  333. ((480/musb->config->clkin) << 1));
  334. SSYNC();
  335. bfin_write_USB_SRP_CLKDIV((get_sclk()/1000) / 32 - 1);
  336. SSYNC();
  337. bfin_write_USB_EP_NI0_RXMAXP(64);
  338. SSYNC();
  339. bfin_write_USB_EP_NI0_TXMAXP(64);
  340. SSYNC();
  341. /* Route INTRUSB/INTR_RX/INTR_TX to USB_INT0*/
  342. bfin_write_USB_GLOBINTR(0x7);
  343. SSYNC();
  344. bfin_write_USB_GLOBAL_CTL(GLOBAL_ENA | EP1_TX_ENA | EP2_TX_ENA |
  345. EP3_TX_ENA | EP4_TX_ENA | EP5_TX_ENA |
  346. EP6_TX_ENA | EP7_TX_ENA | EP1_RX_ENA |
  347. EP2_RX_ENA | EP3_RX_ENA | EP4_RX_ENA |
  348. EP5_RX_ENA | EP6_RX_ENA | EP7_RX_ENA);
  349. SSYNC();
  350. }
  351. static int bfin_musb_init(struct musb *musb)
  352. {
  353. /*
  354. * Rev 1.0 BF549 EZ-KITs require PE7 to be high for both DEVICE
  355. * and OTG HOST modes, while rev 1.1 and greater require PE7 to
  356. * be low for DEVICE mode and high for HOST mode. We set it high
  357. * here because we are in host mode
  358. */
  359. if (gpio_request(musb->config->gpio_vrsel, "USB_VRSEL")) {
  360. printk(KERN_ERR "Failed ro request USB_VRSEL GPIO_%d\n",
  361. musb->config->gpio_vrsel);
  362. return -ENODEV;
  363. }
  364. gpio_direction_output(musb->config->gpio_vrsel, 0);
  365. musb->xceiv = usb_get_phy(USB_PHY_TYPE_USB2);
  366. if (IS_ERR_OR_NULL(musb->xceiv)) {
  367. gpio_free(musb->config->gpio_vrsel);
  368. return -EPROBE_DEFER;
  369. }
  370. bfin_musb_reg_init(musb);
  371. setup_timer(&musb_conn_timer, musb_conn_timer_handler,
  372. (unsigned long) musb);
  373. musb->xceiv->set_power = bfin_musb_set_power;
  374. musb->isr = blackfin_interrupt;
  375. musb->double_buffer_not_ok = true;
  376. return 0;
  377. }
  378. static int bfin_musb_exit(struct musb *musb)
  379. {
  380. gpio_free(musb->config->gpio_vrsel);
  381. usb_put_phy(musb->xceiv);
  382. return 0;
  383. }
  384. static const struct musb_platform_ops bfin_ops = {
  385. .quirks = MUSB_DMA_INVENTRA,
  386. .init = bfin_musb_init,
  387. .exit = bfin_musb_exit,
  388. .fifo_offset = bfin_fifo_offset,
  389. .readb = bfin_readb,
  390. .writeb = bfin_writeb,
  391. .readw = bfin_readw,
  392. .writew = bfin_writew,
  393. .readl = bfin_readl,
  394. .writel = bfin_writel,
  395. .fifo_mode = 2,
  396. .read_fifo = bfin_read_fifo,
  397. .write_fifo = bfin_write_fifo,
  398. #ifdef CONFIG_USB_INVENTRA_DMA
  399. .dma_init = musbhs_dma_controller_create,
  400. .dma_exit = musbhs_dma_controller_destroy,
  401. #endif
  402. .enable = bfin_musb_enable,
  403. .disable = bfin_musb_disable,
  404. .set_mode = bfin_musb_set_mode,
  405. .vbus_status = bfin_musb_vbus_status,
  406. .set_vbus = bfin_musb_set_vbus,
  407. .adjust_channel_params = bfin_musb_adjust_channel_params,
  408. };
  409. static u64 bfin_dmamask = DMA_BIT_MASK(32);
  410. static int bfin_probe(struct platform_device *pdev)
  411. {
  412. struct resource musb_resources[2];
  413. struct musb_hdrc_platform_data *pdata = dev_get_platdata(&pdev->dev);
  414. struct platform_device *musb;
  415. struct bfin_glue *glue;
  416. int ret = -ENOMEM;
  417. glue = devm_kzalloc(&pdev->dev, sizeof(*glue), GFP_KERNEL);
  418. if (!glue)
  419. goto err0;
  420. musb = platform_device_alloc("musb-hdrc", PLATFORM_DEVID_AUTO);
  421. if (!musb)
  422. goto err0;
  423. musb->dev.parent = &pdev->dev;
  424. musb->dev.dma_mask = &bfin_dmamask;
  425. musb->dev.coherent_dma_mask = bfin_dmamask;
  426. glue->dev = &pdev->dev;
  427. glue->musb = musb;
  428. pdata->platform_ops = &bfin_ops;
  429. glue->phy = usb_phy_generic_register();
  430. if (IS_ERR(glue->phy))
  431. goto err1;
  432. platform_set_drvdata(pdev, glue);
  433. memset(musb_resources, 0x00, sizeof(*musb_resources) *
  434. ARRAY_SIZE(musb_resources));
  435. musb_resources[0].name = pdev->resource[0].name;
  436. musb_resources[0].start = pdev->resource[0].start;
  437. musb_resources[0].end = pdev->resource[0].end;
  438. musb_resources[0].flags = pdev->resource[0].flags;
  439. musb_resources[1].name = pdev->resource[1].name;
  440. musb_resources[1].start = pdev->resource[1].start;
  441. musb_resources[1].end = pdev->resource[1].end;
  442. musb_resources[1].flags = pdev->resource[1].flags;
  443. ret = platform_device_add_resources(musb, musb_resources,
  444. ARRAY_SIZE(musb_resources));
  445. if (ret) {
  446. dev_err(&pdev->dev, "failed to add resources\n");
  447. goto err2;
  448. }
  449. ret = platform_device_add_data(musb, pdata, sizeof(*pdata));
  450. if (ret) {
  451. dev_err(&pdev->dev, "failed to add platform_data\n");
  452. goto err2;
  453. }
  454. ret = platform_device_add(musb);
  455. if (ret) {
  456. dev_err(&pdev->dev, "failed to register musb device\n");
  457. goto err2;
  458. }
  459. return 0;
  460. err2:
  461. usb_phy_generic_unregister(glue->phy);
  462. err1:
  463. platform_device_put(musb);
  464. err0:
  465. return ret;
  466. }
  467. static int bfin_remove(struct platform_device *pdev)
  468. {
  469. struct bfin_glue *glue = platform_get_drvdata(pdev);
  470. platform_device_unregister(glue->musb);
  471. usb_phy_generic_unregister(glue->phy);
  472. return 0;
  473. }
  474. #ifdef CONFIG_PM
  475. static int bfin_suspend(struct device *dev)
  476. {
  477. struct bfin_glue *glue = dev_get_drvdata(dev);
  478. struct musb *musb = glue_to_musb(glue);
  479. if (is_host_active(musb))
  480. /*
  481. * During hibernate gpio_vrsel will change from high to low
  482. * low which will generate wakeup event resume the system
  483. * immediately. Set it to 0 before hibernate to avoid this
  484. * wakeup event.
  485. */
  486. gpio_set_value(musb->config->gpio_vrsel, 0);
  487. return 0;
  488. }
  489. static int bfin_resume(struct device *dev)
  490. {
  491. struct bfin_glue *glue = dev_get_drvdata(dev);
  492. struct musb *musb = glue_to_musb(glue);
  493. bfin_musb_reg_init(musb);
  494. return 0;
  495. }
  496. #endif
  497. static SIMPLE_DEV_PM_OPS(bfin_pm_ops, bfin_suspend, bfin_resume);
  498. static struct platform_driver bfin_driver = {
  499. .probe = bfin_probe,
  500. .remove = bfin_remove,
  501. .driver = {
  502. .name = "musb-blackfin",
  503. .pm = &bfin_pm_ops,
  504. },
  505. };
  506. MODULE_DESCRIPTION("Blackfin MUSB Glue Layer");
  507. MODULE_AUTHOR("Bryan Wy <cooloney@kernel.org>");
  508. MODULE_LICENSE("GPL v2");
  509. module_platform_driver(bfin_driver);