phy-fsl-usb.c 28 KB

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  1. /*
  2. * Copyright (C) 2007,2008 Freescale semiconductor, Inc.
  3. *
  4. * Author: Li Yang <LeoLi@freescale.com>
  5. * Jerry Huang <Chang-Ming.Huang@freescale.com>
  6. *
  7. * Initialization based on code from Shlomi Gridish.
  8. *
  9. * This program is free software; you can redistribute it and/or modify it
  10. * under the terms of the GNU General Public License as published by the
  11. * Free Software Foundation; either version 2 of the License, or (at your
  12. * option) any later version.
  13. *
  14. * This program is distributed in the hope that it will be useful, but
  15. * WITHOUT ANY WARRANTY; without even the implied warranty of
  16. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
  17. * General Public License for more details.
  18. *
  19. * You should have received a copy of the GNU General Public License along
  20. * with this program; if not, write to the Free Software Foundation, Inc.,
  21. * 675 Mass Ave, Cambridge, MA 02139, USA.
  22. */
  23. #include <linux/module.h>
  24. #include <linux/kernel.h>
  25. #include <linux/delay.h>
  26. #include <linux/slab.h>
  27. #include <linux/proc_fs.h>
  28. #include <linux/errno.h>
  29. #include <linux/interrupt.h>
  30. #include <linux/io.h>
  31. #include <linux/timer.h>
  32. #include <linux/usb.h>
  33. #include <linux/device.h>
  34. #include <linux/usb/ch9.h>
  35. #include <linux/usb/gadget.h>
  36. #include <linux/workqueue.h>
  37. #include <linux/time.h>
  38. #include <linux/fsl_devices.h>
  39. #include <linux/platform_device.h>
  40. #include <linux/uaccess.h>
  41. #include <asm/unaligned.h>
  42. #include "phy-fsl-usb.h"
  43. #define DRIVER_VERSION "Rev. 1.55"
  44. #define DRIVER_AUTHOR "Jerry Huang/Li Yang"
  45. #define DRIVER_DESC "Freescale USB OTG Transceiver Driver"
  46. #define DRIVER_INFO DRIVER_DESC " " DRIVER_VERSION
  47. static const char driver_name[] = "fsl-usb2-otg";
  48. const pm_message_t otg_suspend_state = {
  49. .event = 1,
  50. };
  51. #define HA_DATA_PULSE
  52. static struct usb_dr_mmap *usb_dr_regs;
  53. static struct fsl_otg *fsl_otg_dev;
  54. static int srp_wait_done;
  55. /* FSM timers */
  56. struct fsl_otg_timer *a_wait_vrise_tmr, *a_wait_bcon_tmr, *a_aidl_bdis_tmr,
  57. *b_ase0_brst_tmr, *b_se0_srp_tmr;
  58. /* Driver specific timers */
  59. struct fsl_otg_timer *b_data_pulse_tmr, *b_vbus_pulse_tmr, *b_srp_fail_tmr,
  60. *b_srp_wait_tmr, *a_wait_enum_tmr;
  61. static struct list_head active_timers;
  62. static struct fsl_otg_config fsl_otg_initdata = {
  63. .otg_port = 1,
  64. };
  65. #ifdef CONFIG_PPC32
  66. static u32 _fsl_readl_be(const unsigned __iomem *p)
  67. {
  68. return in_be32(p);
  69. }
  70. static u32 _fsl_readl_le(const unsigned __iomem *p)
  71. {
  72. return in_le32(p);
  73. }
  74. static void _fsl_writel_be(u32 v, unsigned __iomem *p)
  75. {
  76. out_be32(p, v);
  77. }
  78. static void _fsl_writel_le(u32 v, unsigned __iomem *p)
  79. {
  80. out_le32(p, v);
  81. }
  82. static u32 (*_fsl_readl)(const unsigned __iomem *p);
  83. static void (*_fsl_writel)(u32 v, unsigned __iomem *p);
  84. #define fsl_readl(p) (*_fsl_readl)((p))
  85. #define fsl_writel(v, p) (*_fsl_writel)((v), (p))
  86. #else
  87. #define fsl_readl(addr) readl(addr)
  88. #define fsl_writel(val, addr) writel(val, addr)
  89. #endif /* CONFIG_PPC32 */
  90. int write_ulpi(u8 addr, u8 data)
  91. {
  92. u32 temp;
  93. temp = 0x60000000 | (addr << 16) | data;
  94. fsl_writel(temp, &usb_dr_regs->ulpiview);
  95. return 0;
  96. }
  97. /* -------------------------------------------------------------*/
  98. /* Operations that will be called from OTG Finite State Machine */
  99. /* Charge vbus for vbus pulsing in SRP */
  100. void fsl_otg_chrg_vbus(struct otg_fsm *fsm, int on)
  101. {
  102. u32 tmp;
  103. tmp = fsl_readl(&usb_dr_regs->otgsc) & ~OTGSC_INTSTS_MASK;
  104. if (on)
  105. /* stop discharging, start charging */
  106. tmp = (tmp & ~OTGSC_CTRL_VBUS_DISCHARGE) |
  107. OTGSC_CTRL_VBUS_CHARGE;
  108. else
  109. /* stop charging */
  110. tmp &= ~OTGSC_CTRL_VBUS_CHARGE;
  111. fsl_writel(tmp, &usb_dr_regs->otgsc);
  112. }
  113. /* Discharge vbus through a resistor to ground */
  114. void fsl_otg_dischrg_vbus(int on)
  115. {
  116. u32 tmp;
  117. tmp = fsl_readl(&usb_dr_regs->otgsc) & ~OTGSC_INTSTS_MASK;
  118. if (on)
  119. /* stop charging, start discharging */
  120. tmp = (tmp & ~OTGSC_CTRL_VBUS_CHARGE) |
  121. OTGSC_CTRL_VBUS_DISCHARGE;
  122. else
  123. /* stop discharging */
  124. tmp &= ~OTGSC_CTRL_VBUS_DISCHARGE;
  125. fsl_writel(tmp, &usb_dr_regs->otgsc);
  126. }
  127. /* A-device driver vbus, controlled through PP bit in PORTSC */
  128. void fsl_otg_drv_vbus(struct otg_fsm *fsm, int on)
  129. {
  130. u32 tmp;
  131. if (on) {
  132. tmp = fsl_readl(&usb_dr_regs->portsc) & ~PORTSC_W1C_BITS;
  133. fsl_writel(tmp | PORTSC_PORT_POWER, &usb_dr_regs->portsc);
  134. } else {
  135. tmp = fsl_readl(&usb_dr_regs->portsc) &
  136. ~PORTSC_W1C_BITS & ~PORTSC_PORT_POWER;
  137. fsl_writel(tmp, &usb_dr_regs->portsc);
  138. }
  139. }
  140. /*
  141. * Pull-up D+, signalling connect by periperal. Also used in
  142. * data-line pulsing in SRP
  143. */
  144. void fsl_otg_loc_conn(struct otg_fsm *fsm, int on)
  145. {
  146. u32 tmp;
  147. tmp = fsl_readl(&usb_dr_regs->otgsc) & ~OTGSC_INTSTS_MASK;
  148. if (on)
  149. tmp |= OTGSC_CTRL_DATA_PULSING;
  150. else
  151. tmp &= ~OTGSC_CTRL_DATA_PULSING;
  152. fsl_writel(tmp, &usb_dr_regs->otgsc);
  153. }
  154. /*
  155. * Generate SOF by host. This is controlled through suspend/resume the
  156. * port. In host mode, controller will automatically send SOF.
  157. * Suspend will block the data on the port.
  158. */
  159. void fsl_otg_loc_sof(struct otg_fsm *fsm, int on)
  160. {
  161. u32 tmp;
  162. tmp = fsl_readl(&fsl_otg_dev->dr_mem_map->portsc) & ~PORTSC_W1C_BITS;
  163. if (on)
  164. tmp |= PORTSC_PORT_FORCE_RESUME;
  165. else
  166. tmp |= PORTSC_PORT_SUSPEND;
  167. fsl_writel(tmp, &fsl_otg_dev->dr_mem_map->portsc);
  168. }
  169. /* Start SRP pulsing by data-line pulsing, followed with v-bus pulsing. */
  170. void fsl_otg_start_pulse(struct otg_fsm *fsm)
  171. {
  172. u32 tmp;
  173. srp_wait_done = 0;
  174. #ifdef HA_DATA_PULSE
  175. tmp = fsl_readl(&usb_dr_regs->otgsc) & ~OTGSC_INTSTS_MASK;
  176. tmp |= OTGSC_HA_DATA_PULSE;
  177. fsl_writel(tmp, &usb_dr_regs->otgsc);
  178. #else
  179. fsl_otg_loc_conn(1);
  180. #endif
  181. fsl_otg_add_timer(fsm, b_data_pulse_tmr);
  182. }
  183. void b_data_pulse_end(unsigned long foo)
  184. {
  185. #ifdef HA_DATA_PULSE
  186. #else
  187. fsl_otg_loc_conn(0);
  188. #endif
  189. /* Do VBUS pulse after data pulse */
  190. fsl_otg_pulse_vbus();
  191. }
  192. void fsl_otg_pulse_vbus(void)
  193. {
  194. srp_wait_done = 0;
  195. fsl_otg_chrg_vbus(&fsl_otg_dev->fsm, 1);
  196. /* start the timer to end vbus charge */
  197. fsl_otg_add_timer(&fsl_otg_dev->fsm, b_vbus_pulse_tmr);
  198. }
  199. void b_vbus_pulse_end(unsigned long foo)
  200. {
  201. fsl_otg_chrg_vbus(&fsl_otg_dev->fsm, 0);
  202. /*
  203. * As USB3300 using the same a_sess_vld and b_sess_vld voltage
  204. * we need to discharge the bus for a while to distinguish
  205. * residual voltage of vbus pulsing and A device pull up
  206. */
  207. fsl_otg_dischrg_vbus(1);
  208. fsl_otg_add_timer(&fsl_otg_dev->fsm, b_srp_wait_tmr);
  209. }
  210. void b_srp_end(unsigned long foo)
  211. {
  212. fsl_otg_dischrg_vbus(0);
  213. srp_wait_done = 1;
  214. if ((fsl_otg_dev->phy.otg->state == OTG_STATE_B_SRP_INIT) &&
  215. fsl_otg_dev->fsm.b_sess_vld)
  216. fsl_otg_dev->fsm.b_srp_done = 1;
  217. }
  218. /*
  219. * Workaround for a_host suspending too fast. When a_bus_req=0,
  220. * a_host will start by SRP. It needs to set b_hnp_enable before
  221. * actually suspending to start HNP
  222. */
  223. void a_wait_enum(unsigned long foo)
  224. {
  225. VDBG("a_wait_enum timeout\n");
  226. if (!fsl_otg_dev->phy.otg->host->b_hnp_enable)
  227. fsl_otg_add_timer(&fsl_otg_dev->fsm, a_wait_enum_tmr);
  228. else
  229. otg_statemachine(&fsl_otg_dev->fsm);
  230. }
  231. /* The timeout callback function to set time out bit */
  232. void set_tmout(unsigned long indicator)
  233. {
  234. *(int *)indicator = 1;
  235. }
  236. /* Initialize timers */
  237. int fsl_otg_init_timers(struct otg_fsm *fsm)
  238. {
  239. /* FSM used timers */
  240. a_wait_vrise_tmr = otg_timer_initializer(&set_tmout, TA_WAIT_VRISE,
  241. (unsigned long)&fsm->a_wait_vrise_tmout);
  242. if (!a_wait_vrise_tmr)
  243. return -ENOMEM;
  244. a_wait_bcon_tmr = otg_timer_initializer(&set_tmout, TA_WAIT_BCON,
  245. (unsigned long)&fsm->a_wait_bcon_tmout);
  246. if (!a_wait_bcon_tmr)
  247. return -ENOMEM;
  248. a_aidl_bdis_tmr = otg_timer_initializer(&set_tmout, TA_AIDL_BDIS,
  249. (unsigned long)&fsm->a_aidl_bdis_tmout);
  250. if (!a_aidl_bdis_tmr)
  251. return -ENOMEM;
  252. b_ase0_brst_tmr = otg_timer_initializer(&set_tmout, TB_ASE0_BRST,
  253. (unsigned long)&fsm->b_ase0_brst_tmout);
  254. if (!b_ase0_brst_tmr)
  255. return -ENOMEM;
  256. b_se0_srp_tmr = otg_timer_initializer(&set_tmout, TB_SE0_SRP,
  257. (unsigned long)&fsm->b_se0_srp);
  258. if (!b_se0_srp_tmr)
  259. return -ENOMEM;
  260. b_srp_fail_tmr = otg_timer_initializer(&set_tmout, TB_SRP_FAIL,
  261. (unsigned long)&fsm->b_srp_done);
  262. if (!b_srp_fail_tmr)
  263. return -ENOMEM;
  264. a_wait_enum_tmr = otg_timer_initializer(&a_wait_enum, 10,
  265. (unsigned long)&fsm);
  266. if (!a_wait_enum_tmr)
  267. return -ENOMEM;
  268. /* device driver used timers */
  269. b_srp_wait_tmr = otg_timer_initializer(&b_srp_end, TB_SRP_WAIT, 0);
  270. if (!b_srp_wait_tmr)
  271. return -ENOMEM;
  272. b_data_pulse_tmr = otg_timer_initializer(&b_data_pulse_end,
  273. TB_DATA_PLS, 0);
  274. if (!b_data_pulse_tmr)
  275. return -ENOMEM;
  276. b_vbus_pulse_tmr = otg_timer_initializer(&b_vbus_pulse_end,
  277. TB_VBUS_PLS, 0);
  278. if (!b_vbus_pulse_tmr)
  279. return -ENOMEM;
  280. return 0;
  281. }
  282. /* Uninitialize timers */
  283. void fsl_otg_uninit_timers(void)
  284. {
  285. /* FSM used timers */
  286. kfree(a_wait_vrise_tmr);
  287. kfree(a_wait_bcon_tmr);
  288. kfree(a_aidl_bdis_tmr);
  289. kfree(b_ase0_brst_tmr);
  290. kfree(b_se0_srp_tmr);
  291. kfree(b_srp_fail_tmr);
  292. kfree(a_wait_enum_tmr);
  293. /* device driver used timers */
  294. kfree(b_srp_wait_tmr);
  295. kfree(b_data_pulse_tmr);
  296. kfree(b_vbus_pulse_tmr);
  297. }
  298. static struct fsl_otg_timer *fsl_otg_get_timer(enum otg_fsm_timer t)
  299. {
  300. struct fsl_otg_timer *timer;
  301. /* REVISIT: use array of pointers to timers instead */
  302. switch (t) {
  303. case A_WAIT_VRISE:
  304. timer = a_wait_vrise_tmr;
  305. break;
  306. case A_WAIT_BCON:
  307. timer = a_wait_vrise_tmr;
  308. break;
  309. case A_AIDL_BDIS:
  310. timer = a_wait_vrise_tmr;
  311. break;
  312. case B_ASE0_BRST:
  313. timer = a_wait_vrise_tmr;
  314. break;
  315. case B_SE0_SRP:
  316. timer = a_wait_vrise_tmr;
  317. break;
  318. case B_SRP_FAIL:
  319. timer = a_wait_vrise_tmr;
  320. break;
  321. case A_WAIT_ENUM:
  322. timer = a_wait_vrise_tmr;
  323. break;
  324. default:
  325. timer = NULL;
  326. }
  327. return timer;
  328. }
  329. /* Add timer to timer list */
  330. void fsl_otg_add_timer(struct otg_fsm *fsm, void *gtimer)
  331. {
  332. struct fsl_otg_timer *timer = gtimer;
  333. struct fsl_otg_timer *tmp_timer;
  334. /*
  335. * Check if the timer is already in the active list,
  336. * if so update timer count
  337. */
  338. list_for_each_entry(tmp_timer, &active_timers, list)
  339. if (tmp_timer == timer) {
  340. timer->count = timer->expires;
  341. return;
  342. }
  343. timer->count = timer->expires;
  344. list_add_tail(&timer->list, &active_timers);
  345. }
  346. static void fsl_otg_fsm_add_timer(struct otg_fsm *fsm, enum otg_fsm_timer t)
  347. {
  348. struct fsl_otg_timer *timer;
  349. timer = fsl_otg_get_timer(t);
  350. if (!timer)
  351. return;
  352. fsl_otg_add_timer(fsm, timer);
  353. }
  354. /* Remove timer from the timer list; clear timeout status */
  355. void fsl_otg_del_timer(struct otg_fsm *fsm, void *gtimer)
  356. {
  357. struct fsl_otg_timer *timer = gtimer;
  358. struct fsl_otg_timer *tmp_timer, *del_tmp;
  359. list_for_each_entry_safe(tmp_timer, del_tmp, &active_timers, list)
  360. if (tmp_timer == timer)
  361. list_del(&timer->list);
  362. }
  363. static void fsl_otg_fsm_del_timer(struct otg_fsm *fsm, enum otg_fsm_timer t)
  364. {
  365. struct fsl_otg_timer *timer;
  366. timer = fsl_otg_get_timer(t);
  367. if (!timer)
  368. return;
  369. fsl_otg_del_timer(fsm, timer);
  370. }
  371. /* Reset controller, not reset the bus */
  372. void otg_reset_controller(void)
  373. {
  374. u32 command;
  375. command = fsl_readl(&usb_dr_regs->usbcmd);
  376. command |= (1 << 1);
  377. fsl_writel(command, &usb_dr_regs->usbcmd);
  378. while (fsl_readl(&usb_dr_regs->usbcmd) & (1 << 1))
  379. ;
  380. }
  381. /* Call suspend/resume routines in host driver */
  382. int fsl_otg_start_host(struct otg_fsm *fsm, int on)
  383. {
  384. struct usb_otg *otg = fsm->otg;
  385. struct device *dev;
  386. struct fsl_otg *otg_dev =
  387. container_of(otg->usb_phy, struct fsl_otg, phy);
  388. u32 retval = 0;
  389. if (!otg->host)
  390. return -ENODEV;
  391. dev = otg->host->controller;
  392. /*
  393. * Update a_vbus_vld state as a_vbus_vld int is disabled
  394. * in device mode
  395. */
  396. fsm->a_vbus_vld =
  397. !!(fsl_readl(&usb_dr_regs->otgsc) & OTGSC_STS_A_VBUS_VALID);
  398. if (on) {
  399. /* start fsl usb host controller */
  400. if (otg_dev->host_working)
  401. goto end;
  402. else {
  403. otg_reset_controller();
  404. VDBG("host on......\n");
  405. if (dev->driver->pm && dev->driver->pm->resume) {
  406. retval = dev->driver->pm->resume(dev);
  407. if (fsm->id) {
  408. /* default-b */
  409. fsl_otg_drv_vbus(fsm, 1);
  410. /*
  411. * Workaround: b_host can't driver
  412. * vbus, but PP in PORTSC needs to
  413. * be 1 for host to work.
  414. * So we set drv_vbus bit in
  415. * transceiver to 0 thru ULPI.
  416. */
  417. write_ulpi(0x0c, 0x20);
  418. }
  419. }
  420. otg_dev->host_working = 1;
  421. }
  422. } else {
  423. /* stop fsl usb host controller */
  424. if (!otg_dev->host_working)
  425. goto end;
  426. else {
  427. VDBG("host off......\n");
  428. if (dev && dev->driver) {
  429. if (dev->driver->pm && dev->driver->pm->suspend)
  430. retval = dev->driver->pm->suspend(dev);
  431. if (fsm->id)
  432. /* default-b */
  433. fsl_otg_drv_vbus(fsm, 0);
  434. }
  435. otg_dev->host_working = 0;
  436. }
  437. }
  438. end:
  439. return retval;
  440. }
  441. /*
  442. * Call suspend and resume function in udc driver
  443. * to stop and start udc driver.
  444. */
  445. int fsl_otg_start_gadget(struct otg_fsm *fsm, int on)
  446. {
  447. struct usb_otg *otg = fsm->otg;
  448. struct device *dev;
  449. if (!otg->gadget || !otg->gadget->dev.parent)
  450. return -ENODEV;
  451. VDBG("gadget %s\n", on ? "on" : "off");
  452. dev = otg->gadget->dev.parent;
  453. if (on) {
  454. if (dev->driver->resume)
  455. dev->driver->resume(dev);
  456. } else {
  457. if (dev->driver->suspend)
  458. dev->driver->suspend(dev, otg_suspend_state);
  459. }
  460. return 0;
  461. }
  462. /*
  463. * Called by initialization code of host driver. Register host controller
  464. * to the OTG. Suspend host for OTG role detection.
  465. */
  466. static int fsl_otg_set_host(struct usb_otg *otg, struct usb_bus *host)
  467. {
  468. struct fsl_otg *otg_dev;
  469. if (!otg)
  470. return -ENODEV;
  471. otg_dev = container_of(otg->usb_phy, struct fsl_otg, phy);
  472. if (otg_dev != fsl_otg_dev)
  473. return -ENODEV;
  474. otg->host = host;
  475. otg_dev->fsm.a_bus_drop = 0;
  476. otg_dev->fsm.a_bus_req = 1;
  477. if (host) {
  478. VDBG("host off......\n");
  479. otg->host->otg_port = fsl_otg_initdata.otg_port;
  480. otg->host->is_b_host = otg_dev->fsm.id;
  481. /*
  482. * must leave time for hub_wq to finish its thing
  483. * before yanking the host driver out from under it,
  484. * so suspend the host after a short delay.
  485. */
  486. otg_dev->host_working = 1;
  487. schedule_delayed_work(&otg_dev->otg_event, 100);
  488. return 0;
  489. } else {
  490. /* host driver going away */
  491. if (!(fsl_readl(&otg_dev->dr_mem_map->otgsc) &
  492. OTGSC_STS_USB_ID)) {
  493. /* Mini-A cable connected */
  494. struct otg_fsm *fsm = &otg_dev->fsm;
  495. otg->state = OTG_STATE_UNDEFINED;
  496. fsm->protocol = PROTO_UNDEF;
  497. }
  498. }
  499. otg_dev->host_working = 0;
  500. otg_statemachine(&otg_dev->fsm);
  501. return 0;
  502. }
  503. /* Called by initialization code of udc. Register udc to OTG. */
  504. static int fsl_otg_set_peripheral(struct usb_otg *otg,
  505. struct usb_gadget *gadget)
  506. {
  507. struct fsl_otg *otg_dev;
  508. if (!otg)
  509. return -ENODEV;
  510. otg_dev = container_of(otg->usb_phy, struct fsl_otg, phy);
  511. VDBG("otg_dev 0x%x\n", (int)otg_dev);
  512. VDBG("fsl_otg_dev 0x%x\n", (int)fsl_otg_dev);
  513. if (otg_dev != fsl_otg_dev)
  514. return -ENODEV;
  515. if (!gadget) {
  516. if (!otg->default_a)
  517. otg->gadget->ops->vbus_draw(otg->gadget, 0);
  518. usb_gadget_vbus_disconnect(otg->gadget);
  519. otg->gadget = 0;
  520. otg_dev->fsm.b_bus_req = 0;
  521. otg_statemachine(&otg_dev->fsm);
  522. return 0;
  523. }
  524. otg->gadget = gadget;
  525. otg->gadget->is_a_peripheral = !otg_dev->fsm.id;
  526. otg_dev->fsm.b_bus_req = 1;
  527. /* start the gadget right away if the ID pin says Mini-B */
  528. pr_debug("ID pin=%d\n", otg_dev->fsm.id);
  529. if (otg_dev->fsm.id == 1) {
  530. fsl_otg_start_host(&otg_dev->fsm, 0);
  531. otg_drv_vbus(&otg_dev->fsm, 0);
  532. fsl_otg_start_gadget(&otg_dev->fsm, 1);
  533. }
  534. return 0;
  535. }
  536. /* Set OTG port power, only for B-device */
  537. static int fsl_otg_set_power(struct usb_phy *phy, unsigned mA)
  538. {
  539. if (!fsl_otg_dev)
  540. return -ENODEV;
  541. if (phy->otg->state == OTG_STATE_B_PERIPHERAL)
  542. pr_info("FSL OTG: Draw %d mA\n", mA);
  543. return 0;
  544. }
  545. /*
  546. * Delayed pin detect interrupt processing.
  547. *
  548. * When the Mini-A cable is disconnected from the board,
  549. * the pin-detect interrupt happens before the disconnect
  550. * interrupts for the connected device(s). In order to
  551. * process the disconnect interrupt(s) prior to switching
  552. * roles, the pin-detect interrupts are delayed, and handled
  553. * by this routine.
  554. */
  555. static void fsl_otg_event(struct work_struct *work)
  556. {
  557. struct fsl_otg *og = container_of(work, struct fsl_otg, otg_event.work);
  558. struct otg_fsm *fsm = &og->fsm;
  559. if (fsm->id) { /* switch to gadget */
  560. fsl_otg_start_host(fsm, 0);
  561. otg_drv_vbus(fsm, 0);
  562. fsl_otg_start_gadget(fsm, 1);
  563. }
  564. }
  565. /* B-device start SRP */
  566. static int fsl_otg_start_srp(struct usb_otg *otg)
  567. {
  568. struct fsl_otg *otg_dev;
  569. if (!otg || otg->state != OTG_STATE_B_IDLE)
  570. return -ENODEV;
  571. otg_dev = container_of(otg->usb_phy, struct fsl_otg, phy);
  572. if (otg_dev != fsl_otg_dev)
  573. return -ENODEV;
  574. otg_dev->fsm.b_bus_req = 1;
  575. otg_statemachine(&otg_dev->fsm);
  576. return 0;
  577. }
  578. /* A_host suspend will call this function to start hnp */
  579. static int fsl_otg_start_hnp(struct usb_otg *otg)
  580. {
  581. struct fsl_otg *otg_dev;
  582. if (!otg)
  583. return -ENODEV;
  584. otg_dev = container_of(otg->usb_phy, struct fsl_otg, phy);
  585. if (otg_dev != fsl_otg_dev)
  586. return -ENODEV;
  587. pr_debug("start_hnp...\n");
  588. /* clear a_bus_req to enter a_suspend state */
  589. otg_dev->fsm.a_bus_req = 0;
  590. otg_statemachine(&otg_dev->fsm);
  591. return 0;
  592. }
  593. /*
  594. * Interrupt handler. OTG/host/peripheral share the same int line.
  595. * OTG driver clears OTGSC interrupts and leaves USB interrupts
  596. * intact. It needs to have knowledge of some USB interrupts
  597. * such as port change.
  598. */
  599. irqreturn_t fsl_otg_isr(int irq, void *dev_id)
  600. {
  601. struct otg_fsm *fsm = &((struct fsl_otg *)dev_id)->fsm;
  602. struct usb_otg *otg = ((struct fsl_otg *)dev_id)->phy.otg;
  603. u32 otg_int_src, otg_sc;
  604. otg_sc = fsl_readl(&usb_dr_regs->otgsc);
  605. otg_int_src = otg_sc & OTGSC_INTSTS_MASK & (otg_sc >> 8);
  606. /* Only clear otg interrupts */
  607. fsl_writel(otg_sc, &usb_dr_regs->otgsc);
  608. /*FIXME: ID change not generate when init to 0 */
  609. fsm->id = (otg_sc & OTGSC_STS_USB_ID) ? 1 : 0;
  610. otg->default_a = (fsm->id == 0);
  611. /* process OTG interrupts */
  612. if (otg_int_src) {
  613. if (otg_int_src & OTGSC_INTSTS_USB_ID) {
  614. fsm->id = (otg_sc & OTGSC_STS_USB_ID) ? 1 : 0;
  615. otg->default_a = (fsm->id == 0);
  616. /* clear conn information */
  617. if (fsm->id)
  618. fsm->b_conn = 0;
  619. else
  620. fsm->a_conn = 0;
  621. if (otg->host)
  622. otg->host->is_b_host = fsm->id;
  623. if (otg->gadget)
  624. otg->gadget->is_a_peripheral = !fsm->id;
  625. VDBG("ID int (ID is %d)\n", fsm->id);
  626. if (fsm->id) { /* switch to gadget */
  627. schedule_delayed_work(
  628. &((struct fsl_otg *)dev_id)->otg_event,
  629. 100);
  630. } else { /* switch to host */
  631. cancel_delayed_work(&
  632. ((struct fsl_otg *)dev_id)->
  633. otg_event);
  634. fsl_otg_start_gadget(fsm, 0);
  635. otg_drv_vbus(fsm, 1);
  636. fsl_otg_start_host(fsm, 1);
  637. }
  638. return IRQ_HANDLED;
  639. }
  640. }
  641. return IRQ_NONE;
  642. }
  643. static struct otg_fsm_ops fsl_otg_ops = {
  644. .chrg_vbus = fsl_otg_chrg_vbus,
  645. .drv_vbus = fsl_otg_drv_vbus,
  646. .loc_conn = fsl_otg_loc_conn,
  647. .loc_sof = fsl_otg_loc_sof,
  648. .start_pulse = fsl_otg_start_pulse,
  649. .add_timer = fsl_otg_fsm_add_timer,
  650. .del_timer = fsl_otg_fsm_del_timer,
  651. .start_host = fsl_otg_start_host,
  652. .start_gadget = fsl_otg_start_gadget,
  653. };
  654. /* Initialize the global variable fsl_otg_dev and request IRQ for OTG */
  655. static int fsl_otg_conf(struct platform_device *pdev)
  656. {
  657. struct fsl_otg *fsl_otg_tc;
  658. int status;
  659. if (fsl_otg_dev)
  660. return 0;
  661. /* allocate space to fsl otg device */
  662. fsl_otg_tc = kzalloc(sizeof(struct fsl_otg), GFP_KERNEL);
  663. if (!fsl_otg_tc)
  664. return -ENOMEM;
  665. fsl_otg_tc->phy.otg = kzalloc(sizeof(struct usb_otg), GFP_KERNEL);
  666. if (!fsl_otg_tc->phy.otg) {
  667. kfree(fsl_otg_tc);
  668. return -ENOMEM;
  669. }
  670. INIT_DELAYED_WORK(&fsl_otg_tc->otg_event, fsl_otg_event);
  671. INIT_LIST_HEAD(&active_timers);
  672. status = fsl_otg_init_timers(&fsl_otg_tc->fsm);
  673. if (status) {
  674. pr_info("Couldn't init OTG timers\n");
  675. goto err;
  676. }
  677. mutex_init(&fsl_otg_tc->fsm.lock);
  678. /* Set OTG state machine operations */
  679. fsl_otg_tc->fsm.ops = &fsl_otg_ops;
  680. /* initialize the otg structure */
  681. fsl_otg_tc->phy.label = DRIVER_DESC;
  682. fsl_otg_tc->phy.dev = &pdev->dev;
  683. fsl_otg_tc->phy.set_power = fsl_otg_set_power;
  684. fsl_otg_tc->phy.otg->usb_phy = &fsl_otg_tc->phy;
  685. fsl_otg_tc->phy.otg->set_host = fsl_otg_set_host;
  686. fsl_otg_tc->phy.otg->set_peripheral = fsl_otg_set_peripheral;
  687. fsl_otg_tc->phy.otg->start_hnp = fsl_otg_start_hnp;
  688. fsl_otg_tc->phy.otg->start_srp = fsl_otg_start_srp;
  689. fsl_otg_dev = fsl_otg_tc;
  690. /* Store the otg transceiver */
  691. status = usb_add_phy(&fsl_otg_tc->phy, USB_PHY_TYPE_USB2);
  692. if (status) {
  693. pr_warn(FSL_OTG_NAME ": unable to register OTG transceiver.\n");
  694. goto err;
  695. }
  696. return 0;
  697. err:
  698. fsl_otg_uninit_timers();
  699. kfree(fsl_otg_tc->phy.otg);
  700. kfree(fsl_otg_tc);
  701. return status;
  702. }
  703. /* OTG Initialization */
  704. int usb_otg_start(struct platform_device *pdev)
  705. {
  706. struct fsl_otg *p_otg;
  707. struct usb_phy *otg_trans = usb_get_phy(USB_PHY_TYPE_USB2);
  708. struct otg_fsm *fsm;
  709. int status;
  710. struct resource *res;
  711. u32 temp;
  712. struct fsl_usb2_platform_data *pdata = dev_get_platdata(&pdev->dev);
  713. p_otg = container_of(otg_trans, struct fsl_otg, phy);
  714. fsm = &p_otg->fsm;
  715. /* Initialize the state machine structure with default values */
  716. SET_OTG_STATE(otg_trans, OTG_STATE_UNDEFINED);
  717. fsm->otg = p_otg->phy.otg;
  718. /* We don't require predefined MEM/IRQ resource index */
  719. res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
  720. if (!res)
  721. return -ENXIO;
  722. /* We don't request_mem_region here to enable resource sharing
  723. * with host/device */
  724. usb_dr_regs = ioremap(res->start, sizeof(struct usb_dr_mmap));
  725. p_otg->dr_mem_map = (struct usb_dr_mmap *)usb_dr_regs;
  726. pdata->regs = (void *)usb_dr_regs;
  727. if (pdata->init && pdata->init(pdev) != 0)
  728. return -EINVAL;
  729. #ifdef CONFIG_PPC32
  730. if (pdata->big_endian_mmio) {
  731. _fsl_readl = _fsl_readl_be;
  732. _fsl_writel = _fsl_writel_be;
  733. } else {
  734. _fsl_readl = _fsl_readl_le;
  735. _fsl_writel = _fsl_writel_le;
  736. }
  737. #endif
  738. /* request irq */
  739. p_otg->irq = platform_get_irq(pdev, 0);
  740. status = request_irq(p_otg->irq, fsl_otg_isr,
  741. IRQF_SHARED, driver_name, p_otg);
  742. if (status) {
  743. dev_dbg(p_otg->phy.dev, "can't get IRQ %d, error %d\n",
  744. p_otg->irq, status);
  745. iounmap(p_otg->dr_mem_map);
  746. kfree(p_otg->phy.otg);
  747. kfree(p_otg);
  748. return status;
  749. }
  750. /* stop the controller */
  751. temp = fsl_readl(&p_otg->dr_mem_map->usbcmd);
  752. temp &= ~USB_CMD_RUN_STOP;
  753. fsl_writel(temp, &p_otg->dr_mem_map->usbcmd);
  754. /* reset the controller */
  755. temp = fsl_readl(&p_otg->dr_mem_map->usbcmd);
  756. temp |= USB_CMD_CTRL_RESET;
  757. fsl_writel(temp, &p_otg->dr_mem_map->usbcmd);
  758. /* wait reset completed */
  759. while (fsl_readl(&p_otg->dr_mem_map->usbcmd) & USB_CMD_CTRL_RESET)
  760. ;
  761. /* configure the VBUSHS as IDLE(both host and device) */
  762. temp = USB_MODE_STREAM_DISABLE | (pdata->es ? USB_MODE_ES : 0);
  763. fsl_writel(temp, &p_otg->dr_mem_map->usbmode);
  764. /* configure PHY interface */
  765. temp = fsl_readl(&p_otg->dr_mem_map->portsc);
  766. temp &= ~(PORTSC_PHY_TYPE_SEL | PORTSC_PTW);
  767. switch (pdata->phy_mode) {
  768. case FSL_USB2_PHY_ULPI:
  769. temp |= PORTSC_PTS_ULPI;
  770. break;
  771. case FSL_USB2_PHY_UTMI_WIDE:
  772. temp |= PORTSC_PTW_16BIT;
  773. /* fall through */
  774. case FSL_USB2_PHY_UTMI:
  775. temp |= PORTSC_PTS_UTMI;
  776. /* fall through */
  777. default:
  778. break;
  779. }
  780. fsl_writel(temp, &p_otg->dr_mem_map->portsc);
  781. if (pdata->have_sysif_regs) {
  782. /* configure control enable IO output, big endian register */
  783. temp = __raw_readl(&p_otg->dr_mem_map->control);
  784. temp |= USB_CTRL_IOENB;
  785. __raw_writel(temp, &p_otg->dr_mem_map->control);
  786. }
  787. /* disable all interrupt and clear all OTGSC status */
  788. temp = fsl_readl(&p_otg->dr_mem_map->otgsc);
  789. temp &= ~OTGSC_INTERRUPT_ENABLE_BITS_MASK;
  790. temp |= OTGSC_INTERRUPT_STATUS_BITS_MASK | OTGSC_CTRL_VBUS_DISCHARGE;
  791. fsl_writel(temp, &p_otg->dr_mem_map->otgsc);
  792. /*
  793. * The identification (id) input is FALSE when a Mini-A plug is inserted
  794. * in the devices Mini-AB receptacle. Otherwise, this input is TRUE.
  795. * Also: record initial state of ID pin
  796. */
  797. if (fsl_readl(&p_otg->dr_mem_map->otgsc) & OTGSC_STS_USB_ID) {
  798. p_otg->phy.otg->state = OTG_STATE_UNDEFINED;
  799. p_otg->fsm.id = 1;
  800. } else {
  801. p_otg->phy.otg->state = OTG_STATE_A_IDLE;
  802. p_otg->fsm.id = 0;
  803. }
  804. pr_debug("initial ID pin=%d\n", p_otg->fsm.id);
  805. /* enable OTG ID pin interrupt */
  806. temp = fsl_readl(&p_otg->dr_mem_map->otgsc);
  807. temp |= OTGSC_INTR_USB_ID_EN;
  808. temp &= ~(OTGSC_CTRL_VBUS_DISCHARGE | OTGSC_INTR_1MS_TIMER_EN);
  809. fsl_writel(temp, &p_otg->dr_mem_map->otgsc);
  810. return 0;
  811. }
  812. /*
  813. * state file in sysfs
  814. */
  815. static ssize_t show_fsl_usb2_otg_state(struct device *dev,
  816. struct device_attribute *attr, char *buf)
  817. {
  818. struct otg_fsm *fsm = &fsl_otg_dev->fsm;
  819. char *next = buf;
  820. unsigned size = PAGE_SIZE;
  821. int t;
  822. mutex_lock(&fsm->lock);
  823. /* basic driver infomation */
  824. t = scnprintf(next, size,
  825. DRIVER_DESC "\n" "fsl_usb2_otg version: %s\n\n",
  826. DRIVER_VERSION);
  827. size -= t;
  828. next += t;
  829. /* Registers */
  830. t = scnprintf(next, size,
  831. "OTGSC: 0x%08x\n"
  832. "PORTSC: 0x%08x\n"
  833. "USBMODE: 0x%08x\n"
  834. "USBCMD: 0x%08x\n"
  835. "USBSTS: 0x%08x\n"
  836. "USBINTR: 0x%08x\n",
  837. fsl_readl(&usb_dr_regs->otgsc),
  838. fsl_readl(&usb_dr_regs->portsc),
  839. fsl_readl(&usb_dr_regs->usbmode),
  840. fsl_readl(&usb_dr_regs->usbcmd),
  841. fsl_readl(&usb_dr_regs->usbsts),
  842. fsl_readl(&usb_dr_regs->usbintr));
  843. size -= t;
  844. next += t;
  845. /* State */
  846. t = scnprintf(next, size,
  847. "OTG state: %s\n\n",
  848. usb_otg_state_string(fsl_otg_dev->phy.otg->state));
  849. size -= t;
  850. next += t;
  851. /* State Machine Variables */
  852. t = scnprintf(next, size,
  853. "a_bus_req: %d\n"
  854. "b_bus_req: %d\n"
  855. "a_bus_resume: %d\n"
  856. "a_bus_suspend: %d\n"
  857. "a_conn: %d\n"
  858. "a_sess_vld: %d\n"
  859. "a_srp_det: %d\n"
  860. "a_vbus_vld: %d\n"
  861. "b_bus_resume: %d\n"
  862. "b_bus_suspend: %d\n"
  863. "b_conn: %d\n"
  864. "b_se0_srp: %d\n"
  865. "b_ssend_srp: %d\n"
  866. "b_sess_vld: %d\n"
  867. "id: %d\n",
  868. fsm->a_bus_req,
  869. fsm->b_bus_req,
  870. fsm->a_bus_resume,
  871. fsm->a_bus_suspend,
  872. fsm->a_conn,
  873. fsm->a_sess_vld,
  874. fsm->a_srp_det,
  875. fsm->a_vbus_vld,
  876. fsm->b_bus_resume,
  877. fsm->b_bus_suspend,
  878. fsm->b_conn,
  879. fsm->b_se0_srp,
  880. fsm->b_ssend_srp,
  881. fsm->b_sess_vld,
  882. fsm->id);
  883. size -= t;
  884. next += t;
  885. mutex_unlock(&fsm->lock);
  886. return PAGE_SIZE - size;
  887. }
  888. static DEVICE_ATTR(fsl_usb2_otg_state, S_IRUGO, show_fsl_usb2_otg_state, NULL);
  889. /* Char driver interface to control some OTG input */
  890. /*
  891. * Handle some ioctl command, such as get otg
  892. * status and set host suspend
  893. */
  894. static long fsl_otg_ioctl(struct file *file, unsigned int cmd,
  895. unsigned long arg)
  896. {
  897. u32 retval = 0;
  898. switch (cmd) {
  899. case GET_OTG_STATUS:
  900. retval = fsl_otg_dev->host_working;
  901. break;
  902. case SET_A_SUSPEND_REQ:
  903. fsl_otg_dev->fsm.a_suspend_req_inf = arg;
  904. break;
  905. case SET_A_BUS_DROP:
  906. fsl_otg_dev->fsm.a_bus_drop = arg;
  907. break;
  908. case SET_A_BUS_REQ:
  909. fsl_otg_dev->fsm.a_bus_req = arg;
  910. break;
  911. case SET_B_BUS_REQ:
  912. fsl_otg_dev->fsm.b_bus_req = arg;
  913. break;
  914. default:
  915. break;
  916. }
  917. otg_statemachine(&fsl_otg_dev->fsm);
  918. return retval;
  919. }
  920. static int fsl_otg_open(struct inode *inode, struct file *file)
  921. {
  922. return 0;
  923. }
  924. static int fsl_otg_release(struct inode *inode, struct file *file)
  925. {
  926. return 0;
  927. }
  928. static const struct file_operations otg_fops = {
  929. .owner = THIS_MODULE,
  930. .llseek = NULL,
  931. .read = NULL,
  932. .write = NULL,
  933. .unlocked_ioctl = fsl_otg_ioctl,
  934. .open = fsl_otg_open,
  935. .release = fsl_otg_release,
  936. };
  937. static int fsl_otg_probe(struct platform_device *pdev)
  938. {
  939. int ret;
  940. if (!dev_get_platdata(&pdev->dev))
  941. return -ENODEV;
  942. /* configure the OTG */
  943. ret = fsl_otg_conf(pdev);
  944. if (ret) {
  945. dev_err(&pdev->dev, "Couldn't configure OTG module\n");
  946. return ret;
  947. }
  948. /* start OTG */
  949. ret = usb_otg_start(pdev);
  950. if (ret) {
  951. dev_err(&pdev->dev, "Can't init FSL OTG device\n");
  952. return ret;
  953. }
  954. ret = register_chrdev(FSL_OTG_MAJOR, FSL_OTG_NAME, &otg_fops);
  955. if (ret) {
  956. dev_err(&pdev->dev, "unable to register FSL OTG device\n");
  957. return ret;
  958. }
  959. ret = device_create_file(&pdev->dev, &dev_attr_fsl_usb2_otg_state);
  960. if (ret)
  961. dev_warn(&pdev->dev, "Can't register sysfs attribute\n");
  962. return ret;
  963. }
  964. static int fsl_otg_remove(struct platform_device *pdev)
  965. {
  966. struct fsl_usb2_platform_data *pdata = dev_get_platdata(&pdev->dev);
  967. usb_remove_phy(&fsl_otg_dev->phy);
  968. free_irq(fsl_otg_dev->irq, fsl_otg_dev);
  969. iounmap((void *)usb_dr_regs);
  970. fsl_otg_uninit_timers();
  971. kfree(fsl_otg_dev->phy.otg);
  972. kfree(fsl_otg_dev);
  973. device_remove_file(&pdev->dev, &dev_attr_fsl_usb2_otg_state);
  974. unregister_chrdev(FSL_OTG_MAJOR, FSL_OTG_NAME);
  975. if (pdata->exit)
  976. pdata->exit(pdev);
  977. return 0;
  978. }
  979. struct platform_driver fsl_otg_driver = {
  980. .probe = fsl_otg_probe,
  981. .remove = fsl_otg_remove,
  982. .driver = {
  983. .name = driver_name,
  984. .owner = THIS_MODULE,
  985. },
  986. };
  987. module_platform_driver(fsl_otg_driver);
  988. MODULE_DESCRIPTION(DRIVER_INFO);
  989. MODULE_AUTHOR(DRIVER_AUTHOR);
  990. MODULE_LICENSE("GPL");