io_ti.h 5.4 KB

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  1. /*****************************************************************************
  2. *
  3. * Copyright (C) 1997-2002 Inside Out Networks, Inc.
  4. *
  5. * This program is free software; you can redistribute it and/or modify
  6. * it under the terms of the GNU General Public License as published by
  7. * the Free Software Foundation; either version 2 of the License, or
  8. * (at your option) any later version.
  9. *
  10. *
  11. * Feb-16-2001 DMI Added I2C structure definitions
  12. * May-29-2002 gkh Ported to Linux
  13. *
  14. *
  15. ******************************************************************************/
  16. #ifndef _IO_TI_H_
  17. #define _IO_TI_H_
  18. /* Address Space */
  19. #define DTK_ADDR_SPACE_XDATA 0x03 /* Addr is placed in XDATA space */
  20. #define DTK_ADDR_SPACE_I2C_TYPE_II 0x82 /* Addr is placed in I2C area */
  21. #define DTK_ADDR_SPACE_I2C_TYPE_III 0x83 /* Addr is placed in I2C area */
  22. /* UART Defines */
  23. #define UMPMEM_BASE_UART1 0xFFA0 /* UMP UART1 base address */
  24. #define UMPMEM_BASE_UART2 0xFFB0 /* UMP UART2 base address */
  25. #define UMPMEM_OFFS_UART_LSR 0x05 /* UMP UART LSR register offset */
  26. /* Bits per character */
  27. #define UMP_UART_CHAR5BITS 0x00
  28. #define UMP_UART_CHAR6BITS 0x01
  29. #define UMP_UART_CHAR7BITS 0x02
  30. #define UMP_UART_CHAR8BITS 0x03
  31. /* Parity */
  32. #define UMP_UART_NOPARITY 0x00
  33. #define UMP_UART_ODDPARITY 0x01
  34. #define UMP_UART_EVENPARITY 0x02
  35. #define UMP_UART_MARKPARITY 0x03
  36. #define UMP_UART_SPACEPARITY 0x04
  37. /* Stop bits */
  38. #define UMP_UART_STOPBIT1 0x00
  39. #define UMP_UART_STOPBIT15 0x01
  40. #define UMP_UART_STOPBIT2 0x02
  41. /* Line status register masks */
  42. #define UMP_UART_LSR_OV_MASK 0x01
  43. #define UMP_UART_LSR_PE_MASK 0x02
  44. #define UMP_UART_LSR_FE_MASK 0x04
  45. #define UMP_UART_LSR_BR_MASK 0x08
  46. #define UMP_UART_LSR_ER_MASK 0x0F
  47. #define UMP_UART_LSR_RX_MASK 0x10
  48. #define UMP_UART_LSR_TX_MASK 0x20
  49. #define UMP_UART_LSR_DATA_MASK (LSR_PAR_ERR | LSR_FRM_ERR | LSR_BREAK)
  50. /* Port Settings Constants) */
  51. #define UMP_MASK_UART_FLAGS_RTS_FLOW 0x0001
  52. #define UMP_MASK_UART_FLAGS_RTS_DISABLE 0x0002
  53. #define UMP_MASK_UART_FLAGS_PARITY 0x0008
  54. #define UMP_MASK_UART_FLAGS_OUT_X_DSR_FLOW 0x0010
  55. #define UMP_MASK_UART_FLAGS_OUT_X_CTS_FLOW 0x0020
  56. #define UMP_MASK_UART_FLAGS_OUT_X 0x0040
  57. #define UMP_MASK_UART_FLAGS_OUT_XA 0x0080
  58. #define UMP_MASK_UART_FLAGS_IN_X 0x0100
  59. #define UMP_MASK_UART_FLAGS_DTR_FLOW 0x0800
  60. #define UMP_MASK_UART_FLAGS_DTR_DISABLE 0x1000
  61. #define UMP_MASK_UART_FLAGS_RECEIVE_MS_INT 0x2000
  62. #define UMP_MASK_UART_FLAGS_AUTO_START_ON_ERR 0x4000
  63. #define UMP_DMA_MODE_CONTINOUS 0x01
  64. #define UMP_PIPE_TRANS_TIMEOUT_ENA 0x80
  65. #define UMP_PIPE_TRANSFER_MODE_MASK 0x03
  66. #define UMP_PIPE_TRANS_TIMEOUT_MASK 0x7C
  67. /* Purge port Direction Mask Bits */
  68. #define UMP_PORT_DIR_OUT 0x01
  69. #define UMP_PORT_DIR_IN 0x02
  70. /* Address of Port 0 */
  71. #define UMPM_UART1_PORT 0x03
  72. /* Commands */
  73. #define UMPC_SET_CONFIG 0x05
  74. #define UMPC_OPEN_PORT 0x06
  75. #define UMPC_CLOSE_PORT 0x07
  76. #define UMPC_START_PORT 0x08
  77. #define UMPC_STOP_PORT 0x09
  78. #define UMPC_TEST_PORT 0x0A
  79. #define UMPC_PURGE_PORT 0x0B
  80. /* Force the Firmware to complete the current Read */
  81. #define UMPC_COMPLETE_READ 0x80
  82. /* Force UMP back into BOOT Mode */
  83. #define UMPC_HARDWARE_RESET 0x81
  84. /*
  85. * Copy current download image to type 0xf2 record in 16k I2C
  86. * firmware will change 0xff record to type 2 record when complete
  87. */
  88. #define UMPC_COPY_DNLD_TO_I2C 0x82
  89. /*
  90. * Special function register commands
  91. * wIndex is register address
  92. * wValue is MSB/LSB mask/data
  93. */
  94. #define UMPC_WRITE_SFR 0x83 /* Write SFR Register */
  95. /* wIndex is register address */
  96. #define UMPC_READ_SFR 0x84 /* Read SRF Register */
  97. /* Set or Clear DTR (wValue bit 0 Set/Clear) wIndex ModuleID (port) */
  98. #define UMPC_SET_CLR_DTR 0x85
  99. /* Set or Clear RTS (wValue bit 0 Set/Clear) wIndex ModuleID (port) */
  100. #define UMPC_SET_CLR_RTS 0x86
  101. /* Set or Clear LOOPBACK (wValue bit 0 Set/Clear) wIndex ModuleID (port) */
  102. #define UMPC_SET_CLR_LOOPBACK 0x87
  103. /* Set or Clear BREAK (wValue bit 0 Set/Clear) wIndex ModuleID (port) */
  104. #define UMPC_SET_CLR_BREAK 0x88
  105. /* Read MSR wIndex ModuleID (port) */
  106. #define UMPC_READ_MSR 0x89
  107. /* Toolkit commands */
  108. /* Read-write group */
  109. #define UMPC_MEMORY_READ 0x92
  110. #define UMPC_MEMORY_WRITE 0x93
  111. /*
  112. * UMP DMA Definitions
  113. */
  114. #define UMPD_OEDB1_ADDRESS 0xFF08
  115. #define UMPD_OEDB2_ADDRESS 0xFF10
  116. struct out_endpoint_desc_block {
  117. __u8 Configuration;
  118. __u8 XBufAddr;
  119. __u8 XByteCount;
  120. __u8 Unused1;
  121. __u8 Unused2;
  122. __u8 YBufAddr;
  123. __u8 YByteCount;
  124. __u8 BufferSize;
  125. } __attribute__((packed));
  126. /*
  127. * TYPE DEFINITIONS
  128. * Structures for Firmware commands
  129. */
  130. /* UART settings */
  131. struct ump_uart_config {
  132. __u16 wBaudRate; /* Baud rate */
  133. __u16 wFlags; /* Bitmap mask of flags */
  134. __u8 bDataBits; /* 5..8 - data bits per character */
  135. __u8 bParity; /* Parity settings */
  136. __u8 bStopBits; /* Stop bits settings */
  137. char cXon; /* XON character */
  138. char cXoff; /* XOFF character */
  139. __u8 bUartMode; /* Will be updated when a user */
  140. /* interface is defined */
  141. } __attribute__((packed));
  142. /*
  143. * TYPE DEFINITIONS
  144. * Structures for USB interrupts
  145. */
  146. /* Interrupt packet structure */
  147. struct ump_interrupt {
  148. __u8 bICode; /* Interrupt code (interrupt num) */
  149. __u8 bIInfo; /* Interrupt information */
  150. } __attribute__((packed));
  151. #define TIUMP_GET_PORT_FROM_CODE(c) (((c) >> 6) & 0x01)
  152. #define TIUMP_GET_FUNC_FROM_CODE(c) ((c) & 0x0f)
  153. #define TIUMP_INTERRUPT_CODE_LSR 0x03
  154. #define TIUMP_INTERRUPT_CODE_MSR 0x04
  155. #endif