ili922x.c 14 KB

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  1. /*
  2. * (C) Copyright 2008
  3. * Stefano Babic, DENX Software Engineering, sbabic@denx.de.
  4. *
  5. * This program is free software; you can redistribute it and/or
  6. * modify it under the terms of the GNU General Public License as
  7. * published by the Free Software Foundation; either version 2 of
  8. * the License, or (at your option) any later version.
  9. *
  10. * This driver implements a lcd device for the ILITEK 922x display
  11. * controller. The interface to the display is SPI and the display's
  12. * memory is cyclically updated over the RGB interface.
  13. */
  14. #include <linux/fb.h>
  15. #include <linux/delay.h>
  16. #include <linux/errno.h>
  17. #include <linux/init.h>
  18. #include <linux/kernel.h>
  19. #include <linux/lcd.h>
  20. #include <linux/module.h>
  21. #include <linux/of.h>
  22. #include <linux/slab.h>
  23. #include <linux/spi/spi.h>
  24. #include <linux/string.h>
  25. /* Register offset, see manual section 8.2 */
  26. #define REG_START_OSCILLATION 0x00
  27. #define REG_DRIVER_CODE_READ 0x00
  28. #define REG_DRIVER_OUTPUT_CONTROL 0x01
  29. #define REG_LCD_AC_DRIVEING_CONTROL 0x02
  30. #define REG_ENTRY_MODE 0x03
  31. #define REG_COMPARE_1 0x04
  32. #define REG_COMPARE_2 0x05
  33. #define REG_DISPLAY_CONTROL_1 0x07
  34. #define REG_DISPLAY_CONTROL_2 0x08
  35. #define REG_DISPLAY_CONTROL_3 0x09
  36. #define REG_FRAME_CYCLE_CONTROL 0x0B
  37. #define REG_EXT_INTF_CONTROL 0x0C
  38. #define REG_POWER_CONTROL_1 0x10
  39. #define REG_POWER_CONTROL_2 0x11
  40. #define REG_POWER_CONTROL_3 0x12
  41. #define REG_POWER_CONTROL_4 0x13
  42. #define REG_RAM_ADDRESS_SET 0x21
  43. #define REG_WRITE_DATA_TO_GRAM 0x22
  44. #define REG_RAM_WRITE_MASK1 0x23
  45. #define REG_RAM_WRITE_MASK2 0x24
  46. #define REG_GAMMA_CONTROL_1 0x30
  47. #define REG_GAMMA_CONTROL_2 0x31
  48. #define REG_GAMMA_CONTROL_3 0x32
  49. #define REG_GAMMA_CONTROL_4 0x33
  50. #define REG_GAMMA_CONTROL_5 0x34
  51. #define REG_GAMMA_CONTROL_6 0x35
  52. #define REG_GAMMA_CONTROL_7 0x36
  53. #define REG_GAMMA_CONTROL_8 0x37
  54. #define REG_GAMMA_CONTROL_9 0x38
  55. #define REG_GAMMA_CONTROL_10 0x39
  56. #define REG_GATE_SCAN_CONTROL 0x40
  57. #define REG_VERT_SCROLL_CONTROL 0x41
  58. #define REG_FIRST_SCREEN_DRIVE_POS 0x42
  59. #define REG_SECOND_SCREEN_DRIVE_POS 0x43
  60. #define REG_RAM_ADDR_POS_H 0x44
  61. #define REG_RAM_ADDR_POS_V 0x45
  62. #define REG_OSCILLATOR_CONTROL 0x4F
  63. #define REG_GPIO 0x60
  64. #define REG_OTP_VCM_PROGRAMMING 0x61
  65. #define REG_OTP_VCM_STATUS_ENABLE 0x62
  66. #define REG_OTP_PROGRAMMING_ID_KEY 0x65
  67. /*
  68. * maximum frequency for register access
  69. * (not for the GRAM access)
  70. */
  71. #define ILITEK_MAX_FREQ_REG 4000000
  72. /*
  73. * Device ID as found in the datasheet (supports 9221 and 9222)
  74. */
  75. #define ILITEK_DEVICE_ID 0x9220
  76. #define ILITEK_DEVICE_ID_MASK 0xFFF0
  77. /* Last two bits in the START BYTE */
  78. #define START_RS_INDEX 0
  79. #define START_RS_REG 1
  80. #define START_RW_WRITE 0
  81. #define START_RW_READ 1
  82. /**
  83. * START_BYTE(id, rs, rw)
  84. *
  85. * Set the start byte according to the required operation.
  86. * The start byte is defined as:
  87. * ----------------------------------
  88. * | 0 | 1 | 1 | 1 | 0 | ID | RS | RW |
  89. * ----------------------------------
  90. * @id: display's id as set by the manufacturer
  91. * @rs: operation type bit, one of:
  92. * - START_RS_INDEX set the index register
  93. * - START_RS_REG write/read registers/GRAM
  94. * @rw: read/write operation
  95. * - START_RW_WRITE write
  96. * - START_RW_READ read
  97. */
  98. #define START_BYTE(id, rs, rw) \
  99. (0x70 | (((id) & 0x01) << 2) | (((rs) & 0x01) << 1) | ((rw) & 0x01))
  100. /**
  101. * CHECK_FREQ_REG(spi_device s, spi_transfer x) - Check the frequency
  102. * for the SPI transfer. According to the datasheet, the controller
  103. * accept higher frequency for the GRAM transfer, but it requires
  104. * lower frequency when the registers are read/written.
  105. * The macro sets the frequency in the spi_transfer structure if
  106. * the frequency exceeds the maximum value.
  107. */
  108. #define CHECK_FREQ_REG(s, x) \
  109. do { \
  110. if (s->max_speed_hz > ILITEK_MAX_FREQ_REG) \
  111. ((struct spi_transfer *)x)->speed_hz = \
  112. ILITEK_MAX_FREQ_REG; \
  113. } while (0)
  114. #define CMD_BUFSIZE 16
  115. #define POWER_IS_ON(pwr) ((pwr) <= FB_BLANK_NORMAL)
  116. #define set_tx_byte(b) (tx_invert ? ~(b) : b)
  117. /**
  118. * ili922x_id - id as set by manufacturer
  119. */
  120. static int ili922x_id = 1;
  121. module_param(ili922x_id, int, 0);
  122. static int tx_invert;
  123. module_param(tx_invert, int, 0);
  124. /**
  125. * driver's private structure
  126. */
  127. struct ili922x {
  128. struct spi_device *spi;
  129. struct lcd_device *ld;
  130. int power;
  131. };
  132. /**
  133. * ili922x_read_status - read status register from display
  134. * @spi: spi device
  135. * @rs: output value
  136. */
  137. static int ili922x_read_status(struct spi_device *spi, u16 *rs)
  138. {
  139. struct spi_message msg;
  140. struct spi_transfer xfer;
  141. unsigned char tbuf[CMD_BUFSIZE];
  142. unsigned char rbuf[CMD_BUFSIZE];
  143. int ret, i;
  144. memset(&xfer, 0, sizeof(struct spi_transfer));
  145. spi_message_init(&msg);
  146. xfer.tx_buf = tbuf;
  147. xfer.rx_buf = rbuf;
  148. xfer.cs_change = 1;
  149. CHECK_FREQ_REG(spi, &xfer);
  150. tbuf[0] = set_tx_byte(START_BYTE(ili922x_id, START_RS_INDEX,
  151. START_RW_READ));
  152. /*
  153. * we need 4-byte xfer here due to invalid dummy byte
  154. * received after start byte
  155. */
  156. for (i = 1; i < 4; i++)
  157. tbuf[i] = set_tx_byte(0); /* dummy */
  158. xfer.bits_per_word = 8;
  159. xfer.len = 4;
  160. spi_message_add_tail(&xfer, &msg);
  161. ret = spi_sync(spi, &msg);
  162. if (ret < 0) {
  163. dev_dbg(&spi->dev, "Error sending SPI message 0x%x", ret);
  164. return ret;
  165. }
  166. *rs = (rbuf[2] << 8) + rbuf[3];
  167. return 0;
  168. }
  169. /**
  170. * ili922x_read - read register from display
  171. * @spi: spi device
  172. * @reg: offset of the register to be read
  173. * @rx: output value
  174. */
  175. static int ili922x_read(struct spi_device *spi, u8 reg, u16 *rx)
  176. {
  177. struct spi_message msg;
  178. struct spi_transfer xfer_regindex, xfer_regvalue;
  179. unsigned char tbuf[CMD_BUFSIZE];
  180. unsigned char rbuf[CMD_BUFSIZE];
  181. int ret, len = 0, send_bytes;
  182. memset(&xfer_regindex, 0, sizeof(struct spi_transfer));
  183. memset(&xfer_regvalue, 0, sizeof(struct spi_transfer));
  184. spi_message_init(&msg);
  185. xfer_regindex.tx_buf = tbuf;
  186. xfer_regindex.rx_buf = rbuf;
  187. xfer_regindex.cs_change = 1;
  188. CHECK_FREQ_REG(spi, &xfer_regindex);
  189. tbuf[0] = set_tx_byte(START_BYTE(ili922x_id, START_RS_INDEX,
  190. START_RW_WRITE));
  191. tbuf[1] = set_tx_byte(0);
  192. tbuf[2] = set_tx_byte(reg);
  193. xfer_regindex.bits_per_word = 8;
  194. len = xfer_regindex.len = 3;
  195. spi_message_add_tail(&xfer_regindex, &msg);
  196. send_bytes = len;
  197. tbuf[len++] = set_tx_byte(START_BYTE(ili922x_id, START_RS_REG,
  198. START_RW_READ));
  199. tbuf[len++] = set_tx_byte(0);
  200. tbuf[len] = set_tx_byte(0);
  201. xfer_regvalue.cs_change = 1;
  202. xfer_regvalue.len = 3;
  203. xfer_regvalue.tx_buf = &tbuf[send_bytes];
  204. xfer_regvalue.rx_buf = &rbuf[send_bytes];
  205. CHECK_FREQ_REG(spi, &xfer_regvalue);
  206. spi_message_add_tail(&xfer_regvalue, &msg);
  207. ret = spi_sync(spi, &msg);
  208. if (ret < 0) {
  209. dev_dbg(&spi->dev, "Error sending SPI message 0x%x", ret);
  210. return ret;
  211. }
  212. *rx = (rbuf[1 + send_bytes] << 8) + rbuf[2 + send_bytes];
  213. return 0;
  214. }
  215. /**
  216. * ili922x_write - write a controller register
  217. * @spi: struct spi_device *
  218. * @reg: offset of the register to be written
  219. * @value: value to be written
  220. */
  221. static int ili922x_write(struct spi_device *spi, u8 reg, u16 value)
  222. {
  223. struct spi_message msg;
  224. struct spi_transfer xfer_regindex, xfer_regvalue;
  225. unsigned char tbuf[CMD_BUFSIZE];
  226. unsigned char rbuf[CMD_BUFSIZE];
  227. int ret, len = 0;
  228. memset(&xfer_regindex, 0, sizeof(struct spi_transfer));
  229. memset(&xfer_regvalue, 0, sizeof(struct spi_transfer));
  230. spi_message_init(&msg);
  231. xfer_regindex.tx_buf = tbuf;
  232. xfer_regindex.rx_buf = rbuf;
  233. xfer_regindex.cs_change = 1;
  234. CHECK_FREQ_REG(spi, &xfer_regindex);
  235. tbuf[0] = set_tx_byte(START_BYTE(ili922x_id, START_RS_INDEX,
  236. START_RW_WRITE));
  237. tbuf[1] = set_tx_byte(0);
  238. tbuf[2] = set_tx_byte(reg);
  239. xfer_regindex.bits_per_word = 8;
  240. xfer_regindex.len = 3;
  241. spi_message_add_tail(&xfer_regindex, &msg);
  242. ret = spi_sync(spi, &msg);
  243. spi_message_init(&msg);
  244. len = 0;
  245. tbuf[0] = set_tx_byte(START_BYTE(ili922x_id, START_RS_REG,
  246. START_RW_WRITE));
  247. tbuf[1] = set_tx_byte((value & 0xFF00) >> 8);
  248. tbuf[2] = set_tx_byte(value & 0x00FF);
  249. xfer_regvalue.cs_change = 1;
  250. xfer_regvalue.len = 3;
  251. xfer_regvalue.tx_buf = tbuf;
  252. xfer_regvalue.rx_buf = rbuf;
  253. CHECK_FREQ_REG(spi, &xfer_regvalue);
  254. spi_message_add_tail(&xfer_regvalue, &msg);
  255. ret = spi_sync(spi, &msg);
  256. if (ret < 0) {
  257. dev_err(&spi->dev, "Error sending SPI message 0x%x", ret);
  258. return ret;
  259. }
  260. return 0;
  261. }
  262. #ifdef DEBUG
  263. /**
  264. * ili922x_reg_dump - dump all registers
  265. */
  266. static void ili922x_reg_dump(struct spi_device *spi)
  267. {
  268. u8 reg;
  269. u16 rx;
  270. dev_dbg(&spi->dev, "ILI922x configuration registers:\n");
  271. for (reg = REG_START_OSCILLATION;
  272. reg <= REG_OTP_PROGRAMMING_ID_KEY; reg++) {
  273. ili922x_read(spi, reg, &rx);
  274. dev_dbg(&spi->dev, "reg @ 0x%02X: 0x%04X\n", reg, rx);
  275. }
  276. }
  277. #else
  278. static inline void ili922x_reg_dump(struct spi_device *spi) {}
  279. #endif
  280. /**
  281. * set_write_to_gram_reg - initialize the display to write the GRAM
  282. * @spi: spi device
  283. */
  284. static void set_write_to_gram_reg(struct spi_device *spi)
  285. {
  286. struct spi_message msg;
  287. struct spi_transfer xfer;
  288. unsigned char tbuf[CMD_BUFSIZE];
  289. memset(&xfer, 0, sizeof(struct spi_transfer));
  290. spi_message_init(&msg);
  291. xfer.tx_buf = tbuf;
  292. xfer.rx_buf = NULL;
  293. xfer.cs_change = 1;
  294. tbuf[0] = START_BYTE(ili922x_id, START_RS_INDEX, START_RW_WRITE);
  295. tbuf[1] = 0;
  296. tbuf[2] = REG_WRITE_DATA_TO_GRAM;
  297. xfer.bits_per_word = 8;
  298. xfer.len = 3;
  299. spi_message_add_tail(&xfer, &msg);
  300. spi_sync(spi, &msg);
  301. }
  302. /**
  303. * ili922x_poweron - turn the display on
  304. * @spi: spi device
  305. *
  306. * The sequence to turn on the display is taken from
  307. * the datasheet and/or the example code provided by the
  308. * manufacturer.
  309. */
  310. static int ili922x_poweron(struct spi_device *spi)
  311. {
  312. int ret;
  313. /* Power on */
  314. ret = ili922x_write(spi, REG_POWER_CONTROL_1, 0x0000);
  315. usleep_range(10000, 10500);
  316. ret += ili922x_write(spi, REG_POWER_CONTROL_2, 0x0000);
  317. ret += ili922x_write(spi, REG_POWER_CONTROL_3, 0x0000);
  318. msleep(40);
  319. ret += ili922x_write(spi, REG_POWER_CONTROL_4, 0x0000);
  320. msleep(40);
  321. /* register 0x56 is not documented in the datasheet */
  322. ret += ili922x_write(spi, 0x56, 0x080F);
  323. ret += ili922x_write(spi, REG_POWER_CONTROL_1, 0x4240);
  324. usleep_range(10000, 10500);
  325. ret += ili922x_write(spi, REG_POWER_CONTROL_2, 0x0000);
  326. ret += ili922x_write(spi, REG_POWER_CONTROL_3, 0x0014);
  327. msleep(40);
  328. ret += ili922x_write(spi, REG_POWER_CONTROL_4, 0x1319);
  329. msleep(40);
  330. return ret;
  331. }
  332. /**
  333. * ili922x_poweroff - turn the display off
  334. * @spi: spi device
  335. */
  336. static int ili922x_poweroff(struct spi_device *spi)
  337. {
  338. int ret;
  339. /* Power off */
  340. ret = ili922x_write(spi, REG_POWER_CONTROL_1, 0x0000);
  341. usleep_range(10000, 10500);
  342. ret += ili922x_write(spi, REG_POWER_CONTROL_2, 0x0000);
  343. ret += ili922x_write(spi, REG_POWER_CONTROL_3, 0x0000);
  344. msleep(40);
  345. ret += ili922x_write(spi, REG_POWER_CONTROL_4, 0x0000);
  346. msleep(40);
  347. return ret;
  348. }
  349. /**
  350. * ili922x_display_init - initialize the display by setting
  351. * the configuration registers
  352. * @spi: spi device
  353. */
  354. static void ili922x_display_init(struct spi_device *spi)
  355. {
  356. ili922x_write(spi, REG_START_OSCILLATION, 1);
  357. usleep_range(10000, 10500);
  358. ili922x_write(spi, REG_DRIVER_OUTPUT_CONTROL, 0x691B);
  359. ili922x_write(spi, REG_LCD_AC_DRIVEING_CONTROL, 0x0700);
  360. ili922x_write(spi, REG_ENTRY_MODE, 0x1030);
  361. ili922x_write(spi, REG_COMPARE_1, 0x0000);
  362. ili922x_write(spi, REG_COMPARE_2, 0x0000);
  363. ili922x_write(spi, REG_DISPLAY_CONTROL_1, 0x0037);
  364. ili922x_write(spi, REG_DISPLAY_CONTROL_2, 0x0202);
  365. ili922x_write(spi, REG_DISPLAY_CONTROL_3, 0x0000);
  366. ili922x_write(spi, REG_FRAME_CYCLE_CONTROL, 0x0000);
  367. /* Set RGB interface */
  368. ili922x_write(spi, REG_EXT_INTF_CONTROL, 0x0110);
  369. ili922x_poweron(spi);
  370. ili922x_write(spi, REG_GAMMA_CONTROL_1, 0x0302);
  371. ili922x_write(spi, REG_GAMMA_CONTROL_2, 0x0407);
  372. ili922x_write(spi, REG_GAMMA_CONTROL_3, 0x0304);
  373. ili922x_write(spi, REG_GAMMA_CONTROL_4, 0x0203);
  374. ili922x_write(spi, REG_GAMMA_CONTROL_5, 0x0706);
  375. ili922x_write(spi, REG_GAMMA_CONTROL_6, 0x0407);
  376. ili922x_write(spi, REG_GAMMA_CONTROL_7, 0x0706);
  377. ili922x_write(spi, REG_GAMMA_CONTROL_8, 0x0000);
  378. ili922x_write(spi, REG_GAMMA_CONTROL_9, 0x0C06);
  379. ili922x_write(spi, REG_GAMMA_CONTROL_10, 0x0F00);
  380. ili922x_write(spi, REG_RAM_ADDRESS_SET, 0x0000);
  381. ili922x_write(spi, REG_GATE_SCAN_CONTROL, 0x0000);
  382. ili922x_write(spi, REG_VERT_SCROLL_CONTROL, 0x0000);
  383. ili922x_write(spi, REG_FIRST_SCREEN_DRIVE_POS, 0xDB00);
  384. ili922x_write(spi, REG_SECOND_SCREEN_DRIVE_POS, 0xDB00);
  385. ili922x_write(spi, REG_RAM_ADDR_POS_H, 0xAF00);
  386. ili922x_write(spi, REG_RAM_ADDR_POS_V, 0xDB00);
  387. ili922x_reg_dump(spi);
  388. set_write_to_gram_reg(spi);
  389. }
  390. static int ili922x_lcd_power(struct ili922x *lcd, int power)
  391. {
  392. int ret = 0;
  393. if (POWER_IS_ON(power) && !POWER_IS_ON(lcd->power))
  394. ret = ili922x_poweron(lcd->spi);
  395. else if (!POWER_IS_ON(power) && POWER_IS_ON(lcd->power))
  396. ret = ili922x_poweroff(lcd->spi);
  397. if (!ret)
  398. lcd->power = power;
  399. return ret;
  400. }
  401. static int ili922x_set_power(struct lcd_device *ld, int power)
  402. {
  403. struct ili922x *ili = lcd_get_data(ld);
  404. return ili922x_lcd_power(ili, power);
  405. }
  406. static int ili922x_get_power(struct lcd_device *ld)
  407. {
  408. struct ili922x *ili = lcd_get_data(ld);
  409. return ili->power;
  410. }
  411. static struct lcd_ops ili922x_ops = {
  412. .get_power = ili922x_get_power,
  413. .set_power = ili922x_set_power,
  414. };
  415. static int ili922x_probe(struct spi_device *spi)
  416. {
  417. struct ili922x *ili;
  418. struct lcd_device *lcd;
  419. int ret;
  420. u16 reg = 0;
  421. ili = devm_kzalloc(&spi->dev, sizeof(*ili), GFP_KERNEL);
  422. if (!ili)
  423. return -ENOMEM;
  424. ili->spi = spi;
  425. spi_set_drvdata(spi, ili);
  426. /* check if the device is connected */
  427. ret = ili922x_read(spi, REG_DRIVER_CODE_READ, &reg);
  428. if (ret || ((reg & ILITEK_DEVICE_ID_MASK) != ILITEK_DEVICE_ID)) {
  429. dev_err(&spi->dev,
  430. "no LCD found: Chip ID 0x%x, ret %d\n",
  431. reg, ret);
  432. return -ENODEV;
  433. }
  434. dev_info(&spi->dev, "ILI%x found, SPI freq %d, mode %d\n",
  435. reg, spi->max_speed_hz, spi->mode);
  436. ret = ili922x_read_status(spi, &reg);
  437. if (ret) {
  438. dev_err(&spi->dev, "reading RS failed...\n");
  439. return ret;
  440. }
  441. dev_dbg(&spi->dev, "status: 0x%x\n", reg);
  442. ili922x_display_init(spi);
  443. ili->power = FB_BLANK_POWERDOWN;
  444. lcd = devm_lcd_device_register(&spi->dev, "ili922xlcd", &spi->dev, ili,
  445. &ili922x_ops);
  446. if (IS_ERR(lcd)) {
  447. dev_err(&spi->dev, "cannot register LCD\n");
  448. return PTR_ERR(lcd);
  449. }
  450. ili->ld = lcd;
  451. spi_set_drvdata(spi, ili);
  452. ili922x_lcd_power(ili, FB_BLANK_UNBLANK);
  453. return 0;
  454. }
  455. static int ili922x_remove(struct spi_device *spi)
  456. {
  457. ili922x_poweroff(spi);
  458. return 0;
  459. }
  460. static struct spi_driver ili922x_driver = {
  461. .driver = {
  462. .name = "ili922x",
  463. },
  464. .probe = ili922x_probe,
  465. .remove = ili922x_remove,
  466. };
  467. module_spi_driver(ili922x_driver);
  468. MODULE_AUTHOR("Stefano Babic <sbabic@denx.de>");
  469. MODULE_DESCRIPTION("ILI9221/9222 LCD driver");
  470. MODULE_LICENSE("GPL");
  471. MODULE_PARM_DESC(ili922x_id, "set controller identifier (default=1)");
  472. MODULE_PARM_DESC(tx_invert, "invert bytes before sending");