cg14.c 15 KB

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  1. /* cg14.c: CGFOURTEEN frame buffer driver
  2. *
  3. * Copyright (C) 2003, 2006 David S. Miller (davem@davemloft.net)
  4. * Copyright (C) 1996,1998 Jakub Jelinek (jj@ultra.linux.cz)
  5. * Copyright (C) 1995 Miguel de Icaza (miguel@nuclecu.unam.mx)
  6. *
  7. * Driver layout based loosely on tgafb.c, see that file for credits.
  8. */
  9. #include <linux/module.h>
  10. #include <linux/kernel.h>
  11. #include <linux/errno.h>
  12. #include <linux/string.h>
  13. #include <linux/delay.h>
  14. #include <linux/init.h>
  15. #include <linux/fb.h>
  16. #include <linux/mm.h>
  17. #include <linux/uaccess.h>
  18. #include <linux/of_device.h>
  19. #include <asm/io.h>
  20. #include <asm/fbio.h>
  21. #include "sbuslib.h"
  22. /*
  23. * Local functions.
  24. */
  25. static int cg14_setcolreg(unsigned, unsigned, unsigned, unsigned,
  26. unsigned, struct fb_info *);
  27. static int cg14_mmap(struct fb_info *, struct vm_area_struct *);
  28. static int cg14_ioctl(struct fb_info *, unsigned int, unsigned long);
  29. static int cg14_pan_display(struct fb_var_screeninfo *, struct fb_info *);
  30. /*
  31. * Frame buffer operations
  32. */
  33. static struct fb_ops cg14_ops = {
  34. .owner = THIS_MODULE,
  35. .fb_setcolreg = cg14_setcolreg,
  36. .fb_pan_display = cg14_pan_display,
  37. .fb_fillrect = cfb_fillrect,
  38. .fb_copyarea = cfb_copyarea,
  39. .fb_imageblit = cfb_imageblit,
  40. .fb_mmap = cg14_mmap,
  41. .fb_ioctl = cg14_ioctl,
  42. #ifdef CONFIG_COMPAT
  43. .fb_compat_ioctl = sbusfb_compat_ioctl,
  44. #endif
  45. };
  46. #define CG14_MCR_INTENABLE_SHIFT 7
  47. #define CG14_MCR_INTENABLE_MASK 0x80
  48. #define CG14_MCR_VIDENABLE_SHIFT 6
  49. #define CG14_MCR_VIDENABLE_MASK 0x40
  50. #define CG14_MCR_PIXMODE_SHIFT 4
  51. #define CG14_MCR_PIXMODE_MASK 0x30
  52. #define CG14_MCR_TMR_SHIFT 2
  53. #define CG14_MCR_TMR_MASK 0x0c
  54. #define CG14_MCR_TMENABLE_SHIFT 1
  55. #define CG14_MCR_TMENABLE_MASK 0x02
  56. #define CG14_MCR_RESET_SHIFT 0
  57. #define CG14_MCR_RESET_MASK 0x01
  58. #define CG14_REV_REVISION_SHIFT 4
  59. #define CG14_REV_REVISION_MASK 0xf0
  60. #define CG14_REV_IMPL_SHIFT 0
  61. #define CG14_REV_IMPL_MASK 0x0f
  62. #define CG14_VBR_FRAMEBASE_SHIFT 12
  63. #define CG14_VBR_FRAMEBASE_MASK 0x00fff000
  64. #define CG14_VMCR1_SETUP_SHIFT 0
  65. #define CG14_VMCR1_SETUP_MASK 0x000001ff
  66. #define CG14_VMCR1_VCONFIG_SHIFT 9
  67. #define CG14_VMCR1_VCONFIG_MASK 0x00000e00
  68. #define CG14_VMCR2_REFRESH_SHIFT 0
  69. #define CG14_VMCR2_REFRESH_MASK 0x00000001
  70. #define CG14_VMCR2_TESTROWCNT_SHIFT 1
  71. #define CG14_VMCR2_TESTROWCNT_MASK 0x00000002
  72. #define CG14_VMCR2_FBCONFIG_SHIFT 2
  73. #define CG14_VMCR2_FBCONFIG_MASK 0x0000000c
  74. #define CG14_VCR_REFRESHREQ_SHIFT 0
  75. #define CG14_VCR_REFRESHREQ_MASK 0x000003ff
  76. #define CG14_VCR1_REFRESHENA_SHIFT 10
  77. #define CG14_VCR1_REFRESHENA_MASK 0x00000400
  78. #define CG14_VCA_CAD_SHIFT 0
  79. #define CG14_VCA_CAD_MASK 0x000003ff
  80. #define CG14_VCA_VERS_SHIFT 10
  81. #define CG14_VCA_VERS_MASK 0x00000c00
  82. #define CG14_VCA_RAMSPEED_SHIFT 12
  83. #define CG14_VCA_RAMSPEED_MASK 0x00001000
  84. #define CG14_VCA_8MB_SHIFT 13
  85. #define CG14_VCA_8MB_MASK 0x00002000
  86. #define CG14_MCR_PIXMODE_8 0
  87. #define CG14_MCR_PIXMODE_16 2
  88. #define CG14_MCR_PIXMODE_32 3
  89. struct cg14_regs{
  90. u8 mcr; /* Master Control Reg */
  91. u8 ppr; /* Packed Pixel Reg */
  92. u8 tms[2]; /* Test Mode Status Regs */
  93. u8 msr; /* Master Status Reg */
  94. u8 fsr; /* Fault Status Reg */
  95. u8 rev; /* Revision & Impl */
  96. u8 ccr; /* Clock Control Reg */
  97. u32 tmr; /* Test Mode Read Back */
  98. u8 mod; /* Monitor Operation Data Reg */
  99. u8 acr; /* Aux Control */
  100. u8 xxx0[6];
  101. u16 hct; /* Hor Counter */
  102. u16 vct; /* Vert Counter */
  103. u16 hbs; /* Hor Blank Start */
  104. u16 hbc; /* Hor Blank Clear */
  105. u16 hss; /* Hor Sync Start */
  106. u16 hsc; /* Hor Sync Clear */
  107. u16 csc; /* Composite Sync Clear */
  108. u16 vbs; /* Vert Blank Start */
  109. u16 vbc; /* Vert Blank Clear */
  110. u16 vss; /* Vert Sync Start */
  111. u16 vsc; /* Vert Sync Clear */
  112. u16 xcs;
  113. u16 xcc;
  114. u16 fsa; /* Fault Status Address */
  115. u16 adr; /* Address Registers */
  116. u8 xxx1[0xce];
  117. u8 pcg[0x100]; /* Pixel Clock Generator */
  118. u32 vbr; /* Frame Base Row */
  119. u32 vmcr; /* VBC Master Control */
  120. u32 vcr; /* VBC refresh */
  121. u32 vca; /* VBC Config */
  122. };
  123. #define CG14_CCR_ENABLE 0x04
  124. #define CG14_CCR_SELECT 0x02 /* HW/Full screen */
  125. struct cg14_cursor {
  126. u32 cpl0[32]; /* Enable plane 0 */
  127. u32 cpl1[32]; /* Color selection plane */
  128. u8 ccr; /* Cursor Control Reg */
  129. u8 xxx0[3];
  130. u16 cursx; /* Cursor x,y position */
  131. u16 cursy; /* Cursor x,y position */
  132. u32 color0;
  133. u32 color1;
  134. u32 xxx1[0x1bc];
  135. u32 cpl0i[32]; /* Enable plane 0 autoinc */
  136. u32 cpl1i[32]; /* Color selection autoinc */
  137. };
  138. struct cg14_dac {
  139. u8 addr; /* Address Register */
  140. u8 xxx0[255];
  141. u8 glut; /* Gamma table */
  142. u8 xxx1[255];
  143. u8 select; /* Register Select */
  144. u8 xxx2[255];
  145. u8 mode; /* Mode Register */
  146. };
  147. struct cg14_xlut{
  148. u8 x_xlut [256];
  149. u8 x_xlutd [256];
  150. u8 xxx0[0x600];
  151. u8 x_xlut_inc [256];
  152. u8 x_xlutd_inc [256];
  153. };
  154. /* Color look up table (clut) */
  155. /* Each one of these arrays hold the color lookup table (for 256
  156. * colors) for each MDI page (I assume then there should be 4 MDI
  157. * pages, I still wonder what they are. I have seen NeXTStep split
  158. * the screen in four parts, while operating in 24 bits mode. Each
  159. * integer holds 4 values: alpha value (transparency channel, thanks
  160. * go to John Stone (johns@umr.edu) from OpenBSD), red, green and blue
  161. *
  162. * I currently use the clut instead of the Xlut
  163. */
  164. struct cg14_clut {
  165. u32 c_clut [256];
  166. u32 c_clutd [256]; /* i wonder what the 'd' is for */
  167. u32 c_clut_inc [256];
  168. u32 c_clutd_inc [256];
  169. };
  170. #define CG14_MMAP_ENTRIES 16
  171. struct cg14_par {
  172. spinlock_t lock;
  173. struct cg14_regs __iomem *regs;
  174. struct cg14_clut __iomem *clut;
  175. struct cg14_cursor __iomem *cursor;
  176. u32 flags;
  177. #define CG14_FLAG_BLANKED 0x00000001
  178. unsigned long iospace;
  179. struct sbus_mmap_map mmap_map[CG14_MMAP_ENTRIES];
  180. int mode;
  181. int ramsize;
  182. };
  183. static void __cg14_reset(struct cg14_par *par)
  184. {
  185. struct cg14_regs __iomem *regs = par->regs;
  186. u8 val;
  187. val = sbus_readb(&regs->mcr);
  188. val &= ~(CG14_MCR_PIXMODE_MASK);
  189. sbus_writeb(val, &regs->mcr);
  190. }
  191. static int cg14_pan_display(struct fb_var_screeninfo *var, struct fb_info *info)
  192. {
  193. struct cg14_par *par = (struct cg14_par *) info->par;
  194. unsigned long flags;
  195. /* We just use this to catch switches out of
  196. * graphics mode.
  197. */
  198. spin_lock_irqsave(&par->lock, flags);
  199. __cg14_reset(par);
  200. spin_unlock_irqrestore(&par->lock, flags);
  201. if (var->xoffset || var->yoffset || var->vmode)
  202. return -EINVAL;
  203. return 0;
  204. }
  205. /**
  206. * cg14_setcolreg - Optional function. Sets a color register.
  207. * @regno: boolean, 0 copy local, 1 get_user() function
  208. * @red: frame buffer colormap structure
  209. * @green: The green value which can be up to 16 bits wide
  210. * @blue: The blue value which can be up to 16 bits wide.
  211. * @transp: If supported the alpha value which can be up to 16 bits wide.
  212. * @info: frame buffer info structure
  213. */
  214. static int cg14_setcolreg(unsigned regno,
  215. unsigned red, unsigned green, unsigned blue,
  216. unsigned transp, struct fb_info *info)
  217. {
  218. struct cg14_par *par = (struct cg14_par *) info->par;
  219. struct cg14_clut __iomem *clut = par->clut;
  220. unsigned long flags;
  221. u32 val;
  222. if (regno >= 256)
  223. return 1;
  224. red >>= 8;
  225. green >>= 8;
  226. blue >>= 8;
  227. val = (red | (green << 8) | (blue << 16));
  228. spin_lock_irqsave(&par->lock, flags);
  229. sbus_writel(val, &clut->c_clut[regno]);
  230. spin_unlock_irqrestore(&par->lock, flags);
  231. return 0;
  232. }
  233. static int cg14_mmap(struct fb_info *info, struct vm_area_struct *vma)
  234. {
  235. struct cg14_par *par = (struct cg14_par *) info->par;
  236. return sbusfb_mmap_helper(par->mmap_map,
  237. info->fix.smem_start, info->fix.smem_len,
  238. par->iospace, vma);
  239. }
  240. static int cg14_ioctl(struct fb_info *info, unsigned int cmd, unsigned long arg)
  241. {
  242. struct cg14_par *par = (struct cg14_par *) info->par;
  243. struct cg14_regs __iomem *regs = par->regs;
  244. struct mdi_cfginfo kmdi, __user *mdii;
  245. unsigned long flags;
  246. int cur_mode, mode, ret = 0;
  247. switch (cmd) {
  248. case MDI_RESET:
  249. spin_lock_irqsave(&par->lock, flags);
  250. __cg14_reset(par);
  251. spin_unlock_irqrestore(&par->lock, flags);
  252. break;
  253. case MDI_GET_CFGINFO:
  254. memset(&kmdi, 0, sizeof(kmdi));
  255. spin_lock_irqsave(&par->lock, flags);
  256. kmdi.mdi_type = FBTYPE_MDICOLOR;
  257. kmdi.mdi_height = info->var.yres;
  258. kmdi.mdi_width = info->var.xres;
  259. kmdi.mdi_mode = par->mode;
  260. kmdi.mdi_pixfreq = 72; /* FIXME */
  261. kmdi.mdi_size = par->ramsize;
  262. spin_unlock_irqrestore(&par->lock, flags);
  263. mdii = (struct mdi_cfginfo __user *) arg;
  264. if (copy_to_user(mdii, &kmdi, sizeof(kmdi)))
  265. ret = -EFAULT;
  266. break;
  267. case MDI_SET_PIXELMODE:
  268. if (get_user(mode, (int __user *) arg)) {
  269. ret = -EFAULT;
  270. break;
  271. }
  272. spin_lock_irqsave(&par->lock, flags);
  273. cur_mode = sbus_readb(&regs->mcr);
  274. cur_mode &= ~CG14_MCR_PIXMODE_MASK;
  275. switch(mode) {
  276. case MDI_32_PIX:
  277. cur_mode |= (CG14_MCR_PIXMODE_32 <<
  278. CG14_MCR_PIXMODE_SHIFT);
  279. break;
  280. case MDI_16_PIX:
  281. cur_mode |= (CG14_MCR_PIXMODE_16 <<
  282. CG14_MCR_PIXMODE_SHIFT);
  283. break;
  284. case MDI_8_PIX:
  285. break;
  286. default:
  287. ret = -ENOSYS;
  288. break;
  289. }
  290. if (!ret) {
  291. sbus_writeb(cur_mode, &regs->mcr);
  292. par->mode = mode;
  293. }
  294. spin_unlock_irqrestore(&par->lock, flags);
  295. break;
  296. default:
  297. ret = sbusfb_ioctl_helper(cmd, arg, info,
  298. FBTYPE_MDICOLOR, 8,
  299. info->fix.smem_len);
  300. break;
  301. }
  302. return ret;
  303. }
  304. /*
  305. * Initialisation
  306. */
  307. static void cg14_init_fix(struct fb_info *info, int linebytes,
  308. struct device_node *dp)
  309. {
  310. const char *name = dp->name;
  311. strlcpy(info->fix.id, name, sizeof(info->fix.id));
  312. info->fix.type = FB_TYPE_PACKED_PIXELS;
  313. info->fix.visual = FB_VISUAL_PSEUDOCOLOR;
  314. info->fix.line_length = linebytes;
  315. info->fix.accel = FB_ACCEL_SUN_CG14;
  316. }
  317. static struct sbus_mmap_map __cg14_mmap_map[CG14_MMAP_ENTRIES] = {
  318. {
  319. .voff = CG14_REGS,
  320. .poff = 0x80000000,
  321. .size = 0x1000
  322. },
  323. {
  324. .voff = CG14_XLUT,
  325. .poff = 0x80003000,
  326. .size = 0x1000
  327. },
  328. {
  329. .voff = CG14_CLUT1,
  330. .poff = 0x80004000,
  331. .size = 0x1000
  332. },
  333. {
  334. .voff = CG14_CLUT2,
  335. .poff = 0x80005000,
  336. .size = 0x1000
  337. },
  338. {
  339. .voff = CG14_CLUT3,
  340. .poff = 0x80006000,
  341. .size = 0x1000
  342. },
  343. {
  344. .voff = CG3_MMAP_OFFSET - 0x7000,
  345. .poff = 0x80000000,
  346. .size = 0x7000
  347. },
  348. {
  349. .voff = CG3_MMAP_OFFSET,
  350. .poff = 0x00000000,
  351. .size = SBUS_MMAP_FBSIZE(1)
  352. },
  353. {
  354. .voff = MDI_CURSOR_MAP,
  355. .poff = 0x80001000,
  356. .size = 0x1000
  357. },
  358. {
  359. .voff = MDI_CHUNKY_BGR_MAP,
  360. .poff = 0x01000000,
  361. .size = 0x400000
  362. },
  363. {
  364. .voff = MDI_PLANAR_X16_MAP,
  365. .poff = 0x02000000,
  366. .size = 0x200000
  367. },
  368. {
  369. .voff = MDI_PLANAR_C16_MAP,
  370. .poff = 0x02800000,
  371. .size = 0x200000
  372. },
  373. {
  374. .voff = MDI_PLANAR_X32_MAP,
  375. .poff = 0x03000000,
  376. .size = 0x100000
  377. },
  378. {
  379. .voff = MDI_PLANAR_B32_MAP,
  380. .poff = 0x03400000,
  381. .size = 0x100000
  382. },
  383. {
  384. .voff = MDI_PLANAR_G32_MAP,
  385. .poff = 0x03800000,
  386. .size = 0x100000
  387. },
  388. {
  389. .voff = MDI_PLANAR_R32_MAP,
  390. .poff = 0x03c00000,
  391. .size = 0x100000
  392. },
  393. { .size = 0 }
  394. };
  395. static void cg14_unmap_regs(struct platform_device *op, struct fb_info *info,
  396. struct cg14_par *par)
  397. {
  398. if (par->regs)
  399. of_iounmap(&op->resource[0],
  400. par->regs, sizeof(struct cg14_regs));
  401. if (par->clut)
  402. of_iounmap(&op->resource[0],
  403. par->clut, sizeof(struct cg14_clut));
  404. if (par->cursor)
  405. of_iounmap(&op->resource[0],
  406. par->cursor, sizeof(struct cg14_cursor));
  407. if (info->screen_base)
  408. of_iounmap(&op->resource[1],
  409. info->screen_base, info->fix.smem_len);
  410. }
  411. static int cg14_probe(struct platform_device *op)
  412. {
  413. struct device_node *dp = op->dev.of_node;
  414. struct fb_info *info;
  415. struct cg14_par *par;
  416. int is_8mb, linebytes, i, err;
  417. info = framebuffer_alloc(sizeof(struct cg14_par), &op->dev);
  418. err = -ENOMEM;
  419. if (!info)
  420. goto out_err;
  421. par = info->par;
  422. spin_lock_init(&par->lock);
  423. sbusfb_fill_var(&info->var, dp, 8);
  424. info->var.red.length = 8;
  425. info->var.green.length = 8;
  426. info->var.blue.length = 8;
  427. linebytes = of_getintprop_default(dp, "linebytes",
  428. info->var.xres);
  429. info->fix.smem_len = PAGE_ALIGN(linebytes * info->var.yres);
  430. if (!strcmp(dp->parent->name, "sbus") ||
  431. !strcmp(dp->parent->name, "sbi")) {
  432. info->fix.smem_start = op->resource[0].start;
  433. par->iospace = op->resource[0].flags & IORESOURCE_BITS;
  434. } else {
  435. info->fix.smem_start = op->resource[1].start;
  436. par->iospace = op->resource[0].flags & IORESOURCE_BITS;
  437. }
  438. par->regs = of_ioremap(&op->resource[0], 0,
  439. sizeof(struct cg14_regs), "cg14 regs");
  440. par->clut = of_ioremap(&op->resource[0], CG14_CLUT1,
  441. sizeof(struct cg14_clut), "cg14 clut");
  442. par->cursor = of_ioremap(&op->resource[0], CG14_CURSORREGS,
  443. sizeof(struct cg14_cursor), "cg14 cursor");
  444. info->screen_base = of_ioremap(&op->resource[1], 0,
  445. info->fix.smem_len, "cg14 ram");
  446. if (!par->regs || !par->clut || !par->cursor || !info->screen_base)
  447. goto out_unmap_regs;
  448. is_8mb = (((op->resource[1].end - op->resource[1].start) + 1) ==
  449. (8 * 1024 * 1024));
  450. BUILD_BUG_ON(sizeof(par->mmap_map) != sizeof(__cg14_mmap_map));
  451. memcpy(&par->mmap_map, &__cg14_mmap_map, sizeof(par->mmap_map));
  452. for (i = 0; i < CG14_MMAP_ENTRIES; i++) {
  453. struct sbus_mmap_map *map = &par->mmap_map[i];
  454. if (!map->size)
  455. break;
  456. if (map->poff & 0x80000000)
  457. map->poff = (map->poff & 0x7fffffff) +
  458. (op->resource[0].start -
  459. op->resource[1].start);
  460. if (is_8mb &&
  461. map->size >= 0x100000 &&
  462. map->size <= 0x400000)
  463. map->size *= 2;
  464. }
  465. par->mode = MDI_8_PIX;
  466. par->ramsize = (is_8mb ? 0x800000 : 0x400000);
  467. info->flags = FBINFO_DEFAULT | FBINFO_HWACCEL_YPAN;
  468. info->fbops = &cg14_ops;
  469. __cg14_reset(par);
  470. if (fb_alloc_cmap(&info->cmap, 256, 0))
  471. goto out_unmap_regs;
  472. fb_set_cmap(&info->cmap, info);
  473. cg14_init_fix(info, linebytes, dp);
  474. err = register_framebuffer(info);
  475. if (err < 0)
  476. goto out_dealloc_cmap;
  477. dev_set_drvdata(&op->dev, info);
  478. printk(KERN_INFO "%s: cgfourteen at %lx:%lx, %dMB\n",
  479. dp->full_name,
  480. par->iospace, info->fix.smem_start,
  481. par->ramsize >> 20);
  482. return 0;
  483. out_dealloc_cmap:
  484. fb_dealloc_cmap(&info->cmap);
  485. out_unmap_regs:
  486. cg14_unmap_regs(op, info, par);
  487. framebuffer_release(info);
  488. out_err:
  489. return err;
  490. }
  491. static int cg14_remove(struct platform_device *op)
  492. {
  493. struct fb_info *info = dev_get_drvdata(&op->dev);
  494. struct cg14_par *par = info->par;
  495. unregister_framebuffer(info);
  496. fb_dealloc_cmap(&info->cmap);
  497. cg14_unmap_regs(op, info, par);
  498. framebuffer_release(info);
  499. return 0;
  500. }
  501. static const struct of_device_id cg14_match[] = {
  502. {
  503. .name = "cgfourteen",
  504. },
  505. {},
  506. };
  507. MODULE_DEVICE_TABLE(of, cg14_match);
  508. static struct platform_driver cg14_driver = {
  509. .driver = {
  510. .name = "cg14",
  511. .of_match_table = cg14_match,
  512. },
  513. .probe = cg14_probe,
  514. .remove = cg14_remove,
  515. };
  516. static int __init cg14_init(void)
  517. {
  518. if (fb_get_options("cg14fb", NULL))
  519. return -ENODEV;
  520. return platform_driver_register(&cg14_driver);
  521. }
  522. static void __exit cg14_exit(void)
  523. {
  524. platform_driver_unregister(&cg14_driver);
  525. }
  526. module_init(cg14_init);
  527. module_exit(cg14_exit);
  528. MODULE_DESCRIPTION("framebuffer driver for CGfourteen chipsets");
  529. MODULE_AUTHOR("David S. Miller <davem@davemloft.net>");
  530. MODULE_VERSION("2.0");
  531. MODULE_LICENSE("GPL");