hdmi5.c 18 KB

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  1. /*
  2. * HDMI driver for OMAP5
  3. *
  4. * Copyright (C) 2014 Texas Instruments Incorporated
  5. *
  6. * Authors:
  7. * Yong Zhi
  8. * Mythri pk
  9. * Archit Taneja <archit@ti.com>
  10. * Tomi Valkeinen <tomi.valkeinen@ti.com>
  11. *
  12. * This program is free software; you can redistribute it and/or modify it
  13. * under the terms of the GNU General Public License version 2 as published by
  14. * the Free Software Foundation.
  15. *
  16. * This program is distributed in the hope that it will be useful, but WITHOUT
  17. * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  18. * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
  19. * more details.
  20. *
  21. * You should have received a copy of the GNU General Public License along with
  22. * this program. If not, see <http://www.gnu.org/licenses/>.
  23. */
  24. #define DSS_SUBSYS_NAME "HDMI"
  25. #include <linux/kernel.h>
  26. #include <linux/module.h>
  27. #include <linux/err.h>
  28. #include <linux/io.h>
  29. #include <linux/interrupt.h>
  30. #include <linux/mutex.h>
  31. #include <linux/delay.h>
  32. #include <linux/string.h>
  33. #include <linux/platform_device.h>
  34. #include <linux/pm_runtime.h>
  35. #include <linux/clk.h>
  36. #include <linux/gpio.h>
  37. #include <linux/regulator/consumer.h>
  38. #include <linux/component.h>
  39. #include <video/omapdss.h>
  40. #include <sound/omap-hdmi-audio.h>
  41. #include "hdmi5_core.h"
  42. #include "dss.h"
  43. #include "dss_features.h"
  44. static struct omap_hdmi hdmi;
  45. static int hdmi_runtime_get(void)
  46. {
  47. int r;
  48. DSSDBG("hdmi_runtime_get\n");
  49. r = pm_runtime_get_sync(&hdmi.pdev->dev);
  50. WARN_ON(r < 0);
  51. if (r < 0)
  52. return r;
  53. return 0;
  54. }
  55. static void hdmi_runtime_put(void)
  56. {
  57. int r;
  58. DSSDBG("hdmi_runtime_put\n");
  59. r = pm_runtime_put_sync(&hdmi.pdev->dev);
  60. WARN_ON(r < 0 && r != -ENOSYS);
  61. }
  62. static irqreturn_t hdmi_irq_handler(int irq, void *data)
  63. {
  64. struct hdmi_wp_data *wp = data;
  65. u32 irqstatus;
  66. irqstatus = hdmi_wp_get_irqstatus(wp);
  67. hdmi_wp_set_irqstatus(wp, irqstatus);
  68. if ((irqstatus & HDMI_IRQ_LINK_CONNECT) &&
  69. irqstatus & HDMI_IRQ_LINK_DISCONNECT) {
  70. u32 v;
  71. /*
  72. * If we get both connect and disconnect interrupts at the same
  73. * time, turn off the PHY, clear interrupts, and restart, which
  74. * raises connect interrupt if a cable is connected, or nothing
  75. * if cable is not connected.
  76. */
  77. hdmi_wp_set_phy_pwr(wp, HDMI_PHYPWRCMD_OFF);
  78. /*
  79. * We always get bogus CONNECT & DISCONNECT interrupts when
  80. * setting the PHY to LDOON. To ignore those, we force the RXDET
  81. * line to 0 until the PHY power state has been changed.
  82. */
  83. v = hdmi_read_reg(hdmi.phy.base, HDMI_TXPHY_PAD_CFG_CTRL);
  84. v = FLD_MOD(v, 1, 15, 15); /* FORCE_RXDET_HIGH */
  85. v = FLD_MOD(v, 0, 14, 7); /* RXDET_LINE */
  86. hdmi_write_reg(hdmi.phy.base, HDMI_TXPHY_PAD_CFG_CTRL, v);
  87. hdmi_wp_set_irqstatus(wp, HDMI_IRQ_LINK_CONNECT |
  88. HDMI_IRQ_LINK_DISCONNECT);
  89. hdmi_wp_set_phy_pwr(wp, HDMI_PHYPWRCMD_LDOON);
  90. REG_FLD_MOD(hdmi.phy.base, HDMI_TXPHY_PAD_CFG_CTRL, 0, 15, 15);
  91. } else if (irqstatus & HDMI_IRQ_LINK_CONNECT) {
  92. hdmi_wp_set_phy_pwr(wp, HDMI_PHYPWRCMD_TXON);
  93. } else if (irqstatus & HDMI_IRQ_LINK_DISCONNECT) {
  94. hdmi_wp_set_phy_pwr(wp, HDMI_PHYPWRCMD_LDOON);
  95. }
  96. return IRQ_HANDLED;
  97. }
  98. static int hdmi_init_regulator(void)
  99. {
  100. int r;
  101. struct regulator *reg;
  102. if (hdmi.vdda_reg != NULL)
  103. return 0;
  104. reg = devm_regulator_get(&hdmi.pdev->dev, "vdda");
  105. if (IS_ERR(reg)) {
  106. DSSERR("can't get VDDA regulator\n");
  107. return PTR_ERR(reg);
  108. }
  109. if (regulator_can_change_voltage(reg)) {
  110. r = regulator_set_voltage(reg, 1800000, 1800000);
  111. if (r) {
  112. devm_regulator_put(reg);
  113. DSSWARN("can't set the regulator voltage\n");
  114. return r;
  115. }
  116. }
  117. hdmi.vdda_reg = reg;
  118. return 0;
  119. }
  120. static int hdmi_power_on_core(struct omap_dss_device *dssdev)
  121. {
  122. int r;
  123. r = regulator_enable(hdmi.vdda_reg);
  124. if (r)
  125. return r;
  126. r = hdmi_runtime_get();
  127. if (r)
  128. goto err_runtime_get;
  129. /* Make selection of HDMI in DSS */
  130. dss_select_hdmi_venc_clk_source(DSS_HDMI_M_PCLK);
  131. hdmi.core_enabled = true;
  132. return 0;
  133. err_runtime_get:
  134. regulator_disable(hdmi.vdda_reg);
  135. return r;
  136. }
  137. static void hdmi_power_off_core(struct omap_dss_device *dssdev)
  138. {
  139. hdmi.core_enabled = false;
  140. hdmi_runtime_put();
  141. regulator_disable(hdmi.vdda_reg);
  142. }
  143. static int hdmi_power_on_full(struct omap_dss_device *dssdev)
  144. {
  145. int r;
  146. struct omap_video_timings *p;
  147. struct omap_overlay_manager *mgr = hdmi.output.manager;
  148. struct dss_pll_clock_info hdmi_cinfo = { 0 };
  149. r = hdmi_power_on_core(dssdev);
  150. if (r)
  151. return r;
  152. p = &hdmi.cfg.timings;
  153. DSSDBG("hdmi_power_on x_res= %d y_res = %d\n", p->x_res, p->y_res);
  154. hdmi_pll_compute(&hdmi.pll, p->pixelclock, &hdmi_cinfo);
  155. /* disable and clear irqs */
  156. hdmi_wp_clear_irqenable(&hdmi.wp, 0xffffffff);
  157. hdmi_wp_set_irqstatus(&hdmi.wp,
  158. hdmi_wp_get_irqstatus(&hdmi.wp));
  159. r = dss_pll_enable(&hdmi.pll.pll);
  160. if (r) {
  161. DSSERR("Failed to enable PLL\n");
  162. goto err_pll_enable;
  163. }
  164. r = dss_pll_set_config(&hdmi.pll.pll, &hdmi_cinfo);
  165. if (r) {
  166. DSSERR("Failed to configure PLL\n");
  167. goto err_pll_cfg;
  168. }
  169. r = hdmi_phy_configure(&hdmi.phy, hdmi_cinfo.clkdco,
  170. hdmi_cinfo.clkout[0]);
  171. if (r) {
  172. DSSDBG("Failed to start PHY\n");
  173. goto err_phy_cfg;
  174. }
  175. r = hdmi_wp_set_phy_pwr(&hdmi.wp, HDMI_PHYPWRCMD_LDOON);
  176. if (r)
  177. goto err_phy_pwr;
  178. hdmi5_configure(&hdmi.core, &hdmi.wp, &hdmi.cfg);
  179. /* bypass TV gamma table */
  180. dispc_enable_gamma_table(0);
  181. /* tv size */
  182. dss_mgr_set_timings(mgr, p);
  183. r = hdmi_wp_video_start(&hdmi.wp);
  184. if (r)
  185. goto err_vid_enable;
  186. r = dss_mgr_enable(mgr);
  187. if (r)
  188. goto err_mgr_enable;
  189. hdmi_wp_set_irqenable(&hdmi.wp,
  190. HDMI_IRQ_LINK_CONNECT | HDMI_IRQ_LINK_DISCONNECT);
  191. return 0;
  192. err_mgr_enable:
  193. hdmi_wp_video_stop(&hdmi.wp);
  194. err_vid_enable:
  195. hdmi_wp_set_phy_pwr(&hdmi.wp, HDMI_PHYPWRCMD_OFF);
  196. err_phy_pwr:
  197. err_phy_cfg:
  198. err_pll_cfg:
  199. dss_pll_disable(&hdmi.pll.pll);
  200. err_pll_enable:
  201. hdmi_power_off_core(dssdev);
  202. return -EIO;
  203. }
  204. static void hdmi_power_off_full(struct omap_dss_device *dssdev)
  205. {
  206. struct omap_overlay_manager *mgr = hdmi.output.manager;
  207. hdmi_wp_clear_irqenable(&hdmi.wp, 0xffffffff);
  208. dss_mgr_disable(mgr);
  209. hdmi_wp_video_stop(&hdmi.wp);
  210. hdmi_wp_set_phy_pwr(&hdmi.wp, HDMI_PHYPWRCMD_OFF);
  211. dss_pll_disable(&hdmi.pll.pll);
  212. hdmi_power_off_core(dssdev);
  213. }
  214. static int hdmi_display_check_timing(struct omap_dss_device *dssdev,
  215. struct omap_video_timings *timings)
  216. {
  217. struct omap_dss_device *out = &hdmi.output;
  218. /* TODO: proper interlace support */
  219. if (timings->interlace)
  220. return -EINVAL;
  221. if (!dispc_mgr_timings_ok(out->dispc_channel, timings))
  222. return -EINVAL;
  223. return 0;
  224. }
  225. static void hdmi_display_set_timing(struct omap_dss_device *dssdev,
  226. struct omap_video_timings *timings)
  227. {
  228. mutex_lock(&hdmi.lock);
  229. hdmi.cfg.timings = *timings;
  230. dispc_set_tv_pclk(timings->pixelclock);
  231. mutex_unlock(&hdmi.lock);
  232. }
  233. static void hdmi_display_get_timings(struct omap_dss_device *dssdev,
  234. struct omap_video_timings *timings)
  235. {
  236. *timings = hdmi.cfg.timings;
  237. }
  238. static void hdmi_dump_regs(struct seq_file *s)
  239. {
  240. mutex_lock(&hdmi.lock);
  241. if (hdmi_runtime_get()) {
  242. mutex_unlock(&hdmi.lock);
  243. return;
  244. }
  245. hdmi_wp_dump(&hdmi.wp, s);
  246. hdmi_pll_dump(&hdmi.pll, s);
  247. hdmi_phy_dump(&hdmi.phy, s);
  248. hdmi5_core_dump(&hdmi.core, s);
  249. hdmi_runtime_put();
  250. mutex_unlock(&hdmi.lock);
  251. }
  252. static int read_edid(u8 *buf, int len)
  253. {
  254. int r;
  255. int idlemode;
  256. mutex_lock(&hdmi.lock);
  257. r = hdmi_runtime_get();
  258. BUG_ON(r);
  259. idlemode = REG_GET(hdmi.wp.base, HDMI_WP_SYSCONFIG, 3, 2);
  260. /* No-idle mode */
  261. REG_FLD_MOD(hdmi.wp.base, HDMI_WP_SYSCONFIG, 1, 3, 2);
  262. r = hdmi5_read_edid(&hdmi.core, buf, len);
  263. REG_FLD_MOD(hdmi.wp.base, HDMI_WP_SYSCONFIG, idlemode, 3, 2);
  264. hdmi_runtime_put();
  265. mutex_unlock(&hdmi.lock);
  266. return r;
  267. }
  268. static void hdmi_start_audio_stream(struct omap_hdmi *hd)
  269. {
  270. REG_FLD_MOD(hdmi.wp.base, HDMI_WP_SYSCONFIG, 1, 3, 2);
  271. hdmi_wp_audio_enable(&hd->wp, true);
  272. hdmi_wp_audio_core_req_enable(&hd->wp, true);
  273. }
  274. static void hdmi_stop_audio_stream(struct omap_hdmi *hd)
  275. {
  276. hdmi_wp_audio_core_req_enable(&hd->wp, false);
  277. hdmi_wp_audio_enable(&hd->wp, false);
  278. REG_FLD_MOD(hd->wp.base, HDMI_WP_SYSCONFIG, hd->wp_idlemode, 3, 2);
  279. }
  280. static int hdmi_display_enable(struct omap_dss_device *dssdev)
  281. {
  282. struct omap_dss_device *out = &hdmi.output;
  283. unsigned long flags;
  284. int r = 0;
  285. DSSDBG("ENTER hdmi_display_enable\n");
  286. mutex_lock(&hdmi.lock);
  287. if (out == NULL || out->manager == NULL) {
  288. DSSERR("failed to enable display: no output/manager\n");
  289. r = -ENODEV;
  290. goto err0;
  291. }
  292. r = hdmi_power_on_full(dssdev);
  293. if (r) {
  294. DSSERR("failed to power on device\n");
  295. goto err0;
  296. }
  297. if (hdmi.audio_configured) {
  298. r = hdmi5_audio_config(&hdmi.core, &hdmi.wp, &hdmi.audio_config,
  299. hdmi.cfg.timings.pixelclock);
  300. if (r) {
  301. DSSERR("Error restoring audio configuration: %d", r);
  302. hdmi.audio_abort_cb(&hdmi.pdev->dev);
  303. hdmi.audio_configured = false;
  304. }
  305. }
  306. spin_lock_irqsave(&hdmi.audio_playing_lock, flags);
  307. if (hdmi.audio_configured && hdmi.audio_playing)
  308. hdmi_start_audio_stream(&hdmi);
  309. hdmi.display_enabled = true;
  310. spin_unlock_irqrestore(&hdmi.audio_playing_lock, flags);
  311. mutex_unlock(&hdmi.lock);
  312. return 0;
  313. err0:
  314. mutex_unlock(&hdmi.lock);
  315. return r;
  316. }
  317. static void hdmi_display_disable(struct omap_dss_device *dssdev)
  318. {
  319. unsigned long flags;
  320. DSSDBG("Enter hdmi_display_disable\n");
  321. mutex_lock(&hdmi.lock);
  322. spin_lock_irqsave(&hdmi.audio_playing_lock, flags);
  323. hdmi_stop_audio_stream(&hdmi);
  324. hdmi.display_enabled = false;
  325. spin_unlock_irqrestore(&hdmi.audio_playing_lock, flags);
  326. hdmi_power_off_full(dssdev);
  327. mutex_unlock(&hdmi.lock);
  328. }
  329. static int hdmi_core_enable(struct omap_dss_device *dssdev)
  330. {
  331. int r = 0;
  332. DSSDBG("ENTER omapdss_hdmi_core_enable\n");
  333. mutex_lock(&hdmi.lock);
  334. r = hdmi_power_on_core(dssdev);
  335. if (r) {
  336. DSSERR("failed to power on device\n");
  337. goto err0;
  338. }
  339. mutex_unlock(&hdmi.lock);
  340. return 0;
  341. err0:
  342. mutex_unlock(&hdmi.lock);
  343. return r;
  344. }
  345. static void hdmi_core_disable(struct omap_dss_device *dssdev)
  346. {
  347. DSSDBG("Enter omapdss_hdmi_core_disable\n");
  348. mutex_lock(&hdmi.lock);
  349. hdmi_power_off_core(dssdev);
  350. mutex_unlock(&hdmi.lock);
  351. }
  352. static int hdmi_connect(struct omap_dss_device *dssdev,
  353. struct omap_dss_device *dst)
  354. {
  355. struct omap_overlay_manager *mgr;
  356. int r;
  357. r = hdmi_init_regulator();
  358. if (r)
  359. return r;
  360. mgr = omap_dss_get_overlay_manager(dssdev->dispc_channel);
  361. if (!mgr)
  362. return -ENODEV;
  363. r = dss_mgr_connect(mgr, dssdev);
  364. if (r)
  365. return r;
  366. r = omapdss_output_set_device(dssdev, dst);
  367. if (r) {
  368. DSSERR("failed to connect output to new device: %s\n",
  369. dst->name);
  370. dss_mgr_disconnect(mgr, dssdev);
  371. return r;
  372. }
  373. return 0;
  374. }
  375. static void hdmi_disconnect(struct omap_dss_device *dssdev,
  376. struct omap_dss_device *dst)
  377. {
  378. WARN_ON(dst != dssdev->dst);
  379. if (dst != dssdev->dst)
  380. return;
  381. omapdss_output_unset_device(dssdev);
  382. if (dssdev->manager)
  383. dss_mgr_disconnect(dssdev->manager, dssdev);
  384. }
  385. static int hdmi_read_edid(struct omap_dss_device *dssdev,
  386. u8 *edid, int len)
  387. {
  388. bool need_enable;
  389. int r;
  390. need_enable = hdmi.core_enabled == false;
  391. if (need_enable) {
  392. r = hdmi_core_enable(dssdev);
  393. if (r)
  394. return r;
  395. }
  396. r = read_edid(edid, len);
  397. if (need_enable)
  398. hdmi_core_disable(dssdev);
  399. return r;
  400. }
  401. static int hdmi_set_infoframe(struct omap_dss_device *dssdev,
  402. const struct hdmi_avi_infoframe *avi)
  403. {
  404. hdmi.cfg.infoframe = *avi;
  405. return 0;
  406. }
  407. static int hdmi_set_hdmi_mode(struct omap_dss_device *dssdev,
  408. bool hdmi_mode)
  409. {
  410. hdmi.cfg.hdmi_dvi_mode = hdmi_mode ? HDMI_HDMI : HDMI_DVI;
  411. return 0;
  412. }
  413. static const struct omapdss_hdmi_ops hdmi_ops = {
  414. .connect = hdmi_connect,
  415. .disconnect = hdmi_disconnect,
  416. .enable = hdmi_display_enable,
  417. .disable = hdmi_display_disable,
  418. .check_timings = hdmi_display_check_timing,
  419. .set_timings = hdmi_display_set_timing,
  420. .get_timings = hdmi_display_get_timings,
  421. .read_edid = hdmi_read_edid,
  422. .set_infoframe = hdmi_set_infoframe,
  423. .set_hdmi_mode = hdmi_set_hdmi_mode,
  424. };
  425. static void hdmi_init_output(struct platform_device *pdev)
  426. {
  427. struct omap_dss_device *out = &hdmi.output;
  428. out->dev = &pdev->dev;
  429. out->id = OMAP_DSS_OUTPUT_HDMI;
  430. out->output_type = OMAP_DISPLAY_TYPE_HDMI;
  431. out->name = "hdmi.0";
  432. out->dispc_channel = OMAP_DSS_CHANNEL_DIGIT;
  433. out->ops.hdmi = &hdmi_ops;
  434. out->owner = THIS_MODULE;
  435. omapdss_register_output(out);
  436. }
  437. static void hdmi_uninit_output(struct platform_device *pdev)
  438. {
  439. struct omap_dss_device *out = &hdmi.output;
  440. omapdss_unregister_output(out);
  441. }
  442. static int hdmi_probe_of(struct platform_device *pdev)
  443. {
  444. struct device_node *node = pdev->dev.of_node;
  445. struct device_node *ep;
  446. int r;
  447. ep = omapdss_of_get_first_endpoint(node);
  448. if (!ep)
  449. return 0;
  450. r = hdmi_parse_lanes_of(pdev, ep, &hdmi.phy);
  451. if (r)
  452. goto err;
  453. of_node_put(ep);
  454. return 0;
  455. err:
  456. of_node_put(ep);
  457. return r;
  458. }
  459. /* Audio callbacks */
  460. static int hdmi_audio_startup(struct device *dev,
  461. void (*abort_cb)(struct device *dev))
  462. {
  463. struct omap_hdmi *hd = dev_get_drvdata(dev);
  464. int ret = 0;
  465. mutex_lock(&hd->lock);
  466. if (!hdmi_mode_has_audio(&hd->cfg) || !hd->display_enabled) {
  467. ret = -EPERM;
  468. goto out;
  469. }
  470. hd->audio_abort_cb = abort_cb;
  471. out:
  472. mutex_unlock(&hd->lock);
  473. return ret;
  474. }
  475. static int hdmi_audio_shutdown(struct device *dev)
  476. {
  477. struct omap_hdmi *hd = dev_get_drvdata(dev);
  478. mutex_lock(&hd->lock);
  479. hd->audio_abort_cb = NULL;
  480. hd->audio_configured = false;
  481. hd->audio_playing = false;
  482. mutex_unlock(&hd->lock);
  483. return 0;
  484. }
  485. static int hdmi_audio_start(struct device *dev)
  486. {
  487. struct omap_hdmi *hd = dev_get_drvdata(dev);
  488. unsigned long flags;
  489. WARN_ON(!hdmi_mode_has_audio(&hd->cfg));
  490. spin_lock_irqsave(&hd->audio_playing_lock, flags);
  491. if (hd->display_enabled)
  492. hdmi_start_audio_stream(hd);
  493. hd->audio_playing = true;
  494. spin_unlock_irqrestore(&hd->audio_playing_lock, flags);
  495. return 0;
  496. }
  497. static void hdmi_audio_stop(struct device *dev)
  498. {
  499. struct omap_hdmi *hd = dev_get_drvdata(dev);
  500. unsigned long flags;
  501. WARN_ON(!hdmi_mode_has_audio(&hd->cfg));
  502. spin_lock_irqsave(&hd->audio_playing_lock, flags);
  503. if (hd->display_enabled)
  504. hdmi_stop_audio_stream(hd);
  505. hd->audio_playing = false;
  506. spin_unlock_irqrestore(&hd->audio_playing_lock, flags);
  507. }
  508. static int hdmi_audio_config(struct device *dev,
  509. struct omap_dss_audio *dss_audio)
  510. {
  511. struct omap_hdmi *hd = dev_get_drvdata(dev);
  512. int ret;
  513. mutex_lock(&hd->lock);
  514. if (!hdmi_mode_has_audio(&hd->cfg) || !hd->display_enabled) {
  515. ret = -EPERM;
  516. goto out;
  517. }
  518. ret = hdmi5_audio_config(&hd->core, &hd->wp, dss_audio,
  519. hd->cfg.timings.pixelclock);
  520. if (!ret) {
  521. hd->audio_configured = true;
  522. hd->audio_config = *dss_audio;
  523. }
  524. out:
  525. mutex_unlock(&hd->lock);
  526. return ret;
  527. }
  528. static const struct omap_hdmi_audio_ops hdmi_audio_ops = {
  529. .audio_startup = hdmi_audio_startup,
  530. .audio_shutdown = hdmi_audio_shutdown,
  531. .audio_start = hdmi_audio_start,
  532. .audio_stop = hdmi_audio_stop,
  533. .audio_config = hdmi_audio_config,
  534. };
  535. static int hdmi_audio_register(struct device *dev)
  536. {
  537. struct omap_hdmi_audio_pdata pdata = {
  538. .dev = dev,
  539. .dss_version = omapdss_get_version(),
  540. .audio_dma_addr = hdmi_wp_get_audio_dma_addr(&hdmi.wp),
  541. .ops = &hdmi_audio_ops,
  542. };
  543. hdmi.audio_pdev = platform_device_register_data(
  544. dev, "omap-hdmi-audio", PLATFORM_DEVID_AUTO,
  545. &pdata, sizeof(pdata));
  546. if (IS_ERR(hdmi.audio_pdev))
  547. return PTR_ERR(hdmi.audio_pdev);
  548. hdmi_runtime_get();
  549. hdmi.wp_idlemode =
  550. REG_GET(hdmi.wp.base, HDMI_WP_SYSCONFIG, 3, 2);
  551. hdmi_runtime_put();
  552. return 0;
  553. }
  554. /* HDMI HW IP initialisation */
  555. static int hdmi5_bind(struct device *dev, struct device *master, void *data)
  556. {
  557. struct platform_device *pdev = to_platform_device(dev);
  558. int r;
  559. int irq;
  560. hdmi.pdev = pdev;
  561. dev_set_drvdata(&pdev->dev, &hdmi);
  562. mutex_init(&hdmi.lock);
  563. spin_lock_init(&hdmi.audio_playing_lock);
  564. if (pdev->dev.of_node) {
  565. r = hdmi_probe_of(pdev);
  566. if (r)
  567. return r;
  568. }
  569. r = hdmi_wp_init(pdev, &hdmi.wp);
  570. if (r)
  571. return r;
  572. r = hdmi_pll_init(pdev, &hdmi.pll, &hdmi.wp);
  573. if (r)
  574. return r;
  575. r = hdmi_phy_init(pdev, &hdmi.phy);
  576. if (r)
  577. goto err;
  578. r = hdmi5_core_init(pdev, &hdmi.core);
  579. if (r)
  580. goto err;
  581. irq = platform_get_irq(pdev, 0);
  582. if (irq < 0) {
  583. DSSERR("platform_get_irq failed\n");
  584. r = -ENODEV;
  585. goto err;
  586. }
  587. r = devm_request_threaded_irq(&pdev->dev, irq,
  588. NULL, hdmi_irq_handler,
  589. IRQF_ONESHOT, "OMAP HDMI", &hdmi.wp);
  590. if (r) {
  591. DSSERR("HDMI IRQ request failed\n");
  592. goto err;
  593. }
  594. pm_runtime_enable(&pdev->dev);
  595. hdmi_init_output(pdev);
  596. r = hdmi_audio_register(&pdev->dev);
  597. if (r) {
  598. DSSERR("Registering HDMI audio failed %d\n", r);
  599. hdmi_uninit_output(pdev);
  600. pm_runtime_disable(&pdev->dev);
  601. return r;
  602. }
  603. dss_debugfs_create_file("hdmi", hdmi_dump_regs);
  604. return 0;
  605. err:
  606. hdmi_pll_uninit(&hdmi.pll);
  607. return r;
  608. }
  609. static void hdmi5_unbind(struct device *dev, struct device *master, void *data)
  610. {
  611. struct platform_device *pdev = to_platform_device(dev);
  612. if (hdmi.audio_pdev)
  613. platform_device_unregister(hdmi.audio_pdev);
  614. hdmi_uninit_output(pdev);
  615. hdmi_pll_uninit(&hdmi.pll);
  616. pm_runtime_disable(&pdev->dev);
  617. }
  618. static const struct component_ops hdmi5_component_ops = {
  619. .bind = hdmi5_bind,
  620. .unbind = hdmi5_unbind,
  621. };
  622. static int hdmi5_probe(struct platform_device *pdev)
  623. {
  624. return component_add(&pdev->dev, &hdmi5_component_ops);
  625. }
  626. static int hdmi5_remove(struct platform_device *pdev)
  627. {
  628. component_del(&pdev->dev, &hdmi5_component_ops);
  629. return 0;
  630. }
  631. static int hdmi_runtime_suspend(struct device *dev)
  632. {
  633. dispc_runtime_put();
  634. return 0;
  635. }
  636. static int hdmi_runtime_resume(struct device *dev)
  637. {
  638. int r;
  639. r = dispc_runtime_get();
  640. if (r < 0)
  641. return r;
  642. return 0;
  643. }
  644. static const struct dev_pm_ops hdmi_pm_ops = {
  645. .runtime_suspend = hdmi_runtime_suspend,
  646. .runtime_resume = hdmi_runtime_resume,
  647. };
  648. static const struct of_device_id hdmi_of_match[] = {
  649. { .compatible = "ti,omap5-hdmi", },
  650. { .compatible = "ti,dra7-hdmi", },
  651. {},
  652. };
  653. static struct platform_driver omapdss_hdmihw_driver = {
  654. .probe = hdmi5_probe,
  655. .remove = hdmi5_remove,
  656. .driver = {
  657. .name = "omapdss_hdmi5",
  658. .pm = &hdmi_pm_ops,
  659. .of_match_table = hdmi_of_match,
  660. .suppress_bind_attrs = true,
  661. },
  662. };
  663. int __init hdmi5_init_platform_driver(void)
  664. {
  665. return platform_driver_register(&omapdss_hdmihw_driver);
  666. }
  667. void hdmi5_uninit_platform_driver(void)
  668. {
  669. platform_driver_unregister(&omapdss_hdmihw_driver);
  670. }