pm2fb.c 49 KB

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  1. /*
  2. * Permedia2 framebuffer driver.
  3. *
  4. * 2.5/2.6 driver:
  5. * Copyright (c) 2003 Jim Hague (jim.hague@acm.org)
  6. *
  7. * based on 2.4 driver:
  8. * Copyright (c) 1998-2000 Ilario Nardinocchi (nardinoc@CS.UniBO.IT)
  9. * Copyright (c) 1999 Jakub Jelinek (jakub@redhat.com)
  10. *
  11. * and additional input from James Simmon's port of Hannu Mallat's tdfx
  12. * driver.
  13. *
  14. * I have a Creative Graphics Blaster Exxtreme card - pm2fb on x86. I
  15. * have no access to other pm2fb implementations. Sparc (and thus
  16. * hopefully other big-endian) devices now work, thanks to a lot of
  17. * testing work by Ron Murray. I have no access to CVision hardware,
  18. * and therefore for now I am omitting the CVision code.
  19. *
  20. * Multiple boards support has been on the TODO list for ages.
  21. * Don't expect this to change.
  22. *
  23. * This file is subject to the terms and conditions of the GNU General Public
  24. * License. See the file COPYING in the main directory of this archive for
  25. * more details.
  26. *
  27. *
  28. */
  29. #include <linux/module.h>
  30. #include <linux/moduleparam.h>
  31. #include <linux/kernel.h>
  32. #include <linux/errno.h>
  33. #include <linux/string.h>
  34. #include <linux/mm.h>
  35. #include <linux/slab.h>
  36. #include <linux/delay.h>
  37. #include <linux/fb.h>
  38. #include <linux/init.h>
  39. #include <linux/pci.h>
  40. #include <video/permedia2.h>
  41. #include <video/cvisionppc.h>
  42. #if !defined(__LITTLE_ENDIAN) && !defined(__BIG_ENDIAN)
  43. #error "The endianness of the target host has not been defined."
  44. #endif
  45. #if !defined(CONFIG_PCI)
  46. #error "Only generic PCI cards supported."
  47. #endif
  48. #undef PM2FB_MASTER_DEBUG
  49. #ifdef PM2FB_MASTER_DEBUG
  50. #define DPRINTK(a, b...) \
  51. printk(KERN_DEBUG "pm2fb: %s: " a, __func__ , ## b)
  52. #else
  53. #define DPRINTK(a, b...)
  54. #endif
  55. #define PM2_PIXMAP_SIZE (1600 * 4)
  56. /*
  57. * Driver data
  58. */
  59. static int hwcursor = 1;
  60. static char *mode_option;
  61. /*
  62. * The XFree GLINT driver will (I think to implement hardware cursor
  63. * support on TVP4010 and similar where there is no RAMDAC - see
  64. * comment in set_video) always request +ve sync regardless of what
  65. * the mode requires. This screws me because I have a Sun
  66. * fixed-frequency monitor which absolutely has to have -ve sync. So
  67. * these flags allow the user to specify that requests for +ve sync
  68. * should be silently turned in -ve sync.
  69. */
  70. static bool lowhsync;
  71. static bool lowvsync;
  72. static bool noaccel;
  73. static bool nomtrr;
  74. /*
  75. * The hardware state of the graphics card that isn't part of the
  76. * screeninfo.
  77. */
  78. struct pm2fb_par
  79. {
  80. pm2type_t type; /* Board type */
  81. unsigned char __iomem *v_regs;/* virtual address of p_regs */
  82. u32 memclock; /* memclock */
  83. u32 video; /* video flags before blanking */
  84. u32 mem_config; /* MemConfig reg at probe */
  85. u32 mem_control; /* MemControl reg at probe */
  86. u32 boot_address; /* BootAddress reg at probe */
  87. u32 palette[16];
  88. int wc_cookie;
  89. };
  90. /*
  91. * Here we define the default structs fb_fix_screeninfo and fb_var_screeninfo
  92. * if we don't use modedb.
  93. */
  94. static struct fb_fix_screeninfo pm2fb_fix = {
  95. .id = "",
  96. .type = FB_TYPE_PACKED_PIXELS,
  97. .visual = FB_VISUAL_PSEUDOCOLOR,
  98. .xpanstep = 1,
  99. .ypanstep = 1,
  100. .ywrapstep = 0,
  101. .accel = FB_ACCEL_3DLABS_PERMEDIA2,
  102. };
  103. /*
  104. * Default video mode. In case the modedb doesn't work.
  105. */
  106. static struct fb_var_screeninfo pm2fb_var = {
  107. /* "640x480, 8 bpp @ 60 Hz */
  108. .xres = 640,
  109. .yres = 480,
  110. .xres_virtual = 640,
  111. .yres_virtual = 480,
  112. .bits_per_pixel = 8,
  113. .red = {0, 8, 0},
  114. .blue = {0, 8, 0},
  115. .green = {0, 8, 0},
  116. .activate = FB_ACTIVATE_NOW,
  117. .height = -1,
  118. .width = -1,
  119. .accel_flags = 0,
  120. .pixclock = 39721,
  121. .left_margin = 40,
  122. .right_margin = 24,
  123. .upper_margin = 32,
  124. .lower_margin = 11,
  125. .hsync_len = 96,
  126. .vsync_len = 2,
  127. .vmode = FB_VMODE_NONINTERLACED
  128. };
  129. /*
  130. * Utility functions
  131. */
  132. static inline u32 pm2_RD(struct pm2fb_par *p, s32 off)
  133. {
  134. return fb_readl(p->v_regs + off);
  135. }
  136. static inline void pm2_WR(struct pm2fb_par *p, s32 off, u32 v)
  137. {
  138. fb_writel(v, p->v_regs + off);
  139. }
  140. static inline u32 pm2_RDAC_RD(struct pm2fb_par *p, s32 idx)
  141. {
  142. pm2_WR(p, PM2R_RD_PALETTE_WRITE_ADDRESS, idx);
  143. mb();
  144. return pm2_RD(p, PM2R_RD_INDEXED_DATA);
  145. }
  146. static inline u32 pm2v_RDAC_RD(struct pm2fb_par *p, s32 idx)
  147. {
  148. pm2_WR(p, PM2VR_RD_INDEX_LOW, idx & 0xff);
  149. mb();
  150. return pm2_RD(p, PM2VR_RD_INDEXED_DATA);
  151. }
  152. static inline void pm2_RDAC_WR(struct pm2fb_par *p, s32 idx, u32 v)
  153. {
  154. pm2_WR(p, PM2R_RD_PALETTE_WRITE_ADDRESS, idx);
  155. wmb();
  156. pm2_WR(p, PM2R_RD_INDEXED_DATA, v);
  157. wmb();
  158. }
  159. static inline void pm2v_RDAC_WR(struct pm2fb_par *p, s32 idx, u32 v)
  160. {
  161. pm2_WR(p, PM2VR_RD_INDEX_LOW, idx & 0xff);
  162. wmb();
  163. pm2_WR(p, PM2VR_RD_INDEXED_DATA, v);
  164. wmb();
  165. }
  166. #ifdef CONFIG_FB_PM2_FIFO_DISCONNECT
  167. #define WAIT_FIFO(p, a)
  168. #else
  169. static inline void WAIT_FIFO(struct pm2fb_par *p, u32 a)
  170. {
  171. while (pm2_RD(p, PM2R_IN_FIFO_SPACE) < a)
  172. cpu_relax();
  173. }
  174. #endif
  175. /*
  176. * partial products for the supported horizontal resolutions.
  177. */
  178. #define PACKPP(p0, p1, p2) (((p2) << 6) | ((p1) << 3) | (p0))
  179. static const struct {
  180. u16 width;
  181. u16 pp;
  182. } pp_table[] = {
  183. { 32, PACKPP(1, 0, 0) }, { 64, PACKPP(1, 1, 0) },
  184. { 96, PACKPP(1, 1, 1) }, { 128, PACKPP(2, 1, 1) },
  185. { 160, PACKPP(2, 2, 1) }, { 192, PACKPP(2, 2, 2) },
  186. { 224, PACKPP(3, 2, 1) }, { 256, PACKPP(3, 2, 2) },
  187. { 288, PACKPP(3, 3, 1) }, { 320, PACKPP(3, 3, 2) },
  188. { 384, PACKPP(3, 3, 3) }, { 416, PACKPP(4, 3, 1) },
  189. { 448, PACKPP(4, 3, 2) }, { 512, PACKPP(4, 3, 3) },
  190. { 544, PACKPP(4, 4, 1) }, { 576, PACKPP(4, 4, 2) },
  191. { 640, PACKPP(4, 4, 3) }, { 768, PACKPP(4, 4, 4) },
  192. { 800, PACKPP(5, 4, 1) }, { 832, PACKPP(5, 4, 2) },
  193. { 896, PACKPP(5, 4, 3) }, { 1024, PACKPP(5, 4, 4) },
  194. { 1056, PACKPP(5, 5, 1) }, { 1088, PACKPP(5, 5, 2) },
  195. { 1152, PACKPP(5, 5, 3) }, { 1280, PACKPP(5, 5, 4) },
  196. { 1536, PACKPP(5, 5, 5) }, { 1568, PACKPP(6, 5, 1) },
  197. { 1600, PACKPP(6, 5, 2) }, { 1664, PACKPP(6, 5, 3) },
  198. { 1792, PACKPP(6, 5, 4) }, { 2048, PACKPP(6, 5, 5) },
  199. { 0, 0 } };
  200. static u32 partprod(u32 xres)
  201. {
  202. int i;
  203. for (i = 0; pp_table[i].width && pp_table[i].width != xres; i++)
  204. ;
  205. if (pp_table[i].width == 0)
  206. DPRINTK("invalid width %u\n", xres);
  207. return pp_table[i].pp;
  208. }
  209. static u32 to3264(u32 timing, int bpp, int is64)
  210. {
  211. switch (bpp) {
  212. case 24:
  213. timing *= 3;
  214. case 8:
  215. timing >>= 1;
  216. case 16:
  217. timing >>= 1;
  218. case 32:
  219. break;
  220. }
  221. if (is64)
  222. timing >>= 1;
  223. return timing;
  224. }
  225. static void pm2_mnp(u32 clk, unsigned char *mm, unsigned char *nn,
  226. unsigned char *pp)
  227. {
  228. unsigned char m;
  229. unsigned char n;
  230. unsigned char p;
  231. u32 f;
  232. s32 curr;
  233. s32 delta = 100000;
  234. *mm = *nn = *pp = 0;
  235. for (n = 2; n < 15; n++) {
  236. for (m = 2; m; m++) {
  237. f = PM2_REFERENCE_CLOCK * m / n;
  238. if (f >= 150000 && f <= 300000) {
  239. for (p = 0; p < 5; p++, f >>= 1) {
  240. curr = (clk > f) ? clk - f : f - clk;
  241. if (curr < delta) {
  242. delta = curr;
  243. *mm = m;
  244. *nn = n;
  245. *pp = p;
  246. }
  247. }
  248. }
  249. }
  250. }
  251. }
  252. static void pm2v_mnp(u32 clk, unsigned char *mm, unsigned char *nn,
  253. unsigned char *pp)
  254. {
  255. unsigned char m;
  256. unsigned char n;
  257. unsigned char p;
  258. u32 f;
  259. s32 delta = 1000;
  260. *mm = *nn = *pp = 0;
  261. for (m = 1; m < 128; m++) {
  262. for (n = 2 * m + 1; n; n++) {
  263. for (p = 0; p < 2; p++) {
  264. f = (PM2_REFERENCE_CLOCK >> (p + 1)) * n / m;
  265. if (clk > f - delta && clk < f + delta) {
  266. delta = (clk > f) ? clk - f : f - clk;
  267. *mm = m;
  268. *nn = n;
  269. *pp = p;
  270. }
  271. }
  272. }
  273. }
  274. }
  275. static void clear_palette(struct pm2fb_par *p)
  276. {
  277. int i = 256;
  278. WAIT_FIFO(p, 1);
  279. pm2_WR(p, PM2R_RD_PALETTE_WRITE_ADDRESS, 0);
  280. wmb();
  281. while (i--) {
  282. WAIT_FIFO(p, 3);
  283. pm2_WR(p, PM2R_RD_PALETTE_DATA, 0);
  284. pm2_WR(p, PM2R_RD_PALETTE_DATA, 0);
  285. pm2_WR(p, PM2R_RD_PALETTE_DATA, 0);
  286. }
  287. }
  288. static void reset_card(struct pm2fb_par *p)
  289. {
  290. if (p->type == PM2_TYPE_PERMEDIA2V)
  291. pm2_WR(p, PM2VR_RD_INDEX_HIGH, 0);
  292. pm2_WR(p, PM2R_RESET_STATUS, 0);
  293. mb();
  294. while (pm2_RD(p, PM2R_RESET_STATUS) & PM2F_BEING_RESET)
  295. cpu_relax();
  296. mb();
  297. #ifdef CONFIG_FB_PM2_FIFO_DISCONNECT
  298. DPRINTK("FIFO disconnect enabled\n");
  299. pm2_WR(p, PM2R_FIFO_DISCON, 1);
  300. mb();
  301. #endif
  302. /* Restore stashed memory config information from probe */
  303. WAIT_FIFO(p, 3);
  304. pm2_WR(p, PM2R_MEM_CONTROL, p->mem_control);
  305. pm2_WR(p, PM2R_BOOT_ADDRESS, p->boot_address);
  306. wmb();
  307. pm2_WR(p, PM2R_MEM_CONFIG, p->mem_config);
  308. }
  309. static void reset_config(struct pm2fb_par *p)
  310. {
  311. WAIT_FIFO(p, 53);
  312. pm2_WR(p, PM2R_CHIP_CONFIG, pm2_RD(p, PM2R_CHIP_CONFIG) &
  313. ~(PM2F_VGA_ENABLE | PM2F_VGA_FIXED));
  314. pm2_WR(p, PM2R_BYPASS_WRITE_MASK, ~(0L));
  315. pm2_WR(p, PM2R_FRAMEBUFFER_WRITE_MASK, ~(0L));
  316. pm2_WR(p, PM2R_FIFO_CONTROL, 0);
  317. pm2_WR(p, PM2R_APERTURE_ONE, 0);
  318. pm2_WR(p, PM2R_APERTURE_TWO, 0);
  319. pm2_WR(p, PM2R_RASTERIZER_MODE, 0);
  320. pm2_WR(p, PM2R_DELTA_MODE, PM2F_DELTA_ORDER_RGB);
  321. pm2_WR(p, PM2R_LB_READ_FORMAT, 0);
  322. pm2_WR(p, PM2R_LB_WRITE_FORMAT, 0);
  323. pm2_WR(p, PM2R_LB_READ_MODE, 0);
  324. pm2_WR(p, PM2R_LB_SOURCE_OFFSET, 0);
  325. pm2_WR(p, PM2R_FB_SOURCE_OFFSET, 0);
  326. pm2_WR(p, PM2R_FB_PIXEL_OFFSET, 0);
  327. pm2_WR(p, PM2R_FB_WINDOW_BASE, 0);
  328. pm2_WR(p, PM2R_LB_WINDOW_BASE, 0);
  329. pm2_WR(p, PM2R_FB_SOFT_WRITE_MASK, ~(0L));
  330. pm2_WR(p, PM2R_FB_HARD_WRITE_MASK, ~(0L));
  331. pm2_WR(p, PM2R_FB_READ_PIXEL, 0);
  332. pm2_WR(p, PM2R_DITHER_MODE, 0);
  333. pm2_WR(p, PM2R_AREA_STIPPLE_MODE, 0);
  334. pm2_WR(p, PM2R_DEPTH_MODE, 0);
  335. pm2_WR(p, PM2R_STENCIL_MODE, 0);
  336. pm2_WR(p, PM2R_TEXTURE_ADDRESS_MODE, 0);
  337. pm2_WR(p, PM2R_TEXTURE_READ_MODE, 0);
  338. pm2_WR(p, PM2R_TEXEL_LUT_MODE, 0);
  339. pm2_WR(p, PM2R_YUV_MODE, 0);
  340. pm2_WR(p, PM2R_COLOR_DDA_MODE, 0);
  341. pm2_WR(p, PM2R_TEXTURE_COLOR_MODE, 0);
  342. pm2_WR(p, PM2R_FOG_MODE, 0);
  343. pm2_WR(p, PM2R_ALPHA_BLEND_MODE, 0);
  344. pm2_WR(p, PM2R_LOGICAL_OP_MODE, 0);
  345. pm2_WR(p, PM2R_STATISTICS_MODE, 0);
  346. pm2_WR(p, PM2R_SCISSOR_MODE, 0);
  347. pm2_WR(p, PM2R_FILTER_MODE, PM2F_SYNCHRONIZATION);
  348. pm2_WR(p, PM2R_RD_PIXEL_MASK, 0xff);
  349. switch (p->type) {
  350. case PM2_TYPE_PERMEDIA2:
  351. pm2_RDAC_WR(p, PM2I_RD_MODE_CONTROL, 0); /* no overlay */
  352. pm2_RDAC_WR(p, PM2I_RD_CURSOR_CONTROL, 0);
  353. pm2_RDAC_WR(p, PM2I_RD_MISC_CONTROL, PM2F_RD_PALETTE_WIDTH_8);
  354. pm2_RDAC_WR(p, PM2I_RD_COLOR_KEY_CONTROL, 0);
  355. pm2_RDAC_WR(p, PM2I_RD_OVERLAY_KEY, 0);
  356. pm2_RDAC_WR(p, PM2I_RD_RED_KEY, 0);
  357. pm2_RDAC_WR(p, PM2I_RD_GREEN_KEY, 0);
  358. pm2_RDAC_WR(p, PM2I_RD_BLUE_KEY, 0);
  359. break;
  360. case PM2_TYPE_PERMEDIA2V:
  361. pm2v_RDAC_WR(p, PM2VI_RD_MISC_CONTROL, 1); /* 8bit */
  362. break;
  363. }
  364. }
  365. static void set_aperture(struct pm2fb_par *p, u32 depth)
  366. {
  367. /*
  368. * The hardware is little-endian. When used in big-endian
  369. * hosts, the on-chip aperture settings are used where
  370. * possible to translate from host to card byte order.
  371. */
  372. WAIT_FIFO(p, 2);
  373. #ifdef __LITTLE_ENDIAN
  374. pm2_WR(p, PM2R_APERTURE_ONE, PM2F_APERTURE_STANDARD);
  375. #else
  376. switch (depth) {
  377. case 24: /* RGB->BGR */
  378. /*
  379. * We can't use the aperture to translate host to
  380. * card byte order here, so we switch to BGR mode
  381. * in pm2fb_set_par().
  382. */
  383. case 8: /* B->B */
  384. pm2_WR(p, PM2R_APERTURE_ONE, PM2F_APERTURE_STANDARD);
  385. break;
  386. case 16: /* HL->LH */
  387. pm2_WR(p, PM2R_APERTURE_ONE, PM2F_APERTURE_HALFWORDSWAP);
  388. break;
  389. case 32: /* RGBA->ABGR */
  390. pm2_WR(p, PM2R_APERTURE_ONE, PM2F_APERTURE_BYTESWAP);
  391. break;
  392. }
  393. #endif
  394. /* We don't use aperture two, so this may be superflous */
  395. pm2_WR(p, PM2R_APERTURE_TWO, PM2F_APERTURE_STANDARD);
  396. }
  397. static void set_color(struct pm2fb_par *p, unsigned char regno,
  398. unsigned char r, unsigned char g, unsigned char b)
  399. {
  400. WAIT_FIFO(p, 4);
  401. pm2_WR(p, PM2R_RD_PALETTE_WRITE_ADDRESS, regno);
  402. wmb();
  403. pm2_WR(p, PM2R_RD_PALETTE_DATA, r);
  404. wmb();
  405. pm2_WR(p, PM2R_RD_PALETTE_DATA, g);
  406. wmb();
  407. pm2_WR(p, PM2R_RD_PALETTE_DATA, b);
  408. }
  409. static void set_memclock(struct pm2fb_par *par, u32 clk)
  410. {
  411. int i;
  412. unsigned char m, n, p;
  413. switch (par->type) {
  414. case PM2_TYPE_PERMEDIA2V:
  415. pm2v_mnp(clk/2, &m, &n, &p);
  416. WAIT_FIFO(par, 12);
  417. pm2_WR(par, PM2VR_RD_INDEX_HIGH, PM2VI_RD_MCLK_CONTROL >> 8);
  418. pm2v_RDAC_WR(par, PM2VI_RD_MCLK_CONTROL, 0);
  419. pm2v_RDAC_WR(par, PM2VI_RD_MCLK_PRESCALE, m);
  420. pm2v_RDAC_WR(par, PM2VI_RD_MCLK_FEEDBACK, n);
  421. pm2v_RDAC_WR(par, PM2VI_RD_MCLK_POSTSCALE, p);
  422. pm2v_RDAC_WR(par, PM2VI_RD_MCLK_CONTROL, 1);
  423. rmb();
  424. for (i = 256; i; i--)
  425. if (pm2v_RDAC_RD(par, PM2VI_RD_MCLK_CONTROL) & 2)
  426. break;
  427. pm2_WR(par, PM2VR_RD_INDEX_HIGH, 0);
  428. break;
  429. case PM2_TYPE_PERMEDIA2:
  430. pm2_mnp(clk, &m, &n, &p);
  431. WAIT_FIFO(par, 10);
  432. pm2_RDAC_WR(par, PM2I_RD_MEMORY_CLOCK_3, 6);
  433. pm2_RDAC_WR(par, PM2I_RD_MEMORY_CLOCK_1, m);
  434. pm2_RDAC_WR(par, PM2I_RD_MEMORY_CLOCK_2, n);
  435. pm2_RDAC_WR(par, PM2I_RD_MEMORY_CLOCK_3, 8|p);
  436. pm2_RDAC_RD(par, PM2I_RD_MEMORY_CLOCK_STATUS);
  437. rmb();
  438. for (i = 256; i; i--)
  439. if (pm2_RD(par, PM2R_RD_INDEXED_DATA) & PM2F_PLL_LOCKED)
  440. break;
  441. break;
  442. }
  443. }
  444. static void set_pixclock(struct pm2fb_par *par, u32 clk)
  445. {
  446. int i;
  447. unsigned char m, n, p;
  448. switch (par->type) {
  449. case PM2_TYPE_PERMEDIA2:
  450. pm2_mnp(clk, &m, &n, &p);
  451. WAIT_FIFO(par, 10);
  452. pm2_RDAC_WR(par, PM2I_RD_PIXEL_CLOCK_A3, 0);
  453. pm2_RDAC_WR(par, PM2I_RD_PIXEL_CLOCK_A1, m);
  454. pm2_RDAC_WR(par, PM2I_RD_PIXEL_CLOCK_A2, n);
  455. pm2_RDAC_WR(par, PM2I_RD_PIXEL_CLOCK_A3, 8|p);
  456. pm2_RDAC_RD(par, PM2I_RD_PIXEL_CLOCK_STATUS);
  457. rmb();
  458. for (i = 256; i; i--)
  459. if (pm2_RD(par, PM2R_RD_INDEXED_DATA) & PM2F_PLL_LOCKED)
  460. break;
  461. break;
  462. case PM2_TYPE_PERMEDIA2V:
  463. pm2v_mnp(clk/2, &m, &n, &p);
  464. WAIT_FIFO(par, 8);
  465. pm2_WR(par, PM2VR_RD_INDEX_HIGH, PM2VI_RD_CLK0_PRESCALE >> 8);
  466. pm2v_RDAC_WR(par, PM2VI_RD_CLK0_PRESCALE, m);
  467. pm2v_RDAC_WR(par, PM2VI_RD_CLK0_FEEDBACK, n);
  468. pm2v_RDAC_WR(par, PM2VI_RD_CLK0_POSTSCALE, p);
  469. pm2_WR(par, PM2VR_RD_INDEX_HIGH, 0);
  470. break;
  471. }
  472. }
  473. static void set_video(struct pm2fb_par *p, u32 video)
  474. {
  475. u32 tmp;
  476. u32 vsync = video;
  477. DPRINTK("video = 0x%x\n", video);
  478. /*
  479. * The hardware cursor needs +vsync to recognise vert retrace.
  480. * We may not be using the hardware cursor, but the X Glint
  481. * driver may well. So always set +hsync/+vsync and then set
  482. * the RAMDAC to invert the sync if necessary.
  483. */
  484. vsync &= ~(PM2F_HSYNC_MASK | PM2F_VSYNC_MASK);
  485. vsync |= PM2F_HSYNC_ACT_HIGH | PM2F_VSYNC_ACT_HIGH;
  486. WAIT_FIFO(p, 3);
  487. pm2_WR(p, PM2R_VIDEO_CONTROL, vsync);
  488. switch (p->type) {
  489. case PM2_TYPE_PERMEDIA2:
  490. tmp = PM2F_RD_PALETTE_WIDTH_8;
  491. if ((video & PM2F_HSYNC_MASK) == PM2F_HSYNC_ACT_LOW)
  492. tmp |= 4; /* invert hsync */
  493. if ((video & PM2F_VSYNC_MASK) == PM2F_VSYNC_ACT_LOW)
  494. tmp |= 8; /* invert vsync */
  495. pm2_RDAC_WR(p, PM2I_RD_MISC_CONTROL, tmp);
  496. break;
  497. case PM2_TYPE_PERMEDIA2V:
  498. tmp = 0;
  499. if ((video & PM2F_HSYNC_MASK) == PM2F_HSYNC_ACT_LOW)
  500. tmp |= 1; /* invert hsync */
  501. if ((video & PM2F_VSYNC_MASK) == PM2F_VSYNC_ACT_LOW)
  502. tmp |= 4; /* invert vsync */
  503. pm2v_RDAC_WR(p, PM2VI_RD_SYNC_CONTROL, tmp);
  504. break;
  505. }
  506. }
  507. /*
  508. * pm2fb_check_var - Optional function. Validates a var passed in.
  509. * @var: frame buffer variable screen structure
  510. * @info: frame buffer structure that represents a single frame buffer
  511. *
  512. * Checks to see if the hardware supports the state requested by
  513. * var passed in.
  514. *
  515. * Returns negative errno on error, or zero on success.
  516. */
  517. static int pm2fb_check_var(struct fb_var_screeninfo *var, struct fb_info *info)
  518. {
  519. u32 lpitch;
  520. if (var->bits_per_pixel != 8 && var->bits_per_pixel != 16 &&
  521. var->bits_per_pixel != 24 && var->bits_per_pixel != 32) {
  522. DPRINTK("depth not supported: %u\n", var->bits_per_pixel);
  523. return -EINVAL;
  524. }
  525. if (var->xres != var->xres_virtual) {
  526. DPRINTK("virtual x resolution != "
  527. "physical x resolution not supported\n");
  528. return -EINVAL;
  529. }
  530. if (var->yres > var->yres_virtual) {
  531. DPRINTK("virtual y resolution < "
  532. "physical y resolution not possible\n");
  533. return -EINVAL;
  534. }
  535. /* permedia cannot blit over 2048 */
  536. if (var->yres_virtual > 2047) {
  537. var->yres_virtual = 2047;
  538. }
  539. if (var->xoffset) {
  540. DPRINTK("xoffset not supported\n");
  541. return -EINVAL;
  542. }
  543. if ((var->vmode & FB_VMODE_MASK) == FB_VMODE_INTERLACED) {
  544. DPRINTK("interlace not supported\n");
  545. return -EINVAL;
  546. }
  547. var->xres = (var->xres + 15) & ~15; /* could sometimes be 8 */
  548. lpitch = var->xres * ((var->bits_per_pixel + 7) >> 3);
  549. if (var->xres < 320 || var->xres > 1600) {
  550. DPRINTK("width not supported: %u\n", var->xres);
  551. return -EINVAL;
  552. }
  553. if (var->yres < 200 || var->yres > 1200) {
  554. DPRINTK("height not supported: %u\n", var->yres);
  555. return -EINVAL;
  556. }
  557. if (lpitch * var->yres_virtual > info->fix.smem_len) {
  558. DPRINTK("no memory for screen (%ux%ux%u)\n",
  559. var->xres, var->yres_virtual, var->bits_per_pixel);
  560. return -EINVAL;
  561. }
  562. if (PICOS2KHZ(var->pixclock) > PM2_MAX_PIXCLOCK) {
  563. DPRINTK("pixclock too high (%ldKHz)\n",
  564. PICOS2KHZ(var->pixclock));
  565. return -EINVAL;
  566. }
  567. var->transp.offset = 0;
  568. var->transp.length = 0;
  569. switch (var->bits_per_pixel) {
  570. case 8:
  571. var->red.length = 8;
  572. var->green.length = 8;
  573. var->blue.length = 8;
  574. break;
  575. case 16:
  576. var->red.offset = 11;
  577. var->red.length = 5;
  578. var->green.offset = 5;
  579. var->green.length = 6;
  580. var->blue.offset = 0;
  581. var->blue.length = 5;
  582. break;
  583. case 32:
  584. var->transp.offset = 24;
  585. var->transp.length = 8;
  586. var->red.offset = 16;
  587. var->green.offset = 8;
  588. var->blue.offset = 0;
  589. var->red.length = 8;
  590. var->green.length = 8;
  591. var->blue.length = 8;
  592. break;
  593. case 24:
  594. #ifdef __BIG_ENDIAN
  595. var->red.offset = 0;
  596. var->blue.offset = 16;
  597. #else
  598. var->red.offset = 16;
  599. var->blue.offset = 0;
  600. #endif
  601. var->green.offset = 8;
  602. var->red.length = 8;
  603. var->green.length = 8;
  604. var->blue.length = 8;
  605. break;
  606. }
  607. var->height = -1;
  608. var->width = -1;
  609. var->accel_flags = 0; /* Can't mmap if this is on */
  610. DPRINTK("Checking graphics mode at %dx%d depth %d\n",
  611. var->xres, var->yres, var->bits_per_pixel);
  612. return 0;
  613. }
  614. /**
  615. * pm2fb_set_par - Alters the hardware state.
  616. * @info: frame buffer structure that represents a single frame buffer
  617. *
  618. * Using the fb_var_screeninfo in fb_info we set the resolution of the
  619. * this particular framebuffer.
  620. */
  621. static int pm2fb_set_par(struct fb_info *info)
  622. {
  623. struct pm2fb_par *par = info->par;
  624. u32 pixclock;
  625. u32 width = (info->var.xres_virtual + 7) & ~7;
  626. u32 height = info->var.yres_virtual;
  627. u32 depth = (info->var.bits_per_pixel + 7) & ~7;
  628. u32 hsstart, hsend, hbend, htotal;
  629. u32 vsstart, vsend, vbend, vtotal;
  630. u32 stride;
  631. u32 base;
  632. u32 video = 0;
  633. u32 clrmode = PM2F_RD_COLOR_MODE_RGB | PM2F_RD_GUI_ACTIVE;
  634. u32 txtmap = 0;
  635. u32 pixsize = 0;
  636. u32 clrformat = 0;
  637. u32 misc = 1; /* 8-bit DAC */
  638. u32 xres = (info->var.xres + 31) & ~31;
  639. int data64;
  640. reset_card(par);
  641. reset_config(par);
  642. clear_palette(par);
  643. if (par->memclock)
  644. set_memclock(par, par->memclock);
  645. depth = (depth > 32) ? 32 : depth;
  646. data64 = depth > 8 || par->type == PM2_TYPE_PERMEDIA2V;
  647. pixclock = PICOS2KHZ(info->var.pixclock);
  648. if (pixclock > PM2_MAX_PIXCLOCK) {
  649. DPRINTK("pixclock too high (%uKHz)\n", pixclock);
  650. return -EINVAL;
  651. }
  652. hsstart = to3264(info->var.right_margin, depth, data64);
  653. hsend = hsstart + to3264(info->var.hsync_len, depth, data64);
  654. hbend = hsend + to3264(info->var.left_margin, depth, data64);
  655. htotal = to3264(xres, depth, data64) + hbend - 1;
  656. vsstart = (info->var.lower_margin)
  657. ? info->var.lower_margin - 1
  658. : 0; /* FIXME! */
  659. vsend = info->var.lower_margin + info->var.vsync_len - 1;
  660. vbend = info->var.lower_margin + info->var.vsync_len +
  661. info->var.upper_margin;
  662. vtotal = info->var.yres + vbend - 1;
  663. stride = to3264(width, depth, 1);
  664. base = to3264(info->var.yoffset * xres + info->var.xoffset, depth, 1);
  665. if (data64)
  666. video |= PM2F_DATA_64_ENABLE;
  667. if (info->var.sync & FB_SYNC_HOR_HIGH_ACT) {
  668. if (lowhsync) {
  669. DPRINTK("ignoring +hsync, using -hsync.\n");
  670. video |= PM2F_HSYNC_ACT_LOW;
  671. } else
  672. video |= PM2F_HSYNC_ACT_HIGH;
  673. } else
  674. video |= PM2F_HSYNC_ACT_LOW;
  675. if (info->var.sync & FB_SYNC_VERT_HIGH_ACT) {
  676. if (lowvsync) {
  677. DPRINTK("ignoring +vsync, using -vsync.\n");
  678. video |= PM2F_VSYNC_ACT_LOW;
  679. } else
  680. video |= PM2F_VSYNC_ACT_HIGH;
  681. } else
  682. video |= PM2F_VSYNC_ACT_LOW;
  683. if ((info->var.vmode & FB_VMODE_MASK) == FB_VMODE_INTERLACED) {
  684. DPRINTK("interlaced not supported\n");
  685. return -EINVAL;
  686. }
  687. if ((info->var.vmode & FB_VMODE_MASK) == FB_VMODE_DOUBLE)
  688. video |= PM2F_LINE_DOUBLE;
  689. if ((info->var.activate & FB_ACTIVATE_MASK) == FB_ACTIVATE_NOW)
  690. video |= PM2F_VIDEO_ENABLE;
  691. par->video = video;
  692. info->fix.visual =
  693. (depth == 8) ? FB_VISUAL_PSEUDOCOLOR : FB_VISUAL_TRUECOLOR;
  694. info->fix.line_length = info->var.xres * depth / 8;
  695. info->cmap.len = 256;
  696. /*
  697. * Settings calculated. Now write them out.
  698. */
  699. if (par->type == PM2_TYPE_PERMEDIA2V) {
  700. WAIT_FIFO(par, 1);
  701. pm2_WR(par, PM2VR_RD_INDEX_HIGH, 0);
  702. }
  703. set_aperture(par, depth);
  704. mb();
  705. WAIT_FIFO(par, 19);
  706. switch (depth) {
  707. case 8:
  708. pm2_WR(par, PM2R_FB_READ_PIXEL, 0);
  709. clrformat = 0x2e;
  710. break;
  711. case 16:
  712. pm2_WR(par, PM2R_FB_READ_PIXEL, 1);
  713. clrmode |= PM2F_RD_TRUECOLOR | PM2F_RD_PIXELFORMAT_RGB565;
  714. txtmap = PM2F_TEXTEL_SIZE_16;
  715. pixsize = 1;
  716. clrformat = 0x70;
  717. misc |= 8;
  718. break;
  719. case 32:
  720. pm2_WR(par, PM2R_FB_READ_PIXEL, 2);
  721. clrmode |= PM2F_RD_TRUECOLOR | PM2F_RD_PIXELFORMAT_RGBA8888;
  722. txtmap = PM2F_TEXTEL_SIZE_32;
  723. pixsize = 2;
  724. clrformat = 0x20;
  725. misc |= 8;
  726. break;
  727. case 24:
  728. pm2_WR(par, PM2R_FB_READ_PIXEL, 4);
  729. clrmode |= PM2F_RD_TRUECOLOR | PM2F_RD_PIXELFORMAT_RGB888;
  730. txtmap = PM2F_TEXTEL_SIZE_24;
  731. pixsize = 4;
  732. clrformat = 0x20;
  733. misc |= 8;
  734. break;
  735. }
  736. pm2_WR(par, PM2R_FB_WRITE_MODE, PM2F_FB_WRITE_ENABLE);
  737. pm2_WR(par, PM2R_FB_READ_MODE, partprod(xres));
  738. pm2_WR(par, PM2R_LB_READ_MODE, partprod(xres));
  739. pm2_WR(par, PM2R_TEXTURE_MAP_FORMAT, txtmap | partprod(xres));
  740. pm2_WR(par, PM2R_H_TOTAL, htotal);
  741. pm2_WR(par, PM2R_HS_START, hsstart);
  742. pm2_WR(par, PM2R_HS_END, hsend);
  743. pm2_WR(par, PM2R_HG_END, hbend);
  744. pm2_WR(par, PM2R_HB_END, hbend);
  745. pm2_WR(par, PM2R_V_TOTAL, vtotal);
  746. pm2_WR(par, PM2R_VS_START, vsstart);
  747. pm2_WR(par, PM2R_VS_END, vsend);
  748. pm2_WR(par, PM2R_VB_END, vbend);
  749. pm2_WR(par, PM2R_SCREEN_STRIDE, stride);
  750. wmb();
  751. pm2_WR(par, PM2R_WINDOW_ORIGIN, 0);
  752. pm2_WR(par, PM2R_SCREEN_SIZE, (height << 16) | width);
  753. pm2_WR(par, PM2R_SCISSOR_MODE, PM2F_SCREEN_SCISSOR_ENABLE);
  754. wmb();
  755. pm2_WR(par, PM2R_SCREEN_BASE, base);
  756. wmb();
  757. set_video(par, video);
  758. WAIT_FIFO(par, 10);
  759. switch (par->type) {
  760. case PM2_TYPE_PERMEDIA2:
  761. pm2_RDAC_WR(par, PM2I_RD_COLOR_MODE, clrmode);
  762. pm2_RDAC_WR(par, PM2I_RD_COLOR_KEY_CONTROL,
  763. (depth == 8) ? 0 : PM2F_COLOR_KEY_TEST_OFF);
  764. break;
  765. case PM2_TYPE_PERMEDIA2V:
  766. pm2v_RDAC_WR(par, PM2VI_RD_DAC_CONTROL, 0);
  767. pm2v_RDAC_WR(par, PM2VI_RD_PIXEL_SIZE, pixsize);
  768. pm2v_RDAC_WR(par, PM2VI_RD_COLOR_FORMAT, clrformat);
  769. pm2v_RDAC_WR(par, PM2VI_RD_MISC_CONTROL, misc);
  770. pm2v_RDAC_WR(par, PM2VI_RD_OVERLAY_KEY, 0);
  771. break;
  772. }
  773. set_pixclock(par, pixclock);
  774. DPRINTK("Setting graphics mode at %dx%d depth %d\n",
  775. info->var.xres, info->var.yres, info->var.bits_per_pixel);
  776. return 0;
  777. }
  778. /**
  779. * pm2fb_setcolreg - Sets a color register.
  780. * @regno: boolean, 0 copy local, 1 get_user() function
  781. * @red: frame buffer colormap structure
  782. * @green: The green value which can be up to 16 bits wide
  783. * @blue: The blue value which can be up to 16 bits wide.
  784. * @transp: If supported the alpha value which can be up to 16 bits wide.
  785. * @info: frame buffer info structure
  786. *
  787. * Set a single color register. The values supplied have a 16 bit
  788. * magnitude which needs to be scaled in this function for the hardware.
  789. * Pretty much a direct lift from tdfxfb.c.
  790. *
  791. * Returns negative errno on error, or zero on success.
  792. */
  793. static int pm2fb_setcolreg(unsigned regno, unsigned red, unsigned green,
  794. unsigned blue, unsigned transp,
  795. struct fb_info *info)
  796. {
  797. struct pm2fb_par *par = info->par;
  798. if (regno >= info->cmap.len) /* no. of hw registers */
  799. return -EINVAL;
  800. /*
  801. * Program hardware... do anything you want with transp
  802. */
  803. /* grayscale works only partially under directcolor */
  804. /* grayscale = 0.30*R + 0.59*G + 0.11*B */
  805. if (info->var.grayscale)
  806. red = green = blue = (red * 77 + green * 151 + blue * 28) >> 8;
  807. /* Directcolor:
  808. * var->{color}.offset contains start of bitfield
  809. * var->{color}.length contains length of bitfield
  810. * {hardwarespecific} contains width of DAC
  811. * cmap[X] is programmed to
  812. * (X << red.offset) | (X << green.offset) | (X << blue.offset)
  813. * RAMDAC[X] is programmed to (red, green, blue)
  814. *
  815. * Pseudocolor:
  816. * uses offset = 0 && length = DAC register width.
  817. * var->{color}.offset is 0
  818. * var->{color}.length contains width of DAC
  819. * cmap is not used
  820. * DAC[X] is programmed to (red, green, blue)
  821. * Truecolor:
  822. * does not use RAMDAC (usually has 3 of them).
  823. * var->{color}.offset contains start of bitfield
  824. * var->{color}.length contains length of bitfield
  825. * cmap is programmed to
  826. * (red << red.offset) | (green << green.offset) |
  827. * (blue << blue.offset) | (transp << transp.offset)
  828. * RAMDAC does not exist
  829. */
  830. #define CNVT_TOHW(val, width) ((((val) << (width)) + 0x7FFF -(val)) >> 16)
  831. switch (info->fix.visual) {
  832. case FB_VISUAL_TRUECOLOR:
  833. case FB_VISUAL_PSEUDOCOLOR:
  834. red = CNVT_TOHW(red, info->var.red.length);
  835. green = CNVT_TOHW(green, info->var.green.length);
  836. blue = CNVT_TOHW(blue, info->var.blue.length);
  837. transp = CNVT_TOHW(transp, info->var.transp.length);
  838. break;
  839. case FB_VISUAL_DIRECTCOLOR:
  840. /* example here assumes 8 bit DAC. Might be different
  841. * for your hardware */
  842. red = CNVT_TOHW(red, 8);
  843. green = CNVT_TOHW(green, 8);
  844. blue = CNVT_TOHW(blue, 8);
  845. /* hey, there is bug in transp handling... */
  846. transp = CNVT_TOHW(transp, 8);
  847. break;
  848. }
  849. #undef CNVT_TOHW
  850. /* Truecolor has hardware independent palette */
  851. if (info->fix.visual == FB_VISUAL_TRUECOLOR) {
  852. u32 v;
  853. if (regno >= 16)
  854. return -EINVAL;
  855. v = (red << info->var.red.offset) |
  856. (green << info->var.green.offset) |
  857. (blue << info->var.blue.offset) |
  858. (transp << info->var.transp.offset);
  859. switch (info->var.bits_per_pixel) {
  860. case 8:
  861. break;
  862. case 16:
  863. case 24:
  864. case 32:
  865. par->palette[regno] = v;
  866. break;
  867. }
  868. return 0;
  869. } else if (info->fix.visual == FB_VISUAL_PSEUDOCOLOR)
  870. set_color(par, regno, red, green, blue);
  871. return 0;
  872. }
  873. /**
  874. * pm2fb_pan_display - Pans the display.
  875. * @var: frame buffer variable screen structure
  876. * @info: frame buffer structure that represents a single frame buffer
  877. *
  878. * Pan (or wrap, depending on the `vmode' field) the display using the
  879. * `xoffset' and `yoffset' fields of the `var' structure.
  880. * If the values don't fit, return -EINVAL.
  881. *
  882. * Returns negative errno on error, or zero on success.
  883. *
  884. */
  885. static int pm2fb_pan_display(struct fb_var_screeninfo *var,
  886. struct fb_info *info)
  887. {
  888. struct pm2fb_par *p = info->par;
  889. u32 base;
  890. u32 depth = (info->var.bits_per_pixel + 7) & ~7;
  891. u32 xres = (info->var.xres + 31) & ~31;
  892. depth = (depth > 32) ? 32 : depth;
  893. base = to3264(var->yoffset * xres + var->xoffset, depth, 1);
  894. WAIT_FIFO(p, 1);
  895. pm2_WR(p, PM2R_SCREEN_BASE, base);
  896. return 0;
  897. }
  898. /**
  899. * pm2fb_blank - Blanks the display.
  900. * @blank_mode: the blank mode we want.
  901. * @info: frame buffer structure that represents a single frame buffer
  902. *
  903. * Blank the screen if blank_mode != 0, else unblank. Return 0 if
  904. * blanking succeeded, != 0 if un-/blanking failed due to e.g. a
  905. * video mode which doesn't support it. Implements VESA suspend
  906. * and powerdown modes on hardware that supports disabling hsync/vsync:
  907. * blank_mode == 2: suspend vsync
  908. * blank_mode == 3: suspend hsync
  909. * blank_mode == 4: powerdown
  910. *
  911. * Returns negative errno on error, or zero on success.
  912. *
  913. */
  914. static int pm2fb_blank(int blank_mode, struct fb_info *info)
  915. {
  916. struct pm2fb_par *par = info->par;
  917. u32 video = par->video;
  918. DPRINTK("blank_mode %d\n", blank_mode);
  919. switch (blank_mode) {
  920. case FB_BLANK_UNBLANK:
  921. /* Screen: On */
  922. video |= PM2F_VIDEO_ENABLE;
  923. break;
  924. case FB_BLANK_NORMAL:
  925. /* Screen: Off */
  926. video &= ~PM2F_VIDEO_ENABLE;
  927. break;
  928. case FB_BLANK_VSYNC_SUSPEND:
  929. /* VSync: Off */
  930. video &= ~(PM2F_VSYNC_MASK | PM2F_BLANK_LOW);
  931. break;
  932. case FB_BLANK_HSYNC_SUSPEND:
  933. /* HSync: Off */
  934. video &= ~(PM2F_HSYNC_MASK | PM2F_BLANK_LOW);
  935. break;
  936. case FB_BLANK_POWERDOWN:
  937. /* HSync: Off, VSync: Off */
  938. video &= ~(PM2F_VSYNC_MASK | PM2F_HSYNC_MASK | PM2F_BLANK_LOW);
  939. break;
  940. }
  941. set_video(par, video);
  942. return 0;
  943. }
  944. static int pm2fb_sync(struct fb_info *info)
  945. {
  946. struct pm2fb_par *par = info->par;
  947. WAIT_FIFO(par, 1);
  948. pm2_WR(par, PM2R_SYNC, 0);
  949. mb();
  950. do {
  951. while (pm2_RD(par, PM2R_OUT_FIFO_WORDS) == 0)
  952. cpu_relax();
  953. } while (pm2_RD(par, PM2R_OUT_FIFO) != PM2TAG(PM2R_SYNC));
  954. return 0;
  955. }
  956. static void pm2fb_fillrect(struct fb_info *info,
  957. const struct fb_fillrect *region)
  958. {
  959. struct pm2fb_par *par = info->par;
  960. struct fb_fillrect modded;
  961. int vxres, vyres;
  962. u32 color = (info->fix.visual == FB_VISUAL_TRUECOLOR) ?
  963. ((u32 *)info->pseudo_palette)[region->color] : region->color;
  964. if (info->state != FBINFO_STATE_RUNNING)
  965. return;
  966. if ((info->flags & FBINFO_HWACCEL_DISABLED) ||
  967. region->rop != ROP_COPY ) {
  968. cfb_fillrect(info, region);
  969. return;
  970. }
  971. vxres = info->var.xres_virtual;
  972. vyres = info->var.yres_virtual;
  973. memcpy(&modded, region, sizeof(struct fb_fillrect));
  974. if (!modded.width || !modded.height ||
  975. modded.dx >= vxres || modded.dy >= vyres)
  976. return;
  977. if (modded.dx + modded.width > vxres)
  978. modded.width = vxres - modded.dx;
  979. if (modded.dy + modded.height > vyres)
  980. modded.height = vyres - modded.dy;
  981. if (info->var.bits_per_pixel == 8)
  982. color |= color << 8;
  983. if (info->var.bits_per_pixel <= 16)
  984. color |= color << 16;
  985. WAIT_FIFO(par, 3);
  986. pm2_WR(par, PM2R_CONFIG, PM2F_CONFIG_FB_WRITE_ENABLE);
  987. pm2_WR(par, PM2R_RECTANGLE_ORIGIN, (modded.dy << 16) | modded.dx);
  988. pm2_WR(par, PM2R_RECTANGLE_SIZE, (modded.height << 16) | modded.width);
  989. if (info->var.bits_per_pixel != 24) {
  990. WAIT_FIFO(par, 2);
  991. pm2_WR(par, PM2R_FB_BLOCK_COLOR, color);
  992. wmb();
  993. pm2_WR(par, PM2R_RENDER,
  994. PM2F_RENDER_RECTANGLE | PM2F_RENDER_FASTFILL);
  995. } else {
  996. WAIT_FIFO(par, 4);
  997. pm2_WR(par, PM2R_COLOR_DDA_MODE, 1);
  998. pm2_WR(par, PM2R_CONSTANT_COLOR, color);
  999. wmb();
  1000. pm2_WR(par, PM2R_RENDER,
  1001. PM2F_RENDER_RECTANGLE |
  1002. PM2F_INCREASE_X | PM2F_INCREASE_Y );
  1003. pm2_WR(par, PM2R_COLOR_DDA_MODE, 0);
  1004. }
  1005. }
  1006. static void pm2fb_copyarea(struct fb_info *info,
  1007. const struct fb_copyarea *area)
  1008. {
  1009. struct pm2fb_par *par = info->par;
  1010. struct fb_copyarea modded;
  1011. u32 vxres, vyres;
  1012. if (info->state != FBINFO_STATE_RUNNING)
  1013. return;
  1014. if (info->flags & FBINFO_HWACCEL_DISABLED) {
  1015. cfb_copyarea(info, area);
  1016. return;
  1017. }
  1018. memcpy(&modded, area, sizeof(struct fb_copyarea));
  1019. vxres = info->var.xres_virtual;
  1020. vyres = info->var.yres_virtual;
  1021. if (!modded.width || !modded.height ||
  1022. modded.sx >= vxres || modded.sy >= vyres ||
  1023. modded.dx >= vxres || modded.dy >= vyres)
  1024. return;
  1025. if (modded.sx + modded.width > vxres)
  1026. modded.width = vxres - modded.sx;
  1027. if (modded.dx + modded.width > vxres)
  1028. modded.width = vxres - modded.dx;
  1029. if (modded.sy + modded.height > vyres)
  1030. modded.height = vyres - modded.sy;
  1031. if (modded.dy + modded.height > vyres)
  1032. modded.height = vyres - modded.dy;
  1033. WAIT_FIFO(par, 5);
  1034. pm2_WR(par, PM2R_CONFIG, PM2F_CONFIG_FB_WRITE_ENABLE |
  1035. PM2F_CONFIG_FB_READ_SOURCE_ENABLE);
  1036. pm2_WR(par, PM2R_FB_SOURCE_DELTA,
  1037. ((modded.sy - modded.dy) & 0xfff) << 16 |
  1038. ((modded.sx - modded.dx) & 0xfff));
  1039. pm2_WR(par, PM2R_RECTANGLE_ORIGIN, (modded.dy << 16) | modded.dx);
  1040. pm2_WR(par, PM2R_RECTANGLE_SIZE, (modded.height << 16) | modded.width);
  1041. wmb();
  1042. pm2_WR(par, PM2R_RENDER, PM2F_RENDER_RECTANGLE |
  1043. (modded.dx < modded.sx ? PM2F_INCREASE_X : 0) |
  1044. (modded.dy < modded.sy ? PM2F_INCREASE_Y : 0));
  1045. }
  1046. static void pm2fb_imageblit(struct fb_info *info, const struct fb_image *image)
  1047. {
  1048. struct pm2fb_par *par = info->par;
  1049. u32 height = image->height;
  1050. u32 fgx, bgx;
  1051. const u32 *src = (const u32 *)image->data;
  1052. u32 xres = (info->var.xres + 31) & ~31;
  1053. int raster_mode = 1; /* invert bits */
  1054. #ifdef __LITTLE_ENDIAN
  1055. raster_mode |= 3 << 7; /* reverse byte order */
  1056. #endif
  1057. if (info->state != FBINFO_STATE_RUNNING)
  1058. return;
  1059. if (info->flags & FBINFO_HWACCEL_DISABLED || image->depth != 1) {
  1060. cfb_imageblit(info, image);
  1061. return;
  1062. }
  1063. switch (info->fix.visual) {
  1064. case FB_VISUAL_PSEUDOCOLOR:
  1065. fgx = image->fg_color;
  1066. bgx = image->bg_color;
  1067. break;
  1068. case FB_VISUAL_TRUECOLOR:
  1069. default:
  1070. fgx = par->palette[image->fg_color];
  1071. bgx = par->palette[image->bg_color];
  1072. break;
  1073. }
  1074. if (info->var.bits_per_pixel == 8) {
  1075. fgx |= fgx << 8;
  1076. bgx |= bgx << 8;
  1077. }
  1078. if (info->var.bits_per_pixel <= 16) {
  1079. fgx |= fgx << 16;
  1080. bgx |= bgx << 16;
  1081. }
  1082. WAIT_FIFO(par, 13);
  1083. pm2_WR(par, PM2R_FB_READ_MODE, partprod(xres));
  1084. pm2_WR(par, PM2R_SCISSOR_MIN_XY,
  1085. ((image->dy & 0xfff) << 16) | (image->dx & 0x0fff));
  1086. pm2_WR(par, PM2R_SCISSOR_MAX_XY,
  1087. (((image->dy + image->height) & 0x0fff) << 16) |
  1088. ((image->dx + image->width) & 0x0fff));
  1089. pm2_WR(par, PM2R_SCISSOR_MODE, 1);
  1090. /* GXcopy & UNIT_ENABLE */
  1091. pm2_WR(par, PM2R_LOGICAL_OP_MODE, (0x3 << 1) | 1);
  1092. pm2_WR(par, PM2R_RECTANGLE_ORIGIN,
  1093. ((image->dy & 0xfff) << 16) | (image->dx & 0x0fff));
  1094. pm2_WR(par, PM2R_RECTANGLE_SIZE,
  1095. ((image->height & 0x0fff) << 16) |
  1096. ((image->width) & 0x0fff));
  1097. if (info->var.bits_per_pixel == 24) {
  1098. pm2_WR(par, PM2R_COLOR_DDA_MODE, 1);
  1099. /* clear area */
  1100. pm2_WR(par, PM2R_CONSTANT_COLOR, bgx);
  1101. pm2_WR(par, PM2R_RENDER,
  1102. PM2F_RENDER_RECTANGLE |
  1103. PM2F_INCREASE_X | PM2F_INCREASE_Y);
  1104. /* BitMapPackEachScanline */
  1105. pm2_WR(par, PM2R_RASTERIZER_MODE, raster_mode | (1 << 9));
  1106. pm2_WR(par, PM2R_CONSTANT_COLOR, fgx);
  1107. pm2_WR(par, PM2R_RENDER,
  1108. PM2F_RENDER_RECTANGLE |
  1109. PM2F_INCREASE_X | PM2F_INCREASE_Y |
  1110. PM2F_RENDER_SYNC_ON_BIT_MASK);
  1111. } else {
  1112. pm2_WR(par, PM2R_COLOR_DDA_MODE, 0);
  1113. /* clear area */
  1114. pm2_WR(par, PM2R_FB_BLOCK_COLOR, bgx);
  1115. pm2_WR(par, PM2R_RENDER,
  1116. PM2F_RENDER_RECTANGLE |
  1117. PM2F_RENDER_FASTFILL |
  1118. PM2F_INCREASE_X | PM2F_INCREASE_Y);
  1119. pm2_WR(par, PM2R_RASTERIZER_MODE, raster_mode);
  1120. pm2_WR(par, PM2R_FB_BLOCK_COLOR, fgx);
  1121. pm2_WR(par, PM2R_RENDER,
  1122. PM2F_RENDER_RECTANGLE |
  1123. PM2F_INCREASE_X | PM2F_INCREASE_Y |
  1124. PM2F_RENDER_FASTFILL |
  1125. PM2F_RENDER_SYNC_ON_BIT_MASK);
  1126. }
  1127. while (height--) {
  1128. int width = ((image->width + 7) >> 3)
  1129. + info->pixmap.scan_align - 1;
  1130. width >>= 2;
  1131. WAIT_FIFO(par, width);
  1132. while (width--) {
  1133. pm2_WR(par, PM2R_BIT_MASK_PATTERN, *src);
  1134. src++;
  1135. }
  1136. }
  1137. WAIT_FIFO(par, 3);
  1138. pm2_WR(par, PM2R_RASTERIZER_MODE, 0);
  1139. pm2_WR(par, PM2R_COLOR_DDA_MODE, 0);
  1140. pm2_WR(par, PM2R_SCISSOR_MODE, 0);
  1141. }
  1142. /*
  1143. * Hardware cursor support.
  1144. */
  1145. static const u8 cursor_bits_lookup[16] = {
  1146. 0x00, 0x40, 0x10, 0x50, 0x04, 0x44, 0x14, 0x54,
  1147. 0x01, 0x41, 0x11, 0x51, 0x05, 0x45, 0x15, 0x55
  1148. };
  1149. static int pm2vfb_cursor(struct fb_info *info, struct fb_cursor *cursor)
  1150. {
  1151. struct pm2fb_par *par = info->par;
  1152. u8 mode = PM2F_CURSORMODE_TYPE_X;
  1153. int x = cursor->image.dx - info->var.xoffset;
  1154. int y = cursor->image.dy - info->var.yoffset;
  1155. if (cursor->enable)
  1156. mode |= PM2F_CURSORMODE_CURSOR_ENABLE;
  1157. pm2v_RDAC_WR(par, PM2VI_RD_CURSOR_MODE, mode);
  1158. if (!cursor->enable)
  1159. x = 2047; /* push it outside display */
  1160. pm2v_RDAC_WR(par, PM2VI_RD_CURSOR_X_LOW, x & 0xff);
  1161. pm2v_RDAC_WR(par, PM2VI_RD_CURSOR_X_HIGH, (x >> 8) & 0xf);
  1162. pm2v_RDAC_WR(par, PM2VI_RD_CURSOR_Y_LOW, y & 0xff);
  1163. pm2v_RDAC_WR(par, PM2VI_RD_CURSOR_Y_HIGH, (y >> 8) & 0xf);
  1164. /*
  1165. * If the cursor is not be changed this means either we want the
  1166. * current cursor state (if enable is set) or we want to query what
  1167. * we can do with the cursor (if enable is not set)
  1168. */
  1169. if (!cursor->set)
  1170. return 0;
  1171. if (cursor->set & FB_CUR_SETHOT) {
  1172. pm2v_RDAC_WR(par, PM2VI_RD_CURSOR_X_HOT,
  1173. cursor->hot.x & 0x3f);
  1174. pm2v_RDAC_WR(par, PM2VI_RD_CURSOR_Y_HOT,
  1175. cursor->hot.y & 0x3f);
  1176. }
  1177. if (cursor->set & FB_CUR_SETCMAP) {
  1178. u32 fg_idx = cursor->image.fg_color;
  1179. u32 bg_idx = cursor->image.bg_color;
  1180. struct fb_cmap cmap = info->cmap;
  1181. /* the X11 driver says one should use these color registers */
  1182. pm2_WR(par, PM2VR_RD_INDEX_HIGH, PM2VI_RD_CURSOR_PALETTE >> 8);
  1183. pm2v_RDAC_WR(par, PM2VI_RD_CURSOR_PALETTE + 0,
  1184. cmap.red[bg_idx] >> 8 );
  1185. pm2v_RDAC_WR(par, PM2VI_RD_CURSOR_PALETTE + 1,
  1186. cmap.green[bg_idx] >> 8 );
  1187. pm2v_RDAC_WR(par, PM2VI_RD_CURSOR_PALETTE + 2,
  1188. cmap.blue[bg_idx] >> 8 );
  1189. pm2v_RDAC_WR(par, PM2VI_RD_CURSOR_PALETTE + 3,
  1190. cmap.red[fg_idx] >> 8 );
  1191. pm2v_RDAC_WR(par, PM2VI_RD_CURSOR_PALETTE + 4,
  1192. cmap.green[fg_idx] >> 8 );
  1193. pm2v_RDAC_WR(par, PM2VI_RD_CURSOR_PALETTE + 5,
  1194. cmap.blue[fg_idx] >> 8 );
  1195. pm2_WR(par, PM2VR_RD_INDEX_HIGH, 0);
  1196. }
  1197. if (cursor->set & (FB_CUR_SETSHAPE | FB_CUR_SETIMAGE)) {
  1198. u8 *bitmap = (u8 *)cursor->image.data;
  1199. u8 *mask = (u8 *)cursor->mask;
  1200. int i;
  1201. int pos = PM2VI_RD_CURSOR_PATTERN;
  1202. for (i = 0; i < cursor->image.height; i++) {
  1203. int j = (cursor->image.width + 7) >> 3;
  1204. int k = 8 - j;
  1205. pm2_WR(par, PM2VR_RD_INDEX_HIGH, pos >> 8);
  1206. for (; j > 0; j--) {
  1207. u8 data = *bitmap ^ *mask;
  1208. if (cursor->rop == ROP_COPY)
  1209. data = *mask & *bitmap;
  1210. /* Upper 4 bits of bitmap data */
  1211. pm2v_RDAC_WR(par, pos++,
  1212. cursor_bits_lookup[data >> 4] |
  1213. (cursor_bits_lookup[*mask >> 4] << 1));
  1214. /* Lower 4 bits of bitmap */
  1215. pm2v_RDAC_WR(par, pos++,
  1216. cursor_bits_lookup[data & 0xf] |
  1217. (cursor_bits_lookup[*mask & 0xf] << 1));
  1218. bitmap++;
  1219. mask++;
  1220. }
  1221. for (; k > 0; k--) {
  1222. pm2v_RDAC_WR(par, pos++, 0);
  1223. pm2v_RDAC_WR(par, pos++, 0);
  1224. }
  1225. }
  1226. while (pos < (1024 + PM2VI_RD_CURSOR_PATTERN)) {
  1227. pm2_WR(par, PM2VR_RD_INDEX_HIGH, pos >> 8);
  1228. pm2v_RDAC_WR(par, pos++, 0);
  1229. }
  1230. pm2_WR(par, PM2VR_RD_INDEX_HIGH, 0);
  1231. }
  1232. return 0;
  1233. }
  1234. static int pm2fb_cursor(struct fb_info *info, struct fb_cursor *cursor)
  1235. {
  1236. struct pm2fb_par *par = info->par;
  1237. u8 mode;
  1238. if (!hwcursor)
  1239. return -EINVAL; /* just to force soft_cursor() call */
  1240. /* Too large of a cursor or wrong bpp :-( */
  1241. if (cursor->image.width > 64 ||
  1242. cursor->image.height > 64 ||
  1243. cursor->image.depth > 1)
  1244. return -EINVAL;
  1245. if (par->type == PM2_TYPE_PERMEDIA2V)
  1246. return pm2vfb_cursor(info, cursor);
  1247. mode = 0x40;
  1248. if (cursor->enable)
  1249. mode = 0x43;
  1250. pm2_RDAC_WR(par, PM2I_RD_CURSOR_CONTROL, mode);
  1251. /*
  1252. * If the cursor is not be changed this means either we want the
  1253. * current cursor state (if enable is set) or we want to query what
  1254. * we can do with the cursor (if enable is not set)
  1255. */
  1256. if (!cursor->set)
  1257. return 0;
  1258. if (cursor->set & FB_CUR_SETPOS) {
  1259. int x = cursor->image.dx - info->var.xoffset + 63;
  1260. int y = cursor->image.dy - info->var.yoffset + 63;
  1261. WAIT_FIFO(par, 4);
  1262. pm2_WR(par, PM2R_RD_CURSOR_X_LSB, x & 0xff);
  1263. pm2_WR(par, PM2R_RD_CURSOR_X_MSB, (x >> 8) & 0x7);
  1264. pm2_WR(par, PM2R_RD_CURSOR_Y_LSB, y & 0xff);
  1265. pm2_WR(par, PM2R_RD_CURSOR_Y_MSB, (y >> 8) & 0x7);
  1266. }
  1267. if (cursor->set & FB_CUR_SETCMAP) {
  1268. u32 fg_idx = cursor->image.fg_color;
  1269. u32 bg_idx = cursor->image.bg_color;
  1270. WAIT_FIFO(par, 7);
  1271. pm2_WR(par, PM2R_RD_CURSOR_COLOR_ADDRESS, 1);
  1272. pm2_WR(par, PM2R_RD_CURSOR_COLOR_DATA,
  1273. info->cmap.red[bg_idx] >> 8);
  1274. pm2_WR(par, PM2R_RD_CURSOR_COLOR_DATA,
  1275. info->cmap.green[bg_idx] >> 8);
  1276. pm2_WR(par, PM2R_RD_CURSOR_COLOR_DATA,
  1277. info->cmap.blue[bg_idx] >> 8);
  1278. pm2_WR(par, PM2R_RD_CURSOR_COLOR_DATA,
  1279. info->cmap.red[fg_idx] >> 8);
  1280. pm2_WR(par, PM2R_RD_CURSOR_COLOR_DATA,
  1281. info->cmap.green[fg_idx] >> 8);
  1282. pm2_WR(par, PM2R_RD_CURSOR_COLOR_DATA,
  1283. info->cmap.blue[fg_idx] >> 8);
  1284. }
  1285. if (cursor->set & (FB_CUR_SETSHAPE | FB_CUR_SETIMAGE)) {
  1286. u8 *bitmap = (u8 *)cursor->image.data;
  1287. u8 *mask = (u8 *)cursor->mask;
  1288. int i;
  1289. WAIT_FIFO(par, 1);
  1290. pm2_WR(par, PM2R_RD_PALETTE_WRITE_ADDRESS, 0);
  1291. for (i = 0; i < cursor->image.height; i++) {
  1292. int j = (cursor->image.width + 7) >> 3;
  1293. int k = 8 - j;
  1294. WAIT_FIFO(par, 8);
  1295. for (; j > 0; j--) {
  1296. u8 data = *bitmap ^ *mask;
  1297. if (cursor->rop == ROP_COPY)
  1298. data = *mask & *bitmap;
  1299. /* bitmap data */
  1300. pm2_WR(par, PM2R_RD_CURSOR_DATA, data);
  1301. bitmap++;
  1302. mask++;
  1303. }
  1304. for (; k > 0; k--)
  1305. pm2_WR(par, PM2R_RD_CURSOR_DATA, 0);
  1306. }
  1307. for (; i < 64; i++) {
  1308. int j = 8;
  1309. WAIT_FIFO(par, 8);
  1310. while (j-- > 0)
  1311. pm2_WR(par, PM2R_RD_CURSOR_DATA, 0);
  1312. }
  1313. mask = (u8 *)cursor->mask;
  1314. for (i = 0; i < cursor->image.height; i++) {
  1315. int j = (cursor->image.width + 7) >> 3;
  1316. int k = 8 - j;
  1317. WAIT_FIFO(par, 8);
  1318. for (; j > 0; j--) {
  1319. /* mask */
  1320. pm2_WR(par, PM2R_RD_CURSOR_DATA, *mask);
  1321. mask++;
  1322. }
  1323. for (; k > 0; k--)
  1324. pm2_WR(par, PM2R_RD_CURSOR_DATA, 0);
  1325. }
  1326. for (; i < 64; i++) {
  1327. int j = 8;
  1328. WAIT_FIFO(par, 8);
  1329. while (j-- > 0)
  1330. pm2_WR(par, PM2R_RD_CURSOR_DATA, 0);
  1331. }
  1332. }
  1333. return 0;
  1334. }
  1335. /* ------------ Hardware Independent Functions ------------ */
  1336. /*
  1337. * Frame buffer operations
  1338. */
  1339. static struct fb_ops pm2fb_ops = {
  1340. .owner = THIS_MODULE,
  1341. .fb_check_var = pm2fb_check_var,
  1342. .fb_set_par = pm2fb_set_par,
  1343. .fb_setcolreg = pm2fb_setcolreg,
  1344. .fb_blank = pm2fb_blank,
  1345. .fb_pan_display = pm2fb_pan_display,
  1346. .fb_fillrect = pm2fb_fillrect,
  1347. .fb_copyarea = pm2fb_copyarea,
  1348. .fb_imageblit = pm2fb_imageblit,
  1349. .fb_sync = pm2fb_sync,
  1350. .fb_cursor = pm2fb_cursor,
  1351. };
  1352. /*
  1353. * PCI stuff
  1354. */
  1355. /**
  1356. * Device initialisation
  1357. *
  1358. * Initialise and allocate resource for PCI device.
  1359. *
  1360. * @param pdev PCI device.
  1361. * @param id PCI device ID.
  1362. */
  1363. static int pm2fb_probe(struct pci_dev *pdev, const struct pci_device_id *id)
  1364. {
  1365. struct pm2fb_par *default_par;
  1366. struct fb_info *info;
  1367. int err;
  1368. int retval = -ENXIO;
  1369. err = pci_enable_device(pdev);
  1370. if (err) {
  1371. printk(KERN_WARNING "pm2fb: Can't enable pdev: %d\n", err);
  1372. return err;
  1373. }
  1374. info = framebuffer_alloc(sizeof(struct pm2fb_par), &pdev->dev);
  1375. if (!info)
  1376. return -ENOMEM;
  1377. default_par = info->par;
  1378. switch (pdev->device) {
  1379. case PCI_DEVICE_ID_TI_TVP4020:
  1380. strcpy(pm2fb_fix.id, "TVP4020");
  1381. default_par->type = PM2_TYPE_PERMEDIA2;
  1382. break;
  1383. case PCI_DEVICE_ID_3DLABS_PERMEDIA2:
  1384. strcpy(pm2fb_fix.id, "Permedia2");
  1385. default_par->type = PM2_TYPE_PERMEDIA2;
  1386. break;
  1387. case PCI_DEVICE_ID_3DLABS_PERMEDIA2V:
  1388. strcpy(pm2fb_fix.id, "Permedia2v");
  1389. default_par->type = PM2_TYPE_PERMEDIA2V;
  1390. break;
  1391. }
  1392. pm2fb_fix.mmio_start = pci_resource_start(pdev, 0);
  1393. pm2fb_fix.mmio_len = PM2_REGS_SIZE;
  1394. #if defined(__BIG_ENDIAN)
  1395. /*
  1396. * PM2 has a 64k register file, mapped twice in 128k. Lower
  1397. * map is little-endian, upper map is big-endian.
  1398. */
  1399. pm2fb_fix.mmio_start += PM2_REGS_SIZE;
  1400. DPRINTK("Adjusting register base for big-endian.\n");
  1401. #endif
  1402. DPRINTK("Register base at 0x%lx\n", pm2fb_fix.mmio_start);
  1403. /* Registers - request region and map it. */
  1404. if (!request_mem_region(pm2fb_fix.mmio_start, pm2fb_fix.mmio_len,
  1405. "pm2fb regbase")) {
  1406. printk(KERN_WARNING "pm2fb: Can't reserve regbase.\n");
  1407. goto err_exit_neither;
  1408. }
  1409. default_par->v_regs =
  1410. ioremap_nocache(pm2fb_fix.mmio_start, pm2fb_fix.mmio_len);
  1411. if (!default_par->v_regs) {
  1412. printk(KERN_WARNING "pm2fb: Can't remap %s register area.\n",
  1413. pm2fb_fix.id);
  1414. release_mem_region(pm2fb_fix.mmio_start, pm2fb_fix.mmio_len);
  1415. goto err_exit_neither;
  1416. }
  1417. /* Stash away memory register info for use when we reset the board */
  1418. default_par->mem_control = pm2_RD(default_par, PM2R_MEM_CONTROL);
  1419. default_par->boot_address = pm2_RD(default_par, PM2R_BOOT_ADDRESS);
  1420. default_par->mem_config = pm2_RD(default_par, PM2R_MEM_CONFIG);
  1421. DPRINTK("MemControl 0x%x BootAddress 0x%x MemConfig 0x%x\n",
  1422. default_par->mem_control, default_par->boot_address,
  1423. default_par->mem_config);
  1424. if (default_par->mem_control == 0 &&
  1425. default_par->boot_address == 0x31 &&
  1426. default_par->mem_config == 0x259fffff) {
  1427. default_par->memclock = CVPPC_MEMCLOCK;
  1428. default_par->mem_control = 0;
  1429. default_par->boot_address = 0x20;
  1430. default_par->mem_config = 0xe6002021;
  1431. if (pdev->subsystem_vendor == 0x1048 &&
  1432. pdev->subsystem_device == 0x0a31) {
  1433. DPRINTK("subsystem_vendor: %04x, "
  1434. "subsystem_device: %04x\n",
  1435. pdev->subsystem_vendor, pdev->subsystem_device);
  1436. DPRINTK("We have not been initialized by VGA BIOS and "
  1437. "are running on an Elsa Winner 2000 Office\n");
  1438. DPRINTK("Initializing card timings manually...\n");
  1439. default_par->memclock = 100000;
  1440. }
  1441. if (pdev->subsystem_vendor == 0x3d3d &&
  1442. pdev->subsystem_device == 0x0100) {
  1443. DPRINTK("subsystem_vendor: %04x, "
  1444. "subsystem_device: %04x\n",
  1445. pdev->subsystem_vendor, pdev->subsystem_device);
  1446. DPRINTK("We have not been initialized by VGA BIOS and "
  1447. "are running on an 3dlabs reference board\n");
  1448. DPRINTK("Initializing card timings manually...\n");
  1449. default_par->memclock = 74894;
  1450. }
  1451. }
  1452. /* Now work out how big lfb is going to be. */
  1453. switch (default_par->mem_config & PM2F_MEM_CONFIG_RAM_MASK) {
  1454. case PM2F_MEM_BANKS_1:
  1455. pm2fb_fix.smem_len = 0x200000;
  1456. break;
  1457. case PM2F_MEM_BANKS_2:
  1458. pm2fb_fix.smem_len = 0x400000;
  1459. break;
  1460. case PM2F_MEM_BANKS_3:
  1461. pm2fb_fix.smem_len = 0x600000;
  1462. break;
  1463. case PM2F_MEM_BANKS_4:
  1464. pm2fb_fix.smem_len = 0x800000;
  1465. break;
  1466. }
  1467. pm2fb_fix.smem_start = pci_resource_start(pdev, 1);
  1468. /* Linear frame buffer - request region and map it. */
  1469. if (!request_mem_region(pm2fb_fix.smem_start, pm2fb_fix.smem_len,
  1470. "pm2fb smem")) {
  1471. printk(KERN_WARNING "pm2fb: Can't reserve smem.\n");
  1472. goto err_exit_mmio;
  1473. }
  1474. info->screen_base =
  1475. ioremap_wc(pm2fb_fix.smem_start, pm2fb_fix.smem_len);
  1476. if (!info->screen_base) {
  1477. printk(KERN_WARNING "pm2fb: Can't ioremap smem area.\n");
  1478. release_mem_region(pm2fb_fix.smem_start, pm2fb_fix.smem_len);
  1479. goto err_exit_mmio;
  1480. }
  1481. if (!nomtrr)
  1482. default_par->wc_cookie = arch_phys_wc_add(pm2fb_fix.smem_start,
  1483. pm2fb_fix.smem_len);
  1484. info->fbops = &pm2fb_ops;
  1485. info->fix = pm2fb_fix;
  1486. info->pseudo_palette = default_par->palette;
  1487. info->flags = FBINFO_DEFAULT |
  1488. FBINFO_HWACCEL_YPAN |
  1489. FBINFO_HWACCEL_COPYAREA |
  1490. FBINFO_HWACCEL_IMAGEBLIT |
  1491. FBINFO_HWACCEL_FILLRECT;
  1492. info->pixmap.addr = kmalloc(PM2_PIXMAP_SIZE, GFP_KERNEL);
  1493. if (!info->pixmap.addr) {
  1494. retval = -ENOMEM;
  1495. goto err_exit_pixmap;
  1496. }
  1497. info->pixmap.size = PM2_PIXMAP_SIZE;
  1498. info->pixmap.buf_align = 4;
  1499. info->pixmap.scan_align = 4;
  1500. info->pixmap.access_align = 32;
  1501. info->pixmap.flags = FB_PIXMAP_SYSTEM;
  1502. if (noaccel) {
  1503. printk(KERN_DEBUG "disabling acceleration\n");
  1504. info->flags |= FBINFO_HWACCEL_DISABLED;
  1505. info->pixmap.scan_align = 1;
  1506. }
  1507. if (!mode_option)
  1508. mode_option = "640x480@60";
  1509. err = fb_find_mode(&info->var, info, mode_option, NULL, 0, NULL, 8);
  1510. if (!err || err == 4)
  1511. info->var = pm2fb_var;
  1512. retval = fb_alloc_cmap(&info->cmap, 256, 0);
  1513. if (retval < 0)
  1514. goto err_exit_both;
  1515. retval = register_framebuffer(info);
  1516. if (retval < 0)
  1517. goto err_exit_all;
  1518. fb_info(info, "%s frame buffer device, memory = %dK\n",
  1519. info->fix.id, pm2fb_fix.smem_len / 1024);
  1520. /*
  1521. * Our driver data
  1522. */
  1523. pci_set_drvdata(pdev, info);
  1524. return 0;
  1525. err_exit_all:
  1526. fb_dealloc_cmap(&info->cmap);
  1527. err_exit_both:
  1528. kfree(info->pixmap.addr);
  1529. err_exit_pixmap:
  1530. iounmap(info->screen_base);
  1531. release_mem_region(pm2fb_fix.smem_start, pm2fb_fix.smem_len);
  1532. err_exit_mmio:
  1533. iounmap(default_par->v_regs);
  1534. release_mem_region(pm2fb_fix.mmio_start, pm2fb_fix.mmio_len);
  1535. err_exit_neither:
  1536. framebuffer_release(info);
  1537. return retval;
  1538. }
  1539. /**
  1540. * Device removal.
  1541. *
  1542. * Release all device resources.
  1543. *
  1544. * @param pdev PCI device to clean up.
  1545. */
  1546. static void pm2fb_remove(struct pci_dev *pdev)
  1547. {
  1548. struct fb_info *info = pci_get_drvdata(pdev);
  1549. struct fb_fix_screeninfo *fix = &info->fix;
  1550. struct pm2fb_par *par = info->par;
  1551. unregister_framebuffer(info);
  1552. arch_phys_wc_del(par->wc_cookie);
  1553. iounmap(info->screen_base);
  1554. release_mem_region(fix->smem_start, fix->smem_len);
  1555. iounmap(par->v_regs);
  1556. release_mem_region(fix->mmio_start, fix->mmio_len);
  1557. fb_dealloc_cmap(&info->cmap);
  1558. kfree(info->pixmap.addr);
  1559. framebuffer_release(info);
  1560. }
  1561. static struct pci_device_id pm2fb_id_table[] = {
  1562. { PCI_VENDOR_ID_TI, PCI_DEVICE_ID_TI_TVP4020,
  1563. PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
  1564. { PCI_VENDOR_ID_3DLABS, PCI_DEVICE_ID_3DLABS_PERMEDIA2,
  1565. PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
  1566. { PCI_VENDOR_ID_3DLABS, PCI_DEVICE_ID_3DLABS_PERMEDIA2V,
  1567. PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0 },
  1568. { 0, }
  1569. };
  1570. static struct pci_driver pm2fb_driver = {
  1571. .name = "pm2fb",
  1572. .id_table = pm2fb_id_table,
  1573. .probe = pm2fb_probe,
  1574. .remove = pm2fb_remove,
  1575. };
  1576. MODULE_DEVICE_TABLE(pci, pm2fb_id_table);
  1577. #ifndef MODULE
  1578. /**
  1579. * Parse user specified options.
  1580. *
  1581. * This is, comma-separated options following `video=pm2fb:'.
  1582. */
  1583. static int __init pm2fb_setup(char *options)
  1584. {
  1585. char *this_opt;
  1586. if (!options || !*options)
  1587. return 0;
  1588. while ((this_opt = strsep(&options, ",")) != NULL) {
  1589. if (!*this_opt)
  1590. continue;
  1591. if (!strcmp(this_opt, "lowhsync"))
  1592. lowhsync = 1;
  1593. else if (!strcmp(this_opt, "lowvsync"))
  1594. lowvsync = 1;
  1595. else if (!strncmp(this_opt, "hwcursor=", 9))
  1596. hwcursor = simple_strtoul(this_opt + 9, NULL, 0);
  1597. else if (!strncmp(this_opt, "nomtrr", 6))
  1598. nomtrr = 1;
  1599. else if (!strncmp(this_opt, "noaccel", 7))
  1600. noaccel = 1;
  1601. else
  1602. mode_option = this_opt;
  1603. }
  1604. return 0;
  1605. }
  1606. #endif
  1607. static int __init pm2fb_init(void)
  1608. {
  1609. #ifndef MODULE
  1610. char *option = NULL;
  1611. if (fb_get_options("pm2fb", &option))
  1612. return -ENODEV;
  1613. pm2fb_setup(option);
  1614. #endif
  1615. return pci_register_driver(&pm2fb_driver);
  1616. }
  1617. module_init(pm2fb_init);
  1618. #ifdef MODULE
  1619. /*
  1620. * Cleanup
  1621. */
  1622. static void __exit pm2fb_exit(void)
  1623. {
  1624. pci_unregister_driver(&pm2fb_driver);
  1625. }
  1626. #endif
  1627. #ifdef MODULE
  1628. module_exit(pm2fb_exit);
  1629. module_param(mode_option, charp, 0);
  1630. MODULE_PARM_DESC(mode_option, "Initial video mode e.g. '648x480-8@60'");
  1631. module_param_named(mode, mode_option, charp, 0);
  1632. MODULE_PARM_DESC(mode, "Initial video mode e.g. '648x480-8@60' (deprecated)");
  1633. module_param(lowhsync, bool, 0);
  1634. MODULE_PARM_DESC(lowhsync, "Force horizontal sync low regardless of mode");
  1635. module_param(lowvsync, bool, 0);
  1636. MODULE_PARM_DESC(lowvsync, "Force vertical sync low regardless of mode");
  1637. module_param(noaccel, bool, 0);
  1638. MODULE_PARM_DESC(noaccel, "Disable acceleration");
  1639. module_param(hwcursor, int, 0644);
  1640. MODULE_PARM_DESC(hwcursor, "Enable hardware cursor "
  1641. "(1=enable, 0=disable, default=1)");
  1642. module_param(nomtrr, bool, 0);
  1643. MODULE_PARM_DESC(nomtrr, "Disable MTRR support (0 or 1=disabled) (default=0)");
  1644. MODULE_AUTHOR("Jim Hague <jim.hague@acm.org>");
  1645. MODULE_DESCRIPTION("Permedia2 framebuffer device driver");
  1646. MODULE_LICENSE("GPL");
  1647. #endif